18892ea20SAggelos Economopoulos /******************************************************************************* 28892ea20SAggelos Economopoulos 38892ea20SAggelos Economopoulos Copyright (c) 2006-2009, Myricom Inc. 48892ea20SAggelos Economopoulos All rights reserved. 58892ea20SAggelos Economopoulos 68892ea20SAggelos Economopoulos Redistribution and use in source and binary forms, with or without 78892ea20SAggelos Economopoulos modification, are permitted provided that the following conditions are met: 88892ea20SAggelos Economopoulos 98892ea20SAggelos Economopoulos 1. Redistributions of source code must retain the above copyright notice, 108892ea20SAggelos Economopoulos this list of conditions and the following disclaimer. 118892ea20SAggelos Economopoulos 128892ea20SAggelos Economopoulos 2. Neither the name of the Myricom Inc, nor the names of its 138892ea20SAggelos Economopoulos contributors may be used to endorse or promote products derived from 148892ea20SAggelos Economopoulos this software without specific prior written permission. 158892ea20SAggelos Economopoulos 168892ea20SAggelos Economopoulos THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 178892ea20SAggelos Economopoulos AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 188892ea20SAggelos Economopoulos IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 198892ea20SAggelos Economopoulos ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 208892ea20SAggelos Economopoulos LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 218892ea20SAggelos Economopoulos CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 228892ea20SAggelos Economopoulos SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 238892ea20SAggelos Economopoulos INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 248892ea20SAggelos Economopoulos CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 258892ea20SAggelos Economopoulos ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 268892ea20SAggelos Economopoulos POSSIBILITY OF SUCH DAMAGE. 278892ea20SAggelos Economopoulos 28*89d55360SSepherosa Ziehau $FreeBSD: head/sys/dev/mxge/mxge_mcp.h 188736 2009-02-17 22:15:58Z gallatin $ 298892ea20SAggelos Economopoulos ***************************************************************************/ 308892ea20SAggelos Economopoulos 318892ea20SAggelos Economopoulos #ifndef _myri10ge_mcp_h 328892ea20SAggelos Economopoulos #define _myri10ge_mcp_h 338892ea20SAggelos Economopoulos 348892ea20SAggelos Economopoulos #define MXGEFW_VERSION_MAJOR 1 358892ea20SAggelos Economopoulos #define MXGEFW_VERSION_MINOR 4 368892ea20SAggelos Economopoulos 378892ea20SAggelos Economopoulos #if defined MXGEFW && !defined _stdint_h_ 388892ea20SAggelos Economopoulos typedef signed char int8_t; 398892ea20SAggelos Economopoulos typedef signed short int16_t; 408892ea20SAggelos Economopoulos typedef signed int int32_t; 418892ea20SAggelos Economopoulos typedef signed long long int64_t; 428892ea20SAggelos Economopoulos typedef unsigned char uint8_t; 438892ea20SAggelos Economopoulos typedef unsigned short uint16_t; 448892ea20SAggelos Economopoulos typedef unsigned int uint32_t; 458892ea20SAggelos Economopoulos typedef unsigned long long uint64_t; 468892ea20SAggelos Economopoulos #endif 478892ea20SAggelos Economopoulos 488892ea20SAggelos Economopoulos /* 8 Bytes */ 498892ea20SAggelos Economopoulos struct mcp_dma_addr { 508892ea20SAggelos Economopoulos uint32_t high; 518892ea20SAggelos Economopoulos uint32_t low; 528892ea20SAggelos Economopoulos }; 538892ea20SAggelos Economopoulos typedef struct mcp_dma_addr mcp_dma_addr_t; 548892ea20SAggelos Economopoulos 558892ea20SAggelos Economopoulos /* 4 Bytes */ 568892ea20SAggelos Economopoulos struct mcp_slot { 578892ea20SAggelos Economopoulos uint16_t checksum; 588892ea20SAggelos Economopoulos uint16_t length; 598892ea20SAggelos Economopoulos }; 608892ea20SAggelos Economopoulos typedef struct mcp_slot mcp_slot_t; 618892ea20SAggelos Economopoulos 628892ea20SAggelos Economopoulos #ifdef MXGEFW_NDIS 638892ea20SAggelos Economopoulos /* 8-byte descriptor, exclusively used by NDIS drivers. */ 648892ea20SAggelos Economopoulos struct mcp_slot_8 { 658892ea20SAggelos Economopoulos /* Place hash value at the top so it gets written before length. 668892ea20SAggelos Economopoulos * The driver polls length. 678892ea20SAggelos Economopoulos */ 688892ea20SAggelos Economopoulos uint32_t hash; 698892ea20SAggelos Economopoulos uint16_t checksum; 708892ea20SAggelos Economopoulos uint16_t length; 718892ea20SAggelos Economopoulos }; 728892ea20SAggelos Economopoulos typedef struct mcp_slot_8 mcp_slot_8_t; 738892ea20SAggelos Economopoulos 748892ea20SAggelos Economopoulos /* Two bits of length in mcp_slot are used to indicate hash type. */ 758892ea20SAggelos Economopoulos #define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */ 768892ea20SAggelos Economopoulos #define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */ 778892ea20SAggelos Economopoulos #define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */ 788892ea20SAggelos Economopoulos #define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */ 798892ea20SAggelos Economopoulos #endif 808892ea20SAggelos Economopoulos 818892ea20SAggelos Economopoulos /* 64 Bytes */ 828892ea20SAggelos Economopoulos struct mcp_cmd { 838892ea20SAggelos Economopoulos uint32_t cmd; 848892ea20SAggelos Economopoulos uint32_t data0; /* will be low portion if data > 32 bits */ 858892ea20SAggelos Economopoulos /* 8 */ 868892ea20SAggelos Economopoulos uint32_t data1; /* will be high portion if data > 32 bits */ 878892ea20SAggelos Economopoulos uint32_t data2; /* currently unused.. */ 888892ea20SAggelos Economopoulos /* 16 */ 898892ea20SAggelos Economopoulos struct mcp_dma_addr response_addr; 908892ea20SAggelos Economopoulos /* 24 */ 918892ea20SAggelos Economopoulos uint8_t pad[40]; 928892ea20SAggelos Economopoulos }; 938892ea20SAggelos Economopoulos typedef struct mcp_cmd mcp_cmd_t; 948892ea20SAggelos Economopoulos 958892ea20SAggelos Economopoulos /* 8 Bytes */ 968892ea20SAggelos Economopoulos struct mcp_cmd_response { 978892ea20SAggelos Economopoulos uint32_t data; 988892ea20SAggelos Economopoulos uint32_t result; 998892ea20SAggelos Economopoulos }; 1008892ea20SAggelos Economopoulos typedef struct mcp_cmd_response mcp_cmd_response_t; 1018892ea20SAggelos Economopoulos 1028892ea20SAggelos Economopoulos 1038892ea20SAggelos Economopoulos 1048892ea20SAggelos Economopoulos /* 1058892ea20SAggelos Economopoulos flags used in mcp_kreq_ether_send_t: 1068892ea20SAggelos Economopoulos 1078892ea20SAggelos Economopoulos The SMALL flag is only needed in the first segment. It is raised 1088892ea20SAggelos Economopoulos for packets that are total less or equal 512 bytes. 1098892ea20SAggelos Economopoulos 1108892ea20SAggelos Economopoulos The CKSUM flag must be set in all segments. 1118892ea20SAggelos Economopoulos 1128892ea20SAggelos Economopoulos The PADDED flags is set if the packet needs to be padded, and it 1138892ea20SAggelos Economopoulos must be set for all segments. 1148892ea20SAggelos Economopoulos 1158892ea20SAggelos Economopoulos The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 1168892ea20SAggelos Economopoulos length of all previous segments was odd. 1178892ea20SAggelos Economopoulos */ 1188892ea20SAggelos Economopoulos 1198892ea20SAggelos Economopoulos 1208892ea20SAggelos Economopoulos #define MXGEFW_FLAGS_SMALL 0x1 1218892ea20SAggelos Economopoulos #define MXGEFW_FLAGS_TSO_HDR 0x1 1228892ea20SAggelos Economopoulos #define MXGEFW_FLAGS_FIRST 0x2 1238892ea20SAggelos Economopoulos #define MXGEFW_FLAGS_ALIGN_ODD 0x4 1248892ea20SAggelos Economopoulos #define MXGEFW_FLAGS_CKSUM 0x8 1258892ea20SAggelos Economopoulos #define MXGEFW_FLAGS_TSO_LAST 0x8 1268892ea20SAggelos Economopoulos #define MXGEFW_FLAGS_NO_TSO 0x10 1278892ea20SAggelos Economopoulos #define MXGEFW_FLAGS_TSO_CHOP 0x10 1288892ea20SAggelos Economopoulos #define MXGEFW_FLAGS_TSO_PLD 0x20 1298892ea20SAggelos Economopoulos 1308892ea20SAggelos Economopoulos #define MXGEFW_SEND_SMALL_SIZE 1520 1318892ea20SAggelos Economopoulos #define MXGEFW_MAX_MTU 9400 1328892ea20SAggelos Economopoulos 1338892ea20SAggelos Economopoulos union mcp_pso_or_cumlen { 1348892ea20SAggelos Economopoulos uint16_t pseudo_hdr_offset; 1358892ea20SAggelos Economopoulos uint16_t cum_len; 1368892ea20SAggelos Economopoulos }; 1378892ea20SAggelos Economopoulos typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 1388892ea20SAggelos Economopoulos 1398892ea20SAggelos Economopoulos #define MXGEFW_MAX_SEND_DESC 12 1408892ea20SAggelos Economopoulos #define MXGEFW_PAD 2 1418892ea20SAggelos Economopoulos 1428892ea20SAggelos Economopoulos /* 16 Bytes */ 1438892ea20SAggelos Economopoulos struct mcp_kreq_ether_send { 1448892ea20SAggelos Economopoulos uint32_t addr_high; 1458892ea20SAggelos Economopoulos uint32_t addr_low; 1468892ea20SAggelos Economopoulos uint16_t pseudo_hdr_offset; 1478892ea20SAggelos Economopoulos uint16_t length; 1488892ea20SAggelos Economopoulos uint8_t pad; 1498892ea20SAggelos Economopoulos uint8_t rdma_count; 1508892ea20SAggelos Economopoulos uint8_t cksum_offset; /* where to start computing cksum */ 1518892ea20SAggelos Economopoulos uint8_t flags; /* as defined above */ 1528892ea20SAggelos Economopoulos }; 1538892ea20SAggelos Economopoulos typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 1548892ea20SAggelos Economopoulos 1558892ea20SAggelos Economopoulos /* 8 Bytes */ 1568892ea20SAggelos Economopoulos struct mcp_kreq_ether_recv { 1578892ea20SAggelos Economopoulos uint32_t addr_high; 1588892ea20SAggelos Economopoulos uint32_t addr_low; 1598892ea20SAggelos Economopoulos }; 1608892ea20SAggelos Economopoulos typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 1618892ea20SAggelos Economopoulos 1628892ea20SAggelos Economopoulos 1638892ea20SAggelos Economopoulos /* Commands */ 1648892ea20SAggelos Economopoulos 1658892ea20SAggelos Economopoulos #define MXGEFW_BOOT_HANDOFF 0xfc0000 1668892ea20SAggelos Economopoulos #define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 1678892ea20SAggelos Economopoulos 1688892ea20SAggelos Economopoulos #define MXGEFW_ETH_CMD 0xf80000 1698892ea20SAggelos Economopoulos #define MXGEFW_ETH_SEND_4 0x200000 1708892ea20SAggelos Economopoulos #define MXGEFW_ETH_SEND_1 0x240000 1718892ea20SAggelos Economopoulos #define MXGEFW_ETH_SEND_2 0x280000 1728892ea20SAggelos Economopoulos #define MXGEFW_ETH_SEND_3 0x2c0000 1738892ea20SAggelos Economopoulos #define MXGEFW_ETH_RECV_SMALL 0x300000 1748892ea20SAggelos Economopoulos #define MXGEFW_ETH_RECV_BIG 0x340000 1758892ea20SAggelos Economopoulos #define MXGEFW_ETH_SEND_GO 0x380000 1768892ea20SAggelos Economopoulos #define MXGEFW_ETH_SEND_STOP 0x3C0000 1778892ea20SAggelos Economopoulos 1788892ea20SAggelos Economopoulos #define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 1798892ea20SAggelos Economopoulos #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 1808892ea20SAggelos Economopoulos 1818892ea20SAggelos Economopoulos enum myri10ge_mcp_cmd_type { 1828892ea20SAggelos Economopoulos MXGEFW_CMD_NONE = 0, 1838892ea20SAggelos Economopoulos /* Reset the mcp, it is left in a safe state, waiting 1848892ea20SAggelos Economopoulos for the driver to set all its parameters */ 1858892ea20SAggelos Economopoulos MXGEFW_CMD_RESET = 1, 1868892ea20SAggelos Economopoulos 1878892ea20SAggelos Economopoulos /* get the version number of the current firmware.. 1888892ea20SAggelos Economopoulos (may be available in the eeprom strings..? */ 1898892ea20SAggelos Economopoulos MXGEFW_GET_MCP_VERSION = 2, 1908892ea20SAggelos Economopoulos 1918892ea20SAggelos Economopoulos 1928892ea20SAggelos Economopoulos /* Parameters which must be set by the driver before it can 1938892ea20SAggelos Economopoulos issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 1948892ea20SAggelos Economopoulos MXGEFW_CMD_RESET is issued */ 1958892ea20SAggelos Economopoulos 1968892ea20SAggelos Economopoulos MXGEFW_CMD_SET_INTRQ_DMA = 3, 1978892ea20SAggelos Economopoulos /* data0 = LSW of the host address 1988892ea20SAggelos Economopoulos * data1 = MSW of the host address 1998892ea20SAggelos Economopoulos * data2 = slice number if multiple slices are used 2008892ea20SAggelos Economopoulos */ 2018892ea20SAggelos Economopoulos 2028892ea20SAggelos Economopoulos MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */ 2038892ea20SAggelos Economopoulos MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */ 2048892ea20SAggelos Economopoulos 2058892ea20SAggelos Economopoulos 2068892ea20SAggelos Economopoulos /* Parameters which refer to lanai SRAM addresses where the 2078892ea20SAggelos Economopoulos driver must issue PIO writes for various things */ 2088892ea20SAggelos Economopoulos 2098892ea20SAggelos Economopoulos MXGEFW_CMD_GET_SEND_OFFSET = 6, 2108892ea20SAggelos Economopoulos MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7, 2118892ea20SAggelos Economopoulos MXGEFW_CMD_GET_BIG_RX_OFFSET = 8, 2128892ea20SAggelos Economopoulos /* data0 = slice number if multiple slices are used */ 2138892ea20SAggelos Economopoulos 2148892ea20SAggelos Economopoulos MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9, 2158892ea20SAggelos Economopoulos MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10, 2168892ea20SAggelos Economopoulos 2178892ea20SAggelos Economopoulos /* Parameters which refer to rings stored on the MCP, 2188892ea20SAggelos Economopoulos and whose size is controlled by the mcp */ 2198892ea20SAggelos Economopoulos 2208892ea20SAggelos Economopoulos MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */ 2218892ea20SAggelos Economopoulos MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */ 2228892ea20SAggelos Economopoulos 2238892ea20SAggelos Economopoulos /* Parameters which refer to rings stored in the host, 2248892ea20SAggelos Economopoulos and whose size is controlled by the host. Note that 2258892ea20SAggelos Economopoulos all must be physically contiguous and must contain 2268892ea20SAggelos Economopoulos a power of 2 number of entries. */ 2278892ea20SAggelos Economopoulos 2288892ea20SAggelos Economopoulos MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */ 2298892ea20SAggelos Economopoulos #define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31) 2308892ea20SAggelos Economopoulos 2318892ea20SAggelos Economopoulos /* command to bring ethernet interface up. Above parameters 2328892ea20SAggelos Economopoulos (plus mtu & mac address) must have been exchanged prior 2338892ea20SAggelos Economopoulos to issuing this command */ 2348892ea20SAggelos Economopoulos MXGEFW_CMD_ETHERNET_UP = 14, 2358892ea20SAggelos Economopoulos 2368892ea20SAggelos Economopoulos /* command to bring ethernet interface down. No further sends 2378892ea20SAggelos Economopoulos or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 2388892ea20SAggelos Economopoulos is issued, and all interrupt queues must be flushed prior 2398892ea20SAggelos Economopoulos to ack'ing this command */ 2408892ea20SAggelos Economopoulos 2418892ea20SAggelos Economopoulos MXGEFW_CMD_ETHERNET_DOWN = 15, 2428892ea20SAggelos Economopoulos 2438892ea20SAggelos Economopoulos /* commands the driver may issue live, without resetting 2448892ea20SAggelos Economopoulos the nic. Note that increasing the mtu "live" should 2458892ea20SAggelos Economopoulos only be done if the driver has already supplied buffers 2468892ea20SAggelos Economopoulos sufficiently large to handle the new mtu. Decreasing 2478892ea20SAggelos Economopoulos the mtu live is safe */ 2488892ea20SAggelos Economopoulos 2498892ea20SAggelos Economopoulos MXGEFW_CMD_SET_MTU = 16, 2508892ea20SAggelos Economopoulos MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */ 2518892ea20SAggelos Economopoulos MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */ 2528892ea20SAggelos Economopoulos MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */ 2538892ea20SAggelos Economopoulos 2548892ea20SAggelos Economopoulos MXGEFW_ENABLE_PROMISC = 20, 2558892ea20SAggelos Economopoulos MXGEFW_DISABLE_PROMISC = 21, 2568892ea20SAggelos Economopoulos MXGEFW_SET_MAC_ADDRESS = 22, 2578892ea20SAggelos Economopoulos 2588892ea20SAggelos Economopoulos MXGEFW_ENABLE_FLOW_CONTROL = 23, 2598892ea20SAggelos Economopoulos MXGEFW_DISABLE_FLOW_CONTROL = 24, 2608892ea20SAggelos Economopoulos 2618892ea20SAggelos Economopoulos /* do a DMA test 2628892ea20SAggelos Economopoulos data0,data1 = DMA address 2638892ea20SAggelos Economopoulos data2 = RDMA length (MSH), WDMA length (LSH) 2648892ea20SAggelos Economopoulos command return data = repetitions (MSH), 0.5-ms ticks (LSH) 2658892ea20SAggelos Economopoulos */ 2668892ea20SAggelos Economopoulos MXGEFW_DMA_TEST = 25, 2678892ea20SAggelos Economopoulos 2688892ea20SAggelos Economopoulos MXGEFW_ENABLE_ALLMULTI = 26, 2698892ea20SAggelos Economopoulos MXGEFW_DISABLE_ALLMULTI = 27, 2708892ea20SAggelos Economopoulos 2718892ea20SAggelos Economopoulos /* returns MXGEFW_CMD_ERROR_MULTICAST 2728892ea20SAggelos Economopoulos if there is no room in the cache 2738892ea20SAggelos Economopoulos data0,MSH(data1) = multicast group address */ 2748892ea20SAggelos Economopoulos MXGEFW_JOIN_MULTICAST_GROUP = 28, 2758892ea20SAggelos Economopoulos /* returns MXGEFW_CMD_ERROR_MULTICAST 2768892ea20SAggelos Economopoulos if the address is not in the cache, 2778892ea20SAggelos Economopoulos or is equal to FF-FF-FF-FF-FF-FF 2788892ea20SAggelos Economopoulos data0,MSH(data1) = multicast group address */ 2798892ea20SAggelos Economopoulos MXGEFW_LEAVE_MULTICAST_GROUP = 29, 2808892ea20SAggelos Economopoulos MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30, 2818892ea20SAggelos Economopoulos 2828892ea20SAggelos Economopoulos MXGEFW_CMD_SET_STATS_DMA_V2 = 31, 2838892ea20SAggelos Economopoulos /* data0, data1 = bus addr, 2848892ea20SAggelos Economopoulos * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 2858892ea20SAggelos Economopoulos * adding new stuff to mcp_irq_data without changing the ABI 2868892ea20SAggelos Economopoulos * 2878892ea20SAggelos Economopoulos * If multiple slices are used, data2 contains both the size of the 2888892ea20SAggelos Economopoulos * structure (in the lower 16 bits) and the slice number 2898892ea20SAggelos Economopoulos * (in the upper 16 bits). 2908892ea20SAggelos Economopoulos */ 2918892ea20SAggelos Economopoulos 2928892ea20SAggelos Economopoulos MXGEFW_CMD_UNALIGNED_TEST = 32, 2938892ea20SAggelos Economopoulos /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 2948892ea20SAggelos Economopoulos chipset */ 2958892ea20SAggelos Economopoulos 2968892ea20SAggelos Economopoulos MXGEFW_CMD_UNALIGNED_STATUS = 33, 2978892ea20SAggelos Economopoulos /* return data = boolean, true if the chipset is known to be unaligned */ 2988892ea20SAggelos Economopoulos 2998892ea20SAggelos Economopoulos MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34, 3008892ea20SAggelos Economopoulos /* data0 = number of big buffers to use. It must be 0 or a power of 2. 3018892ea20SAggelos Economopoulos * 0 indicates that the NIC consumes as many buffers as they are required 3028892ea20SAggelos Economopoulos * for packet. This is the default behavior. 3038892ea20SAggelos Economopoulos * A power of 2 number indicates that the NIC always uses the specified 3048892ea20SAggelos Economopoulos * number of buffers for each big receive packet. 3058892ea20SAggelos Economopoulos * It is up to the driver to ensure that this value is big enough for 3068892ea20SAggelos Economopoulos * the NIC to be able to receive maximum-sized packets. 3078892ea20SAggelos Economopoulos */ 3088892ea20SAggelos Economopoulos 3098892ea20SAggelos Economopoulos MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35, 3108892ea20SAggelos Economopoulos MXGEFW_CMD_ENABLE_RSS_QUEUES = 36, 3118892ea20SAggelos Economopoulos /* data0 = number of slices n (0, 1, ..., n-1) to enable 3128892ea20SAggelos Economopoulos * data1 = interrupt mode | use of multiple transmit queues. 3138892ea20SAggelos Economopoulos * 0=share one INTx/MSI. 3148892ea20SAggelos Economopoulos * 1=use one MSI-X per queue. 3158892ea20SAggelos Economopoulos * If all queues share one interrupt, the driver must have set 3168892ea20SAggelos Economopoulos * RSS_SHARED_INTERRUPT_DMA before enabling queues. 3178892ea20SAggelos Economopoulos * 2=enable both receive and send queues. 3188892ea20SAggelos Economopoulos * Without this bit set, only one send queue (slice 0's send queue) 3198892ea20SAggelos Economopoulos * is enabled. The receive queues are always enabled. 3208892ea20SAggelos Economopoulos */ 3218892ea20SAggelos Economopoulos #define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 3228892ea20SAggelos Economopoulos #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 3238892ea20SAggelos Economopoulos #define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 3248892ea20SAggelos Economopoulos 3258892ea20SAggelos Economopoulos MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37, 3268892ea20SAggelos Economopoulos MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38, 3278892ea20SAggelos Economopoulos /* data0, data1 = bus address lsw, msw */ 3288892ea20SAggelos Economopoulos MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39, 3298892ea20SAggelos Economopoulos /* get the offset of the indirection table */ 3308892ea20SAggelos Economopoulos MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40, 3318892ea20SAggelos Economopoulos /* set the size of the indirection table */ 3328892ea20SAggelos Economopoulos MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41, 3338892ea20SAggelos Economopoulos /* get the offset of the secret key */ 3348892ea20SAggelos Economopoulos MXGEFW_CMD_RSS_KEY_UPDATED = 42, 3358892ea20SAggelos Economopoulos /* tell nic that the secret key's been updated */ 3368892ea20SAggelos Economopoulos MXGEFW_CMD_SET_RSS_ENABLE = 43, 3378892ea20SAggelos Economopoulos /* data0 = enable/disable rss 3388892ea20SAggelos Economopoulos * 0: disable rss. nic does not distribute receive packets. 3398892ea20SAggelos Economopoulos * 1: enable rss. nic distributes receive packets among queues. 3408892ea20SAggelos Economopoulos * data1 = hash type 3418892ea20SAggelos Economopoulos * 1: IPV4 (required by RSS) 3428892ea20SAggelos Economopoulos * 2: TCP_IPV4 (required by RSS) 3438892ea20SAggelos Economopoulos * 3: IPV4 | TCP_IPV4 (required by RSS) 3448892ea20SAggelos Economopoulos * 4: source port 3458892ea20SAggelos Economopoulos * 5: source port + destination port 3468892ea20SAggelos Economopoulos */ 3478892ea20SAggelos Economopoulos #define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 3488892ea20SAggelos Economopoulos #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 3498892ea20SAggelos Economopoulos #define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 3508892ea20SAggelos Economopoulos #define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 3518892ea20SAggelos Economopoulos #define MXGEFW_RSS_HASH_TYPE_MAX 0x5 3528892ea20SAggelos Economopoulos 3538892ea20SAggelos Economopoulos MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44, 3548892ea20SAggelos Economopoulos /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 3558892ea20SAggelos Economopoulos * If the header size of a IPv6 TSO packet is larger than the specified 3568892ea20SAggelos Economopoulos * value, then the driver must not use TSO. 3578892ea20SAggelos Economopoulos * This size restriction only applies to IPv6 TSO. 3588892ea20SAggelos Economopoulos * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 3598892ea20SAggelos Economopoulos * always has enough header buffer to store maximum-sized headers. 3608892ea20SAggelos Economopoulos */ 3618892ea20SAggelos Economopoulos 3628892ea20SAggelos Economopoulos MXGEFW_CMD_SET_TSO_MODE = 45, 3638892ea20SAggelos Economopoulos /* data0 = TSO mode. 3648892ea20SAggelos Economopoulos * 0: Linux/FreeBSD style (NIC default) 3658892ea20SAggelos Economopoulos * 1: NDIS/NetBSD style 3668892ea20SAggelos Economopoulos */ 3678892ea20SAggelos Economopoulos #define MXGEFW_TSO_MODE_LINUX 0 3688892ea20SAggelos Economopoulos #define MXGEFW_TSO_MODE_NDIS 1 3698892ea20SAggelos Economopoulos 3708892ea20SAggelos Economopoulos MXGEFW_CMD_MDIO_READ = 46, 3718892ea20SAggelos Economopoulos /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 3728892ea20SAggelos Economopoulos MXGEFW_CMD_MDIO_WRITE = 47, 3738892ea20SAggelos Economopoulos /* data0 = dev_addr, data1 = register/addr, data2 = value */ 3748892ea20SAggelos Economopoulos 3758892ea20SAggelos Economopoulos MXGEFW_CMD_I2C_READ = 48, 3768892ea20SAggelos Economopoulos /* Starts to get a fresh copy of one byte or of the module i2c table, the 3778892ea20SAggelos Economopoulos * obtained data is cached inside the xaui-xfi chip : 3788892ea20SAggelos Economopoulos * data0 : 0 => get one byte, 1=> get 256 bytes 3798892ea20SAggelos Economopoulos * data1 : If data0 == 0: location to refresh 3808892ea20SAggelos Economopoulos * bit 7:0 register location 3818892ea20SAggelos Economopoulos * bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1) 3828892ea20SAggelos Economopoulos * bit 23:16 is the i2c bus number (for multi-port NICs) 3838892ea20SAggelos Economopoulos * If data0 == 1: unused 3848892ea20SAggelos Economopoulos * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 3858892ea20SAggelos Economopoulos * During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts 3868892ea20SAggelos Economopoulos * will return MXGEFW_CMD_ERROR_BUSY 3878892ea20SAggelos Economopoulos */ 3888892ea20SAggelos Economopoulos MXGEFW_CMD_I2C_BYTE = 49, 3898892ea20SAggelos Economopoulos /* Return the last obtained copy of a given byte in the xfp i2c table 3908892ea20SAggelos Economopoulos * (copy cached during the last relevant MXGEFW_CMD_I2C_READ) 3918892ea20SAggelos Economopoulos * data0 : index of the desired table entry 3928892ea20SAggelos Economopoulos * Return data = the byte stored at the requested index in the table 3938892ea20SAggelos Economopoulos */ 3948892ea20SAggelos Economopoulos 3958892ea20SAggelos Economopoulos MXGEFW_CMD_GET_VPUMP_OFFSET = 50, 3968892ea20SAggelos Economopoulos /* Return data = NIC memory offset of mcp_vpump_public_global */ 3978892ea20SAggelos Economopoulos MXGEFW_CMD_RESET_VPUMP = 51, 3988892ea20SAggelos Economopoulos /* Resets the VPUMP state */ 3998892ea20SAggelos Economopoulos 4008892ea20SAggelos Economopoulos MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52, 4018892ea20SAggelos Economopoulos /* data0 = mcp_slot type to use. 4028892ea20SAggelos Economopoulos * 0 = the default 4B mcp_slot 4038892ea20SAggelos Economopoulos * 1 = 8B mcp_slot_8 4048892ea20SAggelos Economopoulos */ 4058892ea20SAggelos Economopoulos #define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 4068892ea20SAggelos Economopoulos #define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 4078892ea20SAggelos Economopoulos 4088892ea20SAggelos Economopoulos MXGEFW_CMD_SET_THROTTLE_FACTOR = 53, 4098892ea20SAggelos Economopoulos /* set the throttle factor for ethp_z8e 4108892ea20SAggelos Economopoulos data0 = throttle_factor 4118892ea20SAggelos Economopoulos throttle_factor = 256 * pcie-raw-speed / tx_speed 4128892ea20SAggelos Economopoulos tx_speed = 256 * pcie-raw-speed / throttle_factor 4138892ea20SAggelos Economopoulos 4148892ea20SAggelos Economopoulos For PCI-E x8: pcie-raw-speed == 16Gb/s 4158892ea20SAggelos Economopoulos For PCI-E x4: pcie-raw-speed == 8Gb/s 4168892ea20SAggelos Economopoulos 4178892ea20SAggelos Economopoulos ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 4188892ea20SAggelos Economopoulos ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 4198892ea20SAggelos Economopoulos 4208892ea20SAggelos Economopoulos with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 4218892ea20SAggelos Economopoulos with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 4228892ea20SAggelos Economopoulos */ 4238892ea20SAggelos Economopoulos 4248892ea20SAggelos Economopoulos MXGEFW_CMD_VPUMP_UP = 54, 4258892ea20SAggelos Economopoulos /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 4268892ea20SAggelos Economopoulos MXGEFW_CMD_GET_VPUMP_CLK = 55, 4278892ea20SAggelos Economopoulos /* Get the lanai clock */ 4288892ea20SAggelos Economopoulos 4298892ea20SAggelos Economopoulos MXGEFW_CMD_GET_DCA_OFFSET = 56, 4308892ea20SAggelos Economopoulos /* offset of dca control for WDMAs */ 4318892ea20SAggelos Economopoulos 4328892ea20SAggelos Economopoulos /* VMWare NetQueue commands */ 4338892ea20SAggelos Economopoulos MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57, 4348892ea20SAggelos Economopoulos MXGEFW_CMD_NETQ_ADD_FILTER = 58, 4358892ea20SAggelos Economopoulos /* data0 = filter_id << 16 | queue << 8 | type */ 4368892ea20SAggelos Economopoulos /* data1 = MS4 of MAC Addr */ 4378892ea20SAggelos Economopoulos /* data2 = LS2_MAC << 16 | VLAN_tag */ 4388892ea20SAggelos Economopoulos MXGEFW_CMD_NETQ_DEL_FILTER = 59, 4398892ea20SAggelos Economopoulos /* data0 = filter_id */ 4408892ea20SAggelos Economopoulos MXGEFW_CMD_NETQ_QUERY1 = 60, 4418892ea20SAggelos Economopoulos MXGEFW_CMD_NETQ_QUERY2 = 61, 4428892ea20SAggelos Economopoulos MXGEFW_CMD_NETQ_QUERY3 = 62, 4438892ea20SAggelos Economopoulos MXGEFW_CMD_NETQ_QUERY4 = 63, 4448892ea20SAggelos Economopoulos 4458892ea20SAggelos Economopoulos MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64, 4468892ea20SAggelos Economopoulos /* When set, small receive buffers can cross page boundaries. 4478892ea20SAggelos Economopoulos * Both small and big receive buffers may start at any address. 4488892ea20SAggelos Economopoulos * This option has performance implications, so use with caution. 4498892ea20SAggelos Economopoulos */ 4508892ea20SAggelos Economopoulos }; 4518892ea20SAggelos Economopoulos typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 4528892ea20SAggelos Economopoulos 4538892ea20SAggelos Economopoulos 4548892ea20SAggelos Economopoulos enum myri10ge_mcp_cmd_status { 4558892ea20SAggelos Economopoulos MXGEFW_CMD_OK = 0, 4568892ea20SAggelos Economopoulos MXGEFW_CMD_UNKNOWN = 1, 4578892ea20SAggelos Economopoulos MXGEFW_CMD_ERROR_RANGE = 2, 4588892ea20SAggelos Economopoulos MXGEFW_CMD_ERROR_BUSY = 3, 4598892ea20SAggelos Economopoulos MXGEFW_CMD_ERROR_EMPTY = 4, 4608892ea20SAggelos Economopoulos MXGEFW_CMD_ERROR_CLOSED = 5, 4618892ea20SAggelos Economopoulos MXGEFW_CMD_ERROR_HASH_ERROR = 6, 4628892ea20SAggelos Economopoulos MXGEFW_CMD_ERROR_BAD_PORT = 7, 4638892ea20SAggelos Economopoulos MXGEFW_CMD_ERROR_RESOURCES = 8, 4648892ea20SAggelos Economopoulos MXGEFW_CMD_ERROR_MULTICAST = 9, 4658892ea20SAggelos Economopoulos MXGEFW_CMD_ERROR_UNALIGNED = 10, 4668892ea20SAggelos Economopoulos MXGEFW_CMD_ERROR_NO_MDIO = 11, 4678892ea20SAggelos Economopoulos MXGEFW_CMD_ERROR_I2C_FAILURE = 12, 4688892ea20SAggelos Economopoulos MXGEFW_CMD_ERROR_I2C_ABSENT = 13, 4698892ea20SAggelos Economopoulos MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14 4708892ea20SAggelos Economopoulos }; 4718892ea20SAggelos Economopoulos typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 4728892ea20SAggelos Economopoulos 4738892ea20SAggelos Economopoulos 4748892ea20SAggelos Economopoulos #define MXGEFW_OLD_IRQ_DATA_LEN 40 4758892ea20SAggelos Economopoulos 4768892ea20SAggelos Economopoulos struct mcp_irq_data { 4778892ea20SAggelos Economopoulos /* add new counters at the beginning */ 4788892ea20SAggelos Economopoulos uint32_t future_use[1]; 4798892ea20SAggelos Economopoulos uint32_t dropped_pause; 4808892ea20SAggelos Economopoulos uint32_t dropped_unicast_filtered; 4818892ea20SAggelos Economopoulos uint32_t dropped_bad_crc32; 4828892ea20SAggelos Economopoulos uint32_t dropped_bad_phy; 4838892ea20SAggelos Economopoulos uint32_t dropped_multicast_filtered; 4848892ea20SAggelos Economopoulos /* 40 Bytes */ 4858892ea20SAggelos Economopoulos uint32_t send_done_count; 4868892ea20SAggelos Economopoulos 4878892ea20SAggelos Economopoulos #define MXGEFW_LINK_DOWN 0 4888892ea20SAggelos Economopoulos #define MXGEFW_LINK_UP 1 4898892ea20SAggelos Economopoulos #define MXGEFW_LINK_MYRINET 2 4908892ea20SAggelos Economopoulos #define MXGEFW_LINK_UNKNOWN 3 4918892ea20SAggelos Economopoulos uint32_t link_up; 4928892ea20SAggelos Economopoulos uint32_t dropped_link_overflow; 4938892ea20SAggelos Economopoulos uint32_t dropped_link_error_or_filtered; 4948892ea20SAggelos Economopoulos uint32_t dropped_runt; 4958892ea20SAggelos Economopoulos uint32_t dropped_overrun; 4968892ea20SAggelos Economopoulos uint32_t dropped_no_small_buffer; 4978892ea20SAggelos Economopoulos uint32_t dropped_no_big_buffer; 4988892ea20SAggelos Economopoulos uint32_t rdma_tags_available; 4998892ea20SAggelos Economopoulos 5008892ea20SAggelos Economopoulos uint8_t tx_stopped; 5018892ea20SAggelos Economopoulos uint8_t link_down; 5028892ea20SAggelos Economopoulos uint8_t stats_updated; 5038892ea20SAggelos Economopoulos uint8_t valid; 5048892ea20SAggelos Economopoulos }; 5058892ea20SAggelos Economopoulos typedef struct mcp_irq_data mcp_irq_data_t; 5068892ea20SAggelos Economopoulos 5078892ea20SAggelos Economopoulos #ifdef MXGEFW_NDIS 5088892ea20SAggelos Economopoulos /* Exclusively used by NDIS drivers */ 5098892ea20SAggelos Economopoulos struct mcp_rss_shared_interrupt { 5108892ea20SAggelos Economopoulos uint8_t pad[2]; 5118892ea20SAggelos Economopoulos uint8_t queue; 5128892ea20SAggelos Economopoulos uint8_t valid; 5138892ea20SAggelos Economopoulos }; 5148892ea20SAggelos Economopoulos #endif 5158892ea20SAggelos Economopoulos 5168892ea20SAggelos Economopoulos /* definitions for NETQ filter type */ 5178892ea20SAggelos Economopoulos #define MXGEFW_NETQ_FILTERTYPE_NONE 0 5188892ea20SAggelos Economopoulos #define MXGEFW_NETQ_FILTERTYPE_MACADDR 1 5198892ea20SAggelos Economopoulos #define MXGEFW_NETQ_FILTERTYPE_VLAN 2 5208892ea20SAggelos Economopoulos #define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3 5218892ea20SAggelos Economopoulos 5228892ea20SAggelos Economopoulos #endif /* _myri10ge_mcp_h */ 523