1 /* 2 * Copyright (c) 2002 Myson Technology Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/ 27 * 28 * $FreeBSD: src/sys/dev/my/if_my.c,v 1.2.2.4 2002/04/17 02:05:27 julian Exp $ 29 * $DragonFly: src/sys/dev/netif/my/if_my.c,v 1.24 2005/12/31 14:07:59 sephe Exp $ 30 * 31 * Myson fast ethernet PCI NIC driver 32 * 33 * $Id: if_my.c,v 1.40 2001/11/30 03:55:00 <yen_cw@myson.com.tw> wpaul Exp $ 34 */ 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/serialize.h> 46 47 #include <sys/thread2.h> 48 49 #include <net/if.h> 50 #include <net/ifq_var.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_media.h> 54 #include <net/if_dl.h> 55 #include <net/bpf.h> 56 57 #include <vm/vm.h> /* for vtophys */ 58 #include <vm/pmap.h> /* for vtophys */ 59 #include <machine/clock.h> /* for DELAY */ 60 #include <machine/bus_memio.h> 61 #include <machine/bus_pio.h> 62 #include <machine/bus.h> 63 #include <machine/resource.h> 64 #include <sys/bus.h> 65 #include <sys/rman.h> 66 67 #include <bus/pci/pcireg.h> 68 #include <bus/pci/pcivar.h> 69 70 #include "../mii_layer/mii.h" 71 #include "../mii_layer/miivar.h" 72 73 #include "miibus_if.h" 74 75 /* 76 * #define MY_USEIOSPACE 77 */ 78 79 static int MY_USEIOSPACE = 1; 80 81 #if (MY_USEIOSPACE) 82 #define MY_RES SYS_RES_IOPORT 83 #define MY_RID MY_PCI_LOIO 84 #else 85 #define MY_RES SYS_RES_MEMORY 86 #define MY_RID MY_PCI_LOMEM 87 #endif 88 89 90 #include "if_myreg.h" 91 92 /* 93 * Various supported device vendors/types and their names. 94 */ 95 static struct my_type my_devs[] = { 96 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 97 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 98 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 99 {0, 0, NULL} 100 }; 101 102 /* 103 * Various supported PHY vendors/types and their names. Note that this driver 104 * will work with pretty much any MII-compliant PHY, so failure to positively 105 * identify the chip is not a fatal error. 106 */ 107 static struct my_type my_phys[] = { 108 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 109 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 110 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 111 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 112 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 113 {0, 0, "<MII-compliant physical interface>"} 114 }; 115 116 static int my_probe(device_t); 117 static int my_attach(device_t); 118 static int my_detach(device_t); 119 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 120 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 121 static void my_rxeof(struct my_softc *); 122 static void my_txeof(struct my_softc *); 123 static void my_txeoc(struct my_softc *); 124 static void my_intr(void *); 125 static void my_start(struct ifnet *); 126 static int my_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 127 static void my_init(void *); 128 static void my_stop(struct my_softc *); 129 static void my_watchdog(struct ifnet *); 130 static void my_shutdown(device_t); 131 static int my_ifmedia_upd(struct ifnet *); 132 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 133 static u_int16_t my_phy_readreg(struct my_softc *, int); 134 static void my_phy_writereg(struct my_softc *, int, int); 135 static void my_autoneg_xmit(struct my_softc *); 136 static void my_autoneg_mii(struct my_softc *, int, int); 137 static void my_setmode_mii(struct my_softc *, int); 138 static void my_getmode_mii(struct my_softc *); 139 static void my_setcfg(struct my_softc *, int); 140 static u_int8_t my_calchash(caddr_t); 141 static void my_setmulti(struct my_softc *); 142 static void my_reset(struct my_softc *); 143 static int my_list_rx_init(struct my_softc *); 144 static int my_list_tx_init(struct my_softc *); 145 static long my_send_cmd_to_phy(struct my_softc *, int, int); 146 147 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 148 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 149 150 static device_method_t my_methods[] = { 151 /* Device interface */ 152 DEVMETHOD(device_probe, my_probe), 153 DEVMETHOD(device_attach, my_attach), 154 DEVMETHOD(device_detach, my_detach), 155 DEVMETHOD(device_shutdown, my_shutdown), 156 157 {0, 0} 158 }; 159 160 static driver_t my_driver = { 161 "my", 162 my_methods, 163 sizeof(struct my_softc) 164 }; 165 166 static devclass_t my_devclass; 167 168 DECLARE_DUMMY_MODULE(if_my); 169 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0); 170 171 static long 172 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 173 { 174 long miir; 175 int i; 176 int mask, data; 177 178 /* enable MII output */ 179 miir = CSR_READ_4(sc, MY_MANAGEMENT); 180 miir &= 0xfffffff0; 181 182 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 183 184 /* send 32 1's preamble */ 185 for (i = 0; i < 32; i++) { 186 /* low MDC; MDO is already high (miir) */ 187 miir &= ~MY_MASK_MIIR_MII_MDC; 188 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 189 190 /* high MDC */ 191 miir |= MY_MASK_MIIR_MII_MDC; 192 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 193 } 194 195 /* calculate ST+OP+PHYAD+REGAD+TA */ 196 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 197 198 /* sent out */ 199 mask = 0x8000; 200 while (mask) { 201 /* low MDC, prepare MDO */ 202 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 203 if (mask & data) 204 miir |= MY_MASK_MIIR_MII_MDO; 205 206 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 207 /* high MDC */ 208 miir |= MY_MASK_MIIR_MII_MDC; 209 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 210 DELAY(30); 211 212 /* next */ 213 mask >>= 1; 214 if (mask == 0x2 && opcode == MY_OP_READ) 215 miir &= ~MY_MASK_MIIR_MII_WRITE; 216 } 217 218 return miir; 219 } 220 221 222 static u_int16_t 223 my_phy_readreg(struct my_softc * sc, int reg) 224 { 225 long miir; 226 int mask, data; 227 228 if (sc->my_info->my_did == MTD803ID) 229 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 230 else { 231 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 232 233 /* read data */ 234 mask = 0x8000; 235 data = 0; 236 while (mask) { 237 /* low MDC */ 238 miir &= ~MY_MASK_MIIR_MII_MDC; 239 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 240 241 /* read MDI */ 242 miir = CSR_READ_4(sc, MY_MANAGEMENT); 243 if (miir & MY_MASK_MIIR_MII_MDI) 244 data |= mask; 245 246 /* high MDC, and wait */ 247 miir |= MY_MASK_MIIR_MII_MDC; 248 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 249 DELAY(30); 250 251 /* next */ 252 mask >>= 1; 253 } 254 255 /* low MDC */ 256 miir &= ~MY_MASK_MIIR_MII_MDC; 257 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 258 } 259 260 return (u_int16_t) data; 261 } 262 263 264 static void 265 my_phy_writereg(struct my_softc * sc, int reg, int data) 266 { 267 long miir; 268 int mask; 269 270 if (sc->my_info->my_did == MTD803ID) 271 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 272 else { 273 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 274 275 /* write data */ 276 mask = 0x8000; 277 while (mask) { 278 /* low MDC, prepare MDO */ 279 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 280 if (mask & data) 281 miir |= MY_MASK_MIIR_MII_MDO; 282 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 283 DELAY(1); 284 285 /* high MDC */ 286 miir |= MY_MASK_MIIR_MII_MDC; 287 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 288 DELAY(1); 289 290 /* next */ 291 mask >>= 1; 292 } 293 294 /* low MDC */ 295 miir &= ~MY_MASK_MIIR_MII_MDC; 296 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 297 } 298 } 299 300 static u_int8_t 301 my_calchash(caddr_t addr) 302 { 303 u_int32_t crc, carry; 304 int i, j; 305 u_int8_t c; 306 307 /* Compute CRC for the address value. */ 308 crc = 0xFFFFFFFF; /* initial value */ 309 310 for (i = 0; i < 6; i++) { 311 c = *(addr + i); 312 for (j = 0; j < 8; j++) { 313 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 314 crc <<= 1; 315 c >>= 1; 316 if (carry) 317 crc = (crc ^ 0x04c11db6) | carry; 318 } 319 } 320 321 /* 322 * return the filter bit position Note: I arrived at the following 323 * nonsense through experimentation. It's not the usual way to 324 * generate the bit position but it's the only thing I could come up 325 * with that works. 326 */ 327 return (~(crc >> 26) & 0x0000003F); 328 } 329 330 331 /* 332 * Program the 64-bit multicast hash filter. 333 */ 334 static void 335 my_setmulti(struct my_softc * sc) 336 { 337 struct ifnet *ifp = &sc->arpcom.ac_if; 338 int h = 0; 339 u_int32_t hashes[2] = {0, 0}; 340 struct ifmultiaddr *ifma; 341 u_int32_t rxfilt; 342 int mcnt = 0; 343 344 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 345 346 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 347 rxfilt |= MY_AM; 348 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 349 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 350 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 351 352 return; 353 } 354 /* first, zot all the existing hash bits */ 355 CSR_WRITE_4(sc, MY_MAR0, 0); 356 CSR_WRITE_4(sc, MY_MAR1, 0); 357 358 /* now program new ones */ 359 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 360 if (ifma->ifma_addr->sa_family != AF_LINK) 361 continue; 362 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 363 if (h < 32) 364 hashes[0] |= (1 << h); 365 else 366 hashes[1] |= (1 << (h - 32)); 367 mcnt++; 368 } 369 370 if (mcnt) 371 rxfilt |= MY_AM; 372 else 373 rxfilt &= ~MY_AM; 374 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 375 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 376 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 377 } 378 379 /* 380 * Initiate an autonegotiation session. 381 */ 382 static void 383 my_autoneg_xmit(struct my_softc * sc) 384 { 385 u_int16_t phy_sts = 0; 386 387 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 388 DELAY(500); 389 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 390 391 phy_sts = my_phy_readreg(sc, PHY_BMCR); 392 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 393 my_phy_writereg(sc, PHY_BMCR, phy_sts); 394 } 395 396 397 /* 398 * Invoke autonegotiation on a PHY. 399 */ 400 static void 401 my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 402 { 403 u_int16_t phy_sts = 0, media, advert, ability; 404 u_int16_t ability2 = 0; 405 struct ifnet *ifp = &sc->arpcom.ac_if; 406 struct ifmedia *ifm = &sc->ifmedia; 407 408 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 409 410 #ifndef FORCE_AUTONEG_TFOUR 411 /* 412 * First, see if autoneg is supported. If not, there's no point in 413 * continuing. 414 */ 415 phy_sts = my_phy_readreg(sc, PHY_BMSR); 416 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 417 if (verbose) 418 printf("my%d: autonegotiation not supported\n", 419 sc->my_unit); 420 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 421 return; 422 } 423 #endif 424 switch (flag) { 425 case MY_FLAG_FORCEDELAY: 426 /* 427 * XXX Never use this option anywhere but in the probe 428 * routine: making the kernel stop dead in its tracks for 429 * three whole seconds after we've gone multi-user is really 430 * bad manners. 431 */ 432 my_autoneg_xmit(sc); 433 DELAY(5000000); 434 break; 435 case MY_FLAG_SCHEDDELAY: 436 /* 437 * Wait for the transmitter to go idle before starting an 438 * autoneg session, otherwise my_start() may clobber our 439 * timeout, and we don't want to allow transmission during an 440 * autoneg session since that can screw it up. 441 */ 442 if (sc->my_cdata.my_tx_head != NULL) { 443 sc->my_want_auto = 1; 444 return; 445 } 446 my_autoneg_xmit(sc); 447 ifp->if_timer = 5; 448 sc->my_autoneg = 1; 449 sc->my_want_auto = 0; 450 return; 451 case MY_FLAG_DELAYTIMEO: 452 ifp->if_timer = 0; 453 sc->my_autoneg = 0; 454 break; 455 default: 456 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 457 return; 458 } 459 460 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 461 if (verbose) 462 printf("my%d: autoneg complete, ", sc->my_unit); 463 phy_sts = my_phy_readreg(sc, PHY_BMSR); 464 } else { 465 if (verbose) 466 printf("my%d: autoneg not complete, ", sc->my_unit); 467 } 468 469 media = my_phy_readreg(sc, PHY_BMCR); 470 471 /* Link is good. Report modes and set duplex mode. */ 472 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 473 if (verbose) 474 printf("my%d: link status good. ", sc->my_unit); 475 advert = my_phy_readreg(sc, PHY_ANAR); 476 ability = my_phy_readreg(sc, PHY_LPAR); 477 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 478 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 479 ability2 = my_phy_readreg(sc, PHY_1000SR); 480 if (ability2 & PHY_1000SR_1000BTXFULL) { 481 advert = 0; 482 ability = 0; 483 /* 484 * this version did not support 1000M, 485 * ifm->ifm_media = 486 * IFM_ETHER | IFM_1000_T | IFM_FDX; 487 */ 488 ifm->ifm_media = 489 IFM_ETHER | IFM_100_TX | IFM_FDX; 490 media &= ~PHY_BMCR_SPEEDSEL; 491 media |= PHY_BMCR_1000; 492 media |= PHY_BMCR_DUPLEX; 493 printf("(full-duplex, 1000Mbps)\n"); 494 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 495 advert = 0; 496 ability = 0; 497 /* 498 * this version did not support 1000M, 499 * ifm->ifm_media = IFM_ETHER | IFM_1000_T; 500 */ 501 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 502 media &= ~PHY_BMCR_SPEEDSEL; 503 media &= ~PHY_BMCR_DUPLEX; 504 media |= PHY_BMCR_1000; 505 printf("(half-duplex, 1000Mbps)\n"); 506 } 507 } 508 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 509 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 510 media |= PHY_BMCR_SPEEDSEL; 511 media &= ~PHY_BMCR_DUPLEX; 512 printf("(100baseT4)\n"); 513 } else if (advert & PHY_ANAR_100BTXFULL && 514 ability & PHY_ANAR_100BTXFULL) { 515 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 516 media |= PHY_BMCR_SPEEDSEL; 517 media |= PHY_BMCR_DUPLEX; 518 printf("(full-duplex, 100Mbps)\n"); 519 } else if (advert & PHY_ANAR_100BTXHALF && 520 ability & PHY_ANAR_100BTXHALF) { 521 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 522 media |= PHY_BMCR_SPEEDSEL; 523 media &= ~PHY_BMCR_DUPLEX; 524 printf("(half-duplex, 100Mbps)\n"); 525 } else if (advert & PHY_ANAR_10BTFULL && 526 ability & PHY_ANAR_10BTFULL) { 527 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 528 media &= ~PHY_BMCR_SPEEDSEL; 529 media |= PHY_BMCR_DUPLEX; 530 printf("(full-duplex, 10Mbps)\n"); 531 } else if (advert) { 532 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 533 media &= ~PHY_BMCR_SPEEDSEL; 534 media &= ~PHY_BMCR_DUPLEX; 535 printf("(half-duplex, 10Mbps)\n"); 536 } 537 media &= ~PHY_BMCR_AUTONEGENBL; 538 539 /* Set ASIC's duplex mode to match the PHY. */ 540 my_phy_writereg(sc, PHY_BMCR, media); 541 my_setcfg(sc, media); 542 } else { 543 if (verbose) 544 printf("my%d: no carrier\n", sc->my_unit); 545 } 546 547 my_init(sc); 548 if (sc->my_tx_pend) { 549 sc->my_autoneg = 0; 550 sc->my_tx_pend = 0; 551 my_start(ifp); 552 } 553 } 554 555 /* 556 * To get PHY ability. 557 */ 558 static void 559 my_getmode_mii(struct my_softc * sc) 560 { 561 struct ifnet *ifp = &sc->arpcom.ac_if; 562 u_int16_t bmsr; 563 564 bmsr = my_phy_readreg(sc, PHY_BMSR); 565 if (bootverbose) 566 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 567 568 /* fallback */ 569 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 570 571 if (bmsr & PHY_BMSR_10BTHALF) { 572 if (bootverbose) 573 printf("my%d: 10Mbps half-duplex mode supported\n", 574 sc->my_unit); 575 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 576 0, NULL); 577 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 578 } 579 if (bmsr & PHY_BMSR_10BTFULL) { 580 if (bootverbose) 581 printf("my%d: 10Mbps full-duplex mode supported\n", 582 sc->my_unit); 583 584 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 585 0, NULL); 586 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 587 } 588 if (bmsr & PHY_BMSR_100BTXHALF) { 589 if (bootverbose) 590 printf("my%d: 100Mbps half-duplex mode supported\n", 591 sc->my_unit); 592 ifp->if_baudrate = 100000000; 593 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 594 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 595 0, NULL); 596 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 597 } 598 if (bmsr & PHY_BMSR_100BTXFULL) { 599 if (bootverbose) 600 printf("my%d: 100Mbps full-duplex mode supported\n", 601 sc->my_unit); 602 ifp->if_baudrate = 100000000; 603 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 604 0, NULL); 605 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 606 } 607 /* Some also support 100BaseT4. */ 608 if (bmsr & PHY_BMSR_100BT4) { 609 if (bootverbose) 610 printf("my%d: 100baseT4 mode supported\n", sc->my_unit); 611 ifp->if_baudrate = 100000000; 612 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 613 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 614 #ifdef FORCE_AUTONEG_TFOUR 615 if (bootverbose) 616 printf("my%d: forcing on autoneg support for BT4\n", 617 sc->my_unit); 618 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 619 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 620 #endif 621 } 622 #if 0 /* this version did not support 1000M, */ 623 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 624 if (bootverbose) 625 printf("my%d: 1000Mbps half-duplex mode supported\n", 626 sc->my_unit); 627 628 ifp->if_baudrate = 1000000000; 629 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 630 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 631 0, NULL); 632 if (bootverbose) 633 printf("my%d: 1000Mbps full-duplex mode supported\n", 634 sc->my_unit); 635 ifp->if_baudrate = 1000000000; 636 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 637 0, NULL); 638 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 639 } 640 #endif 641 if (bmsr & PHY_BMSR_CANAUTONEG) { 642 if (bootverbose) 643 printf("my%d: autoneg supported\n", sc->my_unit); 644 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 645 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 646 } 647 } 648 649 /* 650 * Set speed and duplex mode. 651 */ 652 static void 653 my_setmode_mii(struct my_softc * sc, int media) 654 { 655 struct ifnet *ifp = &sc->arpcom.ac_if; 656 u_int16_t bmcr; 657 658 /* 659 * If an autoneg session is in progress, stop it. 660 */ 661 if (sc->my_autoneg) { 662 printf("my%d: canceling autoneg session\n", sc->my_unit); 663 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 664 bmcr = my_phy_readreg(sc, PHY_BMCR); 665 bmcr &= ~PHY_BMCR_AUTONEGENBL; 666 my_phy_writereg(sc, PHY_BMCR, bmcr); 667 } 668 printf("my%d: selecting MII, ", sc->my_unit); 669 bmcr = my_phy_readreg(sc, PHY_BMCR); 670 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 671 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 672 673 #if 0 /* this version did not support 1000M, */ 674 if (IFM_SUBTYPE(media) == IFM_1000_T) { 675 printf("1000Mbps/T4, half-duplex\n"); 676 bmcr &= ~PHY_BMCR_SPEEDSEL; 677 bmcr &= ~PHY_BMCR_DUPLEX; 678 bmcr |= PHY_BMCR_1000; 679 } 680 #endif 681 if (IFM_SUBTYPE(media) == IFM_100_T4) { 682 printf("100Mbps/T4, half-duplex\n"); 683 bmcr |= PHY_BMCR_SPEEDSEL; 684 bmcr &= ~PHY_BMCR_DUPLEX; 685 } 686 if (IFM_SUBTYPE(media) == IFM_100_TX) { 687 printf("100Mbps, "); 688 bmcr |= PHY_BMCR_SPEEDSEL; 689 } 690 if (IFM_SUBTYPE(media) == IFM_10_T) { 691 printf("10Mbps, "); 692 bmcr &= ~PHY_BMCR_SPEEDSEL; 693 } 694 if ((media & IFM_GMASK) == IFM_FDX) { 695 printf("full duplex\n"); 696 bmcr |= PHY_BMCR_DUPLEX; 697 } else { 698 printf("half duplex\n"); 699 bmcr &= ~PHY_BMCR_DUPLEX; 700 } 701 my_phy_writereg(sc, PHY_BMCR, bmcr); 702 my_setcfg(sc, bmcr); 703 } 704 705 /* 706 * The Myson manual states that in order to fiddle with the 'full-duplex' and 707 * '100Mbps' bits in the netconfig register, we first have to put the 708 * transmit and/or receive logic in the idle state. 709 */ 710 static void 711 my_setcfg(struct my_softc * sc, int bmcr) 712 { 713 int i, restart = 0; 714 715 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 716 restart = 1; 717 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 718 for (i = 0; i < MY_TIMEOUT; i++) { 719 DELAY(10); 720 if (!(CSR_READ_4(sc, MY_TCRRCR) & 721 (MY_TXRUN | MY_RXRUN))) 722 break; 723 } 724 if (i == MY_TIMEOUT) 725 printf("my%d: failed to force tx and rx to idle \n", 726 sc->my_unit); 727 } 728 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 729 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 730 if (bmcr & PHY_BMCR_1000) 731 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 732 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 733 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 734 if (bmcr & PHY_BMCR_DUPLEX) 735 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 736 else 737 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 738 if (restart) 739 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 740 } 741 742 static void 743 my_reset(struct my_softc * sc) 744 { 745 int i; 746 747 MY_SETBIT(sc, MY_BCR, MY_SWR); 748 for (i = 0; i < MY_TIMEOUT; i++) { 749 DELAY(10); 750 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 751 break; 752 } 753 if (i == MY_TIMEOUT) 754 printf("m0x%d: reset never completed!\n", sc->my_unit); 755 756 /* Wait a little while for the chip to get its brains in order. */ 757 DELAY(1000); 758 } 759 760 /* 761 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 762 * list and return a device name if we find a match. 763 */ 764 static int 765 my_probe(device_t dev) 766 { 767 struct my_type *t; 768 uint16_t vendor, product; 769 770 vendor = pci_get_vendor(dev); 771 product = pci_get_device(dev); 772 773 for (t = my_devs; t->my_name != NULL; t++) { 774 if (vendor == t->my_vid && product == t->my_did) { 775 device_set_desc(dev, t->my_name); 776 return (0); 777 } 778 } 779 780 return (ENXIO); 781 } 782 783 /* 784 * Attach the interface. Allocate softc structures, do ifmedia setup and 785 * ethernet/BPF attach. 786 */ 787 static int 788 my_attach(device_t dev) 789 { 790 int i; 791 u_char eaddr[ETHER_ADDR_LEN]; 792 u_int32_t command, iobase; 793 struct my_softc *sc; 794 struct ifnet *ifp; 795 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 796 unsigned int round; 797 caddr_t roundptr; 798 struct my_type *p; 799 u_int16_t phy_vid, phy_did, phy_sts = 0; 800 int rid, unit, error = 0; 801 struct my_type *t; 802 uint16_t vendor, product; 803 804 vendor = pci_get_vendor(dev); 805 product = pci_get_device(dev); 806 807 for (t = my_devs; t->my_name != NULL; t++) { 808 if (vendor == t->my_vid && product == t->my_did) 809 break; 810 } 811 812 if (t->my_name == NULL) 813 return(ENXIO); 814 815 sc = device_get_softc(dev); 816 unit = device_get_unit(dev); 817 818 /* 819 * Map control/status registers. 820 */ 821 command = pci_read_config(dev, PCIR_COMMAND, 4); 822 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 823 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 824 command = pci_read_config(dev, PCIR_COMMAND, 4); 825 826 if (t->my_did == MTD800ID) { 827 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 828 if (iobase & 0x300) 829 MY_USEIOSPACE = 0; 830 } 831 if (MY_USEIOSPACE) { 832 if (!(command & PCIM_CMD_PORTEN)) { 833 printf("my%d: failed to enable I/O ports!\n", unit); 834 error = ENXIO; 835 return(error); 836 } 837 } else { 838 if (!(command & PCIM_CMD_MEMEN)) { 839 printf("my%d: failed to enable memory mapping!\n", 840 unit); 841 error = ENXIO; 842 return(error); 843 } 844 } 845 846 rid = MY_RID; 847 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE); 848 849 if (sc->my_res == NULL) { 850 printf("my%d: couldn't map ports/memory\n", unit); 851 error = ENXIO; 852 goto fail; 853 } 854 sc->my_btag = rman_get_bustag(sc->my_res); 855 sc->my_bhandle = rman_get_bushandle(sc->my_res); 856 857 rid = 0; 858 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 859 RF_SHAREABLE | RF_ACTIVE); 860 861 if (sc->my_irq == NULL) { 862 printf("my%d: couldn't map interrupt\n", unit); 863 error = ENXIO; 864 goto fail; 865 } 866 867 sc->my_info = t; 868 869 /* Reset the adapter. */ 870 my_reset(sc); 871 872 /* 873 * Get station address 874 */ 875 for (i = 0; i < ETHER_ADDR_LEN; ++i) 876 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 877 878 sc->my_unit = unit; 879 880 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 881 M_DEVBUF, M_WAITOK); 882 if (sc->my_ldata_ptr == NULL) { 883 printf("my%d: no memory for list buffers!\n", unit); 884 error = ENXIO; 885 goto fail; 886 } 887 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 888 round = (unsigned int)sc->my_ldata_ptr & 0xF; 889 roundptr = sc->my_ldata_ptr; 890 for (i = 0; i < 8; i++) { 891 if (round % 8) { 892 round++; 893 roundptr++; 894 } else 895 break; 896 } 897 sc->my_ldata = (struct my_list_data *) roundptr; 898 bzero(sc->my_ldata, sizeof(struct my_list_data)); 899 900 ifp = &sc->arpcom.ac_if; 901 ifp->if_softc = sc; 902 if_initname(ifp, "my", unit); 903 ifp->if_mtu = ETHERMTU; 904 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 905 ifp->if_ioctl = my_ioctl; 906 ifp->if_start = my_start; 907 ifp->if_watchdog = my_watchdog; 908 ifp->if_init = my_init; 909 ifp->if_baudrate = 10000000; 910 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 911 ifq_set_ready(&ifp->if_snd); 912 913 if (sc->my_info->my_did == MTD803ID) 914 sc->my_pinfo = my_phys; 915 else { 916 if (bootverbose) 917 printf("my%d: probing for a PHY\n", sc->my_unit); 918 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 919 if (bootverbose) 920 printf("my%d: checking address: %d\n", 921 sc->my_unit, i); 922 sc->my_phy_addr = i; 923 phy_sts = my_phy_readreg(sc, PHY_BMSR); 924 if ((phy_sts != 0) && (phy_sts != 0xffff)) 925 break; 926 else 927 phy_sts = 0; 928 } 929 if (phy_sts) { 930 phy_vid = my_phy_readreg(sc, PHY_VENID); 931 phy_did = my_phy_readreg(sc, PHY_DEVID); 932 if (bootverbose) { 933 printf("my%d: found PHY at address %d, ", 934 sc->my_unit, sc->my_phy_addr); 935 printf("vendor id: %x device id: %x\n", 936 phy_vid, phy_did); 937 } 938 p = my_phys; 939 while (p->my_vid) { 940 if (phy_vid == p->my_vid) { 941 sc->my_pinfo = p; 942 break; 943 } 944 p++; 945 } 946 if (sc->my_pinfo == NULL) 947 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 948 if (bootverbose) 949 printf("my%d: PHY type: %s\n", 950 sc->my_unit, sc->my_pinfo->my_name); 951 } else { 952 printf("my%d: MII without any phy!\n", sc->my_unit); 953 error = ENXIO; 954 goto fail; 955 } 956 } 957 958 /* Do ifmedia setup. */ 959 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 960 my_getmode_mii(sc); 961 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 962 media = sc->ifmedia.ifm_media; 963 my_stop(sc); 964 ifmedia_set(&sc->ifmedia, media); 965 966 ether_ifattach(ifp, eaddr, NULL); 967 968 error = bus_setup_intr(dev, sc->my_irq, INTR_NETSAFE, 969 my_intr, sc, &sc->my_intrhand, 970 ifp->if_serializer); 971 if (error) { 972 ether_ifdetach(ifp); 973 printf("my%d: couldn't set up irq\n", unit); 974 goto fail; 975 } 976 977 return (0); 978 979 fail: 980 my_detach(dev); 981 return (error); 982 } 983 984 static int 985 my_detach(device_t dev) 986 { 987 struct my_softc *sc = device_get_softc(dev); 988 struct ifnet *ifp = &sc->arpcom.ac_if; 989 990 if (device_is_attached(dev)) { 991 lwkt_serialize_enter(ifp->if_serializer); 992 my_stop(sc); 993 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 994 lwkt_serialize_exit(ifp->if_serializer); 995 996 ether_ifdetach(ifp); 997 } 998 999 if (sc->my_irq) 1000 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 1001 if (sc->my_res) 1002 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 1003 1004 return (0); 1005 } 1006 1007 1008 /* 1009 * Initialize the transmit descriptors. 1010 */ 1011 static int 1012 my_list_tx_init(struct my_softc * sc) 1013 { 1014 struct my_chain_data *cd; 1015 struct my_list_data *ld; 1016 int i; 1017 1018 cd = &sc->my_cdata; 1019 ld = sc->my_ldata; 1020 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1021 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1022 if (i == (MY_TX_LIST_CNT - 1)) 1023 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1024 else 1025 cd->my_tx_chain[i].my_nextdesc = 1026 &cd->my_tx_chain[i + 1]; 1027 } 1028 cd->my_tx_free = &cd->my_tx_chain[0]; 1029 cd->my_tx_tail = cd->my_tx_head = NULL; 1030 return (0); 1031 } 1032 1033 /* 1034 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1035 * arrange the descriptors in a closed ring, so that the last descriptor 1036 * points back to the first. 1037 */ 1038 static int 1039 my_list_rx_init(struct my_softc * sc) 1040 { 1041 struct my_chain_data *cd; 1042 struct my_list_data *ld; 1043 int i; 1044 1045 cd = &sc->my_cdata; 1046 ld = sc->my_ldata; 1047 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1048 cd->my_rx_chain[i].my_ptr = 1049 (struct my_desc *) & ld->my_rx_list[i]; 1050 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) 1051 return (ENOBUFS); 1052 if (i == (MY_RX_LIST_CNT - 1)) { 1053 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1054 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1055 } else { 1056 cd->my_rx_chain[i].my_nextdesc = 1057 &cd->my_rx_chain[i + 1]; 1058 ld->my_rx_list[i].my_next = 1059 vtophys(&ld->my_rx_list[i + 1]); 1060 } 1061 } 1062 cd->my_rx_head = &cd->my_rx_chain[0]; 1063 return (0); 1064 } 1065 1066 /* 1067 * Initialize an RX descriptor and attach an MBUF cluster. 1068 */ 1069 static int 1070 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1071 { 1072 struct mbuf *m_new = NULL; 1073 1074 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1075 if (m_new == NULL) { 1076 printf("my%d: no memory for rx list -- packet dropped!\n", 1077 sc->my_unit); 1078 return (ENOBUFS); 1079 } 1080 MCLGET(m_new, MB_DONTWAIT); 1081 if (!(m_new->m_flags & M_EXT)) { 1082 printf("my%d: no memory for rx list -- packet dropped!\n", 1083 sc->my_unit); 1084 m_freem(m_new); 1085 return (ENOBUFS); 1086 } 1087 c->my_mbuf = m_new; 1088 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1089 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1090 c->my_ptr->my_status = MY_OWNByNIC; 1091 return (0); 1092 } 1093 1094 /* 1095 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1096 * level protocols. 1097 */ 1098 static void 1099 my_rxeof(struct my_softc * sc) 1100 { 1101 struct mbuf *m; 1102 struct ifnet *ifp = &sc->arpcom.ac_if; 1103 struct my_chain_onefrag *cur_rx; 1104 int total_len = 0; 1105 u_int32_t rxstat; 1106 1107 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1108 & MY_OWNByNIC)) { 1109 cur_rx = sc->my_cdata.my_rx_head; 1110 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1111 1112 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1113 ifp->if_ierrors++; 1114 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1115 continue; 1116 } 1117 /* No errors; receive the packet. */ 1118 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1119 total_len -= ETHER_CRC_LEN; 1120 1121 if (total_len < MINCLSIZE) { 1122 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1123 total_len, 0, ifp, NULL); 1124 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1125 if (m == NULL) { 1126 ifp->if_ierrors++; 1127 continue; 1128 } 1129 } else { 1130 m = cur_rx->my_mbuf; 1131 /* 1132 * Try to conjure up a new mbuf cluster. If that 1133 * fails, it means we have an out of memory condition 1134 * and should leave the buffer in place and continue. 1135 * This will result in a lost packet, but there's 1136 * little else we can do in this situation. 1137 */ 1138 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1139 ifp->if_ierrors++; 1140 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1141 continue; 1142 } 1143 m->m_pkthdr.rcvif = ifp; 1144 m->m_pkthdr.len = m->m_len = total_len; 1145 } 1146 ifp->if_ipackets++; 1147 ifp->if_input(ifp, m); 1148 } 1149 } 1150 1151 1152 /* 1153 * A frame was downloaded to the chip. It's safe for us to clean up the list 1154 * buffers. 1155 */ 1156 static void 1157 my_txeof(struct my_softc * sc) 1158 { 1159 struct ifnet *ifp = &sc->arpcom.ac_if; 1160 struct my_chain *cur_tx; 1161 1162 /* Clear the timeout timer. */ 1163 ifp->if_timer = 0; 1164 if (sc->my_cdata.my_tx_head == NULL) 1165 return; 1166 /* 1167 * Go through our tx list and free mbufs for those frames that have 1168 * been transmitted. 1169 */ 1170 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1171 u_int32_t txstat; 1172 1173 cur_tx = sc->my_cdata.my_tx_head; 1174 txstat = MY_TXSTATUS(cur_tx); 1175 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1176 break; 1177 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1178 if (txstat & MY_TXERR) { 1179 ifp->if_oerrors++; 1180 if (txstat & MY_EC) /* excessive collision */ 1181 ifp->if_collisions++; 1182 if (txstat & MY_LC) /* late collision */ 1183 ifp->if_collisions++; 1184 } 1185 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1186 MY_NCRShift; 1187 } 1188 ifp->if_opackets++; 1189 m_freem(cur_tx->my_mbuf); 1190 cur_tx->my_mbuf = NULL; 1191 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1192 sc->my_cdata.my_tx_head = NULL; 1193 sc->my_cdata.my_tx_tail = NULL; 1194 break; 1195 } 1196 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1197 } 1198 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1199 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1200 } 1201 } 1202 1203 /* 1204 * TX 'end of channel' interrupt handler. 1205 */ 1206 static void 1207 my_txeoc(struct my_softc * sc) 1208 { 1209 struct ifnet *ifp = &sc->arpcom.ac_if; 1210 1211 ifp->if_timer = 0; 1212 if (sc->my_cdata.my_tx_head == NULL) { 1213 ifp->if_flags &= ~IFF_OACTIVE; 1214 sc->my_cdata.my_tx_tail = NULL; 1215 if (sc->my_want_auto) 1216 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1217 } else { 1218 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1219 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1220 ifp->if_timer = 5; 1221 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1222 } 1223 } 1224 } 1225 1226 static void 1227 my_intr(void *arg) 1228 { 1229 struct my_softc *sc = arg; 1230 struct ifnet *ifp = &sc->arpcom.ac_if; 1231 u_int32_t status; 1232 1233 if (!(ifp->if_flags & IFF_UP)) 1234 return; 1235 1236 /* Disable interrupts. */ 1237 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1238 1239 for (;;) { 1240 status = CSR_READ_4(sc, MY_ISR); 1241 status &= MY_INTRS; 1242 if (status) 1243 CSR_WRITE_4(sc, MY_ISR, status); 1244 else 1245 break; 1246 1247 if (status & MY_RI) /* receive interrupt */ 1248 my_rxeof(sc); 1249 1250 if ((status & MY_RBU) || (status & MY_RxErr)) { 1251 /* rx buffer unavailable or rx error */ 1252 ifp->if_ierrors++; 1253 #ifdef foo 1254 my_stop(sc); 1255 my_reset(sc); 1256 my_init(sc); 1257 #endif 1258 } 1259 if (status & MY_TI) /* tx interrupt */ 1260 my_txeof(sc); 1261 if (status & MY_ETI) /* tx early interrupt */ 1262 my_txeof(sc); 1263 if (status & MY_TBU) /* tx buffer unavailable */ 1264 my_txeoc(sc); 1265 1266 #if 0 /* 90/1/18 delete */ 1267 if (status & MY_FBE) { 1268 my_reset(sc); 1269 my_init(sc); 1270 } 1271 #endif 1272 1273 } 1274 1275 /* Re-enable interrupts. */ 1276 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1277 if (!ifq_is_empty(&ifp->if_snd)) 1278 my_start(ifp); 1279 } 1280 1281 /* 1282 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1283 * pointers to the fragment pointers. 1284 */ 1285 static int 1286 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1287 { 1288 struct my_desc *f = NULL; 1289 int total_len; 1290 struct mbuf *m, *m_new = NULL; 1291 1292 /* calculate the total tx pkt length */ 1293 total_len = 0; 1294 for (m = m_head; m != NULL; m = m->m_next) 1295 total_len += m->m_len; 1296 /* 1297 * Start packing the mbufs in this chain into the fragment pointers. 1298 * Stop when we run out of fragments or hit the end of the mbuf 1299 * chain. 1300 */ 1301 m = m_head; 1302 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1303 if (m_new == NULL) { 1304 printf("my%d: no memory for tx list", sc->my_unit); 1305 return (1); 1306 } 1307 if (m_head->m_pkthdr.len > MHLEN) { 1308 MCLGET(m_new, MB_DONTWAIT); 1309 if (!(m_new->m_flags & M_EXT)) { 1310 m_freem(m_new); 1311 printf("my%d: no memory for tx list", sc->my_unit); 1312 return (1); 1313 } 1314 } 1315 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1316 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1317 m_freem(m_head); 1318 m_head = m_new; 1319 f = &c->my_ptr->my_frag[0]; 1320 f->my_status = 0; 1321 f->my_data = vtophys(mtod(m_new, caddr_t)); 1322 total_len = m_new->m_len; 1323 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1324 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1325 f->my_ctl |= total_len; /* buffer size */ 1326 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1327 if (sc->my_info->my_did == MTD891ID) 1328 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1329 c->my_mbuf = m_head; 1330 c->my_lastdesc = 0; 1331 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1332 return (0); 1333 } 1334 1335 /* 1336 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1337 * to the mbuf data regions directly in the transmit lists. We also save a 1338 * copy of the pointers since the transmit list fragment pointers are 1339 * physical addresses. 1340 */ 1341 static void 1342 my_start(struct ifnet * ifp) 1343 { 1344 struct my_softc *sc = ifp->if_softc; 1345 struct mbuf *m_head = NULL; 1346 struct my_chain *cur_tx = NULL, *start_tx; 1347 1348 crit_enter(); 1349 1350 if (sc->my_autoneg) { 1351 sc->my_tx_pend = 1; 1352 crit_exit(); 1353 return; 1354 } 1355 /* 1356 * Check for an available queue slot. If there are none, punt. 1357 */ 1358 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1359 ifp->if_flags |= IFF_OACTIVE; 1360 crit_exit(); 1361 return; 1362 } 1363 1364 start_tx = sc->my_cdata.my_tx_free; 1365 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1366 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1367 if (m_head == NULL) 1368 break; 1369 1370 /* Pick a descriptor off the free list. */ 1371 cur_tx = sc->my_cdata.my_tx_free; 1372 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1373 1374 /* Pack the data into the descriptor. */ 1375 my_encap(sc, cur_tx, m_head); 1376 1377 if (cur_tx != start_tx) 1378 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1379 BPF_MTAP(ifp, cur_tx->my_mbuf); 1380 } 1381 /* 1382 * If there are no packets queued, bail. 1383 */ 1384 if (cur_tx == NULL) { 1385 crit_exit(); 1386 return; 1387 } 1388 /* 1389 * Place the request for the upload interrupt in the last descriptor 1390 * in the chain. This way, if we're chaining several packets at once, 1391 * we'll only get an interupt once for the whole chain rather than 1392 * once for each packet. 1393 */ 1394 MY_TXCTL(cur_tx) |= MY_TXIC; 1395 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1396 sc->my_cdata.my_tx_tail = cur_tx; 1397 if (sc->my_cdata.my_tx_head == NULL) 1398 sc->my_cdata.my_tx_head = start_tx; 1399 MY_TXOWN(start_tx) = MY_OWNByNIC; 1400 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1401 1402 /* 1403 * Set a timeout in case the chip goes out to lunch. 1404 */ 1405 ifp->if_timer = 5; 1406 1407 crit_exit(); 1408 } 1409 1410 static void 1411 my_init(void *xsc) 1412 { 1413 struct my_softc *sc = xsc; 1414 struct ifnet *ifp = &sc->arpcom.ac_if; 1415 u_int16_t phy_bmcr = 0; 1416 1417 crit_enter(); 1418 if (sc->my_autoneg) { 1419 crit_exit(); 1420 return; 1421 } 1422 if (sc->my_pinfo != NULL) 1423 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1424 /* 1425 * Cancel pending I/O and free all RX/TX buffers. 1426 */ 1427 my_stop(sc); 1428 my_reset(sc); 1429 1430 /* 1431 * Set cache alignment and burst length. 1432 */ 1433 #if 0 /* 89/9/1 modify, */ 1434 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1435 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1436 #endif 1437 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1438 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1439 /* 1440 * 89/12/29 add, for mtd891, 1441 */ 1442 if (sc->my_info->my_did == MTD891ID) { 1443 MY_SETBIT(sc, MY_BCR, MY_PROG); 1444 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1445 } 1446 my_setcfg(sc, phy_bmcr); 1447 /* Init circular RX list. */ 1448 if (my_list_rx_init(sc) == ENOBUFS) { 1449 printf("my%d: init failed: no memory for rx buffers\n", 1450 sc->my_unit); 1451 my_stop(sc); 1452 crit_exit(); 1453 return; 1454 } 1455 /* Init TX descriptors. */ 1456 my_list_tx_init(sc); 1457 1458 /* If we want promiscuous mode, set the allframes bit. */ 1459 if (ifp->if_flags & IFF_PROMISC) 1460 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1461 else 1462 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1463 1464 /* 1465 * Set capture broadcast bit to capture broadcast frames. 1466 */ 1467 if (ifp->if_flags & IFF_BROADCAST) 1468 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1469 else 1470 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1471 1472 /* 1473 * Program the multicast filter, if necessary. 1474 */ 1475 my_setmulti(sc); 1476 1477 /* 1478 * Load the address of the RX list. 1479 */ 1480 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1481 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1482 1483 /* 1484 * Enable interrupts. 1485 */ 1486 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1487 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1488 1489 /* Enable receiver and transmitter. */ 1490 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1491 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1492 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1493 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1494 1495 /* Restore state of BMCR */ 1496 if (sc->my_pinfo != NULL) 1497 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1498 ifp->if_flags |= IFF_RUNNING; 1499 ifp->if_flags &= ~IFF_OACTIVE; 1500 crit_exit(); 1501 } 1502 1503 /* 1504 * Set media options. 1505 */ 1506 1507 static int 1508 my_ifmedia_upd(struct ifnet * ifp) 1509 { 1510 struct my_softc *sc = ifp->if_softc; 1511 struct ifmedia *ifm = &sc->ifmedia; 1512 1513 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1514 return (EINVAL); 1515 1516 crit_enter(); 1517 1518 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1519 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1520 else 1521 my_setmode_mii(sc, ifm->ifm_media); 1522 1523 crit_exit(); 1524 1525 return (0); 1526 } 1527 1528 /* 1529 * Report current media status. 1530 */ 1531 1532 static void 1533 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1534 { 1535 struct my_softc *sc = ifp->if_softc; 1536 u_int16_t advert = 0, ability = 0; 1537 1538 crit_enter(); 1539 1540 ifmr->ifm_active = IFM_ETHER; 1541 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1542 #if 0 /* this version did not support 1000M, */ 1543 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1544 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1545 #endif 1546 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1547 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1548 else 1549 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1550 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1551 ifmr->ifm_active |= IFM_FDX; 1552 else 1553 ifmr->ifm_active |= IFM_HDX; 1554 1555 crit_exit(); 1556 1557 return; 1558 } 1559 ability = my_phy_readreg(sc, PHY_LPAR); 1560 advert = my_phy_readreg(sc, PHY_ANAR); 1561 1562 #if 0 /* this version did not support 1000M, */ 1563 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1564 ability2 = my_phy_readreg(sc, PHY_1000SR); 1565 if (ability2 & PHY_1000SR_1000BTXFULL) { 1566 advert = 0; 1567 ability = 0; 1568 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_FDX; 1569 } else if (ability & PHY_1000SR_1000BTXHALF) { 1570 advert = 0; 1571 ability = 0; 1572 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_HDX; 1573 } 1574 } 1575 #endif 1576 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1577 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1578 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1579 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1580 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1581 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1582 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1583 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1584 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1585 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1586 1587 crit_exit(); 1588 } 1589 1590 static int 1591 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data, struct ucred *cr) 1592 { 1593 struct my_softc *sc = ifp->if_softc; 1594 struct ifreq *ifr = (struct ifreq *) data; 1595 int error = 0; 1596 1597 crit_enter(); 1598 switch (command) { 1599 case SIOCSIFFLAGS: 1600 if (ifp->if_flags & IFF_UP) 1601 my_init(sc); 1602 else if (ifp->if_flags & IFF_RUNNING) 1603 my_stop(sc); 1604 error = 0; 1605 break; 1606 case SIOCADDMULTI: 1607 case SIOCDELMULTI: 1608 my_setmulti(sc); 1609 error = 0; 1610 break; 1611 case SIOCGIFMEDIA: 1612 case SIOCSIFMEDIA: 1613 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1614 break; 1615 default: 1616 error = ether_ioctl(ifp, command, data); 1617 break; 1618 } 1619 1620 crit_exit(); 1621 return (error); 1622 } 1623 1624 static void 1625 my_watchdog(struct ifnet * ifp) 1626 { 1627 struct my_softc *sc = ifp->if_softc; 1628 1629 crit_enter(); 1630 1631 if (sc->my_autoneg) { 1632 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1633 crit_exit(); 1634 return; 1635 } 1636 ifp->if_oerrors++; 1637 printf("my%d: watchdog timeout\n", sc->my_unit); 1638 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1639 printf("my%d: no carrier - transceiver cable problem?\n", 1640 sc->my_unit); 1641 my_stop(sc); 1642 my_reset(sc); 1643 my_init(sc); 1644 if (!ifq_is_empty(&ifp->if_snd)) 1645 my_start(ifp); 1646 crit_exit(); 1647 } 1648 1649 1650 /* 1651 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1652 */ 1653 static void 1654 my_stop(struct my_softc * sc) 1655 { 1656 struct ifnet *ifp = &sc->arpcom.ac_if; 1657 int i; 1658 1659 ifp->if_timer = 0; 1660 1661 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1662 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1663 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1664 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1665 1666 /* 1667 * Free data in the RX lists. 1668 */ 1669 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1670 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1671 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1672 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1673 } 1674 } 1675 bzero((char *)&sc->my_ldata->my_rx_list, 1676 sizeof(sc->my_ldata->my_rx_list)); 1677 /* 1678 * Free the TX list buffers. 1679 */ 1680 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1681 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1682 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1683 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1684 } 1685 } 1686 bzero((char *)&sc->my_ldata->my_tx_list, 1687 sizeof(sc->my_ldata->my_tx_list)); 1688 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1689 } 1690 1691 /* 1692 * Stop all chip I/O so that the kernel's probe routines don't get confused 1693 * by errant DMAs when rebooting. 1694 */ 1695 static void 1696 my_shutdown(device_t dev) 1697 { 1698 struct my_softc *sc; 1699 1700 sc = device_get_softc(dev); 1701 my_stop(sc); 1702 return; 1703 } 1704