1 /* 2 * Copyright (c) 2002 Myson Technology Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/ 27 * 28 * $FreeBSD: src/sys/dev/my/if_my.c,v 1.2.2.4 2002/04/17 02:05:27 julian Exp $ 29 * $DragonFly: src/sys/dev/netif/my/if_my.c,v 1.6 2004/01/06 01:40:48 dillon Exp $ 30 * 31 * Myson fast ethernet PCI NIC driver 32 * 33 * $Id: if_my.c,v 1.40 2001/11/30 03:55:00 <yen_cw@myson.com.tw> wpaul Exp $ 34 */ 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/types.h> 44 #include <sys/bus.h> 45 #include <sys/module.h> 46 47 #define NBPFILTER 1 48 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_media.h> 53 #include <net/if_dl.h> 54 #include <net/bpf.h> 55 56 #include <vm/vm.h> /* for vtophys */ 57 #include <vm/pmap.h> /* for vtophys */ 58 #include <machine/clock.h> /* for DELAY */ 59 #include <machine/bus_memio.h> 60 #include <machine/bus_pio.h> 61 #include <machine/bus.h> 62 #include <machine/resource.h> 63 #include <sys/bus.h> 64 #include <sys/rman.h> 65 66 #include <bus/pci/pcireg.h> 67 #include <bus/pci/pcivar.h> 68 69 #include "../mii_layer/mii.h" 70 #include "../mii_layer/miivar.h" 71 72 #include "miibus_if.h" 73 74 /* 75 * #define MY_USEIOSPACE 76 */ 77 78 static int MY_USEIOSPACE = 1; 79 80 #if (MY_USEIOSPACE) 81 #define MY_RES SYS_RES_IOPORT 82 #define MY_RID MY_PCI_LOIO 83 #else 84 #define MY_RES SYS_RES_MEMORY 85 #define MY_RID MY_PCI_LOMEM 86 #endif 87 88 89 #include "if_myreg.h" 90 91 /* 92 * Various supported device vendors/types and their names. 93 */ 94 struct my_type *my_info_tmp; 95 static struct my_type my_devs[] = { 96 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 97 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 98 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 99 {0, 0, NULL} 100 }; 101 102 /* 103 * Various supported PHY vendors/types and their names. Note that this driver 104 * will work with pretty much any MII-compliant PHY, so failure to positively 105 * identify the chip is not a fatal error. 106 */ 107 static struct my_type my_phys[] = { 108 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 109 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 110 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 111 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 112 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 113 {0, 0, "<MII-compliant physical interface>"} 114 }; 115 116 static int my_probe(device_t); 117 static int my_attach(device_t); 118 static int my_detach(device_t); 119 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 120 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 121 static void my_rxeof(struct my_softc *); 122 static void my_txeof(struct my_softc *); 123 static void my_txeoc(struct my_softc *); 124 static void my_intr(void *); 125 static void my_start(struct ifnet *); 126 static int my_ioctl(struct ifnet *, u_long, caddr_t); 127 static void my_init(void *); 128 static void my_stop(struct my_softc *); 129 static void my_watchdog(struct ifnet *); 130 static void my_shutdown(device_t); 131 static int my_ifmedia_upd(struct ifnet *); 132 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 133 static u_int16_t my_phy_readreg(struct my_softc *, int); 134 static void my_phy_writereg(struct my_softc *, int, int); 135 static void my_autoneg_xmit(struct my_softc *); 136 static void my_autoneg_mii(struct my_softc *, int, int); 137 static void my_setmode_mii(struct my_softc *, int); 138 static void my_getmode_mii(struct my_softc *); 139 static void my_setcfg(struct my_softc *, int); 140 static u_int8_t my_calchash(caddr_t); 141 static void my_setmulti(struct my_softc *); 142 static void my_reset(struct my_softc *); 143 static int my_list_rx_init(struct my_softc *); 144 static int my_list_tx_init(struct my_softc *); 145 static long my_send_cmd_to_phy(struct my_softc *, int, int); 146 147 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 148 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 149 150 static device_method_t my_methods[] = { 151 /* Device interface */ 152 DEVMETHOD(device_probe, my_probe), 153 DEVMETHOD(device_attach, my_attach), 154 DEVMETHOD(device_detach, my_detach), 155 DEVMETHOD(device_shutdown, my_shutdown), 156 157 {0, 0} 158 }; 159 160 static driver_t my_driver = { 161 "my", 162 my_methods, 163 sizeof(struct my_softc) 164 }; 165 166 static devclass_t my_devclass; 167 168 DECLARE_DUMMY_MODULE(if_my); 169 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0); 170 171 static long 172 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 173 { 174 long miir; 175 int i; 176 int mask, data; 177 178 MY_LOCK(sc); 179 180 /* enable MII output */ 181 miir = CSR_READ_4(sc, MY_MANAGEMENT); 182 miir &= 0xfffffff0; 183 184 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 185 186 /* send 32 1's preamble */ 187 for (i = 0; i < 32; i++) { 188 /* low MDC; MDO is already high (miir) */ 189 miir &= ~MY_MASK_MIIR_MII_MDC; 190 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 191 192 /* high MDC */ 193 miir |= MY_MASK_MIIR_MII_MDC; 194 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 195 } 196 197 /* calculate ST+OP+PHYAD+REGAD+TA */ 198 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 199 200 /* sent out */ 201 mask = 0x8000; 202 while (mask) { 203 /* low MDC, prepare MDO */ 204 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 205 if (mask & data) 206 miir |= MY_MASK_MIIR_MII_MDO; 207 208 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 209 /* high MDC */ 210 miir |= MY_MASK_MIIR_MII_MDC; 211 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 212 DELAY(30); 213 214 /* next */ 215 mask >>= 1; 216 if (mask == 0x2 && opcode == MY_OP_READ) 217 miir &= ~MY_MASK_MIIR_MII_WRITE; 218 } 219 220 MY_UNLOCK(sc); 221 return miir; 222 } 223 224 225 static u_int16_t 226 my_phy_readreg(struct my_softc * sc, int reg) 227 { 228 long miir; 229 int mask, data; 230 231 MY_LOCK(sc); 232 233 if (sc->my_info->my_did == MTD803ID) 234 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 235 else { 236 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 237 238 /* read data */ 239 mask = 0x8000; 240 data = 0; 241 while (mask) { 242 /* low MDC */ 243 miir &= ~MY_MASK_MIIR_MII_MDC; 244 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 245 246 /* read MDI */ 247 miir = CSR_READ_4(sc, MY_MANAGEMENT); 248 if (miir & MY_MASK_MIIR_MII_MDI) 249 data |= mask; 250 251 /* high MDC, and wait */ 252 miir |= MY_MASK_MIIR_MII_MDC; 253 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 254 DELAY(30); 255 256 /* next */ 257 mask >>= 1; 258 } 259 260 /* low MDC */ 261 miir &= ~MY_MASK_MIIR_MII_MDC; 262 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 263 } 264 265 MY_UNLOCK(sc); 266 return (u_int16_t) data; 267 } 268 269 270 static void 271 my_phy_writereg(struct my_softc * sc, int reg, int data) 272 { 273 long miir; 274 int mask; 275 276 MY_LOCK(sc); 277 278 if (sc->my_info->my_did == MTD803ID) 279 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 280 else { 281 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 282 283 /* write data */ 284 mask = 0x8000; 285 while (mask) { 286 /* low MDC, prepare MDO */ 287 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 288 if (mask & data) 289 miir |= MY_MASK_MIIR_MII_MDO; 290 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 291 DELAY(1); 292 293 /* high MDC */ 294 miir |= MY_MASK_MIIR_MII_MDC; 295 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 296 DELAY(1); 297 298 /* next */ 299 mask >>= 1; 300 } 301 302 /* low MDC */ 303 miir &= ~MY_MASK_MIIR_MII_MDC; 304 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 305 } 306 MY_UNLOCK(sc); 307 return; 308 } 309 310 static u_int8_t 311 my_calchash(caddr_t addr) 312 { 313 u_int32_t crc, carry; 314 int i, j; 315 u_int8_t c; 316 317 /* Compute CRC for the address value. */ 318 crc = 0xFFFFFFFF; /* initial value */ 319 320 for (i = 0; i < 6; i++) { 321 c = *(addr + i); 322 for (j = 0; j < 8; j++) { 323 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 324 crc <<= 1; 325 c >>= 1; 326 if (carry) 327 crc = (crc ^ 0x04c11db6) | carry; 328 } 329 } 330 331 /* 332 * return the filter bit position Note: I arrived at the following 333 * nonsense through experimentation. It's not the usual way to 334 * generate the bit position but it's the only thing I could come up 335 * with that works. 336 */ 337 return (~(crc >> 26) & 0x0000003F); 338 } 339 340 341 /* 342 * Program the 64-bit multicast hash filter. 343 */ 344 static void 345 my_setmulti(struct my_softc * sc) 346 { 347 struct ifnet *ifp; 348 int h = 0; 349 u_int32_t hashes[2] = {0, 0}; 350 struct ifmultiaddr *ifma; 351 u_int32_t rxfilt; 352 int mcnt = 0; 353 354 MY_LOCK(sc); 355 356 ifp = &sc->arpcom.ac_if; 357 358 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 359 360 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 361 rxfilt |= MY_AM; 362 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 363 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 364 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 365 366 MY_UNLOCK(sc); 367 368 return; 369 } 370 /* first, zot all the existing hash bits */ 371 CSR_WRITE_4(sc, MY_MAR0, 0); 372 CSR_WRITE_4(sc, MY_MAR1, 0); 373 374 /* now program new ones */ 375 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 376 if (ifma->ifma_addr->sa_family != AF_LINK) 377 continue; 378 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 379 if (h < 32) 380 hashes[0] |= (1 << h); 381 else 382 hashes[1] |= (1 << (h - 32)); 383 mcnt++; 384 } 385 386 if (mcnt) 387 rxfilt |= MY_AM; 388 else 389 rxfilt &= ~MY_AM; 390 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 391 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 392 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 393 MY_UNLOCK(sc); 394 return; 395 } 396 397 /* 398 * Initiate an autonegotiation session. 399 */ 400 static void 401 my_autoneg_xmit(struct my_softc * sc) 402 { 403 u_int16_t phy_sts = 0; 404 405 MY_LOCK(sc); 406 407 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 408 DELAY(500); 409 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 410 411 phy_sts = my_phy_readreg(sc, PHY_BMCR); 412 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 413 my_phy_writereg(sc, PHY_BMCR, phy_sts); 414 415 MY_UNLOCK(sc); 416 return; 417 } 418 419 420 /* 421 * Invoke autonegotiation on a PHY. 422 */ 423 static void 424 my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 425 { 426 u_int16_t phy_sts = 0, media, advert, ability; 427 u_int16_t ability2 = 0; 428 struct ifnet *ifp; 429 struct ifmedia *ifm; 430 431 MY_LOCK(sc); 432 433 ifm = &sc->ifmedia; 434 ifp = &sc->arpcom.ac_if; 435 436 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 437 438 #ifndef FORCE_AUTONEG_TFOUR 439 /* 440 * First, see if autoneg is supported. If not, there's no point in 441 * continuing. 442 */ 443 phy_sts = my_phy_readreg(sc, PHY_BMSR); 444 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 445 if (verbose) 446 printf("my%d: autonegotiation not supported\n", 447 sc->my_unit); 448 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 449 MY_UNLOCK(sc); 450 return; 451 } 452 #endif 453 switch (flag) { 454 case MY_FLAG_FORCEDELAY: 455 /* 456 * XXX Never use this option anywhere but in the probe 457 * routine: making the kernel stop dead in its tracks for 458 * three whole seconds after we've gone multi-user is really 459 * bad manners. 460 */ 461 my_autoneg_xmit(sc); 462 DELAY(5000000); 463 break; 464 case MY_FLAG_SCHEDDELAY: 465 /* 466 * Wait for the transmitter to go idle before starting an 467 * autoneg session, otherwise my_start() may clobber our 468 * timeout, and we don't want to allow transmission during an 469 * autoneg session since that can screw it up. 470 */ 471 if (sc->my_cdata.my_tx_head != NULL) { 472 sc->my_want_auto = 1; 473 MY_UNLOCK(sc); 474 return; 475 } 476 my_autoneg_xmit(sc); 477 ifp->if_timer = 5; 478 sc->my_autoneg = 1; 479 sc->my_want_auto = 0; 480 MY_UNLOCK(sc); 481 return; 482 case MY_FLAG_DELAYTIMEO: 483 ifp->if_timer = 0; 484 sc->my_autoneg = 0; 485 break; 486 default: 487 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 488 MY_UNLOCK(sc); 489 return; 490 } 491 492 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 493 if (verbose) 494 printf("my%d: autoneg complete, ", sc->my_unit); 495 phy_sts = my_phy_readreg(sc, PHY_BMSR); 496 } else { 497 if (verbose) 498 printf("my%d: autoneg not complete, ", sc->my_unit); 499 } 500 501 media = my_phy_readreg(sc, PHY_BMCR); 502 503 /* Link is good. Report modes and set duplex mode. */ 504 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 505 if (verbose) 506 printf("my%d: link status good. ", sc->my_unit); 507 advert = my_phy_readreg(sc, PHY_ANAR); 508 ability = my_phy_readreg(sc, PHY_LPAR); 509 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 510 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 511 ability2 = my_phy_readreg(sc, PHY_1000SR); 512 if (ability2 & PHY_1000SR_1000BTXFULL) { 513 advert = 0; 514 ability = 0; 515 /* 516 * this version did not support 1000M, 517 * ifm->ifm_media = 518 * IFM_ETHER|IFM_1000_TX|IFM_FDX; 519 */ 520 ifm->ifm_media = 521 IFM_ETHER | IFM_100_TX | IFM_FDX; 522 media &= ~PHY_BMCR_SPEEDSEL; 523 media |= PHY_BMCR_1000; 524 media |= PHY_BMCR_DUPLEX; 525 printf("(full-duplex, 1000Mbps)\n"); 526 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 527 advert = 0; 528 ability = 0; 529 /* 530 * this version did not support 1000M, 531 * ifm->ifm_media = IFM_ETHER|IFM_1000_TX; 532 */ 533 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 534 media &= ~PHY_BMCR_SPEEDSEL; 535 media &= ~PHY_BMCR_DUPLEX; 536 media |= PHY_BMCR_1000; 537 printf("(half-duplex, 1000Mbps)\n"); 538 } 539 } 540 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 541 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 542 media |= PHY_BMCR_SPEEDSEL; 543 media &= ~PHY_BMCR_DUPLEX; 544 printf("(100baseT4)\n"); 545 } else if (advert & PHY_ANAR_100BTXFULL && 546 ability & PHY_ANAR_100BTXFULL) { 547 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 548 media |= PHY_BMCR_SPEEDSEL; 549 media |= PHY_BMCR_DUPLEX; 550 printf("(full-duplex, 100Mbps)\n"); 551 } else if (advert & PHY_ANAR_100BTXHALF && 552 ability & PHY_ANAR_100BTXHALF) { 553 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 554 media |= PHY_BMCR_SPEEDSEL; 555 media &= ~PHY_BMCR_DUPLEX; 556 printf("(half-duplex, 100Mbps)\n"); 557 } else if (advert & PHY_ANAR_10BTFULL && 558 ability & PHY_ANAR_10BTFULL) { 559 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 560 media &= ~PHY_BMCR_SPEEDSEL; 561 media |= PHY_BMCR_DUPLEX; 562 printf("(full-duplex, 10Mbps)\n"); 563 } else if (advert) { 564 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 565 media &= ~PHY_BMCR_SPEEDSEL; 566 media &= ~PHY_BMCR_DUPLEX; 567 printf("(half-duplex, 10Mbps)\n"); 568 } 569 media &= ~PHY_BMCR_AUTONEGENBL; 570 571 /* Set ASIC's duplex mode to match the PHY. */ 572 my_phy_writereg(sc, PHY_BMCR, media); 573 my_setcfg(sc, media); 574 } else { 575 if (verbose) 576 printf("my%d: no carrier\n", sc->my_unit); 577 } 578 579 my_init(sc); 580 if (sc->my_tx_pend) { 581 sc->my_autoneg = 0; 582 sc->my_tx_pend = 0; 583 my_start(ifp); 584 } 585 MY_UNLOCK(sc); 586 return; 587 } 588 589 /* 590 * To get PHY ability. 591 */ 592 static void 593 my_getmode_mii(struct my_softc * sc) 594 { 595 u_int16_t bmsr; 596 struct ifnet *ifp; 597 598 MY_LOCK(sc); 599 ifp = &sc->arpcom.ac_if; 600 bmsr = my_phy_readreg(sc, PHY_BMSR); 601 if (bootverbose) 602 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 603 604 /* fallback */ 605 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 606 607 if (bmsr & PHY_BMSR_10BTHALF) { 608 if (bootverbose) 609 printf("my%d: 10Mbps half-duplex mode supported\n", 610 sc->my_unit); 611 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 612 0, NULL); 613 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 614 } 615 if (bmsr & PHY_BMSR_10BTFULL) { 616 if (bootverbose) 617 printf("my%d: 10Mbps full-duplex mode supported\n", 618 sc->my_unit); 619 620 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 621 0, NULL); 622 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 623 } 624 if (bmsr & PHY_BMSR_100BTXHALF) { 625 if (bootverbose) 626 printf("my%d: 100Mbps half-duplex mode supported\n", 627 sc->my_unit); 628 ifp->if_baudrate = 100000000; 629 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 630 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 631 0, NULL); 632 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 633 } 634 if (bmsr & PHY_BMSR_100BTXFULL) { 635 if (bootverbose) 636 printf("my%d: 100Mbps full-duplex mode supported\n", 637 sc->my_unit); 638 ifp->if_baudrate = 100000000; 639 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 640 0, NULL); 641 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 642 } 643 /* Some also support 100BaseT4. */ 644 if (bmsr & PHY_BMSR_100BT4) { 645 if (bootverbose) 646 printf("my%d: 100baseT4 mode supported\n", sc->my_unit); 647 ifp->if_baudrate = 100000000; 648 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 649 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 650 #ifdef FORCE_AUTONEG_TFOUR 651 if (bootverbose) 652 printf("my%d: forcing on autoneg support for BT4\n", 653 sc->my_unit); 654 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 655 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 656 #endif 657 } 658 #if 0 /* this version did not support 1000M, */ 659 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 660 if (bootverbose) 661 printf("my%d: 1000Mbps half-duplex mode supported\n", 662 sc->my_unit); 663 664 ifp->if_baudrate = 1000000000; 665 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX, 0, NULL); 666 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX | IFM_HDX, 667 0, NULL); 668 if (bootverbose) 669 printf("my%d: 1000Mbps full-duplex mode supported\n", 670 sc->my_unit); 671 ifp->if_baudrate = 1000000000; 672 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX | IFM_FDX, 673 0, NULL); 674 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_TX | IFM_FDX; 675 } 676 #endif 677 if (bmsr & PHY_BMSR_CANAUTONEG) { 678 if (bootverbose) 679 printf("my%d: autoneg supported\n", sc->my_unit); 680 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 681 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 682 } 683 MY_UNLOCK(sc); 684 return; 685 } 686 687 /* 688 * Set speed and duplex mode. 689 */ 690 static void 691 my_setmode_mii(struct my_softc * sc, int media) 692 { 693 u_int16_t bmcr; 694 struct ifnet *ifp; 695 696 MY_LOCK(sc); 697 ifp = &sc->arpcom.ac_if; 698 /* 699 * If an autoneg session is in progress, stop it. 700 */ 701 if (sc->my_autoneg) { 702 printf("my%d: canceling autoneg session\n", sc->my_unit); 703 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 704 bmcr = my_phy_readreg(sc, PHY_BMCR); 705 bmcr &= ~PHY_BMCR_AUTONEGENBL; 706 my_phy_writereg(sc, PHY_BMCR, bmcr); 707 } 708 printf("my%d: selecting MII, ", sc->my_unit); 709 bmcr = my_phy_readreg(sc, PHY_BMCR); 710 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 711 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 712 713 #if 0 /* this version did not support 1000M, */ 714 if (IFM_SUBTYPE(media) == IFM_1000_TX) { 715 printf("1000Mbps/T4, half-duplex\n"); 716 bmcr &= ~PHY_BMCR_SPEEDSEL; 717 bmcr &= ~PHY_BMCR_DUPLEX; 718 bmcr |= PHY_BMCR_1000; 719 } 720 #endif 721 if (IFM_SUBTYPE(media) == IFM_100_T4) { 722 printf("100Mbps/T4, half-duplex\n"); 723 bmcr |= PHY_BMCR_SPEEDSEL; 724 bmcr &= ~PHY_BMCR_DUPLEX; 725 } 726 if (IFM_SUBTYPE(media) == IFM_100_TX) { 727 printf("100Mbps, "); 728 bmcr |= PHY_BMCR_SPEEDSEL; 729 } 730 if (IFM_SUBTYPE(media) == IFM_10_T) { 731 printf("10Mbps, "); 732 bmcr &= ~PHY_BMCR_SPEEDSEL; 733 } 734 if ((media & IFM_GMASK) == IFM_FDX) { 735 printf("full duplex\n"); 736 bmcr |= PHY_BMCR_DUPLEX; 737 } else { 738 printf("half duplex\n"); 739 bmcr &= ~PHY_BMCR_DUPLEX; 740 } 741 my_phy_writereg(sc, PHY_BMCR, bmcr); 742 my_setcfg(sc, bmcr); 743 MY_UNLOCK(sc); 744 return; 745 } 746 747 /* 748 * The Myson manual states that in order to fiddle with the 'full-duplex' and 749 * '100Mbps' bits in the netconfig register, we first have to put the 750 * transmit and/or receive logic in the idle state. 751 */ 752 static void 753 my_setcfg(struct my_softc * sc, int bmcr) 754 { 755 int i, restart = 0; 756 757 MY_LOCK(sc); 758 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 759 restart = 1; 760 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 761 for (i = 0; i < MY_TIMEOUT; i++) { 762 DELAY(10); 763 if (!(CSR_READ_4(sc, MY_TCRRCR) & 764 (MY_TXRUN | MY_RXRUN))) 765 break; 766 } 767 if (i == MY_TIMEOUT) 768 printf("my%d: failed to force tx and rx to idle \n", 769 sc->my_unit); 770 } 771 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 772 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 773 if (bmcr & PHY_BMCR_1000) 774 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 775 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 776 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 777 if (bmcr & PHY_BMCR_DUPLEX) 778 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 779 else 780 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 781 if (restart) 782 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 783 MY_UNLOCK(sc); 784 return; 785 } 786 787 static void 788 my_reset(struct my_softc * sc) 789 { 790 int i; 791 792 MY_LOCK(sc); 793 MY_SETBIT(sc, MY_BCR, MY_SWR); 794 for (i = 0; i < MY_TIMEOUT; i++) { 795 DELAY(10); 796 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 797 break; 798 } 799 if (i == MY_TIMEOUT) 800 printf("m0x%d: reset never completed!\n", sc->my_unit); 801 802 /* Wait a little while for the chip to get its brains in order. */ 803 DELAY(1000); 804 MY_UNLOCK(sc); 805 return; 806 } 807 808 /* 809 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 810 * list and return a device name if we find a match. 811 */ 812 static int 813 my_probe(device_t dev) 814 { 815 struct my_type *t; 816 817 t = my_devs; 818 while (t->my_name != NULL) { 819 if ((pci_get_vendor(dev) == t->my_vid) && 820 (pci_get_device(dev) == t->my_did)) { 821 device_set_desc(dev, t->my_name); 822 my_info_tmp = t; 823 return (0); 824 } 825 t++; 826 } 827 return (ENXIO); 828 } 829 830 /* 831 * Attach the interface. Allocate softc structures, do ifmedia setup and 832 * ethernet/BPF attach. 833 */ 834 static int 835 my_attach(device_t dev) 836 { 837 int s, i; 838 u_char eaddr[ETHER_ADDR_LEN]; 839 u_int32_t command, iobase; 840 struct my_softc *sc; 841 struct ifnet *ifp; 842 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 843 unsigned int round; 844 caddr_t roundptr; 845 struct my_type *p; 846 u_int16_t phy_vid, phy_did, phy_sts = 0; 847 int rid, unit, error = 0; 848 849 s = splimp(); 850 sc = device_get_softc(dev); 851 unit = device_get_unit(dev); 852 if (sc == NULL) { 853 printf("my%d: no memory for softc struct!\n", unit); 854 error = ENXIO; 855 goto fail; 856 857 } 858 bzero(sc, sizeof(struct my_softc)); 859 /*mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);*/ 860 MY_LOCK(sc); 861 862 /* 863 * Map control/status registers. 864 */ 865 #if 0 866 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 867 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 868 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4); 869 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 870 #endif 871 command = pci_read_config(dev, PCIR_COMMAND, 4); 872 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 873 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 874 command = pci_read_config(dev, PCIR_COMMAND, 4); 875 876 if (my_info_tmp->my_did == MTD800ID) { 877 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 878 if (iobase & 0x300) 879 MY_USEIOSPACE = 0; 880 } 881 if (MY_USEIOSPACE) { 882 if (!(command & PCIM_CMD_PORTEN)) { 883 printf("my%d: failed to enable I/O ports!\n", unit); 884 free(sc, M_DEVBUF); 885 error = ENXIO; 886 goto fail; 887 } 888 #if 0 889 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) { 890 printf("my%d: couldn't map ports\n", unit); 891 error = ENXIO; 892 goto fail; 893 } 894 895 sc->my_btag = I386_BUS_SPACE_IO; 896 #endif 897 } else { 898 if (!(command & PCIM_CMD_MEMEN)) { 899 printf("my%d: failed to enable memory mapping!\n", 900 unit); 901 error = ENXIO; 902 goto fail; 903 } 904 #if 0 905 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) { 906 printf ("my%d: couldn't map memory\n", unit); 907 error = ENXIO; 908 goto fail; 909 } 910 sc->my_btag = I386_BUS_SPACE_MEM; 911 sc->my_bhandle = vbase; 912 #endif 913 } 914 915 rid = MY_RID; 916 sc->my_res = bus_alloc_resource(dev, MY_RES, &rid, 917 0, ~0, 1, RF_ACTIVE); 918 919 if (sc->my_res == NULL) { 920 printf("my%d: couldn't map ports/memory\n", unit); 921 error = ENXIO; 922 goto fail; 923 } 924 sc->my_btag = rman_get_bustag(sc->my_res); 925 sc->my_bhandle = rman_get_bushandle(sc->my_res); 926 927 rid = 0; 928 sc->my_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 929 RF_SHAREABLE | RF_ACTIVE); 930 931 if (sc->my_irq == NULL) { 932 printf("my%d: couldn't map interrupt\n", unit); 933 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 934 error = ENXIO; 935 goto fail; 936 } 937 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET, 938 my_intr, sc, &sc->my_intrhand); 939 940 if (error) { 941 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 942 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 943 printf("my%d: couldn't set up irq\n", unit); 944 goto fail; 945 } 946 callout_handle_init(&sc->my_stat_ch); 947 948 sc->my_info = my_info_tmp; 949 950 /* Reset the adapter. */ 951 my_reset(sc); 952 953 /* 954 * Get station address 955 */ 956 for (i = 0; i < ETHER_ADDR_LEN; ++i) 957 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 958 959 /* 960 * A Myson chip was detected. Inform the world. 961 */ 962 printf("my%d: Ethernet address: %6D\n", unit, eaddr, ":"); 963 964 sc->my_unit = unit; 965 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 966 967 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 968 M_DEVBUF, M_NOWAIT); 969 if (sc->my_ldata_ptr == NULL) { 970 free(sc, M_DEVBUF); 971 printf("my%d: no memory for list buffers!\n", unit); 972 error = ENXIO; 973 goto fail; 974 } 975 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 976 round = (unsigned int)sc->my_ldata_ptr & 0xF; 977 roundptr = sc->my_ldata_ptr; 978 for (i = 0; i < 8; i++) { 979 if (round % 8) { 980 round++; 981 roundptr++; 982 } else 983 break; 984 } 985 sc->my_ldata = (struct my_list_data *) roundptr; 986 bzero(sc->my_ldata, sizeof(struct my_list_data)); 987 988 ifp = &sc->arpcom.ac_if; 989 ifp->if_softc = sc; 990 if_initname(ifp, "my", unit); 991 ifp->if_mtu = ETHERMTU; 992 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 993 ifp->if_ioctl = my_ioctl; 994 ifp->if_output = ether_output; 995 ifp->if_start = my_start; 996 ifp->if_watchdog = my_watchdog; 997 ifp->if_init = my_init; 998 ifp->if_baudrate = 10000000; 999 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1000 1001 if (sc->my_info->my_did == MTD803ID) 1002 sc->my_pinfo = my_phys; 1003 else { 1004 if (bootverbose) 1005 printf("my%d: probing for a PHY\n", sc->my_unit); 1006 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 1007 if (bootverbose) 1008 printf("my%d: checking address: %d\n", 1009 sc->my_unit, i); 1010 sc->my_phy_addr = i; 1011 phy_sts = my_phy_readreg(sc, PHY_BMSR); 1012 if ((phy_sts != 0) && (phy_sts != 0xffff)) 1013 break; 1014 else 1015 phy_sts = 0; 1016 } 1017 if (phy_sts) { 1018 phy_vid = my_phy_readreg(sc, PHY_VENID); 1019 phy_did = my_phy_readreg(sc, PHY_DEVID); 1020 if (bootverbose) { 1021 printf("my%d: found PHY at address %d, ", 1022 sc->my_unit, sc->my_phy_addr); 1023 printf("vendor id: %x device id: %x\n", 1024 phy_vid, phy_did); 1025 } 1026 p = my_phys; 1027 while (p->my_vid) { 1028 if (phy_vid == p->my_vid) { 1029 sc->my_pinfo = p; 1030 break; 1031 } 1032 p++; 1033 } 1034 if (sc->my_pinfo == NULL) 1035 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 1036 if (bootverbose) 1037 printf("my%d: PHY type: %s\n", 1038 sc->my_unit, sc->my_pinfo->my_name); 1039 } else { 1040 printf("my%d: MII without any phy!\n", sc->my_unit); 1041 error = ENXIO; 1042 goto fail; 1043 } 1044 } 1045 1046 /* Do ifmedia setup. */ 1047 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 1048 my_getmode_mii(sc); 1049 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 1050 media = sc->ifmedia.ifm_media; 1051 my_stop(sc); 1052 ifmedia_set(&sc->ifmedia, media); 1053 1054 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1055 1056 #if 0 1057 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC); 1058 shutdownhook_establish(my_shutdown, sc); 1059 #endif 1060 1061 MY_UNLOCK(sc); 1062 return (0); 1063 1064 fail: 1065 MY_UNLOCK(sc); 1066 /*mtx_destroy(&sc->my_mtx);*/ 1067 splx(s); 1068 return (error); 1069 } 1070 1071 static int 1072 my_detach(device_t dev) 1073 { 1074 struct my_softc *sc; 1075 struct ifnet *ifp; 1076 int s; 1077 1078 s = splimp(); 1079 sc = device_get_softc(dev); 1080 MY_LOCK(sc); 1081 ifp = &sc->arpcom.ac_if; 1082 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1083 my_stop(sc); 1084 1085 #if 0 1086 bus_generic_detach(dev); 1087 device_delete_child(dev, sc->rl_miibus); 1088 #endif 1089 1090 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 1091 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 1092 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 1093 #if 0 1094 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF); 1095 #endif 1096 free(sc, M_DEVBUF); 1097 MY_UNLOCK(sc); 1098 splx(s); 1099 /*mtx_destroy(&sc->my_mtx);*/ 1100 return (0); 1101 } 1102 1103 1104 /* 1105 * Initialize the transmit descriptors. 1106 */ 1107 static int 1108 my_list_tx_init(struct my_softc * sc) 1109 { 1110 struct my_chain_data *cd; 1111 struct my_list_data *ld; 1112 int i; 1113 1114 MY_LOCK(sc); 1115 cd = &sc->my_cdata; 1116 ld = sc->my_ldata; 1117 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1118 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1119 if (i == (MY_TX_LIST_CNT - 1)) 1120 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1121 else 1122 cd->my_tx_chain[i].my_nextdesc = 1123 &cd->my_tx_chain[i + 1]; 1124 } 1125 cd->my_tx_free = &cd->my_tx_chain[0]; 1126 cd->my_tx_tail = cd->my_tx_head = NULL; 1127 MY_UNLOCK(sc); 1128 return (0); 1129 } 1130 1131 /* 1132 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1133 * arrange the descriptors in a closed ring, so that the last descriptor 1134 * points back to the first. 1135 */ 1136 static int 1137 my_list_rx_init(struct my_softc * sc) 1138 { 1139 struct my_chain_data *cd; 1140 struct my_list_data *ld; 1141 int i; 1142 1143 MY_LOCK(sc); 1144 cd = &sc->my_cdata; 1145 ld = sc->my_ldata; 1146 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1147 cd->my_rx_chain[i].my_ptr = 1148 (struct my_desc *) & ld->my_rx_list[i]; 1149 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) 1150 return (ENOBUFS); 1151 if (i == (MY_RX_LIST_CNT - 1)) { 1152 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1153 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1154 } else { 1155 cd->my_rx_chain[i].my_nextdesc = 1156 &cd->my_rx_chain[i + 1]; 1157 ld->my_rx_list[i].my_next = 1158 vtophys(&ld->my_rx_list[i + 1]); 1159 } 1160 } 1161 cd->my_rx_head = &cd->my_rx_chain[0]; 1162 MY_UNLOCK(sc); 1163 return (0); 1164 } 1165 1166 /* 1167 * Initialize an RX descriptor and attach an MBUF cluster. 1168 */ 1169 static int 1170 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1171 { 1172 struct mbuf *m_new = NULL; 1173 1174 MY_LOCK(sc); 1175 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1176 if (m_new == NULL) { 1177 printf("my%d: no memory for rx list -- packet dropped!\n", 1178 sc->my_unit); 1179 return (ENOBUFS); 1180 } 1181 MCLGET(m_new, M_DONTWAIT); 1182 if (!(m_new->m_flags & M_EXT)) { 1183 printf("my%d: no memory for rx list -- packet dropped!\n", 1184 sc->my_unit); 1185 m_freem(m_new); 1186 return (ENOBUFS); 1187 } 1188 c->my_mbuf = m_new; 1189 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1190 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1191 c->my_ptr->my_status = MY_OWNByNIC; 1192 MY_UNLOCK(sc); 1193 return (0); 1194 } 1195 1196 /* 1197 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1198 * level protocols. 1199 */ 1200 static void 1201 my_rxeof(struct my_softc * sc) 1202 { 1203 struct ether_header *eh; 1204 struct mbuf *m; 1205 struct ifnet *ifp; 1206 struct my_chain_onefrag *cur_rx; 1207 int total_len = 0; 1208 u_int32_t rxstat; 1209 1210 MY_LOCK(sc); 1211 ifp = &sc->arpcom.ac_if; 1212 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1213 & MY_OWNByNIC)) { 1214 cur_rx = sc->my_cdata.my_rx_head; 1215 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1216 1217 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1218 ifp->if_ierrors++; 1219 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1220 continue; 1221 } 1222 /* No errors; receive the packet. */ 1223 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1224 total_len -= ETHER_CRC_LEN; 1225 1226 if (total_len < MINCLSIZE) { 1227 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1228 total_len, 0, ifp, NULL); 1229 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1230 if (m == NULL) { 1231 ifp->if_ierrors++; 1232 continue; 1233 } 1234 } else { 1235 m = cur_rx->my_mbuf; 1236 /* 1237 * Try to conjure up a new mbuf cluster. If that 1238 * fails, it means we have an out of memory condition 1239 * and should leave the buffer in place and continue. 1240 * This will result in a lost packet, but there's 1241 * little else we can do in this situation. 1242 */ 1243 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1244 ifp->if_ierrors++; 1245 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1246 continue; 1247 } 1248 m->m_pkthdr.rcvif = ifp; 1249 m->m_pkthdr.len = m->m_len = total_len; 1250 } 1251 ifp->if_ipackets++; 1252 eh = mtod(m, struct ether_header *); 1253 #if NBPFILTER > 0 1254 /* 1255 * Handle BPF listeners. Let the BPF user see the packet, but 1256 * don't pass it up to the ether_input() layer unless it's a 1257 * broadcast packet, multicast packet, matches our ethernet 1258 * address or the interface is in promiscuous mode. 1259 */ 1260 if (ifp->if_bpf) { 1261 bpf_mtap(ifp, m); 1262 if (ifp->if_flags & IFF_PROMISC && 1263 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1264 ETHER_ADDR_LEN) && 1265 (eh->ether_dhost[0] & 1) == 0)) { 1266 m_freem(m); 1267 continue; 1268 } 1269 } 1270 #endif 1271 /* Remove header from mbuf and pass it on. */ 1272 m_adj(m, sizeof(struct ether_header)); 1273 ether_input(ifp, eh, m); 1274 } 1275 MY_UNLOCK(sc); 1276 return; 1277 } 1278 1279 1280 /* 1281 * A frame was downloaded to the chip. It's safe for us to clean up the list 1282 * buffers. 1283 */ 1284 static void 1285 my_txeof(struct my_softc * sc) 1286 { 1287 struct my_chain *cur_tx; 1288 struct ifnet *ifp; 1289 1290 MY_LOCK(sc); 1291 ifp = &sc->arpcom.ac_if; 1292 /* Clear the timeout timer. */ 1293 ifp->if_timer = 0; 1294 if (sc->my_cdata.my_tx_head == NULL) 1295 return; 1296 /* 1297 * Go through our tx list and free mbufs for those frames that have 1298 * been transmitted. 1299 */ 1300 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1301 u_int32_t txstat; 1302 1303 cur_tx = sc->my_cdata.my_tx_head; 1304 txstat = MY_TXSTATUS(cur_tx); 1305 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1306 break; 1307 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1308 if (txstat & MY_TXERR) { 1309 ifp->if_oerrors++; 1310 if (txstat & MY_EC) /* excessive collision */ 1311 ifp->if_collisions++; 1312 if (txstat & MY_LC) /* late collision */ 1313 ifp->if_collisions++; 1314 } 1315 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1316 MY_NCRShift; 1317 } 1318 ifp->if_opackets++; 1319 m_freem(cur_tx->my_mbuf); 1320 cur_tx->my_mbuf = NULL; 1321 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1322 sc->my_cdata.my_tx_head = NULL; 1323 sc->my_cdata.my_tx_tail = NULL; 1324 break; 1325 } 1326 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1327 } 1328 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1329 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1330 } 1331 MY_UNLOCK(sc); 1332 return; 1333 } 1334 1335 /* 1336 * TX 'end of channel' interrupt handler. 1337 */ 1338 static void 1339 my_txeoc(struct my_softc * sc) 1340 { 1341 struct ifnet *ifp; 1342 1343 MY_LOCK(sc); 1344 ifp = &sc->arpcom.ac_if; 1345 ifp->if_timer = 0; 1346 if (sc->my_cdata.my_tx_head == NULL) { 1347 ifp->if_flags &= ~IFF_OACTIVE; 1348 sc->my_cdata.my_tx_tail = NULL; 1349 if (sc->my_want_auto) 1350 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1351 } else { 1352 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1353 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1354 ifp->if_timer = 5; 1355 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1356 } 1357 } 1358 MY_UNLOCK(sc); 1359 return; 1360 } 1361 1362 static void 1363 my_intr(void *arg) 1364 { 1365 struct my_softc *sc; 1366 struct ifnet *ifp; 1367 u_int32_t status; 1368 1369 sc = arg; 1370 MY_LOCK(sc); 1371 ifp = &sc->arpcom.ac_if; 1372 if (!(ifp->if_flags & IFF_UP)) { 1373 MY_UNLOCK(sc); 1374 return; 1375 } 1376 /* Disable interrupts. */ 1377 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1378 1379 for (;;) { 1380 status = CSR_READ_4(sc, MY_ISR); 1381 status &= MY_INTRS; 1382 if (status) 1383 CSR_WRITE_4(sc, MY_ISR, status); 1384 else 1385 break; 1386 1387 if (status & MY_RI) /* receive interrupt */ 1388 my_rxeof(sc); 1389 1390 if ((status & MY_RBU) || (status & MY_RxErr)) { 1391 /* rx buffer unavailable or rx error */ 1392 ifp->if_ierrors++; 1393 #ifdef foo 1394 my_stop(sc); 1395 my_reset(sc); 1396 my_init(sc); 1397 #endif 1398 } 1399 if (status & MY_TI) /* tx interrupt */ 1400 my_txeof(sc); 1401 if (status & MY_ETI) /* tx early interrupt */ 1402 my_txeof(sc); 1403 if (status & MY_TBU) /* tx buffer unavailable */ 1404 my_txeoc(sc); 1405 1406 #if 0 /* 90/1/18 delete */ 1407 if (status & MY_FBE) { 1408 my_reset(sc); 1409 my_init(sc); 1410 } 1411 #endif 1412 1413 } 1414 1415 /* Re-enable interrupts. */ 1416 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1417 if (ifp->if_snd.ifq_head != NULL) 1418 my_start(ifp); 1419 MY_UNLOCK(sc); 1420 return; 1421 } 1422 1423 /* 1424 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1425 * pointers to the fragment pointers. 1426 */ 1427 static int 1428 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1429 { 1430 struct my_desc *f = NULL; 1431 int total_len; 1432 struct mbuf *m, *m_new = NULL; 1433 1434 MY_LOCK(sc); 1435 /* calculate the total tx pkt length */ 1436 total_len = 0; 1437 for (m = m_head; m != NULL; m = m->m_next) 1438 total_len += m->m_len; 1439 /* 1440 * Start packing the mbufs in this chain into the fragment pointers. 1441 * Stop when we run out of fragments or hit the end of the mbuf 1442 * chain. 1443 */ 1444 m = m_head; 1445 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1446 if (m_new == NULL) { 1447 printf("my%d: no memory for tx list", sc->my_unit); 1448 return (1); 1449 } 1450 if (m_head->m_pkthdr.len > MHLEN) { 1451 MCLGET(m_new, M_DONTWAIT); 1452 if (!(m_new->m_flags & M_EXT)) { 1453 m_freem(m_new); 1454 printf("my%d: no memory for tx list", sc->my_unit); 1455 return (1); 1456 } 1457 } 1458 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1459 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1460 m_freem(m_head); 1461 m_head = m_new; 1462 f = &c->my_ptr->my_frag[0]; 1463 f->my_status = 0; 1464 f->my_data = vtophys(mtod(m_new, caddr_t)); 1465 total_len = m_new->m_len; 1466 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1467 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1468 f->my_ctl |= total_len; /* buffer size */ 1469 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1470 if (sc->my_info->my_did == MTD891ID) 1471 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1472 c->my_mbuf = m_head; 1473 c->my_lastdesc = 0; 1474 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1475 MY_UNLOCK(sc); 1476 return (0); 1477 } 1478 1479 /* 1480 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1481 * to the mbuf data regions directly in the transmit lists. We also save a 1482 * copy of the pointers since the transmit list fragment pointers are 1483 * physical addresses. 1484 */ 1485 static void 1486 my_start(struct ifnet * ifp) 1487 { 1488 struct my_softc *sc; 1489 struct mbuf *m_head = NULL; 1490 struct my_chain *cur_tx = NULL, *start_tx; 1491 1492 sc = ifp->if_softc; 1493 MY_LOCK(sc); 1494 if (sc->my_autoneg) { 1495 sc->my_tx_pend = 1; 1496 MY_UNLOCK(sc); 1497 return; 1498 } 1499 /* 1500 * Check for an available queue slot. If there are none, punt. 1501 */ 1502 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1503 ifp->if_flags |= IFF_OACTIVE; 1504 MY_UNLOCK(sc); 1505 return; 1506 } 1507 start_tx = sc->my_cdata.my_tx_free; 1508 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1509 IF_DEQUEUE(&ifp->if_snd, m_head); 1510 if (m_head == NULL) 1511 break; 1512 1513 /* Pick a descriptor off the free list. */ 1514 cur_tx = sc->my_cdata.my_tx_free; 1515 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1516 1517 /* Pack the data into the descriptor. */ 1518 my_encap(sc, cur_tx, m_head); 1519 1520 if (cur_tx != start_tx) 1521 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1522 #if NBPFILTER > 0 1523 /* 1524 * If there's a BPF listener, bounce a copy of this frame to 1525 * him. 1526 */ 1527 if (ifp->if_bpf) 1528 bpf_mtap(ifp, cur_tx->my_mbuf); 1529 #endif 1530 } 1531 /* 1532 * If there are no packets queued, bail. 1533 */ 1534 if (cur_tx == NULL) { 1535 MY_UNLOCK(sc); 1536 return; 1537 } 1538 /* 1539 * Place the request for the upload interrupt in the last descriptor 1540 * in the chain. This way, if we're chaining several packets at once, 1541 * we'll only get an interupt once for the whole chain rather than 1542 * once for each packet. 1543 */ 1544 MY_TXCTL(cur_tx) |= MY_TXIC; 1545 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1546 sc->my_cdata.my_tx_tail = cur_tx; 1547 if (sc->my_cdata.my_tx_head == NULL) 1548 sc->my_cdata.my_tx_head = start_tx; 1549 MY_TXOWN(start_tx) = MY_OWNByNIC; 1550 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1551 1552 /* 1553 * Set a timeout in case the chip goes out to lunch. 1554 */ 1555 ifp->if_timer = 5; 1556 MY_UNLOCK(sc); 1557 return; 1558 } 1559 1560 static void 1561 my_init(void *xsc) 1562 { 1563 struct my_softc *sc = xsc; 1564 struct ifnet *ifp = &sc->arpcom.ac_if; 1565 int s; 1566 u_int16_t phy_bmcr = 0; 1567 1568 MY_LOCK(sc); 1569 if (sc->my_autoneg) { 1570 MY_UNLOCK(sc); 1571 return; 1572 } 1573 s = splimp(); 1574 if (sc->my_pinfo != NULL) 1575 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1576 /* 1577 * Cancel pending I/O and free all RX/TX buffers. 1578 */ 1579 my_stop(sc); 1580 my_reset(sc); 1581 1582 /* 1583 * Set cache alignment and burst length. 1584 */ 1585 #if 0 /* 89/9/1 modify, */ 1586 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1587 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1588 #endif 1589 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1590 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1591 /* 1592 * 89/12/29 add, for mtd891, 1593 */ 1594 if (sc->my_info->my_did == MTD891ID) { 1595 MY_SETBIT(sc, MY_BCR, MY_PROG); 1596 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1597 } 1598 my_setcfg(sc, phy_bmcr); 1599 /* Init circular RX list. */ 1600 if (my_list_rx_init(sc) == ENOBUFS) { 1601 printf("my%d: init failed: no memory for rx buffers\n", 1602 sc->my_unit); 1603 my_stop(sc); 1604 (void)splx(s); 1605 MY_UNLOCK(sc); 1606 return; 1607 } 1608 /* Init TX descriptors. */ 1609 my_list_tx_init(sc); 1610 1611 /* If we want promiscuous mode, set the allframes bit. */ 1612 if (ifp->if_flags & IFF_PROMISC) 1613 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1614 else 1615 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1616 1617 /* 1618 * Set capture broadcast bit to capture broadcast frames. 1619 */ 1620 if (ifp->if_flags & IFF_BROADCAST) 1621 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1622 else 1623 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1624 1625 /* 1626 * Program the multicast filter, if necessary. 1627 */ 1628 my_setmulti(sc); 1629 1630 /* 1631 * Load the address of the RX list. 1632 */ 1633 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1634 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1635 1636 /* 1637 * Enable interrupts. 1638 */ 1639 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1640 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1641 1642 /* Enable receiver and transmitter. */ 1643 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1644 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1645 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1646 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1647 1648 /* Restore state of BMCR */ 1649 if (sc->my_pinfo != NULL) 1650 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1651 ifp->if_flags |= IFF_RUNNING; 1652 ifp->if_flags &= ~IFF_OACTIVE; 1653 (void)splx(s); 1654 MY_UNLOCK(sc); 1655 return; 1656 } 1657 1658 /* 1659 * Set media options. 1660 */ 1661 1662 static int 1663 my_ifmedia_upd(struct ifnet * ifp) 1664 { 1665 struct my_softc *sc; 1666 struct ifmedia *ifm; 1667 1668 sc = ifp->if_softc; 1669 MY_LOCK(sc); 1670 ifm = &sc->ifmedia; 1671 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 1672 MY_UNLOCK(sc); 1673 return (EINVAL); 1674 } 1675 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1676 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1677 else 1678 my_setmode_mii(sc, ifm->ifm_media); 1679 MY_UNLOCK(sc); 1680 return (0); 1681 } 1682 1683 /* 1684 * Report current media status. 1685 */ 1686 1687 static void 1688 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1689 { 1690 struct my_softc *sc; 1691 u_int16_t advert = 0, ability = 0; 1692 1693 sc = ifp->if_softc; 1694 MY_LOCK(sc); 1695 ifmr->ifm_active = IFM_ETHER; 1696 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1697 #if 0 /* this version did not support 1000M, */ 1698 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1699 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1700 #endif 1701 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1702 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1703 else 1704 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1705 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1706 ifmr->ifm_active |= IFM_FDX; 1707 else 1708 ifmr->ifm_active |= IFM_HDX; 1709 1710 MY_UNLOCK(sc); 1711 return; 1712 } 1713 ability = my_phy_readreg(sc, PHY_LPAR); 1714 advert = my_phy_readreg(sc, PHY_ANAR); 1715 1716 #if 0 /* this version did not support 1000M, */ 1717 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1718 ability2 = my_phy_readreg(sc, PHY_1000SR); 1719 if (ability2 & PHY_1000SR_1000BTXFULL) { 1720 advert = 0; 1721 ability = 0; 1722 ifmr->ifm_active = IFM_ETHER|IFM_1000_TX|IFM_FDX; 1723 } else if (ability & PHY_1000SR_1000BTXHALF) { 1724 advert = 0; 1725 ability = 0; 1726 ifmr->ifm_active = IFM_ETHER|IFM_1000_TX|IFM_HDX; 1727 } 1728 } 1729 #endif 1730 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1731 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1732 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1733 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1734 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1735 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1736 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1737 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1738 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1739 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1740 MY_UNLOCK(sc); 1741 return; 1742 } 1743 1744 static int 1745 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 1746 { 1747 struct my_softc *sc = ifp->if_softc; 1748 struct ifreq *ifr = (struct ifreq *) data; 1749 int s, error = 0; 1750 1751 s = splimp(); 1752 MY_LOCK(sc); 1753 switch (command) { 1754 case SIOCSIFADDR: 1755 case SIOCGIFADDR: 1756 case SIOCSIFMTU: 1757 error = ether_ioctl(ifp, command, data); 1758 break; 1759 case SIOCSIFFLAGS: 1760 if (ifp->if_flags & IFF_UP) 1761 my_init(sc); 1762 else if (ifp->if_flags & IFF_RUNNING) 1763 my_stop(sc); 1764 error = 0; 1765 break; 1766 case SIOCADDMULTI: 1767 case SIOCDELMULTI: 1768 my_setmulti(sc); 1769 error = 0; 1770 break; 1771 case SIOCGIFMEDIA: 1772 case SIOCSIFMEDIA: 1773 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1774 break; 1775 default: 1776 error = EINVAL; 1777 break; 1778 } 1779 MY_UNLOCK(sc); 1780 (void)splx(s); 1781 return (error); 1782 } 1783 1784 static void 1785 my_watchdog(struct ifnet * ifp) 1786 { 1787 struct my_softc *sc; 1788 1789 sc = ifp->if_softc; 1790 MY_LOCK(sc); 1791 if (sc->my_autoneg) { 1792 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1793 MY_UNLOCK(sc); 1794 return; 1795 } 1796 ifp->if_oerrors++; 1797 printf("my%d: watchdog timeout\n", sc->my_unit); 1798 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1799 printf("my%d: no carrier - transceiver cable problem?\n", 1800 sc->my_unit); 1801 my_stop(sc); 1802 my_reset(sc); 1803 my_init(sc); 1804 if (ifp->if_snd.ifq_head != NULL) 1805 my_start(ifp); 1806 MY_LOCK(sc); 1807 return; 1808 } 1809 1810 1811 /* 1812 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1813 */ 1814 static void 1815 my_stop(struct my_softc * sc) 1816 { 1817 int i; 1818 struct ifnet *ifp; 1819 1820 MY_LOCK(sc); 1821 ifp = &sc->arpcom.ac_if; 1822 ifp->if_timer = 0; 1823 1824 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1825 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1826 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1827 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1828 1829 /* 1830 * Free data in the RX lists. 1831 */ 1832 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1833 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1834 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1835 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1836 } 1837 } 1838 bzero((char *)&sc->my_ldata->my_rx_list, 1839 sizeof(sc->my_ldata->my_rx_list)); 1840 /* 1841 * Free the TX list buffers. 1842 */ 1843 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1844 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1845 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1846 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1847 } 1848 } 1849 bzero((char *)&sc->my_ldata->my_tx_list, 1850 sizeof(sc->my_ldata->my_tx_list)); 1851 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1852 MY_UNLOCK(sc); 1853 return; 1854 } 1855 1856 /* 1857 * Stop all chip I/O so that the kernel's probe routines don't get confused 1858 * by errant DMAs when rebooting. 1859 */ 1860 static void 1861 my_shutdown(device_t dev) 1862 { 1863 struct my_softc *sc; 1864 1865 sc = device_get_softc(dev); 1866 my_stop(sc); 1867 return; 1868 } 1869