1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $ 34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.6 2004/01/06 01:40:48 dillon Exp $ 35 * 36 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $ 37 */ 38 39 /* 40 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 41 * for FreeBSD. Datasheets are available from: 42 * 43 * http://www.national.com/ds/DP/DP83820.pdf 44 * http://www.national.com/ds/DP/DP83821.pdf 45 * 46 * These chips are used on several low cost gigabit ethernet NICs 47 * sold by D-Link, Addtron, SMC and Asante. Both parts are 48 * virtually the same, except the 83820 is a 64-bit/32-bit part, 49 * while the 83821 is 32-bit only. 50 * 51 * Many cards also use National gigE transceivers, such as the 52 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 53 * contains a full register description that applies to all of these 54 * components: 55 * 56 * http://www.national.com/ds/DP/DP83861.pdf 57 * 58 * Written by Bill Paul <wpaul@bsdi.com> 59 * BSDi Open Source Solutions 60 */ 61 62 /* 63 * The NatSemi DP83820 and 83821 controllers are enhanced versions 64 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 65 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 66 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 67 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 68 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 69 * matching buffers, one perfect address filter buffer and interrupt 70 * moderation. The 83820 supports both 64-bit and 32-bit addressing 71 * and data transfers: the 64-bit support can be toggled on or off 72 * via software. This affects the size of certain fields in the DMA 73 * descriptors. 74 * 75 * There are two bugs/misfeatures in the 83820/83821 that I have 76 * discovered so far: 77 * 78 * - Receive buffers must be aligned on 64-bit boundaries, which means 79 * you must resort to copying data in order to fix up the payload 80 * alignment. 81 * 82 * - In order to transmit jumbo frames larger than 8170 bytes, you have 83 * to turn off transmit checksum offloading, because the chip can't 84 * compute the checksum on an outgoing frame unless it fits entirely 85 * within the TX FIFO, which is only 8192 bytes in size. If you have 86 * TX checksum offload enabled and you transmit attempt to transmit a 87 * frame larger than 8170 bytes, the transmitter will wedge. 88 * 89 * To work around the latter problem, TX checksum offload is disabled 90 * if the user selects an MTU larger than 8152 (8170 - 18). 91 */ 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/sockio.h> 96 #include <sys/mbuf.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 101 #include <net/if.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_types.h> 107 #include <net/vlan/if_vlan_var.h> 108 109 #include <net/bpf.h> 110 111 #include <vm/vm.h> /* for vtophys */ 112 #include <vm/pmap.h> /* for vtophys */ 113 #include <machine/clock.h> /* for DELAY */ 114 #include <machine/bus_pio.h> 115 #include <machine/bus_memio.h> 116 #include <machine/bus.h> 117 #include <machine/resource.h> 118 #include <sys/bus.h> 119 #include <sys/rman.h> 120 121 #include "../mii_layer/mii.h" 122 #include "../mii_layer/miivar.h" 123 124 #include <bus/pci/pcireg.h> 125 #include <bus/pci/pcivar.h> 126 127 #define NGE_USEIOSPACE 128 129 #include "if_ngereg.h" 130 131 132 /* "controller miibus0" required. See GENERIC if you get errors here. */ 133 #include "miibus_if.h" 134 135 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 136 137 /* 138 * Various supported device vendors/types and their names. 139 */ 140 static struct nge_type nge_devs[] = { 141 { NGE_VENDORID, NGE_DEVICEID, 142 "National Semiconductor Gigabit Ethernet" }, 143 { 0, 0, NULL } 144 }; 145 146 static int nge_probe (device_t); 147 static int nge_attach (device_t); 148 static int nge_detach (device_t); 149 150 static int nge_alloc_jumbo_mem (struct nge_softc *); 151 static void nge_free_jumbo_mem (struct nge_softc *); 152 static void *nge_jalloc (struct nge_softc *); 153 static void nge_jfree (caddr_t, u_int); 154 static void nge_jref (caddr_t, u_int); 155 156 static int nge_newbuf (struct nge_softc *, 157 struct nge_desc *, struct mbuf *); 158 static int nge_encap (struct nge_softc *, 159 struct mbuf *, u_int32_t *); 160 static void nge_rxeof (struct nge_softc *); 161 static void nge_txeof (struct nge_softc *); 162 static void nge_intr (void *); 163 static void nge_tick (void *); 164 static void nge_start (struct ifnet *); 165 static int nge_ioctl (struct ifnet *, u_long, caddr_t); 166 static void nge_init (void *); 167 static void nge_stop (struct nge_softc *); 168 static void nge_watchdog (struct ifnet *); 169 static void nge_shutdown (device_t); 170 static int nge_ifmedia_upd (struct ifnet *); 171 static void nge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 172 173 static void nge_delay (struct nge_softc *); 174 static void nge_eeprom_idle (struct nge_softc *); 175 static void nge_eeprom_putbyte (struct nge_softc *, int); 176 static void nge_eeprom_getword (struct nge_softc *, int, u_int16_t *); 177 static void nge_read_eeprom (struct nge_softc *, caddr_t, int, int, int); 178 179 static void nge_mii_sync (struct nge_softc *); 180 static void nge_mii_send (struct nge_softc *, u_int32_t, int); 181 static int nge_mii_readreg (struct nge_softc *, struct nge_mii_frame *); 182 static int nge_mii_writereg (struct nge_softc *, struct nge_mii_frame *); 183 184 static int nge_miibus_readreg (device_t, int, int); 185 static int nge_miibus_writereg (device_t, int, int, int); 186 static void nge_miibus_statchg (device_t); 187 188 static void nge_setmulti (struct nge_softc *); 189 static u_int32_t nge_crc (struct nge_softc *, caddr_t); 190 static void nge_reset (struct nge_softc *); 191 static int nge_list_rx_init (struct nge_softc *); 192 static int nge_list_tx_init (struct nge_softc *); 193 194 #ifdef NGE_USEIOSPACE 195 #define NGE_RES SYS_RES_IOPORT 196 #define NGE_RID NGE_PCI_LOIO 197 #else 198 #define NGE_RES SYS_RES_MEMORY 199 #define NGE_RID NGE_PCI_LOMEM 200 #endif 201 202 static device_method_t nge_methods[] = { 203 /* Device interface */ 204 DEVMETHOD(device_probe, nge_probe), 205 DEVMETHOD(device_attach, nge_attach), 206 DEVMETHOD(device_detach, nge_detach), 207 DEVMETHOD(device_shutdown, nge_shutdown), 208 209 /* bus interface */ 210 DEVMETHOD(bus_print_child, bus_generic_print_child), 211 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 212 213 /* MII interface */ 214 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 215 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 216 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 217 218 { 0, 0 } 219 }; 220 221 static driver_t nge_driver = { 222 "nge", 223 nge_methods, 224 sizeof(struct nge_softc) 225 }; 226 227 static devclass_t nge_devclass; 228 229 DECLARE_DUMMY_MODULE(if_nge); 230 MODULE_DEPEND(if_nge, miibus, 1, 1, 1); 231 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 232 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 233 234 #define NGE_SETBIT(sc, reg, x) \ 235 CSR_WRITE_4(sc, reg, \ 236 CSR_READ_4(sc, reg) | (x)) 237 238 #define NGE_CLRBIT(sc, reg, x) \ 239 CSR_WRITE_4(sc, reg, \ 240 CSR_READ_4(sc, reg) & ~(x)) 241 242 #define SIO_SET(x) \ 243 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x) 244 245 #define SIO_CLR(x) \ 246 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x) 247 248 static void nge_delay(sc) 249 struct nge_softc *sc; 250 { 251 int idx; 252 253 for (idx = (300 / 33) + 1; idx > 0; idx--) 254 CSR_READ_4(sc, NGE_CSR); 255 256 return; 257 } 258 259 static void nge_eeprom_idle(sc) 260 struct nge_softc *sc; 261 { 262 int i; 263 264 SIO_SET(NGE_MEAR_EE_CSEL); 265 nge_delay(sc); 266 SIO_SET(NGE_MEAR_EE_CLK); 267 nge_delay(sc); 268 269 for (i = 0; i < 25; i++) { 270 SIO_CLR(NGE_MEAR_EE_CLK); 271 nge_delay(sc); 272 SIO_SET(NGE_MEAR_EE_CLK); 273 nge_delay(sc); 274 } 275 276 SIO_CLR(NGE_MEAR_EE_CLK); 277 nge_delay(sc); 278 SIO_CLR(NGE_MEAR_EE_CSEL); 279 nge_delay(sc); 280 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 281 282 return; 283 } 284 285 /* 286 * Send a read command and address to the EEPROM, check for ACK. 287 */ 288 static void nge_eeprom_putbyte(sc, addr) 289 struct nge_softc *sc; 290 int addr; 291 { 292 int d, i; 293 294 d = addr | NGE_EECMD_READ; 295 296 /* 297 * Feed in each bit and stobe the clock. 298 */ 299 for (i = 0x400; i; i >>= 1) { 300 if (d & i) { 301 SIO_SET(NGE_MEAR_EE_DIN); 302 } else { 303 SIO_CLR(NGE_MEAR_EE_DIN); 304 } 305 nge_delay(sc); 306 SIO_SET(NGE_MEAR_EE_CLK); 307 nge_delay(sc); 308 SIO_CLR(NGE_MEAR_EE_CLK); 309 nge_delay(sc); 310 } 311 312 return; 313 } 314 315 /* 316 * Read a word of data stored in the EEPROM at address 'addr.' 317 */ 318 static void nge_eeprom_getword(sc, addr, dest) 319 struct nge_softc *sc; 320 int addr; 321 u_int16_t *dest; 322 { 323 int i; 324 u_int16_t word = 0; 325 326 /* Force EEPROM to idle state. */ 327 nge_eeprom_idle(sc); 328 329 /* Enter EEPROM access mode. */ 330 nge_delay(sc); 331 SIO_CLR(NGE_MEAR_EE_CLK); 332 nge_delay(sc); 333 SIO_SET(NGE_MEAR_EE_CSEL); 334 nge_delay(sc); 335 336 /* 337 * Send address of word we want to read. 338 */ 339 nge_eeprom_putbyte(sc, addr); 340 341 /* 342 * Start reading bits from EEPROM. 343 */ 344 for (i = 0x8000; i; i >>= 1) { 345 SIO_SET(NGE_MEAR_EE_CLK); 346 nge_delay(sc); 347 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 348 word |= i; 349 nge_delay(sc); 350 SIO_CLR(NGE_MEAR_EE_CLK); 351 nge_delay(sc); 352 } 353 354 /* Turn off EEPROM access mode. */ 355 nge_eeprom_idle(sc); 356 357 *dest = word; 358 359 return; 360 } 361 362 /* 363 * Read a sequence of words from the EEPROM. 364 */ 365 static void nge_read_eeprom(sc, dest, off, cnt, swap) 366 struct nge_softc *sc; 367 caddr_t dest; 368 int off; 369 int cnt; 370 int swap; 371 { 372 int i; 373 u_int16_t word = 0, *ptr; 374 375 for (i = 0; i < cnt; i++) { 376 nge_eeprom_getword(sc, off + i, &word); 377 ptr = (u_int16_t *)(dest + (i * 2)); 378 if (swap) 379 *ptr = ntohs(word); 380 else 381 *ptr = word; 382 } 383 384 return; 385 } 386 387 /* 388 * Sync the PHYs by setting data bit and strobing the clock 32 times. 389 */ 390 static void nge_mii_sync(sc) 391 struct nge_softc *sc; 392 { 393 int i; 394 395 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 396 397 for (i = 0; i < 32; i++) { 398 SIO_SET(NGE_MEAR_MII_CLK); 399 DELAY(1); 400 SIO_CLR(NGE_MEAR_MII_CLK); 401 DELAY(1); 402 } 403 404 return; 405 } 406 407 /* 408 * Clock a series of bits through the MII. 409 */ 410 static void nge_mii_send(sc, bits, cnt) 411 struct nge_softc *sc; 412 u_int32_t bits; 413 int cnt; 414 { 415 int i; 416 417 SIO_CLR(NGE_MEAR_MII_CLK); 418 419 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 420 if (bits & i) { 421 SIO_SET(NGE_MEAR_MII_DATA); 422 } else { 423 SIO_CLR(NGE_MEAR_MII_DATA); 424 } 425 DELAY(1); 426 SIO_CLR(NGE_MEAR_MII_CLK); 427 DELAY(1); 428 SIO_SET(NGE_MEAR_MII_CLK); 429 } 430 } 431 432 /* 433 * Read an PHY register through the MII. 434 */ 435 static int nge_mii_readreg(sc, frame) 436 struct nge_softc *sc; 437 struct nge_mii_frame *frame; 438 439 { 440 int i, ack, s; 441 442 s = splimp(); 443 444 /* 445 * Set up frame for RX. 446 */ 447 frame->mii_stdelim = NGE_MII_STARTDELIM; 448 frame->mii_opcode = NGE_MII_READOP; 449 frame->mii_turnaround = 0; 450 frame->mii_data = 0; 451 452 CSR_WRITE_4(sc, NGE_MEAR, 0); 453 454 /* 455 * Turn on data xmit. 456 */ 457 SIO_SET(NGE_MEAR_MII_DIR); 458 459 nge_mii_sync(sc); 460 461 /* 462 * Send command/address info. 463 */ 464 nge_mii_send(sc, frame->mii_stdelim, 2); 465 nge_mii_send(sc, frame->mii_opcode, 2); 466 nge_mii_send(sc, frame->mii_phyaddr, 5); 467 nge_mii_send(sc, frame->mii_regaddr, 5); 468 469 /* Idle bit */ 470 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 471 DELAY(1); 472 SIO_SET(NGE_MEAR_MII_CLK); 473 DELAY(1); 474 475 /* Turn off xmit. */ 476 SIO_CLR(NGE_MEAR_MII_DIR); 477 /* Check for ack */ 478 SIO_CLR(NGE_MEAR_MII_CLK); 479 DELAY(1); 480 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 481 SIO_SET(NGE_MEAR_MII_CLK); 482 DELAY(1); 483 484 /* 485 * Now try reading data bits. If the ack failed, we still 486 * need to clock through 16 cycles to keep the PHY(s) in sync. 487 */ 488 if (ack) { 489 for(i = 0; i < 16; i++) { 490 SIO_CLR(NGE_MEAR_MII_CLK); 491 DELAY(1); 492 SIO_SET(NGE_MEAR_MII_CLK); 493 DELAY(1); 494 } 495 goto fail; 496 } 497 498 for (i = 0x8000; i; i >>= 1) { 499 SIO_CLR(NGE_MEAR_MII_CLK); 500 DELAY(1); 501 if (!ack) { 502 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 503 frame->mii_data |= i; 504 DELAY(1); 505 } 506 SIO_SET(NGE_MEAR_MII_CLK); 507 DELAY(1); 508 } 509 510 fail: 511 512 SIO_CLR(NGE_MEAR_MII_CLK); 513 DELAY(1); 514 SIO_SET(NGE_MEAR_MII_CLK); 515 DELAY(1); 516 517 splx(s); 518 519 if (ack) 520 return(1); 521 return(0); 522 } 523 524 /* 525 * Write to a PHY register through the MII. 526 */ 527 static int nge_mii_writereg(sc, frame) 528 struct nge_softc *sc; 529 struct nge_mii_frame *frame; 530 531 { 532 int s; 533 534 s = splimp(); 535 /* 536 * Set up frame for TX. 537 */ 538 539 frame->mii_stdelim = NGE_MII_STARTDELIM; 540 frame->mii_opcode = NGE_MII_WRITEOP; 541 frame->mii_turnaround = NGE_MII_TURNAROUND; 542 543 /* 544 * Turn on data output. 545 */ 546 SIO_SET(NGE_MEAR_MII_DIR); 547 548 nge_mii_sync(sc); 549 550 nge_mii_send(sc, frame->mii_stdelim, 2); 551 nge_mii_send(sc, frame->mii_opcode, 2); 552 nge_mii_send(sc, frame->mii_phyaddr, 5); 553 nge_mii_send(sc, frame->mii_regaddr, 5); 554 nge_mii_send(sc, frame->mii_turnaround, 2); 555 nge_mii_send(sc, frame->mii_data, 16); 556 557 /* Idle bit. */ 558 SIO_SET(NGE_MEAR_MII_CLK); 559 DELAY(1); 560 SIO_CLR(NGE_MEAR_MII_CLK); 561 DELAY(1); 562 563 /* 564 * Turn off xmit. 565 */ 566 SIO_CLR(NGE_MEAR_MII_DIR); 567 568 splx(s); 569 570 return(0); 571 } 572 573 static int nge_miibus_readreg(dev, phy, reg) 574 device_t dev; 575 int phy, reg; 576 { 577 struct nge_softc *sc; 578 struct nge_mii_frame frame; 579 580 sc = device_get_softc(dev); 581 582 bzero((char *)&frame, sizeof(frame)); 583 584 frame.mii_phyaddr = phy; 585 frame.mii_regaddr = reg; 586 nge_mii_readreg(sc, &frame); 587 588 return(frame.mii_data); 589 } 590 591 static int nge_miibus_writereg(dev, phy, reg, data) 592 device_t dev; 593 int phy, reg, data; 594 { 595 struct nge_softc *sc; 596 struct nge_mii_frame frame; 597 598 sc = device_get_softc(dev); 599 600 bzero((char *)&frame, sizeof(frame)); 601 602 frame.mii_phyaddr = phy; 603 frame.mii_regaddr = reg; 604 frame.mii_data = data; 605 nge_mii_writereg(sc, &frame); 606 607 return(0); 608 } 609 610 static void nge_miibus_statchg(dev) 611 device_t dev; 612 { 613 int status; 614 struct nge_softc *sc; 615 struct mii_data *mii; 616 617 sc = device_get_softc(dev); 618 if (sc->nge_tbi) { 619 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 620 == IFM_AUTO) { 621 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 622 if (status == 0 || status & NGE_TBIANAR_FDX) { 623 NGE_SETBIT(sc, NGE_TX_CFG, 624 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 625 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 626 } else { 627 NGE_CLRBIT(sc, NGE_TX_CFG, 628 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 629 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 630 } 631 632 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 633 != IFM_FDX) { 634 NGE_CLRBIT(sc, NGE_TX_CFG, 635 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 636 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 637 } else { 638 NGE_SETBIT(sc, NGE_TX_CFG, 639 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 640 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 641 } 642 } else { 643 mii = device_get_softc(sc->nge_miibus); 644 645 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 646 NGE_SETBIT(sc, NGE_TX_CFG, 647 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 648 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 649 } else { 650 NGE_CLRBIT(sc, NGE_TX_CFG, 651 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 652 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 653 } 654 655 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 656 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 657 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 658 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 659 } else { 660 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 661 } 662 } 663 return; 664 } 665 666 static u_int32_t nge_crc(sc, addr) 667 struct nge_softc *sc; 668 caddr_t addr; 669 { 670 u_int32_t crc, carry; 671 int i, j; 672 u_int8_t c; 673 674 /* Compute CRC for the address value. */ 675 crc = 0xFFFFFFFF; /* initial value */ 676 677 for (i = 0; i < 6; i++) { 678 c = *(addr + i); 679 for (j = 0; j < 8; j++) { 680 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 681 crc <<= 1; 682 c >>= 1; 683 if (carry) 684 crc = (crc ^ 0x04c11db6) | carry; 685 } 686 } 687 688 /* 689 * return the filter bit position 690 */ 691 692 return((crc >> 21) & 0x00000FFF); 693 } 694 695 static void nge_setmulti(sc) 696 struct nge_softc *sc; 697 { 698 struct ifnet *ifp; 699 struct ifmultiaddr *ifma; 700 u_int32_t h = 0, i, filtsave; 701 int bit, index; 702 703 ifp = &sc->arpcom.ac_if; 704 705 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 706 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 707 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 708 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 709 return; 710 } 711 712 /* 713 * We have to explicitly enable the multicast hash table 714 * on the NatSemi chip if we want to use it, which we do. 715 * We also have to tell it that we don't want to use the 716 * hash table for matching unicast addresses. 717 */ 718 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 719 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 720 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 721 722 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 723 724 /* first, zot all the existing hash bits */ 725 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 726 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 727 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 728 } 729 730 /* 731 * From the 11 bits returned by the crc routine, the top 7 732 * bits represent the 16-bit word in the mcast hash table 733 * that needs to be updated, and the lower 4 bits represent 734 * which bit within that byte needs to be set. 735 */ 736 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 737 if (ifma->ifma_addr->sa_family != AF_LINK) 738 continue; 739 h = nge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 740 index = (h >> 4) & 0x7F; 741 bit = h & 0xF; 742 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 743 NGE_FILTADDR_MCAST_LO + (index * 2)); 744 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 745 } 746 747 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 748 749 return; 750 } 751 752 static void nge_reset(sc) 753 struct nge_softc *sc; 754 { 755 int i; 756 757 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 758 759 for (i = 0; i < NGE_TIMEOUT; i++) { 760 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 761 break; 762 } 763 764 if (i == NGE_TIMEOUT) 765 printf("nge%d: reset never completed\n", sc->nge_unit); 766 767 /* Wait a little while for the chip to get its brains in order. */ 768 DELAY(1000); 769 770 /* 771 * If this is a NetSemi chip, make sure to clear 772 * PME mode. 773 */ 774 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 775 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 776 777 return; 778 } 779 780 /* 781 * Probe for an NatSemi chip. Check the PCI vendor and device 782 * IDs against our list and return a device name if we find a match. 783 */ 784 static int nge_probe(dev) 785 device_t dev; 786 { 787 struct nge_type *t; 788 789 t = nge_devs; 790 791 while(t->nge_name != NULL) { 792 if ((pci_get_vendor(dev) == t->nge_vid) && 793 (pci_get_device(dev) == t->nge_did)) { 794 device_set_desc(dev, t->nge_name); 795 return(0); 796 } 797 t++; 798 } 799 800 return(ENXIO); 801 } 802 803 /* 804 * Attach the interface. Allocate softc structures, do ifmedia 805 * setup and ethernet/BPF attach. 806 */ 807 static int nge_attach(dev) 808 device_t dev; 809 { 810 int s; 811 u_char eaddr[ETHER_ADDR_LEN]; 812 u_int32_t command; 813 struct nge_softc *sc; 814 struct ifnet *ifp; 815 int unit, error = 0, rid; 816 const char *sep = ""; 817 818 s = splimp(); 819 820 sc = device_get_softc(dev); 821 unit = device_get_unit(dev); 822 bzero(sc, sizeof(struct nge_softc)); 823 824 /* 825 * Handle power management nonsense. 826 */ 827 828 829 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF; 830 if (command == 0x01) { 831 832 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4); 833 if (command & NGE_PSTATE_MASK) { 834 u_int32_t iobase, membase, irq; 835 836 /* Save important PCI config data. */ 837 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 838 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 839 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 840 841 /* Reset the power state. */ 842 printf("nge%d: chip is in D%d power mode " 843 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK); 844 command &= 0xFFFFFFFC; 845 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4); 846 847 /* Restore PCI config data. */ 848 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 849 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 850 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 851 } 852 } 853 854 /* 855 * Map control/status registers. 856 */ 857 command = pci_read_config(dev, PCIR_COMMAND, 4); 858 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 859 pci_write_config(dev, PCIR_COMMAND, command, 4); 860 command = pci_read_config(dev, PCIR_COMMAND, 4); 861 862 #ifdef NGE_USEIOSPACE 863 if (!(command & PCIM_CMD_PORTEN)) { 864 printf("nge%d: failed to enable I/O ports!\n", unit); 865 error = ENXIO;; 866 goto fail; 867 } 868 #else 869 if (!(command & PCIM_CMD_MEMEN)) { 870 printf("nge%d: failed to enable memory mapping!\n", unit); 871 error = ENXIO;; 872 goto fail; 873 } 874 #endif 875 876 rid = NGE_RID; 877 sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid, 878 0, ~0, 1, RF_ACTIVE); 879 880 if (sc->nge_res == NULL) { 881 printf("nge%d: couldn't map ports/memory\n", unit); 882 error = ENXIO; 883 goto fail; 884 } 885 886 sc->nge_btag = rman_get_bustag(sc->nge_res); 887 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 888 889 /* Allocate interrupt */ 890 rid = 0; 891 sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 892 RF_SHAREABLE | RF_ACTIVE); 893 894 if (sc->nge_irq == NULL) { 895 printf("nge%d: couldn't map interrupt\n", unit); 896 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 897 error = ENXIO; 898 goto fail; 899 } 900 901 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 902 nge_intr, sc, &sc->nge_intrhand); 903 904 if (error) { 905 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 906 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 907 printf("nge%d: couldn't set up irq\n", unit); 908 goto fail; 909 } 910 911 /* Reset the adapter. */ 912 nge_reset(sc); 913 914 /* 915 * Get station address from the EEPROM. 916 */ 917 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 918 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 919 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 920 921 /* 922 * A NatSemi chip was detected. Inform the world. 923 */ 924 printf("nge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 925 926 sc->nge_unit = unit; 927 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 928 929 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 930 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 931 932 if (sc->nge_ldata == NULL) { 933 printf("nge%d: no memory for list buffers!\n", unit); 934 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 935 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 936 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 937 error = ENXIO; 938 goto fail; 939 } 940 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 941 942 /* Try to allocate memory for jumbo buffers. */ 943 if (nge_alloc_jumbo_mem(sc)) { 944 printf("nge%d: jumbo buffer allocation failed\n", 945 sc->nge_unit); 946 contigfree(sc->nge_ldata, 947 sizeof(struct nge_list_data), M_DEVBUF); 948 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 949 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 950 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 951 error = ENXIO; 952 goto fail; 953 } 954 955 ifp = &sc->arpcom.ac_if; 956 ifp->if_softc = sc; 957 if_initname(ifp, "nge", unit); 958 ifp->if_mtu = ETHERMTU; 959 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 960 ifp->if_ioctl = nge_ioctl; 961 ifp->if_output = ether_output; 962 ifp->if_start = nge_start; 963 ifp->if_watchdog = nge_watchdog; 964 ifp->if_init = nge_init; 965 ifp->if_baudrate = 1000000000; 966 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 967 ifp->if_hwassist = NGE_CSUM_FEATURES; 968 ifp->if_capabilities = IFCAP_HWCSUM; 969 ifp->if_capenable = ifp->if_capabilities; 970 971 /* 972 * Do MII setup. 973 */ 974 if (mii_phy_probe(dev, &sc->nge_miibus, 975 nge_ifmedia_upd, nge_ifmedia_sts)) { 976 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 977 sc->nge_tbi = 1; 978 device_printf(dev, "Using TBI\n"); 979 980 sc->nge_miibus = dev; 981 982 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 983 nge_ifmedia_sts); 984 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 985 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 986 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 987 device_printf(dev, " "); 988 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 989 PRINT("1000baseSX"); 990 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 991 PRINT("1000baseSX-FDX"); 992 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 993 PRINT("auto"); 994 995 printf("\n"); 996 #undef ADD 997 #undef PRINT 998 ifmedia_set(&sc->nge_ifmedia, 999 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 1000 1001 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1002 | NGE_GPIO_GP4_OUT 1003 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 1004 | NGE_GPIO_GP3_OUTENB 1005 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 1006 1007 } else { 1008 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 1009 nge_free_jumbo_mem(sc); 1010 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1011 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1012 bus_release_resource(dev, NGE_RES, NGE_RID, 1013 sc->nge_res); 1014 error = ENXIO; 1015 goto fail; 1016 } 1017 } 1018 1019 /* 1020 * Call MI attach routine. 1021 */ 1022 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1023 callout_handle_init(&sc->nge_stat_ch); 1024 1025 fail: 1026 1027 splx(s); 1028 return(error); 1029 } 1030 1031 static int nge_detach(dev) 1032 device_t dev; 1033 { 1034 struct nge_softc *sc; 1035 struct ifnet *ifp; 1036 int s; 1037 1038 s = splimp(); 1039 1040 sc = device_get_softc(dev); 1041 ifp = &sc->arpcom.ac_if; 1042 1043 nge_reset(sc); 1044 nge_stop(sc); 1045 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1046 1047 bus_generic_detach(dev); 1048 if (!sc->nge_tbi) { 1049 device_delete_child(dev, sc->nge_miibus); 1050 } 1051 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1052 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1053 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 1054 1055 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 1056 nge_free_jumbo_mem(sc); 1057 1058 splx(s); 1059 1060 return(0); 1061 } 1062 1063 /* 1064 * Initialize the transmit descriptors. 1065 */ 1066 static int nge_list_tx_init(sc) 1067 struct nge_softc *sc; 1068 { 1069 struct nge_list_data *ld; 1070 struct nge_ring_data *cd; 1071 int i; 1072 1073 cd = &sc->nge_cdata; 1074 ld = sc->nge_ldata; 1075 1076 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1077 if (i == (NGE_TX_LIST_CNT - 1)) { 1078 ld->nge_tx_list[i].nge_nextdesc = 1079 &ld->nge_tx_list[0]; 1080 ld->nge_tx_list[i].nge_next = 1081 vtophys(&ld->nge_tx_list[0]); 1082 } else { 1083 ld->nge_tx_list[i].nge_nextdesc = 1084 &ld->nge_tx_list[i + 1]; 1085 ld->nge_tx_list[i].nge_next = 1086 vtophys(&ld->nge_tx_list[i + 1]); 1087 } 1088 ld->nge_tx_list[i].nge_mbuf = NULL; 1089 ld->nge_tx_list[i].nge_ptr = 0; 1090 ld->nge_tx_list[i].nge_ctl = 0; 1091 } 1092 1093 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1094 1095 return(0); 1096 } 1097 1098 1099 /* 1100 * Initialize the RX descriptors and allocate mbufs for them. Note that 1101 * we arrange the descriptors in a closed ring, so that the last descriptor 1102 * points back to the first. 1103 */ 1104 static int nge_list_rx_init(sc) 1105 struct nge_softc *sc; 1106 { 1107 struct nge_list_data *ld; 1108 struct nge_ring_data *cd; 1109 int i; 1110 1111 ld = sc->nge_ldata; 1112 cd = &sc->nge_cdata; 1113 1114 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1115 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1116 return(ENOBUFS); 1117 if (i == (NGE_RX_LIST_CNT - 1)) { 1118 ld->nge_rx_list[i].nge_nextdesc = 1119 &ld->nge_rx_list[0]; 1120 ld->nge_rx_list[i].nge_next = 1121 vtophys(&ld->nge_rx_list[0]); 1122 } else { 1123 ld->nge_rx_list[i].nge_nextdesc = 1124 &ld->nge_rx_list[i + 1]; 1125 ld->nge_rx_list[i].nge_next = 1126 vtophys(&ld->nge_rx_list[i + 1]); 1127 } 1128 } 1129 1130 cd->nge_rx_prod = 0; 1131 1132 return(0); 1133 } 1134 1135 /* 1136 * Initialize an RX descriptor and attach an MBUF cluster. 1137 */ 1138 static int nge_newbuf(sc, c, m) 1139 struct nge_softc *sc; 1140 struct nge_desc *c; 1141 struct mbuf *m; 1142 { 1143 struct mbuf *m_new = NULL; 1144 caddr_t *buf = NULL; 1145 1146 if (m == NULL) { 1147 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1148 if (m_new == NULL) { 1149 printf("nge%d: no memory for rx list " 1150 "-- packet dropped!\n", sc->nge_unit); 1151 return(ENOBUFS); 1152 } 1153 1154 /* Allocate the jumbo buffer */ 1155 buf = nge_jalloc(sc); 1156 if (buf == NULL) { 1157 #ifdef NGE_VERBOSE 1158 printf("nge%d: jumbo allocation failed " 1159 "-- packet dropped!\n", sc->nge_unit); 1160 #endif 1161 m_freem(m_new); 1162 return(ENOBUFS); 1163 } 1164 /* Attach the buffer to the mbuf */ 1165 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 1166 m_new->m_flags |= M_EXT; 1167 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 1168 m_new->m_len = NGE_MCLBYTES; 1169 m_new->m_ext.ext_free = nge_jfree; 1170 m_new->m_ext.ext_ref = nge_jref; 1171 } else { 1172 m_new = m; 1173 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES; 1174 m_new->m_data = m_new->m_ext.ext_buf; 1175 } 1176 1177 m_adj(m_new, sizeof(u_int64_t)); 1178 1179 c->nge_mbuf = m_new; 1180 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1181 c->nge_ctl = m_new->m_len; 1182 c->nge_extsts = 0; 1183 1184 return(0); 1185 } 1186 1187 static int nge_alloc_jumbo_mem(sc) 1188 struct nge_softc *sc; 1189 { 1190 caddr_t ptr; 1191 int i; 1192 struct nge_jpool_entry *entry; 1193 1194 /* Grab a big chunk o' storage. */ 1195 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1196 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1197 1198 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1199 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1200 return(ENOBUFS); 1201 } 1202 1203 SLIST_INIT(&sc->nge_jfree_listhead); 1204 SLIST_INIT(&sc->nge_jinuse_listhead); 1205 1206 /* 1207 * Now divide it up into 9K pieces and save the addresses 1208 * in an array. 1209 */ 1210 ptr = sc->nge_cdata.nge_jumbo_buf; 1211 for (i = 0; i < NGE_JSLOTS; i++) { 1212 u_int64_t **aptr; 1213 aptr = (u_int64_t **)ptr; 1214 aptr[0] = (u_int64_t *)sc; 1215 ptr += sizeof(u_int64_t); 1216 sc->nge_cdata.nge_jslots[i].nge_buf = ptr; 1217 sc->nge_cdata.nge_jslots[i].nge_inuse = 0; 1218 ptr += NGE_MCLBYTES; 1219 entry = malloc(sizeof(struct nge_jpool_entry), 1220 M_DEVBUF, M_NOWAIT); 1221 if (entry == NULL) { 1222 printf("nge%d: no memory for jumbo " 1223 "buffer queue!\n", sc->nge_unit); 1224 return(ENOBUFS); 1225 } 1226 entry->slot = i; 1227 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1228 entry, jpool_entries); 1229 } 1230 1231 return(0); 1232 } 1233 1234 static void nge_free_jumbo_mem(sc) 1235 struct nge_softc *sc; 1236 { 1237 int i; 1238 struct nge_jpool_entry *entry; 1239 1240 for (i = 0; i < NGE_JSLOTS; i++) { 1241 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1242 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1243 free(entry, M_DEVBUF); 1244 } 1245 1246 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1247 1248 return; 1249 } 1250 1251 /* 1252 * Allocate a jumbo buffer. 1253 */ 1254 static void *nge_jalloc(sc) 1255 struct nge_softc *sc; 1256 { 1257 struct nge_jpool_entry *entry; 1258 1259 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1260 1261 if (entry == NULL) { 1262 #ifdef NGE_VERBOSE 1263 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1264 #endif 1265 return(NULL); 1266 } 1267 1268 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1269 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1270 sc->nge_cdata.nge_jslots[entry->slot].nge_inuse = 1; 1271 return(sc->nge_cdata.nge_jslots[entry->slot].nge_buf); 1272 } 1273 1274 /* 1275 * Adjust usage count on a jumbo buffer. In general this doesn't 1276 * get used much because our jumbo buffers don't get passed around 1277 * a lot, but it's implemented for correctness. 1278 */ 1279 static void nge_jref(buf, size) 1280 caddr_t buf; 1281 u_int size; 1282 { 1283 struct nge_softc *sc; 1284 u_int64_t **aptr; 1285 int i; 1286 1287 /* Extract the softc struct pointer. */ 1288 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 1289 sc = (struct nge_softc *)(aptr[0]); 1290 1291 if (sc == NULL) 1292 panic("nge_jref: can't find softc pointer!"); 1293 1294 if (size != NGE_MCLBYTES) 1295 panic("nge_jref: adjusting refcount of buf of wrong size!"); 1296 1297 /* calculate the slot this buffer belongs to */ 1298 1299 i = ((vm_offset_t)aptr 1300 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1301 1302 if ((i < 0) || (i >= NGE_JSLOTS)) 1303 panic("nge_jref: asked to reference buffer " 1304 "that we don't manage!"); 1305 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0) 1306 panic("nge_jref: buffer already free!"); 1307 else 1308 sc->nge_cdata.nge_jslots[i].nge_inuse++; 1309 1310 return; 1311 } 1312 1313 /* 1314 * Release a jumbo buffer. 1315 */ 1316 static void nge_jfree(buf, size) 1317 caddr_t buf; 1318 u_int size; 1319 { 1320 struct nge_softc *sc; 1321 u_int64_t **aptr; 1322 int i; 1323 struct nge_jpool_entry *entry; 1324 1325 /* Extract the softc struct pointer. */ 1326 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 1327 sc = (struct nge_softc *)(aptr[0]); 1328 1329 if (sc == NULL) 1330 panic("nge_jfree: can't find softc pointer!"); 1331 1332 if (size != NGE_MCLBYTES) 1333 panic("nge_jfree: freeing buffer of wrong size!"); 1334 1335 /* calculate the slot this buffer belongs to */ 1336 1337 i = ((vm_offset_t)aptr 1338 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1339 1340 if ((i < 0) || (i >= NGE_JSLOTS)) 1341 panic("nge_jfree: asked to free buffer that we don't manage!"); 1342 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0) 1343 panic("nge_jfree: buffer already free!"); 1344 else { 1345 sc->nge_cdata.nge_jslots[i].nge_inuse--; 1346 if(sc->nge_cdata.nge_jslots[i].nge_inuse == 0) { 1347 entry = SLIST_FIRST(&sc->nge_jinuse_listhead); 1348 if (entry == NULL) 1349 panic("nge_jfree: buffer not in use!"); 1350 entry->slot = i; 1351 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, 1352 jpool_entries); 1353 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1354 entry, jpool_entries); 1355 } 1356 } 1357 1358 return; 1359 } 1360 /* 1361 * A frame has been uploaded: pass the resulting mbuf chain up to 1362 * the higher level protocols. 1363 */ 1364 static void nge_rxeof(sc) 1365 struct nge_softc *sc; 1366 { 1367 struct ether_header *eh; 1368 struct mbuf *m; 1369 struct ifnet *ifp; 1370 struct nge_desc *cur_rx; 1371 int i, total_len = 0; 1372 u_int32_t rxstat; 1373 1374 ifp = &sc->arpcom.ac_if; 1375 i = sc->nge_cdata.nge_rx_prod; 1376 1377 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1378 struct mbuf *m0 = NULL; 1379 u_int32_t extsts; 1380 1381 #ifdef DEVICE_POLLING 1382 if (ifp->if_ipending & IFF_POLLING) { 1383 if (sc->rxcycles <= 0) 1384 break; 1385 sc->rxcycles--; 1386 } 1387 #endif /* DEVICE_POLLING */ 1388 1389 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1390 rxstat = cur_rx->nge_rxstat; 1391 extsts = cur_rx->nge_extsts; 1392 m = cur_rx->nge_mbuf; 1393 cur_rx->nge_mbuf = NULL; 1394 total_len = NGE_RXBYTES(cur_rx); 1395 NGE_INC(i, NGE_RX_LIST_CNT); 1396 /* 1397 * If an error occurs, update stats, clear the 1398 * status word and leave the mbuf cluster in place: 1399 * it should simply get re-used next time this descriptor 1400 * comes up in the ring. 1401 */ 1402 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1403 ifp->if_ierrors++; 1404 nge_newbuf(sc, cur_rx, m); 1405 continue; 1406 } 1407 1408 /* 1409 * Ok. NatSemi really screwed up here. This is the 1410 * only gigE chip I know of with alignment constraints 1411 * on receive buffers. RX buffers must be 64-bit aligned. 1412 */ 1413 #ifdef __i386__ 1414 /* 1415 * By popular demand, ignore the alignment problems 1416 * on the Intel x86 platform. The performance hit 1417 * incurred due to unaligned accesses is much smaller 1418 * than the hit produced by forcing buffer copies all 1419 * the time, especially with jumbo frames. We still 1420 * need to fix up the alignment everywhere else though. 1421 */ 1422 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1423 #endif 1424 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1425 total_len + ETHER_ALIGN, 0, ifp, NULL); 1426 nge_newbuf(sc, cur_rx, m); 1427 if (m0 == NULL) { 1428 printf("nge%d: no receive buffers " 1429 "available -- packet dropped!\n", 1430 sc->nge_unit); 1431 ifp->if_ierrors++; 1432 continue; 1433 } 1434 m_adj(m0, ETHER_ALIGN); 1435 m = m0; 1436 #ifdef __i386__ 1437 } else { 1438 m->m_pkthdr.rcvif = ifp; 1439 m->m_pkthdr.len = m->m_len = total_len; 1440 } 1441 #endif 1442 1443 ifp->if_ipackets++; 1444 eh = mtod(m, struct ether_header *); 1445 1446 /* Remove header from mbuf and pass it on. */ 1447 m_adj(m, sizeof(struct ether_header)); 1448 1449 /* Do IP checksum checking. */ 1450 if (extsts & NGE_RXEXTSTS_IPPKT) 1451 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1452 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1453 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1454 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1455 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1456 (extsts & NGE_RXEXTSTS_UDPPKT && 1457 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1458 m->m_pkthdr.csum_flags |= 1459 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1460 m->m_pkthdr.csum_data = 0xffff; 1461 } 1462 1463 /* 1464 * If we received a packet with a vlan tag, pass it 1465 * to vlan_input() instead of ether_input(). 1466 */ 1467 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1468 VLAN_INPUT_TAG(eh, m, extsts & NGE_RXEXTSTS_VTCI); 1469 continue; 1470 } 1471 1472 ether_input(ifp, eh, m); 1473 } 1474 1475 sc->nge_cdata.nge_rx_prod = i; 1476 1477 return; 1478 } 1479 1480 /* 1481 * A frame was downloaded to the chip. It's safe for us to clean up 1482 * the list buffers. 1483 */ 1484 1485 static void nge_txeof(sc) 1486 struct nge_softc *sc; 1487 { 1488 struct nge_desc *cur_tx = NULL; 1489 struct ifnet *ifp; 1490 u_int32_t idx; 1491 1492 ifp = &sc->arpcom.ac_if; 1493 1494 /* Clear the timeout timer. */ 1495 ifp->if_timer = 0; 1496 1497 /* 1498 * Go through our tx list and free mbufs for those 1499 * frames that have been transmitted. 1500 */ 1501 idx = sc->nge_cdata.nge_tx_cons; 1502 while (idx != sc->nge_cdata.nge_tx_prod) { 1503 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1504 1505 if (NGE_OWNDESC(cur_tx)) 1506 break; 1507 1508 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1509 sc->nge_cdata.nge_tx_cnt--; 1510 NGE_INC(idx, NGE_TX_LIST_CNT); 1511 continue; 1512 } 1513 1514 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1515 ifp->if_oerrors++; 1516 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1517 ifp->if_collisions++; 1518 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1519 ifp->if_collisions++; 1520 } 1521 1522 ifp->if_collisions += 1523 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1524 1525 ifp->if_opackets++; 1526 if (cur_tx->nge_mbuf != NULL) { 1527 m_freem(cur_tx->nge_mbuf); 1528 cur_tx->nge_mbuf = NULL; 1529 } 1530 1531 sc->nge_cdata.nge_tx_cnt--; 1532 NGE_INC(idx, NGE_TX_LIST_CNT); 1533 ifp->if_timer = 0; 1534 } 1535 1536 sc->nge_cdata.nge_tx_cons = idx; 1537 1538 if (cur_tx != NULL) 1539 ifp->if_flags &= ~IFF_OACTIVE; 1540 1541 return; 1542 } 1543 1544 static void nge_tick(xsc) 1545 void *xsc; 1546 { 1547 struct nge_softc *sc; 1548 struct mii_data *mii; 1549 struct ifnet *ifp; 1550 int s; 1551 1552 s = splimp(); 1553 1554 sc = xsc; 1555 ifp = &sc->arpcom.ac_if; 1556 1557 if (sc->nge_tbi) { 1558 if (!sc->nge_link) { 1559 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1560 & NGE_TBIBMSR_ANEG_DONE) { 1561 printf("nge%d: gigabit link up\n", 1562 sc->nge_unit); 1563 nge_miibus_statchg(sc->nge_miibus); 1564 sc->nge_link++; 1565 if (ifp->if_snd.ifq_head != NULL) 1566 nge_start(ifp); 1567 } 1568 } 1569 } else { 1570 mii = device_get_softc(sc->nge_miibus); 1571 mii_tick(mii); 1572 1573 if (!sc->nge_link) { 1574 if (mii->mii_media_status & IFM_ACTIVE && 1575 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1576 sc->nge_link++; 1577 if (IFM_SUBTYPE(mii->mii_media_active) 1578 == IFM_1000_TX) 1579 printf("nge%d: gigabit link up\n", 1580 sc->nge_unit); 1581 if (ifp->if_snd.ifq_head != NULL) 1582 nge_start(ifp); 1583 } 1584 } 1585 } 1586 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1587 1588 splx(s); 1589 1590 return; 1591 } 1592 1593 #ifdef DEVICE_POLLING 1594 static poll_handler_t nge_poll; 1595 1596 static void 1597 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1598 { 1599 struct nge_softc *sc = ifp->if_softc; 1600 1601 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1602 CSR_WRITE_4(sc, NGE_IER, 1); 1603 return; 1604 } 1605 1606 /* 1607 * On the nge, reading the status register also clears it. 1608 * So before returning to intr mode we must make sure that all 1609 * possible pending sources of interrupts have been served. 1610 * In practice this means run to completion the *eof routines, 1611 * and then call the interrupt routine 1612 */ 1613 sc->rxcycles = count; 1614 nge_rxeof(sc); 1615 nge_txeof(sc); 1616 if (ifp->if_snd.ifq_head != NULL) 1617 nge_start(ifp); 1618 1619 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1620 u_int32_t status; 1621 1622 /* Reading the ISR register clears all interrupts. */ 1623 status = CSR_READ_4(sc, NGE_ISR); 1624 1625 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1626 nge_rxeof(sc); 1627 1628 if (status & (NGE_ISR_RX_IDLE)) 1629 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1630 1631 if (status & NGE_ISR_SYSERR) { 1632 nge_reset(sc); 1633 nge_init(sc); 1634 } 1635 } 1636 } 1637 #endif /* DEVICE_POLLING */ 1638 1639 static void nge_intr(arg) 1640 void *arg; 1641 { 1642 struct nge_softc *sc; 1643 struct ifnet *ifp; 1644 u_int32_t status; 1645 1646 sc = arg; 1647 ifp = &sc->arpcom.ac_if; 1648 1649 #ifdef DEVICE_POLLING 1650 if (ifp->if_ipending & IFF_POLLING) 1651 return; 1652 if (ether_poll_register(nge_poll, ifp)) { /* ok, disable interrupts */ 1653 CSR_WRITE_4(sc, NGE_IER, 0); 1654 nge_poll(ifp, 0, 1); 1655 return; 1656 } 1657 #endif /* DEVICE_POLLING */ 1658 1659 /* Supress unwanted interrupts */ 1660 if (!(ifp->if_flags & IFF_UP)) { 1661 nge_stop(sc); 1662 return; 1663 } 1664 1665 /* Disable interrupts. */ 1666 CSR_WRITE_4(sc, NGE_IER, 0); 1667 1668 /* Data LED on for TBI mode */ 1669 if(sc->nge_tbi) 1670 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1671 | NGE_GPIO_GP3_OUT); 1672 1673 for (;;) { 1674 /* Reading the ISR register clears all interrupts. */ 1675 status = CSR_READ_4(sc, NGE_ISR); 1676 1677 if ((status & NGE_INTRS) == 0) 1678 break; 1679 1680 if ((status & NGE_ISR_TX_DESC_OK) || 1681 (status & NGE_ISR_TX_ERR) || 1682 (status & NGE_ISR_TX_OK) || 1683 (status & NGE_ISR_TX_IDLE)) 1684 nge_txeof(sc); 1685 1686 if ((status & NGE_ISR_RX_DESC_OK) || 1687 (status & NGE_ISR_RX_ERR) || 1688 (status & NGE_ISR_RX_OFLOW) || 1689 (status & NGE_ISR_RX_FIFO_OFLOW) || 1690 (status & NGE_ISR_RX_IDLE) || 1691 (status & NGE_ISR_RX_OK)) 1692 nge_rxeof(sc); 1693 1694 if ((status & NGE_ISR_RX_IDLE)) 1695 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1696 1697 if (status & NGE_ISR_SYSERR) { 1698 nge_reset(sc); 1699 ifp->if_flags &= ~IFF_RUNNING; 1700 nge_init(sc); 1701 } 1702 1703 #ifdef notyet 1704 /* mii_tick should only be called once per second */ 1705 if (status & NGE_ISR_PHY_INTR) { 1706 sc->nge_link = 0; 1707 nge_tick(sc); 1708 } 1709 #endif 1710 } 1711 1712 /* Re-enable interrupts. */ 1713 CSR_WRITE_4(sc, NGE_IER, 1); 1714 1715 if (ifp->if_snd.ifq_head != NULL) 1716 nge_start(ifp); 1717 1718 /* Data LED off for TBI mode */ 1719 1720 if(sc->nge_tbi) 1721 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1722 & ~NGE_GPIO_GP3_OUT); 1723 1724 return; 1725 } 1726 1727 /* 1728 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1729 * pointers to the fragment pointers. 1730 */ 1731 static int nge_encap(sc, m_head, txidx) 1732 struct nge_softc *sc; 1733 struct mbuf *m_head; 1734 u_int32_t *txidx; 1735 { 1736 struct nge_desc *f = NULL; 1737 struct mbuf *m; 1738 int frag, cur, cnt = 0; 1739 struct ifvlan *ifv = NULL; 1740 1741 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1742 m_head->m_pkthdr.rcvif != NULL && 1743 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1744 ifv = m_head->m_pkthdr.rcvif->if_softc; 1745 1746 /* 1747 * Start packing the mbufs in this chain into 1748 * the fragment pointers. Stop when we run out 1749 * of fragments or hit the end of the mbuf chain. 1750 */ 1751 m = m_head; 1752 cur = frag = *txidx; 1753 1754 for (m = m_head; m != NULL; m = m->m_next) { 1755 if (m->m_len != 0) { 1756 if ((NGE_TX_LIST_CNT - 1757 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1758 return(ENOBUFS); 1759 f = &sc->nge_ldata->nge_tx_list[frag]; 1760 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1761 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1762 if (cnt != 0) 1763 f->nge_ctl |= NGE_CMDSTS_OWN; 1764 cur = frag; 1765 NGE_INC(frag, NGE_TX_LIST_CNT); 1766 cnt++; 1767 } 1768 } 1769 1770 if (m != NULL) 1771 return(ENOBUFS); 1772 1773 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1774 if (m_head->m_pkthdr.csum_flags) { 1775 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1776 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1777 NGE_TXEXTSTS_IPCSUM; 1778 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1779 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1780 NGE_TXEXTSTS_TCPCSUM; 1781 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1782 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1783 NGE_TXEXTSTS_UDPCSUM; 1784 } 1785 1786 if (ifv != NULL) { 1787 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1788 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag); 1789 } 1790 1791 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1792 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1793 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1794 sc->nge_cdata.nge_tx_cnt += cnt; 1795 *txidx = frag; 1796 1797 return(0); 1798 } 1799 1800 /* 1801 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1802 * to the mbuf data regions directly in the transmit lists. We also save a 1803 * copy of the pointers since the transmit list fragment pointers are 1804 * physical addresses. 1805 */ 1806 1807 static void nge_start(ifp) 1808 struct ifnet *ifp; 1809 { 1810 struct nge_softc *sc; 1811 struct mbuf *m_head = NULL; 1812 u_int32_t idx; 1813 1814 sc = ifp->if_softc; 1815 1816 if (!sc->nge_link) 1817 return; 1818 1819 idx = sc->nge_cdata.nge_tx_prod; 1820 1821 if (ifp->if_flags & IFF_OACTIVE) 1822 return; 1823 1824 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1825 IF_DEQUEUE(&ifp->if_snd, m_head); 1826 if (m_head == NULL) 1827 break; 1828 1829 if (nge_encap(sc, m_head, &idx)) { 1830 IF_PREPEND(&ifp->if_snd, m_head); 1831 ifp->if_flags |= IFF_OACTIVE; 1832 break; 1833 } 1834 1835 /* 1836 * If there's a BPF listener, bounce a copy of this frame 1837 * to him. 1838 */ 1839 if (ifp->if_bpf) 1840 bpf_mtap(ifp, m_head); 1841 1842 } 1843 1844 /* Transmit */ 1845 sc->nge_cdata.nge_tx_prod = idx; 1846 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1847 1848 /* 1849 * Set a timeout in case the chip goes out to lunch. 1850 */ 1851 ifp->if_timer = 5; 1852 1853 return; 1854 } 1855 1856 static void nge_init(xsc) 1857 void *xsc; 1858 { 1859 struct nge_softc *sc = xsc; 1860 struct ifnet *ifp = &sc->arpcom.ac_if; 1861 struct mii_data *mii; 1862 int s; 1863 1864 if (ifp->if_flags & IFF_RUNNING) 1865 return; 1866 1867 s = splimp(); 1868 1869 /* 1870 * Cancel pending I/O and free all RX/TX buffers. 1871 */ 1872 nge_stop(sc); 1873 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1874 1875 if (sc->nge_tbi) { 1876 mii = NULL; 1877 } else { 1878 mii = device_get_softc(sc->nge_miibus); 1879 } 1880 1881 /* Set MAC address */ 1882 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1883 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1884 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1885 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1886 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1887 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1888 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1889 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1890 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1891 1892 /* Init circular RX list. */ 1893 if (nge_list_rx_init(sc) == ENOBUFS) { 1894 printf("nge%d: initialization failed: no " 1895 "memory for rx buffers\n", sc->nge_unit); 1896 nge_stop(sc); 1897 (void)splx(s); 1898 return; 1899 } 1900 1901 /* 1902 * Init tx descriptors. 1903 */ 1904 nge_list_tx_init(sc); 1905 1906 /* 1907 * For the NatSemi chip, we have to explicitly enable the 1908 * reception of ARP frames, as well as turn on the 'perfect 1909 * match' filter where we store the station address, otherwise 1910 * we won't receive unicasts meant for this host. 1911 */ 1912 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1913 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1914 1915 /* If we want promiscuous mode, set the allframes bit. */ 1916 if (ifp->if_flags & IFF_PROMISC) { 1917 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1918 } else { 1919 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1920 } 1921 1922 /* 1923 * Set the capture broadcast bit to capture broadcast frames. 1924 */ 1925 if (ifp->if_flags & IFF_BROADCAST) { 1926 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1927 } else { 1928 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1929 } 1930 1931 /* 1932 * Load the multicast filter. 1933 */ 1934 nge_setmulti(sc); 1935 1936 /* Turn the receive filter on */ 1937 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1938 1939 /* 1940 * Load the address of the RX and TX lists. 1941 */ 1942 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1943 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1944 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1945 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1946 1947 /* Set RX configuration */ 1948 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1949 /* 1950 * Enable hardware checksum validation for all IPv4 1951 * packets, do not reject packets with bad checksums. 1952 */ 1953 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1954 1955 /* 1956 * Tell the chip to detect and strip VLAN tag info from 1957 * received frames. The tag will be provided in the extsts 1958 * field in the RX descriptors. 1959 */ 1960 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1961 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1962 1963 /* Set TX configuration */ 1964 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1965 1966 /* 1967 * Enable TX IPv4 checksumming on a per-packet basis. 1968 */ 1969 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1970 1971 /* 1972 * Tell the chip to insert VLAN tags on a per-packet basis as 1973 * dictated by the code in the frame encapsulation routine. 1974 */ 1975 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1976 1977 /* Set full/half duplex mode. */ 1978 if (sc->nge_tbi) { 1979 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1980 == IFM_FDX) { 1981 NGE_SETBIT(sc, NGE_TX_CFG, 1982 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1983 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1984 } else { 1985 NGE_CLRBIT(sc, NGE_TX_CFG, 1986 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1987 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1988 } 1989 } else { 1990 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1991 NGE_SETBIT(sc, NGE_TX_CFG, 1992 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1993 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1994 } else { 1995 NGE_CLRBIT(sc, NGE_TX_CFG, 1996 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1997 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1998 } 1999 } 2000 2001 /* 2002 * Enable the delivery of PHY interrupts based on 2003 * link/speed/duplex status changes. Also enable the 2004 * extsts field in the DMA descriptors (needed for 2005 * TCP/IP checksum offload on transmit). 2006 */ 2007 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD| 2008 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 2009 2010 /* 2011 * Configure interrupt holdoff (moderation). We can 2012 * have the chip delay interrupt delivery for a certain 2013 * period. Units are in 100us, and the max setting 2014 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 2015 */ 2016 CSR_WRITE_4(sc, NGE_IHR, 0x01); 2017 2018 /* 2019 * Enable interrupts. 2020 */ 2021 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 2022 #ifdef DEVICE_POLLING 2023 /* 2024 * ... only enable interrupts if we are not polling, make sure 2025 * they are off otherwise. 2026 */ 2027 if (ifp->if_ipending & IFF_POLLING) 2028 CSR_WRITE_4(sc, NGE_IER, 0); 2029 else 2030 #endif /* DEVICE_POLLING */ 2031 CSR_WRITE_4(sc, NGE_IER, 1); 2032 2033 /* Enable receiver and transmitter. */ 2034 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2035 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 2036 2037 nge_ifmedia_upd(ifp); 2038 2039 ifp->if_flags |= IFF_RUNNING; 2040 ifp->if_flags &= ~IFF_OACTIVE; 2041 2042 (void)splx(s); 2043 2044 return; 2045 } 2046 2047 /* 2048 * Set media options. 2049 */ 2050 static int nge_ifmedia_upd(ifp) 2051 struct ifnet *ifp; 2052 { 2053 struct nge_softc *sc; 2054 struct mii_data *mii; 2055 2056 sc = ifp->if_softc; 2057 2058 if (sc->nge_tbi) { 2059 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 2060 == IFM_AUTO) { 2061 CSR_WRITE_4(sc, NGE_TBI_ANAR, 2062 CSR_READ_4(sc, NGE_TBI_ANAR) 2063 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 2064 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 2065 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 2066 | NGE_TBIBMCR_RESTART_ANEG); 2067 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 2068 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 2069 & IFM_GMASK) == IFM_FDX) { 2070 NGE_SETBIT(sc, NGE_TX_CFG, 2071 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2072 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2073 2074 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2075 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2076 } else { 2077 NGE_CLRBIT(sc, NGE_TX_CFG, 2078 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2079 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2080 2081 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2082 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2083 } 2084 2085 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 2086 & ~NGE_GPIO_GP3_OUT); 2087 } else { 2088 mii = device_get_softc(sc->nge_miibus); 2089 sc->nge_link = 0; 2090 if (mii->mii_instance) { 2091 struct mii_softc *miisc; 2092 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2093 miisc = LIST_NEXT(miisc, mii_list)) 2094 mii_phy_reset(miisc); 2095 } 2096 mii_mediachg(mii); 2097 } 2098 2099 return(0); 2100 } 2101 2102 /* 2103 * Report current media status. 2104 */ 2105 static void nge_ifmedia_sts(ifp, ifmr) 2106 struct ifnet *ifp; 2107 struct ifmediareq *ifmr; 2108 { 2109 struct nge_softc *sc; 2110 struct mii_data *mii; 2111 2112 sc = ifp->if_softc; 2113 2114 if (sc->nge_tbi) { 2115 ifmr->ifm_status = IFM_AVALID; 2116 ifmr->ifm_active = IFM_ETHER; 2117 2118 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2119 ifmr->ifm_status |= IFM_ACTIVE; 2120 } 2121 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 2122 ifmr->ifm_active |= IFM_LOOP; 2123 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2124 ifmr->ifm_active |= IFM_NONE; 2125 ifmr->ifm_status = 0; 2126 return; 2127 } 2128 ifmr->ifm_active |= IFM_1000_SX; 2129 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 2130 == IFM_AUTO) { 2131 ifmr->ifm_active |= IFM_AUTO; 2132 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2133 & NGE_TBIANAR_FDX) { 2134 ifmr->ifm_active |= IFM_FDX; 2135 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2136 & NGE_TBIANAR_HDX) { 2137 ifmr->ifm_active |= IFM_HDX; 2138 } 2139 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 2140 == IFM_FDX) 2141 ifmr->ifm_active |= IFM_FDX; 2142 else 2143 ifmr->ifm_active |= IFM_HDX; 2144 2145 } else { 2146 mii = device_get_softc(sc->nge_miibus); 2147 mii_pollstat(mii); 2148 ifmr->ifm_active = mii->mii_media_active; 2149 ifmr->ifm_status = mii->mii_media_status; 2150 } 2151 2152 return; 2153 } 2154 2155 static int nge_ioctl(ifp, command, data) 2156 struct ifnet *ifp; 2157 u_long command; 2158 caddr_t data; 2159 { 2160 struct nge_softc *sc = ifp->if_softc; 2161 struct ifreq *ifr = (struct ifreq *) data; 2162 struct mii_data *mii; 2163 int s, error = 0; 2164 2165 s = splimp(); 2166 2167 switch(command) { 2168 case SIOCSIFADDR: 2169 case SIOCGIFADDR: 2170 error = ether_ioctl(ifp, command, data); 2171 break; 2172 case SIOCSIFMTU: 2173 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 2174 error = EINVAL; 2175 else { 2176 ifp->if_mtu = ifr->ifr_mtu; 2177 /* 2178 * Workaround: if the MTU is larger than 2179 * 8152 (TX FIFO size minus 64 minus 18), turn off 2180 * TX checksum offloading. 2181 */ 2182 if (ifr->ifr_mtu >= 8152) 2183 ifp->if_hwassist = 0; 2184 else 2185 ifp->if_hwassist = NGE_CSUM_FEATURES; 2186 } 2187 break; 2188 case SIOCSIFFLAGS: 2189 if (ifp->if_flags & IFF_UP) { 2190 if (ifp->if_flags & IFF_RUNNING && 2191 ifp->if_flags & IFF_PROMISC && 2192 !(sc->nge_if_flags & IFF_PROMISC)) { 2193 NGE_SETBIT(sc, NGE_RXFILT_CTL, 2194 NGE_RXFILTCTL_ALLPHYS| 2195 NGE_RXFILTCTL_ALLMULTI); 2196 } else if (ifp->if_flags & IFF_RUNNING && 2197 !(ifp->if_flags & IFF_PROMISC) && 2198 sc->nge_if_flags & IFF_PROMISC) { 2199 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2200 NGE_RXFILTCTL_ALLPHYS); 2201 if (!(ifp->if_flags & IFF_ALLMULTI)) 2202 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2203 NGE_RXFILTCTL_ALLMULTI); 2204 } else { 2205 ifp->if_flags &= ~IFF_RUNNING; 2206 nge_init(sc); 2207 } 2208 } else { 2209 if (ifp->if_flags & IFF_RUNNING) 2210 nge_stop(sc); 2211 } 2212 sc->nge_if_flags = ifp->if_flags; 2213 error = 0; 2214 break; 2215 case SIOCADDMULTI: 2216 case SIOCDELMULTI: 2217 nge_setmulti(sc); 2218 error = 0; 2219 break; 2220 case SIOCGIFMEDIA: 2221 case SIOCSIFMEDIA: 2222 if (sc->nge_tbi) { 2223 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 2224 command); 2225 } else { 2226 mii = device_get_softc(sc->nge_miibus); 2227 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2228 command); 2229 } 2230 break; 2231 default: 2232 error = EINVAL; 2233 break; 2234 } 2235 2236 (void)splx(s); 2237 2238 return(error); 2239 } 2240 2241 static void nge_watchdog(ifp) 2242 struct ifnet *ifp; 2243 { 2244 struct nge_softc *sc; 2245 2246 sc = ifp->if_softc; 2247 2248 ifp->if_oerrors++; 2249 printf("nge%d: watchdog timeout\n", sc->nge_unit); 2250 2251 nge_stop(sc); 2252 nge_reset(sc); 2253 ifp->if_flags &= ~IFF_RUNNING; 2254 nge_init(sc); 2255 2256 if (ifp->if_snd.ifq_head != NULL) 2257 nge_start(ifp); 2258 2259 return; 2260 } 2261 2262 /* 2263 * Stop the adapter and free any mbufs allocated to the 2264 * RX and TX lists. 2265 */ 2266 static void nge_stop(sc) 2267 struct nge_softc *sc; 2268 { 2269 int i; 2270 struct ifnet *ifp; 2271 struct ifmedia_entry *ifm; 2272 struct mii_data *mii; 2273 int mtmp, itmp; 2274 2275 ifp = &sc->arpcom.ac_if; 2276 ifp->if_timer = 0; 2277 if (sc->nge_tbi) { 2278 mii = NULL; 2279 } else { 2280 mii = device_get_softc(sc->nge_miibus); 2281 } 2282 2283 untimeout(nge_tick, sc, sc->nge_stat_ch); 2284 #ifdef DEVICE_POLLING 2285 ether_poll_deregister(ifp); 2286 #endif 2287 CSR_WRITE_4(sc, NGE_IER, 0); 2288 CSR_WRITE_4(sc, NGE_IMR, 0); 2289 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2290 DELAY(1000); 2291 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2292 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2293 2294 /* 2295 * Isolate/power down the PHY, but leave the media selection 2296 * unchanged so that things will be put back to normal when 2297 * we bring the interface back up. 2298 */ 2299 itmp = ifp->if_flags; 2300 ifp->if_flags |= IFF_UP; 2301 2302 if (sc->nge_tbi) 2303 ifm = sc->nge_ifmedia.ifm_cur; 2304 else 2305 ifm = mii->mii_media.ifm_cur; 2306 2307 mtmp = ifm->ifm_media; 2308 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2309 2310 if (!sc->nge_tbi) 2311 mii_mediachg(mii); 2312 ifm->ifm_media = mtmp; 2313 ifp->if_flags = itmp; 2314 2315 sc->nge_link = 0; 2316 2317 /* 2318 * Free data in the RX lists. 2319 */ 2320 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2321 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2322 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2323 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2324 } 2325 } 2326 bzero((char *)&sc->nge_ldata->nge_rx_list, 2327 sizeof(sc->nge_ldata->nge_rx_list)); 2328 2329 /* 2330 * Free the TX list buffers. 2331 */ 2332 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2333 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2334 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2335 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2336 } 2337 } 2338 2339 bzero((char *)&sc->nge_ldata->nge_tx_list, 2340 sizeof(sc->nge_ldata->nge_tx_list)); 2341 2342 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2343 2344 return; 2345 } 2346 2347 /* 2348 * Stop all chip I/O so that the kernel's probe routines don't 2349 * get confused by errant DMAs when rebooting. 2350 */ 2351 static void nge_shutdown(dev) 2352 device_t dev; 2353 { 2354 struct nge_softc *sc; 2355 2356 sc = device_get_softc(dev); 2357 2358 nge_reset(sc); 2359 nge_stop(sc); 2360 2361 return; 2362 } 2363