1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $ 34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.46 2008/03/10 12:59:51 sephe Exp $ 35 */ 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #include "opt_polling.h" 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/sockio.h> 96 #include <sys/mbuf.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 #include <sys/serialize.h> 101 #include <sys/bus.h> 102 #include <sys/rman.h> 103 #include <sys/thread2.h> 104 105 #include <net/if.h> 106 #include <net/ifq_var.h> 107 #include <net/if_arp.h> 108 #include <net/ethernet.h> 109 #include <net/if_dl.h> 110 #include <net/if_media.h> 111 #include <net/if_types.h> 112 #include <net/vlan/if_vlan_var.h> 113 #include <net/vlan/if_vlan_ether.h> 114 115 #include <net/bpf.h> 116 117 #include <vm/vm.h> /* for vtophys */ 118 #include <vm/pmap.h> /* for vtophys */ 119 120 #include <dev/netif/mii_layer/mii.h> 121 #include <dev/netif/mii_layer/miivar.h> 122 123 #include <bus/pci/pcidevs.h> 124 #include <bus/pci/pcireg.h> 125 #include <bus/pci/pcivar.h> 126 127 #define NGE_USEIOSPACE 128 129 #include "if_ngereg.h" 130 131 132 /* "controller miibus0" required. See GENERIC if you get errors here. */ 133 #include "miibus_if.h" 134 135 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 136 137 /* 138 * Various supported device vendors/types and their names. 139 */ 140 static struct nge_type nge_devs[] = { 141 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 142 "National Semiconductor Gigabit Ethernet" }, 143 { 0, 0, NULL } 144 }; 145 146 static int nge_probe(device_t); 147 static int nge_attach(device_t); 148 static int nge_detach(device_t); 149 150 static int nge_alloc_jumbo_mem(struct nge_softc *); 151 static struct nge_jslot 152 *nge_jalloc(struct nge_softc *); 153 static void nge_jfree(void *); 154 static void nge_jref(void *); 155 156 static int nge_newbuf(struct nge_softc *, struct nge_desc *, 157 struct mbuf *); 158 static int nge_encap(struct nge_softc *, struct mbuf *, uint32_t *); 159 static void nge_rxeof(struct nge_softc *); 160 static void nge_txeof(struct nge_softc *); 161 static void nge_intr(void *); 162 static void nge_tick(void *); 163 static void nge_start(struct ifnet *); 164 static int nge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 165 static void nge_init(void *); 166 static void nge_stop(struct nge_softc *); 167 static void nge_watchdog(struct ifnet *); 168 static void nge_shutdown(device_t); 169 static int nge_ifmedia_upd(struct ifnet *); 170 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 171 172 static void nge_delay(struct nge_softc *); 173 static void nge_eeprom_idle(struct nge_softc *); 174 static void nge_eeprom_putbyte(struct nge_softc *, int); 175 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *); 176 static void nge_read_eeprom(struct nge_softc *, void *, int, int); 177 178 static void nge_mii_sync(struct nge_softc *); 179 static void nge_mii_send(struct nge_softc *, uint32_t, int); 180 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *); 181 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *); 182 183 static int nge_miibus_readreg(device_t, int, int); 184 static int nge_miibus_writereg(device_t, int, int, int); 185 static void nge_miibus_statchg(device_t); 186 187 static void nge_setmulti(struct nge_softc *); 188 static void nge_reset(struct nge_softc *); 189 static int nge_list_rx_init(struct nge_softc *); 190 static int nge_list_tx_init(struct nge_softc *); 191 #ifdef DEVICE_POLLING 192 static void nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 193 #endif 194 195 #ifdef NGE_USEIOSPACE 196 #define NGE_RES SYS_RES_IOPORT 197 #define NGE_RID NGE_PCI_LOIO 198 #else 199 #define NGE_RES SYS_RES_MEMORY 200 #define NGE_RID NGE_PCI_LOMEM 201 #endif 202 203 static device_method_t nge_methods[] = { 204 /* Device interface */ 205 DEVMETHOD(device_probe, nge_probe), 206 DEVMETHOD(device_attach, nge_attach), 207 DEVMETHOD(device_detach, nge_detach), 208 DEVMETHOD(device_shutdown, nge_shutdown), 209 210 /* bus interface */ 211 DEVMETHOD(bus_print_child, bus_generic_print_child), 212 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 213 214 /* MII interface */ 215 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 216 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 217 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 218 219 { 0, 0 } 220 }; 221 222 static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc)); 223 static devclass_t nge_devclass; 224 225 DECLARE_DUMMY_MODULE(if_nge); 226 MODULE_DEPEND(if_nge, miibus, 1, 1, 1); 227 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 228 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 229 230 #define NGE_SETBIT(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 232 233 #define NGE_CLRBIT(sc, reg, x) \ 234 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 235 236 #define SIO_SET(x) \ 237 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 238 239 #define SIO_CLR(x) \ 240 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 241 242 static void 243 nge_delay(struct nge_softc *sc) 244 { 245 int idx; 246 247 for (idx = (300 / 33) + 1; idx > 0; idx--) 248 CSR_READ_4(sc, NGE_CSR); 249 } 250 251 static void 252 nge_eeprom_idle(struct nge_softc *sc) 253 { 254 int i; 255 256 SIO_SET(NGE_MEAR_EE_CSEL); 257 nge_delay(sc); 258 SIO_SET(NGE_MEAR_EE_CLK); 259 nge_delay(sc); 260 261 for (i = 0; i < 25; i++) { 262 SIO_CLR(NGE_MEAR_EE_CLK); 263 nge_delay(sc); 264 SIO_SET(NGE_MEAR_EE_CLK); 265 nge_delay(sc); 266 } 267 268 SIO_CLR(NGE_MEAR_EE_CLK); 269 nge_delay(sc); 270 SIO_CLR(NGE_MEAR_EE_CSEL); 271 nge_delay(sc); 272 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 273 } 274 275 /* 276 * Send a read command and address to the EEPROM, check for ACK. 277 */ 278 static void 279 nge_eeprom_putbyte(struct nge_softc *sc, int addr) 280 { 281 int d, i; 282 283 d = addr | NGE_EECMD_READ; 284 285 /* 286 * Feed in each bit and stobe the clock. 287 */ 288 for (i = 0x400; i; i >>= 1) { 289 if (d & i) 290 SIO_SET(NGE_MEAR_EE_DIN); 291 else 292 SIO_CLR(NGE_MEAR_EE_DIN); 293 nge_delay(sc); 294 SIO_SET(NGE_MEAR_EE_CLK); 295 nge_delay(sc); 296 SIO_CLR(NGE_MEAR_EE_CLK); 297 nge_delay(sc); 298 } 299 } 300 301 /* 302 * Read a word of data stored in the EEPROM at address 'addr.' 303 */ 304 static void 305 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest) 306 { 307 int i; 308 uint16_t word = 0; 309 310 /* Force EEPROM to idle state. */ 311 nge_eeprom_idle(sc); 312 313 /* Enter EEPROM access mode. */ 314 nge_delay(sc); 315 SIO_CLR(NGE_MEAR_EE_CLK); 316 nge_delay(sc); 317 SIO_SET(NGE_MEAR_EE_CSEL); 318 nge_delay(sc); 319 320 /* 321 * Send address of word we want to read. 322 */ 323 nge_eeprom_putbyte(sc, addr); 324 325 /* 326 * Start reading bits from EEPROM. 327 */ 328 for (i = 0x8000; i; i >>= 1) { 329 SIO_SET(NGE_MEAR_EE_CLK); 330 nge_delay(sc); 331 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 332 word |= i; 333 nge_delay(sc); 334 SIO_CLR(NGE_MEAR_EE_CLK); 335 nge_delay(sc); 336 } 337 338 /* Turn off EEPROM access mode. */ 339 nge_eeprom_idle(sc); 340 341 *dest = word; 342 } 343 344 /* 345 * Read a sequence of words from the EEPROM. 346 */ 347 static void 348 nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt) 349 { 350 int i; 351 uint16_t word = 0, *ptr; 352 353 for (i = 0; i < cnt; i++) { 354 nge_eeprom_getword(sc, off + i, &word); 355 ptr = (uint16_t *)((uint8_t *)dest + (i * 2)); 356 *ptr = word; 357 } 358 } 359 360 /* 361 * Sync the PHYs by setting data bit and strobing the clock 32 times. 362 */ 363 static void 364 nge_mii_sync(struct nge_softc *sc) 365 { 366 int i; 367 368 SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA); 369 370 for (i = 0; i < 32; i++) { 371 SIO_SET(NGE_MEAR_MII_CLK); 372 DELAY(1); 373 SIO_CLR(NGE_MEAR_MII_CLK); 374 DELAY(1); 375 } 376 } 377 378 /* 379 * Clock a series of bits through the MII. 380 */ 381 static void 382 nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt) 383 { 384 int i; 385 386 SIO_CLR(NGE_MEAR_MII_CLK); 387 388 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 389 if (bits & i) 390 SIO_SET(NGE_MEAR_MII_DATA); 391 else 392 SIO_CLR(NGE_MEAR_MII_DATA); 393 DELAY(1); 394 SIO_CLR(NGE_MEAR_MII_CLK); 395 DELAY(1); 396 SIO_SET(NGE_MEAR_MII_CLK); 397 } 398 } 399 400 /* 401 * Read an PHY register through the MII. 402 */ 403 static int 404 nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame) 405 { 406 int ack, i; 407 408 /* 409 * Set up frame for RX. 410 */ 411 frame->mii_stdelim = NGE_MII_STARTDELIM; 412 frame->mii_opcode = NGE_MII_READOP; 413 frame->mii_turnaround = 0; 414 frame->mii_data = 0; 415 416 CSR_WRITE_4(sc, NGE_MEAR, 0); 417 418 /* 419 * Turn on data xmit. 420 */ 421 SIO_SET(NGE_MEAR_MII_DIR); 422 423 nge_mii_sync(sc); 424 425 /* 426 * Send command/address info. 427 */ 428 nge_mii_send(sc, frame->mii_stdelim, 2); 429 nge_mii_send(sc, frame->mii_opcode, 2); 430 nge_mii_send(sc, frame->mii_phyaddr, 5); 431 nge_mii_send(sc, frame->mii_regaddr, 5); 432 433 /* Idle bit */ 434 SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA)); 435 DELAY(1); 436 SIO_SET(NGE_MEAR_MII_CLK); 437 DELAY(1); 438 439 /* Turn off xmit. */ 440 SIO_CLR(NGE_MEAR_MII_DIR); 441 /* Check for ack */ 442 SIO_CLR(NGE_MEAR_MII_CLK); 443 DELAY(1); 444 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 445 SIO_SET(NGE_MEAR_MII_CLK); 446 DELAY(1); 447 448 /* 449 * Now try reading data bits. If the ack failed, we still 450 * need to clock through 16 cycles to keep the PHY(s) in sync. 451 */ 452 if (ack) { 453 for(i = 0; i < 16; i++) { 454 SIO_CLR(NGE_MEAR_MII_CLK); 455 DELAY(1); 456 SIO_SET(NGE_MEAR_MII_CLK); 457 DELAY(1); 458 } 459 goto fail; 460 } 461 462 for (i = 0x8000; i; i >>= 1) { 463 SIO_CLR(NGE_MEAR_MII_CLK); 464 DELAY(1); 465 if (!ack) { 466 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 467 frame->mii_data |= i; 468 DELAY(1); 469 } 470 SIO_SET(NGE_MEAR_MII_CLK); 471 DELAY(1); 472 } 473 474 fail: 475 SIO_CLR(NGE_MEAR_MII_CLK); 476 DELAY(1); 477 SIO_SET(NGE_MEAR_MII_CLK); 478 DELAY(1); 479 480 if (ack) 481 return(1); 482 return(0); 483 } 484 485 /* 486 * Write to a PHY register through the MII. 487 */ 488 static int 489 nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame) 490 { 491 /* 492 * Set up frame for TX. 493 */ 494 495 frame->mii_stdelim = NGE_MII_STARTDELIM; 496 frame->mii_opcode = NGE_MII_WRITEOP; 497 frame->mii_turnaround = NGE_MII_TURNAROUND; 498 499 /* 500 * Turn on data output. 501 */ 502 SIO_SET(NGE_MEAR_MII_DIR); 503 504 nge_mii_sync(sc); 505 506 nge_mii_send(sc, frame->mii_stdelim, 2); 507 nge_mii_send(sc, frame->mii_opcode, 2); 508 nge_mii_send(sc, frame->mii_phyaddr, 5); 509 nge_mii_send(sc, frame->mii_regaddr, 5); 510 nge_mii_send(sc, frame->mii_turnaround, 2); 511 nge_mii_send(sc, frame->mii_data, 16); 512 513 /* Idle bit. */ 514 SIO_SET(NGE_MEAR_MII_CLK); 515 DELAY(1); 516 SIO_CLR(NGE_MEAR_MII_CLK); 517 DELAY(1); 518 519 /* 520 * Turn off xmit. 521 */ 522 SIO_CLR(NGE_MEAR_MII_DIR); 523 524 return(0); 525 } 526 527 static int 528 nge_miibus_readreg(device_t dev, int phy, int reg) 529 { 530 struct nge_softc *sc = device_get_softc(dev); 531 struct nge_mii_frame frame; 532 533 bzero((char *)&frame, sizeof(frame)); 534 535 frame.mii_phyaddr = phy; 536 frame.mii_regaddr = reg; 537 nge_mii_readreg(sc, &frame); 538 539 return(frame.mii_data); 540 } 541 542 static int 543 nge_miibus_writereg(device_t dev, int phy, int reg, int data) 544 { 545 struct nge_softc *sc = device_get_softc(dev); 546 struct nge_mii_frame frame; 547 548 bzero((char *)&frame, sizeof(frame)); 549 550 frame.mii_phyaddr = phy; 551 frame.mii_regaddr = reg; 552 frame.mii_data = data; 553 nge_mii_writereg(sc, &frame); 554 555 return(0); 556 } 557 558 static void 559 nge_miibus_statchg(device_t dev) 560 { 561 struct nge_softc *sc = device_get_softc(dev); 562 struct mii_data *mii; 563 int status; 564 565 if (sc->nge_tbi) { 566 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 567 == IFM_AUTO) { 568 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 569 if (status == 0 || status & NGE_TBIANAR_FDX) { 570 NGE_SETBIT(sc, NGE_TX_CFG, 571 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 572 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 573 } else { 574 NGE_CLRBIT(sc, NGE_TX_CFG, 575 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 576 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 577 } 578 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 579 != IFM_FDX) { 580 NGE_CLRBIT(sc, NGE_TX_CFG, 581 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 582 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 583 } else { 584 NGE_SETBIT(sc, NGE_TX_CFG, 585 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 586 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 587 } 588 } else { 589 mii = device_get_softc(sc->nge_miibus); 590 591 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 592 NGE_SETBIT(sc, NGE_TX_CFG, 593 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 594 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 595 } else { 596 NGE_CLRBIT(sc, NGE_TX_CFG, 597 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 598 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 599 } 600 601 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 602 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 603 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 604 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 605 } else { 606 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 607 } 608 } 609 } 610 611 static void 612 nge_setmulti(struct nge_softc *sc) 613 { 614 struct ifnet *ifp = &sc->arpcom.ac_if; 615 struct ifmultiaddr *ifma; 616 uint32_t filtsave, h = 0, i; 617 int bit, index; 618 619 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 620 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 621 NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH); 622 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 623 return; 624 } 625 626 /* 627 * We have to explicitly enable the multicast hash table 628 * on the NatSemi chip if we want to use it, which we do. 629 * We also have to tell it that we don't want to use the 630 * hash table for matching unicast addresses. 631 */ 632 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 633 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 634 NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH); 635 636 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 637 638 /* first, zot all the existing hash bits */ 639 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 640 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 641 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 642 } 643 644 /* 645 * From the 11 bits returned by the crc routine, the top 7 646 * bits represent the 16-bit word in the mcast hash table 647 * that needs to be updated, and the lower 4 bits represent 648 * which bit within that byte needs to be set. 649 */ 650 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 651 if (ifma->ifma_addr->sa_family != AF_LINK) 652 continue; 653 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 654 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21; 655 index = (h >> 4) & 0x7F; 656 bit = h & 0xF; 657 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 658 NGE_FILTADDR_MCAST_LO + (index * 2)); 659 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 660 } 661 662 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 663 } 664 665 static void 666 nge_reset(struct nge_softc *sc) 667 { 668 int i; 669 670 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 671 672 for (i = 0; i < NGE_TIMEOUT; i++) { 673 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0) 674 break; 675 } 676 677 if (i == NGE_TIMEOUT) 678 kprintf("nge%d: reset never completed\n", sc->nge_unit); 679 680 /* Wait a little while for the chip to get its brains in order. */ 681 DELAY(1000); 682 683 /* 684 * If this is a NetSemi chip, make sure to clear 685 * PME mode. 686 */ 687 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 688 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 689 } 690 691 /* 692 * Probe for an NatSemi chip. Check the PCI vendor and device 693 * IDs against our list and return a device name if we find a match. 694 */ 695 static int 696 nge_probe(device_t dev) 697 { 698 struct nge_type *t; 699 uint16_t vendor, product; 700 701 vendor = pci_get_vendor(dev); 702 product = pci_get_device(dev); 703 704 for (t = nge_devs; t->nge_name != NULL; t++) { 705 if (vendor == t->nge_vid && product == t->nge_did) { 706 device_set_desc(dev, t->nge_name); 707 return(0); 708 } 709 } 710 711 return(ENXIO); 712 } 713 714 /* 715 * Attach the interface. Allocate softc structures, do ifmedia 716 * setup and ethernet/BPF attach. 717 */ 718 static int 719 nge_attach(device_t dev) 720 { 721 struct nge_softc *sc; 722 struct ifnet *ifp; 723 uint8_t eaddr[ETHER_ADDR_LEN]; 724 uint32_t command; 725 int error = 0, rid, unit; 726 const char *sep = ""; 727 728 sc = device_get_softc(dev); 729 unit = device_get_unit(dev); 730 callout_init(&sc->nge_stat_timer); 731 lwkt_serialize_init(&sc->nge_jslot_serializer); 732 733 /* 734 * Handle power management nonsense. 735 */ 736 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF; 737 if (command == 0x01) { 738 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4); 739 if (command & NGE_PSTATE_MASK) { 740 uint32_t iobase, membase, irq; 741 742 /* Save important PCI config data. */ 743 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 744 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 745 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 746 747 /* Reset the power state. */ 748 kprintf("nge%d: chip is in D%d power mode " 749 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK); 750 command &= 0xFFFFFFFC; 751 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4); 752 753 /* Restore PCI config data. */ 754 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 755 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 756 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 757 } 758 } 759 760 /* 761 * Map control/status registers. 762 */ 763 command = pci_read_config(dev, PCIR_COMMAND, 4); 764 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 765 pci_write_config(dev, PCIR_COMMAND, command, 4); 766 command = pci_read_config(dev, PCIR_COMMAND, 4); 767 768 #ifdef NGE_USEIOSPACE 769 if (!(command & PCIM_CMD_PORTEN)) { 770 kprintf("nge%d: failed to enable I/O ports!\n", unit); 771 error = ENXIO; 772 return(error); 773 } 774 #else 775 if (!(command & PCIM_CMD_MEMEN)) { 776 kprintf("nge%d: failed to enable memory mapping!\n", unit); 777 error = ENXIO; 778 return(error); 779 } 780 #endif 781 782 rid = NGE_RID; 783 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE); 784 785 if (sc->nge_res == NULL) { 786 kprintf("nge%d: couldn't map ports/memory\n", unit); 787 error = ENXIO; 788 return(error); 789 } 790 791 sc->nge_btag = rman_get_bustag(sc->nge_res); 792 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 793 794 /* Allocate interrupt */ 795 rid = 0; 796 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 797 RF_SHAREABLE | RF_ACTIVE); 798 799 if (sc->nge_irq == NULL) { 800 kprintf("nge%d: couldn't map interrupt\n", unit); 801 error = ENXIO; 802 goto fail; 803 } 804 805 /* Reset the adapter. */ 806 nge_reset(sc); 807 808 /* 809 * Get station address from the EEPROM. 810 */ 811 nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1); 812 nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1); 813 nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1); 814 815 sc->nge_unit = unit; 816 817 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 818 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 819 820 if (sc->nge_ldata == NULL) { 821 kprintf("nge%d: no memory for list buffers!\n", unit); 822 error = ENXIO; 823 goto fail; 824 } 825 826 /* Try to allocate memory for jumbo buffers. */ 827 if (nge_alloc_jumbo_mem(sc)) { 828 kprintf("nge%d: jumbo buffer allocation failed\n", 829 sc->nge_unit); 830 error = ENXIO; 831 goto fail; 832 } 833 834 ifp = &sc->arpcom.ac_if; 835 ifp->if_softc = sc; 836 if_initname(ifp, "nge", unit); 837 ifp->if_mtu = ETHERMTU; 838 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 839 ifp->if_ioctl = nge_ioctl; 840 ifp->if_start = nge_start; 841 #ifdef DEVICE_POLLING 842 ifp->if_poll = nge_poll; 843 #endif 844 ifp->if_watchdog = nge_watchdog; 845 ifp->if_init = nge_init; 846 ifp->if_baudrate = 1000000000; 847 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1); 848 ifq_set_ready(&ifp->if_snd); 849 ifp->if_hwassist = NGE_CSUM_FEATURES; 850 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING; 851 ifp->if_capenable = ifp->if_capabilities; 852 853 /* 854 * Do MII setup. 855 */ 856 if (mii_phy_probe(dev, &sc->nge_miibus, 857 nge_ifmedia_upd, nge_ifmedia_sts)) { 858 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 859 sc->nge_tbi = 1; 860 device_printf(dev, "Using TBI\n"); 861 862 sc->nge_miibus = dev; 863 864 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 865 nge_ifmedia_sts); 866 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 867 #define PRINT(s) kprintf("%s%s", sep, s); sep = ", " 868 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 869 device_printf(dev, " "); 870 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 871 PRINT("1000baseSX"); 872 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 873 PRINT("1000baseSX-FDX"); 874 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 875 PRINT("auto"); 876 877 kprintf("\n"); 878 #undef ADD 879 #undef PRINT 880 ifmedia_set(&sc->nge_ifmedia, 881 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 882 883 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 884 | NGE_GPIO_GP4_OUT 885 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 886 | NGE_GPIO_GP3_OUTENB 887 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 888 889 } else { 890 kprintf("nge%d: MII without any PHY!\n", sc->nge_unit); 891 error = ENXIO; 892 goto fail; 893 } 894 } 895 896 /* 897 * Call MI attach routine. 898 */ 899 ether_ifattach(ifp, eaddr, NULL); 900 901 error = bus_setup_intr(dev, sc->nge_irq, INTR_NETSAFE, 902 nge_intr, sc, &sc->nge_intrhand, 903 ifp->if_serializer); 904 if (error) { 905 ether_ifdetach(ifp); 906 device_printf(dev, "couldn't set up irq\n"); 907 goto fail; 908 } 909 910 return(0); 911 fail: 912 nge_detach(dev); 913 return(error); 914 } 915 916 static int 917 nge_detach(device_t dev) 918 { 919 struct nge_softc *sc = device_get_softc(dev); 920 struct ifnet *ifp = &sc->arpcom.ac_if; 921 922 if (device_is_attached(dev)) { 923 lwkt_serialize_enter(ifp->if_serializer); 924 nge_reset(sc); 925 nge_stop(sc); 926 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 927 lwkt_serialize_exit(ifp->if_serializer); 928 929 ether_ifdetach(ifp); 930 } 931 932 if (sc->nge_miibus) 933 device_delete_child(dev, sc->nge_miibus); 934 bus_generic_detach(dev); 935 936 if (sc->nge_irq) 937 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 938 if (sc->nge_res) 939 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 940 if (sc->nge_ldata) { 941 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), 942 M_DEVBUF); 943 } 944 if (sc->nge_cdata.nge_jumbo_buf) 945 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 946 947 return(0); 948 } 949 950 /* 951 * Initialize the transmit descriptors. 952 */ 953 static int 954 nge_list_tx_init(struct nge_softc *sc) 955 { 956 struct nge_list_data *ld; 957 struct nge_ring_data *cd; 958 int i; 959 960 cd = &sc->nge_cdata; 961 ld = sc->nge_ldata; 962 963 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 964 if (i == (NGE_TX_LIST_CNT - 1)) { 965 ld->nge_tx_list[i].nge_nextdesc = 966 &ld->nge_tx_list[0]; 967 ld->nge_tx_list[i].nge_next = 968 vtophys(&ld->nge_tx_list[0]); 969 } else { 970 ld->nge_tx_list[i].nge_nextdesc = 971 &ld->nge_tx_list[i + 1]; 972 ld->nge_tx_list[i].nge_next = 973 vtophys(&ld->nge_tx_list[i + 1]); 974 } 975 ld->nge_tx_list[i].nge_mbuf = NULL; 976 ld->nge_tx_list[i].nge_ptr = 0; 977 ld->nge_tx_list[i].nge_ctl = 0; 978 } 979 980 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 981 982 return(0); 983 } 984 985 986 /* 987 * Initialize the RX descriptors and allocate mbufs for them. Note that 988 * we arrange the descriptors in a closed ring, so that the last descriptor 989 * points back to the first. 990 */ 991 static int 992 nge_list_rx_init(struct nge_softc *sc) 993 { 994 struct nge_list_data *ld; 995 struct nge_ring_data *cd; 996 int i; 997 998 ld = sc->nge_ldata; 999 cd = &sc->nge_cdata; 1000 1001 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1002 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1003 return(ENOBUFS); 1004 if (i == (NGE_RX_LIST_CNT - 1)) { 1005 ld->nge_rx_list[i].nge_nextdesc = 1006 &ld->nge_rx_list[0]; 1007 ld->nge_rx_list[i].nge_next = 1008 vtophys(&ld->nge_rx_list[0]); 1009 } else { 1010 ld->nge_rx_list[i].nge_nextdesc = 1011 &ld->nge_rx_list[i + 1]; 1012 ld->nge_rx_list[i].nge_next = 1013 vtophys(&ld->nge_rx_list[i + 1]); 1014 } 1015 } 1016 1017 cd->nge_rx_prod = 0; 1018 1019 return(0); 1020 } 1021 1022 /* 1023 * Initialize an RX descriptor and attach an MBUF cluster. 1024 */ 1025 static int 1026 nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m) 1027 { 1028 struct mbuf *m_new = NULL; 1029 struct nge_jslot *buf; 1030 1031 if (m == NULL) { 1032 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1033 if (m_new == NULL) { 1034 kprintf("nge%d: no memory for rx list " 1035 "-- packet dropped!\n", sc->nge_unit); 1036 return(ENOBUFS); 1037 } 1038 1039 /* Allocate the jumbo buffer */ 1040 buf = nge_jalloc(sc); 1041 if (buf == NULL) { 1042 #ifdef NGE_VERBOSE 1043 kprintf("nge%d: jumbo allocation failed " 1044 "-- packet dropped!\n", sc->nge_unit); 1045 #endif 1046 m_freem(m_new); 1047 return(ENOBUFS); 1048 } 1049 /* Attach the buffer to the mbuf */ 1050 m_new->m_ext.ext_arg = buf; 1051 m_new->m_ext.ext_buf = buf->nge_buf; 1052 m_new->m_ext.ext_free = nge_jfree; 1053 m_new->m_ext.ext_ref = nge_jref; 1054 m_new->m_ext.ext_size = NGE_JUMBO_FRAMELEN; 1055 1056 m_new->m_data = m_new->m_ext.ext_buf; 1057 m_new->m_flags |= M_EXT; 1058 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 1059 } else { 1060 m_new = m; 1061 m_new->m_len = m_new->m_pkthdr.len = NGE_JLEN; 1062 m_new->m_data = m_new->m_ext.ext_buf; 1063 } 1064 1065 m_adj(m_new, sizeof(uint64_t)); 1066 1067 c->nge_mbuf = m_new; 1068 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1069 c->nge_ctl = m_new->m_len; 1070 c->nge_extsts = 0; 1071 1072 return(0); 1073 } 1074 1075 static int 1076 nge_alloc_jumbo_mem(struct nge_softc *sc) 1077 { 1078 caddr_t ptr; 1079 int i; 1080 struct nge_jslot *entry; 1081 1082 /* Grab a big chunk o' storage. */ 1083 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1084 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 1085 1086 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1087 kprintf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1088 return(ENOBUFS); 1089 } 1090 1091 SLIST_INIT(&sc->nge_jfree_listhead); 1092 1093 /* 1094 * Now divide it up into 9K pieces and save the addresses 1095 * in an array. 1096 */ 1097 ptr = sc->nge_cdata.nge_jumbo_buf; 1098 for (i = 0; i < NGE_JSLOTS; i++) { 1099 entry = &sc->nge_cdata.nge_jslots[i]; 1100 entry->nge_sc = sc; 1101 entry->nge_buf = ptr; 1102 entry->nge_inuse = 0; 1103 entry->nge_slot = i; 1104 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link); 1105 ptr += NGE_JLEN; 1106 } 1107 1108 return(0); 1109 } 1110 1111 1112 /* 1113 * Allocate a jumbo buffer. 1114 */ 1115 static struct nge_jslot * 1116 nge_jalloc(struct nge_softc *sc) 1117 { 1118 struct nge_jslot *entry; 1119 1120 lwkt_serialize_enter(&sc->nge_jslot_serializer); 1121 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1122 if (entry) { 1123 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jslot_link); 1124 entry->nge_inuse = 1; 1125 } else { 1126 #ifdef NGE_VERBOSE 1127 kprintf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1128 #endif 1129 } 1130 lwkt_serialize_exit(&sc->nge_jslot_serializer); 1131 return(entry); 1132 } 1133 1134 /* 1135 * Adjust usage count on a jumbo buffer. In general this doesn't 1136 * get used much because our jumbo buffers don't get passed around 1137 * a lot, but it's implemented for correctness. 1138 */ 1139 static void 1140 nge_jref(void *arg) 1141 { 1142 struct nge_jslot *entry = (struct nge_jslot *)arg; 1143 struct nge_softc *sc = entry->nge_sc; 1144 1145 if (sc == NULL) 1146 panic("nge_jref: can't find softc pointer!"); 1147 1148 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) 1149 panic("nge_jref: asked to reference buffer " 1150 "that we don't manage!"); 1151 else if (entry->nge_inuse == 0) 1152 panic("nge_jref: buffer already free!"); 1153 else 1154 atomic_add_int(&entry->nge_inuse, 1); 1155 } 1156 1157 /* 1158 * Release a jumbo buffer. 1159 */ 1160 static void 1161 nge_jfree(void *arg) 1162 { 1163 struct nge_jslot *entry = (struct nge_jslot *)arg; 1164 struct nge_softc *sc = entry->nge_sc; 1165 1166 if (sc == NULL) 1167 panic("nge_jref: can't find softc pointer!"); 1168 1169 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) { 1170 panic("nge_jref: asked to reference buffer " 1171 "that we don't manage!"); 1172 } else if (entry->nge_inuse == 0) { 1173 panic("nge_jref: buffer already free!"); 1174 } else { 1175 lwkt_serialize_enter(&sc->nge_jslot_serializer); 1176 atomic_subtract_int(&entry->nge_inuse, 1); 1177 if (entry->nge_inuse == 0) { 1178 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1179 entry, jslot_link); 1180 } 1181 lwkt_serialize_exit(&sc->nge_jslot_serializer); 1182 } 1183 } 1184 /* 1185 * A frame has been uploaded: pass the resulting mbuf chain up to 1186 * the higher level protocols. 1187 */ 1188 static void 1189 nge_rxeof(struct nge_softc *sc) 1190 { 1191 struct mbuf *m; 1192 struct ifnet *ifp = &sc->arpcom.ac_if; 1193 struct nge_desc *cur_rx; 1194 int i, total_len = 0; 1195 uint32_t rxstat; 1196 1197 i = sc->nge_cdata.nge_rx_prod; 1198 1199 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1200 struct mbuf *m0 = NULL; 1201 uint32_t extsts; 1202 1203 #ifdef DEVICE_POLLING 1204 if (ifp->if_flags & IFF_POLLING) { 1205 if (sc->rxcycles <= 0) 1206 break; 1207 sc->rxcycles--; 1208 } 1209 #endif /* DEVICE_POLLING */ 1210 1211 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1212 rxstat = cur_rx->nge_rxstat; 1213 extsts = cur_rx->nge_extsts; 1214 m = cur_rx->nge_mbuf; 1215 cur_rx->nge_mbuf = NULL; 1216 total_len = NGE_RXBYTES(cur_rx); 1217 NGE_INC(i, NGE_RX_LIST_CNT); 1218 /* 1219 * If an error occurs, update stats, clear the 1220 * status word and leave the mbuf cluster in place: 1221 * it should simply get re-used next time this descriptor 1222 * comes up in the ring. 1223 */ 1224 if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) { 1225 ifp->if_ierrors++; 1226 nge_newbuf(sc, cur_rx, m); 1227 continue; 1228 } 1229 1230 /* 1231 * Ok. NatSemi really screwed up here. This is the 1232 * only gigE chip I know of with alignment constraints 1233 * on receive buffers. RX buffers must be 64-bit aligned. 1234 */ 1235 #ifdef __i386__ 1236 /* 1237 * By popular demand, ignore the alignment problems 1238 * on the Intel x86 platform. The performance hit 1239 * incurred due to unaligned accesses is much smaller 1240 * than the hit produced by forcing buffer copies all 1241 * the time, especially with jumbo frames. We still 1242 * need to fix up the alignment everywhere else though. 1243 */ 1244 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1245 #endif 1246 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1247 total_len + ETHER_ALIGN, 0, ifp, NULL); 1248 nge_newbuf(sc, cur_rx, m); 1249 if (m0 == NULL) { 1250 kprintf("nge%d: no receive buffers " 1251 "available -- packet dropped!\n", 1252 sc->nge_unit); 1253 ifp->if_ierrors++; 1254 continue; 1255 } 1256 m_adj(m0, ETHER_ALIGN); 1257 m = m0; 1258 #ifdef __i386__ 1259 } else { 1260 m->m_pkthdr.rcvif = ifp; 1261 m->m_pkthdr.len = m->m_len = total_len; 1262 } 1263 #endif 1264 1265 ifp->if_ipackets++; 1266 1267 /* Do IP checksum checking. */ 1268 if (extsts & NGE_RXEXTSTS_IPPKT) 1269 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1270 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1271 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1272 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1273 (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) || 1274 (extsts & NGE_RXEXTSTS_UDPPKT && 1275 (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) { 1276 m->m_pkthdr.csum_flags |= 1277 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 1278 CSUM_FRAG_NOT_CHECKED; 1279 m->m_pkthdr.csum_data = 0xffff; 1280 } 1281 1282 /* 1283 * If we received a packet with a vlan tag, pass it 1284 * to vlan_input() instead of ether_input(). 1285 */ 1286 if (extsts & NGE_RXEXTSTS_VLANPKT) 1287 VLAN_INPUT_TAG(m, extsts & NGE_RXEXTSTS_VTCI); 1288 else 1289 ifp->if_input(ifp, m); 1290 } 1291 1292 sc->nge_cdata.nge_rx_prod = i; 1293 } 1294 1295 /* 1296 * A frame was downloaded to the chip. It's safe for us to clean up 1297 * the list buffers. 1298 */ 1299 static void 1300 nge_txeof(struct nge_softc *sc) 1301 { 1302 struct ifnet *ifp = &sc->arpcom.ac_if; 1303 struct nge_desc *cur_tx = NULL; 1304 uint32_t idx; 1305 1306 /* Clear the timeout timer. */ 1307 ifp->if_timer = 0; 1308 1309 /* 1310 * Go through our tx list and free mbufs for those 1311 * frames that have been transmitted. 1312 */ 1313 idx = sc->nge_cdata.nge_tx_cons; 1314 while (idx != sc->nge_cdata.nge_tx_prod) { 1315 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1316 1317 if (NGE_OWNDESC(cur_tx)) 1318 break; 1319 1320 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1321 sc->nge_cdata.nge_tx_cnt--; 1322 NGE_INC(idx, NGE_TX_LIST_CNT); 1323 continue; 1324 } 1325 1326 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1327 ifp->if_oerrors++; 1328 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1329 ifp->if_collisions++; 1330 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1331 ifp->if_collisions++; 1332 } 1333 1334 ifp->if_collisions += 1335 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1336 1337 ifp->if_opackets++; 1338 if (cur_tx->nge_mbuf != NULL) { 1339 m_freem(cur_tx->nge_mbuf); 1340 cur_tx->nge_mbuf = NULL; 1341 } 1342 1343 sc->nge_cdata.nge_tx_cnt--; 1344 NGE_INC(idx, NGE_TX_LIST_CNT); 1345 ifp->if_timer = 0; 1346 } 1347 1348 sc->nge_cdata.nge_tx_cons = idx; 1349 1350 if (cur_tx != NULL) 1351 ifp->if_flags &= ~IFF_OACTIVE; 1352 } 1353 1354 static void 1355 nge_tick(void *xsc) 1356 { 1357 struct nge_softc *sc = xsc; 1358 struct ifnet *ifp = &sc->arpcom.ac_if; 1359 struct mii_data *mii; 1360 1361 lwkt_serialize_enter(ifp->if_serializer); 1362 1363 if (sc->nge_tbi) { 1364 if (sc->nge_link == 0) { 1365 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1366 & NGE_TBIBMSR_ANEG_DONE) { 1367 kprintf("nge%d: gigabit link up\n", 1368 sc->nge_unit); 1369 nge_miibus_statchg(sc->nge_miibus); 1370 sc->nge_link++; 1371 if (!ifq_is_empty(&ifp->if_snd)) 1372 nge_start(ifp); 1373 } 1374 } 1375 } else { 1376 mii = device_get_softc(sc->nge_miibus); 1377 mii_tick(mii); 1378 1379 if (sc->nge_link == 0) { 1380 if (mii->mii_media_status & IFM_ACTIVE && 1381 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1382 sc->nge_link++; 1383 if (IFM_SUBTYPE(mii->mii_media_active) 1384 == IFM_1000_T) 1385 kprintf("nge%d: gigabit link up\n", 1386 sc->nge_unit); 1387 if (!ifq_is_empty(&ifp->if_snd)) 1388 nge_start(ifp); 1389 } 1390 } 1391 } 1392 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc); 1393 1394 lwkt_serialize_exit(ifp->if_serializer); 1395 } 1396 1397 #ifdef DEVICE_POLLING 1398 1399 static void 1400 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1401 { 1402 struct nge_softc *sc = ifp->if_softc; 1403 1404 switch(cmd) { 1405 case POLL_REGISTER: 1406 /* disable interrupts */ 1407 CSR_WRITE_4(sc, NGE_IER, 0); 1408 break; 1409 case POLL_DEREGISTER: 1410 /* enable interrupts */ 1411 CSR_WRITE_4(sc, NGE_IER, 1); 1412 break; 1413 default: 1414 /* 1415 * On the nge, reading the status register also clears it. 1416 * So before returning to intr mode we must make sure that all 1417 * possible pending sources of interrupts have been served. 1418 * In practice this means run to completion the *eof routines, 1419 * and then call the interrupt routine 1420 */ 1421 sc->rxcycles = count; 1422 nge_rxeof(sc); 1423 nge_txeof(sc); 1424 if (!ifq_is_empty(&ifp->if_snd)) 1425 nge_start(ifp); 1426 1427 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1428 uint32_t status; 1429 1430 /* Reading the ISR register clears all interrupts. */ 1431 status = CSR_READ_4(sc, NGE_ISR); 1432 1433 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1434 nge_rxeof(sc); 1435 1436 if (status & (NGE_ISR_RX_IDLE)) 1437 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1438 1439 if (status & NGE_ISR_SYSERR) { 1440 nge_reset(sc); 1441 nge_init(sc); 1442 } 1443 } 1444 break; 1445 } 1446 } 1447 1448 #endif /* DEVICE_POLLING */ 1449 1450 static void 1451 nge_intr(void *arg) 1452 { 1453 struct nge_softc *sc = arg; 1454 struct ifnet *ifp = &sc->arpcom.ac_if; 1455 uint32_t status; 1456 1457 /* Supress unwanted interrupts */ 1458 if (!(ifp->if_flags & IFF_UP)) { 1459 nge_stop(sc); 1460 return; 1461 } 1462 1463 /* Disable interrupts. */ 1464 CSR_WRITE_4(sc, NGE_IER, 0); 1465 1466 /* Data LED on for TBI mode */ 1467 if(sc->nge_tbi) 1468 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1469 | NGE_GPIO_GP3_OUT); 1470 1471 for (;;) { 1472 /* Reading the ISR register clears all interrupts. */ 1473 status = CSR_READ_4(sc, NGE_ISR); 1474 1475 if ((status & NGE_INTRS) == 0) 1476 break; 1477 1478 if ((status & NGE_ISR_TX_DESC_OK) || 1479 (status & NGE_ISR_TX_ERR) || 1480 (status & NGE_ISR_TX_OK) || 1481 (status & NGE_ISR_TX_IDLE)) 1482 nge_txeof(sc); 1483 1484 if ((status & NGE_ISR_RX_DESC_OK) || 1485 (status & NGE_ISR_RX_ERR) || 1486 (status & NGE_ISR_RX_OFLOW) || 1487 (status & NGE_ISR_RX_FIFO_OFLOW) || 1488 (status & NGE_ISR_RX_IDLE) || 1489 (status & NGE_ISR_RX_OK)) 1490 nge_rxeof(sc); 1491 1492 if ((status & NGE_ISR_RX_IDLE)) 1493 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1494 1495 if (status & NGE_ISR_SYSERR) { 1496 nge_reset(sc); 1497 ifp->if_flags &= ~IFF_RUNNING; 1498 nge_init(sc); 1499 } 1500 1501 #ifdef notyet 1502 /* mii_tick should only be called once per second */ 1503 if (status & NGE_ISR_PHY_INTR) { 1504 sc->nge_link = 0; 1505 nge_tick_serialized(sc); 1506 } 1507 #endif 1508 } 1509 1510 /* Re-enable interrupts. */ 1511 CSR_WRITE_4(sc, NGE_IER, 1); 1512 1513 if (!ifq_is_empty(&ifp->if_snd)) 1514 nge_start(ifp); 1515 1516 /* Data LED off for TBI mode */ 1517 1518 if(sc->nge_tbi) 1519 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1520 & ~NGE_GPIO_GP3_OUT); 1521 } 1522 1523 /* 1524 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1525 * pointers to the fragment pointers. 1526 */ 1527 static int 1528 nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1529 { 1530 struct nge_desc *f = NULL; 1531 struct mbuf *m; 1532 int frag, cur, cnt = 0; 1533 1534 /* 1535 * Start packing the mbufs in this chain into 1536 * the fragment pointers. Stop when we run out 1537 * of fragments or hit the end of the mbuf chain. 1538 */ 1539 m = m_head; 1540 cur = frag = *txidx; 1541 1542 for (m = m_head; m != NULL; m = m->m_next) { 1543 if (m->m_len != 0) { 1544 if ((NGE_TX_LIST_CNT - 1545 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1546 return(ENOBUFS); 1547 f = &sc->nge_ldata->nge_tx_list[frag]; 1548 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1549 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1550 if (cnt != 0) 1551 f->nge_ctl |= NGE_CMDSTS_OWN; 1552 cur = frag; 1553 NGE_INC(frag, NGE_TX_LIST_CNT); 1554 cnt++; 1555 } 1556 } 1557 1558 if (m != NULL) 1559 return(ENOBUFS); 1560 1561 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1562 if (m_head->m_pkthdr.csum_flags) { 1563 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1564 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1565 NGE_TXEXTSTS_IPCSUM; 1566 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1567 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1568 NGE_TXEXTSTS_TCPCSUM; 1569 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1570 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1571 NGE_TXEXTSTS_UDPCSUM; 1572 } 1573 1574 if (m_head->m_flags & M_VLANTAG) { 1575 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1576 (NGE_TXEXTSTS_VLANPKT|m_head->m_pkthdr.ether_vlantag); 1577 } 1578 1579 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1580 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1581 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1582 sc->nge_cdata.nge_tx_cnt += cnt; 1583 *txidx = frag; 1584 1585 return(0); 1586 } 1587 1588 /* 1589 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1590 * to the mbuf data regions directly in the transmit lists. We also save a 1591 * copy of the pointers since the transmit list fragment pointers are 1592 * physical addresses. 1593 */ 1594 1595 static void 1596 nge_start(struct ifnet *ifp) 1597 { 1598 struct nge_softc *sc = ifp->if_softc; 1599 struct mbuf *m_head = NULL; 1600 uint32_t idx; 1601 int need_trans; 1602 1603 if (!sc->nge_link) 1604 return; 1605 1606 idx = sc->nge_cdata.nge_tx_prod; 1607 1608 if (ifp->if_flags & IFF_OACTIVE) 1609 return; 1610 1611 need_trans = 0; 1612 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1613 m_head = ifq_poll(&ifp->if_snd); 1614 if (m_head == NULL) 1615 break; 1616 1617 if (nge_encap(sc, m_head, &idx)) { 1618 ifp->if_flags |= IFF_OACTIVE; 1619 break; 1620 } 1621 ifq_dequeue(&ifp->if_snd, m_head); 1622 need_trans = 1; 1623 1624 ETHER_BPF_MTAP(ifp, m_head); 1625 } 1626 1627 if (!need_trans) 1628 return; 1629 1630 /* Transmit */ 1631 sc->nge_cdata.nge_tx_prod = idx; 1632 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1633 1634 /* 1635 * Set a timeout in case the chip goes out to lunch. 1636 */ 1637 ifp->if_timer = 5; 1638 } 1639 1640 static void 1641 nge_init(void *xsc) 1642 { 1643 struct nge_softc *sc = xsc; 1644 struct ifnet *ifp = &sc->arpcom.ac_if; 1645 struct mii_data *mii; 1646 1647 if (ifp->if_flags & IFF_RUNNING) { 1648 return; 1649 } 1650 1651 /* 1652 * Cancel pending I/O and free all RX/TX buffers. 1653 */ 1654 nge_stop(sc); 1655 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc); 1656 1657 if (sc->nge_tbi) 1658 mii = NULL; 1659 else 1660 mii = device_get_softc(sc->nge_miibus); 1661 1662 /* Set MAC address */ 1663 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1664 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1665 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1666 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1667 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1668 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1669 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1670 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1671 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1672 1673 /* Init circular RX list. */ 1674 if (nge_list_rx_init(sc) == ENOBUFS) { 1675 kprintf("nge%d: initialization failed: no " 1676 "memory for rx buffers\n", sc->nge_unit); 1677 nge_stop(sc); 1678 return; 1679 } 1680 1681 /* 1682 * Init tx descriptors. 1683 */ 1684 nge_list_tx_init(sc); 1685 1686 /* 1687 * For the NatSemi chip, we have to explicitly enable the 1688 * reception of ARP frames, as well as turn on the 'perfect 1689 * match' filter where we store the station address, otherwise 1690 * we won't receive unicasts meant for this host. 1691 */ 1692 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1693 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1694 1695 /* If we want promiscuous mode, set the allframes bit. */ 1696 if (ifp->if_flags & IFF_PROMISC) 1697 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1698 else 1699 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1700 1701 /* 1702 * Set the capture broadcast bit to capture broadcast frames. 1703 */ 1704 if (ifp->if_flags & IFF_BROADCAST) 1705 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1706 else 1707 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1708 1709 /* 1710 * Load the multicast filter. 1711 */ 1712 nge_setmulti(sc); 1713 1714 /* Turn the receive filter on */ 1715 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1716 1717 /* 1718 * Load the address of the RX and TX lists. 1719 */ 1720 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1721 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1722 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1723 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1724 1725 /* Set RX configuration */ 1726 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1727 /* 1728 * Enable hardware checksum validation for all IPv4 1729 * packets, do not reject packets with bad checksums. 1730 */ 1731 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1732 1733 /* 1734 * Tell the chip to detect and strip VLAN tag info from 1735 * received frames. The tag will be provided in the extsts 1736 * field in the RX descriptors. 1737 */ 1738 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1739 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1740 1741 /* Set TX configuration */ 1742 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1743 1744 /* 1745 * Enable TX IPv4 checksumming on a per-packet basis. 1746 */ 1747 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1748 1749 /* 1750 * Tell the chip to insert VLAN tags on a per-packet basis as 1751 * dictated by the code in the frame encapsulation routine. 1752 */ 1753 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1754 1755 /* Set full/half duplex mode. */ 1756 if (sc->nge_tbi) { 1757 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1758 == IFM_FDX) { 1759 NGE_SETBIT(sc, NGE_TX_CFG, 1760 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1761 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1762 } else { 1763 NGE_CLRBIT(sc, NGE_TX_CFG, 1764 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1765 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1766 } 1767 } else { 1768 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1769 NGE_SETBIT(sc, NGE_TX_CFG, 1770 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1771 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1772 } else { 1773 NGE_CLRBIT(sc, NGE_TX_CFG, 1774 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1775 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1776 } 1777 } 1778 1779 /* 1780 * Enable the delivery of PHY interrupts based on 1781 * link/speed/duplex status changes. Also enable the 1782 * extsts field in the DMA descriptors (needed for 1783 * TCP/IP checksum offload on transmit). 1784 */ 1785 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD | 1786 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB); 1787 1788 /* 1789 * Configure interrupt holdoff (moderation). We can 1790 * have the chip delay interrupt delivery for a certain 1791 * period. Units are in 100us, and the max setting 1792 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1793 */ 1794 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1795 1796 /* 1797 * Enable interrupts. 1798 */ 1799 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1800 #ifdef DEVICE_POLLING 1801 /* 1802 * ... only enable interrupts if we are not polling, make sure 1803 * they are off otherwise. 1804 */ 1805 if (ifp->if_flags & IFF_POLLING) 1806 CSR_WRITE_4(sc, NGE_IER, 0); 1807 else 1808 #endif /* DEVICE_POLLING */ 1809 CSR_WRITE_4(sc, NGE_IER, 1); 1810 1811 /* Enable receiver and transmitter. */ 1812 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE); 1813 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1814 1815 nge_ifmedia_upd(ifp); 1816 1817 ifp->if_flags |= IFF_RUNNING; 1818 ifp->if_flags &= ~IFF_OACTIVE; 1819 } 1820 1821 /* 1822 * Set media options. 1823 */ 1824 static int 1825 nge_ifmedia_upd(struct ifnet *ifp) 1826 { 1827 struct nge_softc *sc = ifp->if_softc; 1828 struct mii_data *mii; 1829 1830 if (sc->nge_tbi) { 1831 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1832 == IFM_AUTO) { 1833 CSR_WRITE_4(sc, NGE_TBI_ANAR, 1834 CSR_READ_4(sc, NGE_TBI_ANAR) 1835 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 1836 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 1837 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 1838 | NGE_TBIBMCR_RESTART_ANEG); 1839 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 1840 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 1841 & IFM_GMASK) == IFM_FDX) { 1842 NGE_SETBIT(sc, NGE_TX_CFG, 1843 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1844 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1845 1846 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1847 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1848 } else { 1849 NGE_CLRBIT(sc, NGE_TX_CFG, 1850 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1851 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1852 1853 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1854 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1855 } 1856 1857 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1858 & ~NGE_GPIO_GP3_OUT); 1859 } else { 1860 mii = device_get_softc(sc->nge_miibus); 1861 sc->nge_link = 0; 1862 if (mii->mii_instance) { 1863 struct mii_softc *miisc; 1864 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1865 miisc = LIST_NEXT(miisc, mii_list)) 1866 mii_phy_reset(miisc); 1867 } 1868 mii_mediachg(mii); 1869 } 1870 1871 return(0); 1872 } 1873 1874 /* 1875 * Report current media status. 1876 */ 1877 static void 1878 nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1879 { 1880 struct nge_softc *sc = ifp->if_softc; 1881 struct mii_data *mii; 1882 1883 if (sc->nge_tbi) { 1884 ifmr->ifm_status = IFM_AVALID; 1885 ifmr->ifm_active = IFM_ETHER; 1886 1887 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) 1888 ifmr->ifm_status |= IFM_ACTIVE; 1889 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 1890 ifmr->ifm_active |= IFM_LOOP; 1891 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 1892 ifmr->ifm_active |= IFM_NONE; 1893 ifmr->ifm_status = 0; 1894 return; 1895 } 1896 ifmr->ifm_active |= IFM_1000_SX; 1897 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1898 == IFM_AUTO) { 1899 ifmr->ifm_active |= IFM_AUTO; 1900 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 1901 & NGE_TBIANAR_FDX) { 1902 ifmr->ifm_active |= IFM_FDX; 1903 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 1904 & NGE_TBIANAR_HDX) { 1905 ifmr->ifm_active |= IFM_HDX; 1906 } 1907 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1908 == IFM_FDX) 1909 ifmr->ifm_active |= IFM_FDX; 1910 else 1911 ifmr->ifm_active |= IFM_HDX; 1912 1913 } else { 1914 mii = device_get_softc(sc->nge_miibus); 1915 mii_pollstat(mii); 1916 ifmr->ifm_active = mii->mii_media_active; 1917 ifmr->ifm_status = mii->mii_media_status; 1918 } 1919 } 1920 1921 static int 1922 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1923 { 1924 struct nge_softc *sc = ifp->if_softc; 1925 struct ifreq *ifr = (struct ifreq *) data; 1926 struct mii_data *mii; 1927 int error = 0; 1928 1929 switch(command) { 1930 case SIOCSIFMTU: 1931 if (ifr->ifr_mtu > NGE_JUMBO_MTU) { 1932 error = EINVAL; 1933 } else { 1934 ifp->if_mtu = ifr->ifr_mtu; 1935 /* 1936 * Workaround: if the MTU is larger than 1937 * 8152 (TX FIFO size minus 64 minus 18), turn off 1938 * TX checksum offloading. 1939 */ 1940 if (ifr->ifr_mtu >= 8152) 1941 ifp->if_hwassist = 0; 1942 else 1943 ifp->if_hwassist = NGE_CSUM_FEATURES; 1944 } 1945 break; 1946 case SIOCSIFFLAGS: 1947 if (ifp->if_flags & IFF_UP) { 1948 if (ifp->if_flags & IFF_RUNNING && 1949 ifp->if_flags & IFF_PROMISC && 1950 !(sc->nge_if_flags & IFF_PROMISC)) { 1951 NGE_SETBIT(sc, NGE_RXFILT_CTL, 1952 NGE_RXFILTCTL_ALLPHYS| 1953 NGE_RXFILTCTL_ALLMULTI); 1954 } else if (ifp->if_flags & IFF_RUNNING && 1955 !(ifp->if_flags & IFF_PROMISC) && 1956 sc->nge_if_flags & IFF_PROMISC) { 1957 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1958 NGE_RXFILTCTL_ALLPHYS); 1959 if (!(ifp->if_flags & IFF_ALLMULTI)) 1960 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1961 NGE_RXFILTCTL_ALLMULTI); 1962 } else { 1963 ifp->if_flags &= ~IFF_RUNNING; 1964 nge_init(sc); 1965 } 1966 } else { 1967 if (ifp->if_flags & IFF_RUNNING) 1968 nge_stop(sc); 1969 } 1970 sc->nge_if_flags = ifp->if_flags; 1971 error = 0; 1972 break; 1973 case SIOCADDMULTI: 1974 case SIOCDELMULTI: 1975 nge_setmulti(sc); 1976 error = 0; 1977 break; 1978 case SIOCGIFMEDIA: 1979 case SIOCSIFMEDIA: 1980 if (sc->nge_tbi) { 1981 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 1982 command); 1983 } else { 1984 mii = device_get_softc(sc->nge_miibus); 1985 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1986 command); 1987 } 1988 break; 1989 default: 1990 error = ether_ioctl(ifp, command, data); 1991 break; 1992 } 1993 return(error); 1994 } 1995 1996 static void 1997 nge_watchdog(struct ifnet *ifp) 1998 { 1999 struct nge_softc *sc = ifp->if_softc; 2000 2001 ifp->if_oerrors++; 2002 kprintf("nge%d: watchdog timeout\n", sc->nge_unit); 2003 2004 nge_stop(sc); 2005 nge_reset(sc); 2006 ifp->if_flags &= ~IFF_RUNNING; 2007 nge_init(sc); 2008 2009 if (!ifq_is_empty(&ifp->if_snd)) 2010 nge_start(ifp); 2011 } 2012 2013 /* 2014 * Stop the adapter and free any mbufs allocated to the 2015 * RX and TX lists. 2016 */ 2017 static void 2018 nge_stop(struct nge_softc *sc) 2019 { 2020 struct ifnet *ifp = &sc->arpcom.ac_if; 2021 struct ifmedia_entry *ifm; 2022 struct mii_data *mii; 2023 int i, itmp, mtmp, dtmp; 2024 2025 ifp->if_timer = 0; 2026 if (sc->nge_tbi) 2027 mii = NULL; 2028 else 2029 mii = device_get_softc(sc->nge_miibus); 2030 2031 callout_stop(&sc->nge_stat_timer); 2032 CSR_WRITE_4(sc, NGE_IER, 0); 2033 CSR_WRITE_4(sc, NGE_IMR, 0); 2034 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2035 DELAY(1000); 2036 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2037 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2038 2039 /* 2040 * Isolate/power down the PHY, but leave the media selection 2041 * unchanged so that things will be put back to normal when 2042 * we bring the interface back up. 2043 */ 2044 itmp = ifp->if_flags; 2045 ifp->if_flags |= IFF_UP; 2046 2047 if (sc->nge_tbi) 2048 ifm = sc->nge_ifmedia.ifm_cur; 2049 else 2050 ifm = mii->mii_media.ifm_cur; 2051 2052 mtmp = ifm->ifm_media; 2053 dtmp = ifm->ifm_data; 2054 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2055 ifm->ifm_data = MII_MEDIA_NONE; 2056 2057 if (!sc->nge_tbi) 2058 mii_mediachg(mii); 2059 ifm->ifm_media = mtmp; 2060 ifm->ifm_data = dtmp; 2061 ifp->if_flags = itmp; 2062 2063 sc->nge_link = 0; 2064 2065 /* 2066 * Free data in the RX lists. 2067 */ 2068 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2069 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2070 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2071 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2072 } 2073 } 2074 bzero(&sc->nge_ldata->nge_rx_list, 2075 sizeof(sc->nge_ldata->nge_rx_list)); 2076 2077 /* 2078 * Free the TX list buffers. 2079 */ 2080 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2081 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2082 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2083 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2084 } 2085 } 2086 2087 bzero(&sc->nge_ldata->nge_tx_list, 2088 sizeof(sc->nge_ldata->nge_tx_list)); 2089 2090 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2091 } 2092 2093 /* 2094 * Stop all chip I/O so that the kernel's probe routines don't 2095 * get confused by errant DMAs when rebooting. 2096 */ 2097 static void 2098 nge_shutdown(device_t dev) 2099 { 2100 struct nge_softc *sc = device_get_softc(dev); 2101 struct ifnet *ifp = &sc->arpcom.ac_if; 2102 2103 lwkt_serialize_enter(ifp->if_serializer); 2104 nge_reset(sc); 2105 nge_stop(sc); 2106 lwkt_serialize_exit(ifp->if_serializer); 2107 } 2108 2109