1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $ 34 */ 35 36 /* 37 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 38 * for FreeBSD. Datasheets are available from: 39 * 40 * http://www.national.com/ds/DP/DP83820.pdf 41 * http://www.national.com/ds/DP/DP83821.pdf 42 * 43 * These chips are used on several low cost gigabit ethernet NICs 44 * sold by D-Link, Addtron, SMC and Asante. Both parts are 45 * virtually the same, except the 83820 is a 64-bit/32-bit part, 46 * while the 83821 is 32-bit only. 47 * 48 * Many cards also use National gigE transceivers, such as the 49 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 50 * contains a full register description that applies to all of these 51 * components: 52 * 53 * http://www.national.com/ds/DP/DP83861.pdf 54 * 55 * Written by Bill Paul <wpaul@bsdi.com> 56 * BSDi Open Source Solutions 57 */ 58 59 /* 60 * The NatSemi DP83820 and 83821 controllers are enhanced versions 61 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 62 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 63 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 64 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 65 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 66 * matching buffers, one perfect address filter buffer and interrupt 67 * moderation. The 83820 supports both 64-bit and 32-bit addressing 68 * and data transfers: the 64-bit support can be toggled on or off 69 * via software. This affects the size of certain fields in the DMA 70 * descriptors. 71 * 72 * There are two bugs/misfeatures in the 83820/83821 that I have 73 * discovered so far: 74 * 75 * - Receive buffers must be aligned on 64-bit boundaries, which means 76 * you must resort to copying data in order to fix up the payload 77 * alignment. 78 * 79 * - In order to transmit jumbo frames larger than 8170 bytes, you have 80 * to turn off transmit checksum offloading, because the chip can't 81 * compute the checksum on an outgoing frame unless it fits entirely 82 * within the TX FIFO, which is only 8192 bytes in size. If you have 83 * TX checksum offload enabled and you transmit attempt to transmit a 84 * frame larger than 8170 bytes, the transmitter will wedge. 85 * 86 * To work around the latter problem, TX checksum offload is disabled 87 * if the user selects an MTU larger than 8152 (8170 - 18). 88 */ 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/ethernet.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_types.h> 104 #include <net/if_vlan_var.h> 105 106 #include <net/bpf.h> 107 108 #include <vm/vm.h> /* for vtophys */ 109 #include <vm/pmap.h> /* for vtophys */ 110 #include <machine/clock.h> /* for DELAY */ 111 #include <machine/bus_pio.h> 112 #include <machine/bus_memio.h> 113 #include <machine/bus.h> 114 #include <machine/resource.h> 115 #include <sys/bus.h> 116 #include <sys/rman.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 #include <pci/pcireg.h> 122 #include <pci/pcivar.h> 123 124 #define NGE_USEIOSPACE 125 126 #include <dev/nge/if_ngereg.h> 127 128 MODULE_DEPEND(nge, miibus, 1, 1, 1); 129 130 /* "controller miibus0" required. See GENERIC if you get errors here. */ 131 #include "miibus_if.h" 132 133 #ifndef lint 134 static const char rcsid[] = 135 "$FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $"; 136 #endif 137 138 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 139 140 /* 141 * Various supported device vendors/types and their names. 142 */ 143 static struct nge_type nge_devs[] = { 144 { NGE_VENDORID, NGE_DEVICEID, 145 "National Semiconductor Gigabit Ethernet" }, 146 { 0, 0, NULL } 147 }; 148 149 static int nge_probe (device_t); 150 static int nge_attach (device_t); 151 static int nge_detach (device_t); 152 153 static int nge_alloc_jumbo_mem (struct nge_softc *); 154 static void nge_free_jumbo_mem (struct nge_softc *); 155 static void *nge_jalloc (struct nge_softc *); 156 static void nge_jfree (caddr_t, u_int); 157 static void nge_jref (caddr_t, u_int); 158 159 static int nge_newbuf (struct nge_softc *, 160 struct nge_desc *, struct mbuf *); 161 static int nge_encap (struct nge_softc *, 162 struct mbuf *, u_int32_t *); 163 static void nge_rxeof (struct nge_softc *); 164 static void nge_txeof (struct nge_softc *); 165 static void nge_intr (void *); 166 static void nge_tick (void *); 167 static void nge_start (struct ifnet *); 168 static int nge_ioctl (struct ifnet *, u_long, caddr_t); 169 static void nge_init (void *); 170 static void nge_stop (struct nge_softc *); 171 static void nge_watchdog (struct ifnet *); 172 static void nge_shutdown (device_t); 173 static int nge_ifmedia_upd (struct ifnet *); 174 static void nge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 175 176 static void nge_delay (struct nge_softc *); 177 static void nge_eeprom_idle (struct nge_softc *); 178 static void nge_eeprom_putbyte (struct nge_softc *, int); 179 static void nge_eeprom_getword (struct nge_softc *, int, u_int16_t *); 180 static void nge_read_eeprom (struct nge_softc *, caddr_t, int, int, int); 181 182 static void nge_mii_sync (struct nge_softc *); 183 static void nge_mii_send (struct nge_softc *, u_int32_t, int); 184 static int nge_mii_readreg (struct nge_softc *, struct nge_mii_frame *); 185 static int nge_mii_writereg (struct nge_softc *, struct nge_mii_frame *); 186 187 static int nge_miibus_readreg (device_t, int, int); 188 static int nge_miibus_writereg (device_t, int, int, int); 189 static void nge_miibus_statchg (device_t); 190 191 static void nge_setmulti (struct nge_softc *); 192 static u_int32_t nge_crc (struct nge_softc *, caddr_t); 193 static void nge_reset (struct nge_softc *); 194 static int nge_list_rx_init (struct nge_softc *); 195 static int nge_list_tx_init (struct nge_softc *); 196 197 #ifdef NGE_USEIOSPACE 198 #define NGE_RES SYS_RES_IOPORT 199 #define NGE_RID NGE_PCI_LOIO 200 #else 201 #define NGE_RES SYS_RES_MEMORY 202 #define NGE_RID NGE_PCI_LOMEM 203 #endif 204 205 static device_method_t nge_methods[] = { 206 /* Device interface */ 207 DEVMETHOD(device_probe, nge_probe), 208 DEVMETHOD(device_attach, nge_attach), 209 DEVMETHOD(device_detach, nge_detach), 210 DEVMETHOD(device_shutdown, nge_shutdown), 211 212 /* bus interface */ 213 DEVMETHOD(bus_print_child, bus_generic_print_child), 214 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 215 216 /* MII interface */ 217 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 218 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 219 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 220 221 { 0, 0 } 222 }; 223 224 static driver_t nge_driver = { 225 "nge", 226 nge_methods, 227 sizeof(struct nge_softc) 228 }; 229 230 static devclass_t nge_devclass; 231 232 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 233 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 234 235 #define NGE_SETBIT(sc, reg, x) \ 236 CSR_WRITE_4(sc, reg, \ 237 CSR_READ_4(sc, reg) | (x)) 238 239 #define NGE_CLRBIT(sc, reg, x) \ 240 CSR_WRITE_4(sc, reg, \ 241 CSR_READ_4(sc, reg) & ~(x)) 242 243 #define SIO_SET(x) \ 244 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x) 245 246 #define SIO_CLR(x) \ 247 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x) 248 249 static void nge_delay(sc) 250 struct nge_softc *sc; 251 { 252 int idx; 253 254 for (idx = (300 / 33) + 1; idx > 0; idx--) 255 CSR_READ_4(sc, NGE_CSR); 256 257 return; 258 } 259 260 static void nge_eeprom_idle(sc) 261 struct nge_softc *sc; 262 { 263 register int i; 264 265 SIO_SET(NGE_MEAR_EE_CSEL); 266 nge_delay(sc); 267 SIO_SET(NGE_MEAR_EE_CLK); 268 nge_delay(sc); 269 270 for (i = 0; i < 25; i++) { 271 SIO_CLR(NGE_MEAR_EE_CLK); 272 nge_delay(sc); 273 SIO_SET(NGE_MEAR_EE_CLK); 274 nge_delay(sc); 275 } 276 277 SIO_CLR(NGE_MEAR_EE_CLK); 278 nge_delay(sc); 279 SIO_CLR(NGE_MEAR_EE_CSEL); 280 nge_delay(sc); 281 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 282 283 return; 284 } 285 286 /* 287 * Send a read command and address to the EEPROM, check for ACK. 288 */ 289 static void nge_eeprom_putbyte(sc, addr) 290 struct nge_softc *sc; 291 int addr; 292 { 293 register int d, i; 294 295 d = addr | NGE_EECMD_READ; 296 297 /* 298 * Feed in each bit and stobe the clock. 299 */ 300 for (i = 0x400; i; i >>= 1) { 301 if (d & i) { 302 SIO_SET(NGE_MEAR_EE_DIN); 303 } else { 304 SIO_CLR(NGE_MEAR_EE_DIN); 305 } 306 nge_delay(sc); 307 SIO_SET(NGE_MEAR_EE_CLK); 308 nge_delay(sc); 309 SIO_CLR(NGE_MEAR_EE_CLK); 310 nge_delay(sc); 311 } 312 313 return; 314 } 315 316 /* 317 * Read a word of data stored in the EEPROM at address 'addr.' 318 */ 319 static void nge_eeprom_getword(sc, addr, dest) 320 struct nge_softc *sc; 321 int addr; 322 u_int16_t *dest; 323 { 324 register int i; 325 u_int16_t word = 0; 326 327 /* Force EEPROM to idle state. */ 328 nge_eeprom_idle(sc); 329 330 /* Enter EEPROM access mode. */ 331 nge_delay(sc); 332 SIO_CLR(NGE_MEAR_EE_CLK); 333 nge_delay(sc); 334 SIO_SET(NGE_MEAR_EE_CSEL); 335 nge_delay(sc); 336 337 /* 338 * Send address of word we want to read. 339 */ 340 nge_eeprom_putbyte(sc, addr); 341 342 /* 343 * Start reading bits from EEPROM. 344 */ 345 for (i = 0x8000; i; i >>= 1) { 346 SIO_SET(NGE_MEAR_EE_CLK); 347 nge_delay(sc); 348 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 349 word |= i; 350 nge_delay(sc); 351 SIO_CLR(NGE_MEAR_EE_CLK); 352 nge_delay(sc); 353 } 354 355 /* Turn off EEPROM access mode. */ 356 nge_eeprom_idle(sc); 357 358 *dest = word; 359 360 return; 361 } 362 363 /* 364 * Read a sequence of words from the EEPROM. 365 */ 366 static void nge_read_eeprom(sc, dest, off, cnt, swap) 367 struct nge_softc *sc; 368 caddr_t dest; 369 int off; 370 int cnt; 371 int swap; 372 { 373 int i; 374 u_int16_t word = 0, *ptr; 375 376 for (i = 0; i < cnt; i++) { 377 nge_eeprom_getword(sc, off + i, &word); 378 ptr = (u_int16_t *)(dest + (i * 2)); 379 if (swap) 380 *ptr = ntohs(word); 381 else 382 *ptr = word; 383 } 384 385 return; 386 } 387 388 /* 389 * Sync the PHYs by setting data bit and strobing the clock 32 times. 390 */ 391 static void nge_mii_sync(sc) 392 struct nge_softc *sc; 393 { 394 register int i; 395 396 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 397 398 for (i = 0; i < 32; i++) { 399 SIO_SET(NGE_MEAR_MII_CLK); 400 DELAY(1); 401 SIO_CLR(NGE_MEAR_MII_CLK); 402 DELAY(1); 403 } 404 405 return; 406 } 407 408 /* 409 * Clock a series of bits through the MII. 410 */ 411 static void nge_mii_send(sc, bits, cnt) 412 struct nge_softc *sc; 413 u_int32_t bits; 414 int cnt; 415 { 416 int i; 417 418 SIO_CLR(NGE_MEAR_MII_CLK); 419 420 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 421 if (bits & i) { 422 SIO_SET(NGE_MEAR_MII_DATA); 423 } else { 424 SIO_CLR(NGE_MEAR_MII_DATA); 425 } 426 DELAY(1); 427 SIO_CLR(NGE_MEAR_MII_CLK); 428 DELAY(1); 429 SIO_SET(NGE_MEAR_MII_CLK); 430 } 431 } 432 433 /* 434 * Read an PHY register through the MII. 435 */ 436 static int nge_mii_readreg(sc, frame) 437 struct nge_softc *sc; 438 struct nge_mii_frame *frame; 439 440 { 441 int i, ack, s; 442 443 s = splimp(); 444 445 /* 446 * Set up frame for RX. 447 */ 448 frame->mii_stdelim = NGE_MII_STARTDELIM; 449 frame->mii_opcode = NGE_MII_READOP; 450 frame->mii_turnaround = 0; 451 frame->mii_data = 0; 452 453 CSR_WRITE_4(sc, NGE_MEAR, 0); 454 455 /* 456 * Turn on data xmit. 457 */ 458 SIO_SET(NGE_MEAR_MII_DIR); 459 460 nge_mii_sync(sc); 461 462 /* 463 * Send command/address info. 464 */ 465 nge_mii_send(sc, frame->mii_stdelim, 2); 466 nge_mii_send(sc, frame->mii_opcode, 2); 467 nge_mii_send(sc, frame->mii_phyaddr, 5); 468 nge_mii_send(sc, frame->mii_regaddr, 5); 469 470 /* Idle bit */ 471 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 472 DELAY(1); 473 SIO_SET(NGE_MEAR_MII_CLK); 474 DELAY(1); 475 476 /* Turn off xmit. */ 477 SIO_CLR(NGE_MEAR_MII_DIR); 478 /* Check for ack */ 479 SIO_CLR(NGE_MEAR_MII_CLK); 480 DELAY(1); 481 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 482 SIO_SET(NGE_MEAR_MII_CLK); 483 DELAY(1); 484 485 /* 486 * Now try reading data bits. If the ack failed, we still 487 * need to clock through 16 cycles to keep the PHY(s) in sync. 488 */ 489 if (ack) { 490 for(i = 0; i < 16; i++) { 491 SIO_CLR(NGE_MEAR_MII_CLK); 492 DELAY(1); 493 SIO_SET(NGE_MEAR_MII_CLK); 494 DELAY(1); 495 } 496 goto fail; 497 } 498 499 for (i = 0x8000; i; i >>= 1) { 500 SIO_CLR(NGE_MEAR_MII_CLK); 501 DELAY(1); 502 if (!ack) { 503 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 504 frame->mii_data |= i; 505 DELAY(1); 506 } 507 SIO_SET(NGE_MEAR_MII_CLK); 508 DELAY(1); 509 } 510 511 fail: 512 513 SIO_CLR(NGE_MEAR_MII_CLK); 514 DELAY(1); 515 SIO_SET(NGE_MEAR_MII_CLK); 516 DELAY(1); 517 518 splx(s); 519 520 if (ack) 521 return(1); 522 return(0); 523 } 524 525 /* 526 * Write to a PHY register through the MII. 527 */ 528 static int nge_mii_writereg(sc, frame) 529 struct nge_softc *sc; 530 struct nge_mii_frame *frame; 531 532 { 533 int s; 534 535 s = splimp(); 536 /* 537 * Set up frame for TX. 538 */ 539 540 frame->mii_stdelim = NGE_MII_STARTDELIM; 541 frame->mii_opcode = NGE_MII_WRITEOP; 542 frame->mii_turnaround = NGE_MII_TURNAROUND; 543 544 /* 545 * Turn on data output. 546 */ 547 SIO_SET(NGE_MEAR_MII_DIR); 548 549 nge_mii_sync(sc); 550 551 nge_mii_send(sc, frame->mii_stdelim, 2); 552 nge_mii_send(sc, frame->mii_opcode, 2); 553 nge_mii_send(sc, frame->mii_phyaddr, 5); 554 nge_mii_send(sc, frame->mii_regaddr, 5); 555 nge_mii_send(sc, frame->mii_turnaround, 2); 556 nge_mii_send(sc, frame->mii_data, 16); 557 558 /* Idle bit. */ 559 SIO_SET(NGE_MEAR_MII_CLK); 560 DELAY(1); 561 SIO_CLR(NGE_MEAR_MII_CLK); 562 DELAY(1); 563 564 /* 565 * Turn off xmit. 566 */ 567 SIO_CLR(NGE_MEAR_MII_DIR); 568 569 splx(s); 570 571 return(0); 572 } 573 574 static int nge_miibus_readreg(dev, phy, reg) 575 device_t dev; 576 int phy, reg; 577 { 578 struct nge_softc *sc; 579 struct nge_mii_frame frame; 580 581 sc = device_get_softc(dev); 582 583 bzero((char *)&frame, sizeof(frame)); 584 585 frame.mii_phyaddr = phy; 586 frame.mii_regaddr = reg; 587 nge_mii_readreg(sc, &frame); 588 589 return(frame.mii_data); 590 } 591 592 static int nge_miibus_writereg(dev, phy, reg, data) 593 device_t dev; 594 int phy, reg, data; 595 { 596 struct nge_softc *sc; 597 struct nge_mii_frame frame; 598 599 sc = device_get_softc(dev); 600 601 bzero((char *)&frame, sizeof(frame)); 602 603 frame.mii_phyaddr = phy; 604 frame.mii_regaddr = reg; 605 frame.mii_data = data; 606 nge_mii_writereg(sc, &frame); 607 608 return(0); 609 } 610 611 static void nge_miibus_statchg(dev) 612 device_t dev; 613 { 614 int status; 615 struct nge_softc *sc; 616 struct mii_data *mii; 617 618 sc = device_get_softc(dev); 619 if (sc->nge_tbi) { 620 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 621 == IFM_AUTO) { 622 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 623 if (status == 0 || status & NGE_TBIANAR_FDX) { 624 NGE_SETBIT(sc, NGE_TX_CFG, 625 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 626 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 627 } else { 628 NGE_CLRBIT(sc, NGE_TX_CFG, 629 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 630 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 631 } 632 633 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 634 != IFM_FDX) { 635 NGE_CLRBIT(sc, NGE_TX_CFG, 636 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 637 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 638 } else { 639 NGE_SETBIT(sc, NGE_TX_CFG, 640 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 641 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 642 } 643 } else { 644 mii = device_get_softc(sc->nge_miibus); 645 646 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 647 NGE_SETBIT(sc, NGE_TX_CFG, 648 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 649 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 650 } else { 651 NGE_CLRBIT(sc, NGE_TX_CFG, 652 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 653 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 654 } 655 656 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 657 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 658 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 659 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 660 } else { 661 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 662 } 663 } 664 return; 665 } 666 667 static u_int32_t nge_crc(sc, addr) 668 struct nge_softc *sc; 669 caddr_t addr; 670 { 671 u_int32_t crc, carry; 672 int i, j; 673 u_int8_t c; 674 675 /* Compute CRC for the address value. */ 676 crc = 0xFFFFFFFF; /* initial value */ 677 678 for (i = 0; i < 6; i++) { 679 c = *(addr + i); 680 for (j = 0; j < 8; j++) { 681 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 682 crc <<= 1; 683 c >>= 1; 684 if (carry) 685 crc = (crc ^ 0x04c11db6) | carry; 686 } 687 } 688 689 /* 690 * return the filter bit position 691 */ 692 693 return((crc >> 21) & 0x00000FFF); 694 } 695 696 static void nge_setmulti(sc) 697 struct nge_softc *sc; 698 { 699 struct ifnet *ifp; 700 struct ifmultiaddr *ifma; 701 u_int32_t h = 0, i, filtsave; 702 int bit, index; 703 704 ifp = &sc->arpcom.ac_if; 705 706 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 707 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 708 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 709 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 710 return; 711 } 712 713 /* 714 * We have to explicitly enable the multicast hash table 715 * on the NatSemi chip if we want to use it, which we do. 716 * We also have to tell it that we don't want to use the 717 * hash table for matching unicast addresses. 718 */ 719 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 720 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 721 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 722 723 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 724 725 /* first, zot all the existing hash bits */ 726 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 727 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 728 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 729 } 730 731 /* 732 * From the 11 bits returned by the crc routine, the top 7 733 * bits represent the 16-bit word in the mcast hash table 734 * that needs to be updated, and the lower 4 bits represent 735 * which bit within that byte needs to be set. 736 */ 737 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 738 if (ifma->ifma_addr->sa_family != AF_LINK) 739 continue; 740 h = nge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 741 index = (h >> 4) & 0x7F; 742 bit = h & 0xF; 743 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 744 NGE_FILTADDR_MCAST_LO + (index * 2)); 745 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 746 } 747 748 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 749 750 return; 751 } 752 753 static void nge_reset(sc) 754 struct nge_softc *sc; 755 { 756 register int i; 757 758 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 759 760 for (i = 0; i < NGE_TIMEOUT; i++) { 761 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 762 break; 763 } 764 765 if (i == NGE_TIMEOUT) 766 printf("nge%d: reset never completed\n", sc->nge_unit); 767 768 /* Wait a little while for the chip to get its brains in order. */ 769 DELAY(1000); 770 771 /* 772 * If this is a NetSemi chip, make sure to clear 773 * PME mode. 774 */ 775 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 776 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 777 778 return; 779 } 780 781 /* 782 * Probe for an NatSemi chip. Check the PCI vendor and device 783 * IDs against our list and return a device name if we find a match. 784 */ 785 static int nge_probe(dev) 786 device_t dev; 787 { 788 struct nge_type *t; 789 790 t = nge_devs; 791 792 while(t->nge_name != NULL) { 793 if ((pci_get_vendor(dev) == t->nge_vid) && 794 (pci_get_device(dev) == t->nge_did)) { 795 device_set_desc(dev, t->nge_name); 796 return(0); 797 } 798 t++; 799 } 800 801 return(ENXIO); 802 } 803 804 /* 805 * Attach the interface. Allocate softc structures, do ifmedia 806 * setup and ethernet/BPF attach. 807 */ 808 static int nge_attach(dev) 809 device_t dev; 810 { 811 int s; 812 u_char eaddr[ETHER_ADDR_LEN]; 813 u_int32_t command; 814 struct nge_softc *sc; 815 struct ifnet *ifp; 816 int unit, error = 0, rid; 817 const char *sep = ""; 818 819 s = splimp(); 820 821 sc = device_get_softc(dev); 822 unit = device_get_unit(dev); 823 bzero(sc, sizeof(struct nge_softc)); 824 825 /* 826 * Handle power management nonsense. 827 */ 828 829 830 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF; 831 if (command == 0x01) { 832 833 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4); 834 if (command & NGE_PSTATE_MASK) { 835 u_int32_t iobase, membase, irq; 836 837 /* Save important PCI config data. */ 838 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 839 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 840 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 841 842 /* Reset the power state. */ 843 printf("nge%d: chip is in D%d power mode " 844 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK); 845 command &= 0xFFFFFFFC; 846 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4); 847 848 /* Restore PCI config data. */ 849 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 850 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 851 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 852 } 853 } 854 855 /* 856 * Map control/status registers. 857 */ 858 command = pci_read_config(dev, PCIR_COMMAND, 4); 859 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 860 pci_write_config(dev, PCIR_COMMAND, command, 4); 861 command = pci_read_config(dev, PCIR_COMMAND, 4); 862 863 #ifdef NGE_USEIOSPACE 864 if (!(command & PCIM_CMD_PORTEN)) { 865 printf("nge%d: failed to enable I/O ports!\n", unit); 866 error = ENXIO;; 867 goto fail; 868 } 869 #else 870 if (!(command & PCIM_CMD_MEMEN)) { 871 printf("nge%d: failed to enable memory mapping!\n", unit); 872 error = ENXIO;; 873 goto fail; 874 } 875 #endif 876 877 rid = NGE_RID; 878 sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid, 879 0, ~0, 1, RF_ACTIVE); 880 881 if (sc->nge_res == NULL) { 882 printf("nge%d: couldn't map ports/memory\n", unit); 883 error = ENXIO; 884 goto fail; 885 } 886 887 sc->nge_btag = rman_get_bustag(sc->nge_res); 888 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 889 890 /* Allocate interrupt */ 891 rid = 0; 892 sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 893 RF_SHAREABLE | RF_ACTIVE); 894 895 if (sc->nge_irq == NULL) { 896 printf("nge%d: couldn't map interrupt\n", unit); 897 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 898 error = ENXIO; 899 goto fail; 900 } 901 902 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 903 nge_intr, sc, &sc->nge_intrhand); 904 905 if (error) { 906 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 907 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 908 printf("nge%d: couldn't set up irq\n", unit); 909 goto fail; 910 } 911 912 /* Reset the adapter. */ 913 nge_reset(sc); 914 915 /* 916 * Get station address from the EEPROM. 917 */ 918 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 919 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 920 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 921 922 /* 923 * A NatSemi chip was detected. Inform the world. 924 */ 925 printf("nge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 926 927 sc->nge_unit = unit; 928 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 929 930 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 931 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 932 933 if (sc->nge_ldata == NULL) { 934 printf("nge%d: no memory for list buffers!\n", unit); 935 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 936 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 937 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 938 error = ENXIO; 939 goto fail; 940 } 941 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 942 943 /* Try to allocate memory for jumbo buffers. */ 944 if (nge_alloc_jumbo_mem(sc)) { 945 printf("nge%d: jumbo buffer allocation failed\n", 946 sc->nge_unit); 947 contigfree(sc->nge_ldata, 948 sizeof(struct nge_list_data), M_DEVBUF); 949 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 950 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 951 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 952 error = ENXIO; 953 goto fail; 954 } 955 956 ifp = &sc->arpcom.ac_if; 957 ifp->if_softc = sc; 958 ifp->if_unit = unit; 959 ifp->if_name = "nge"; 960 ifp->if_mtu = ETHERMTU; 961 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 962 ifp->if_ioctl = nge_ioctl; 963 ifp->if_output = ether_output; 964 ifp->if_start = nge_start; 965 ifp->if_watchdog = nge_watchdog; 966 ifp->if_init = nge_init; 967 ifp->if_baudrate = 1000000000; 968 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 969 ifp->if_hwassist = NGE_CSUM_FEATURES; 970 ifp->if_capabilities = IFCAP_HWCSUM; 971 ifp->if_capenable = ifp->if_capabilities; 972 973 /* 974 * Do MII setup. 975 */ 976 if (mii_phy_probe(dev, &sc->nge_miibus, 977 nge_ifmedia_upd, nge_ifmedia_sts)) { 978 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 979 sc->nge_tbi = 1; 980 device_printf(dev, "Using TBI\n"); 981 982 sc->nge_miibus = dev; 983 984 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 985 nge_ifmedia_sts); 986 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 987 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 988 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 989 device_printf(dev, " "); 990 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 991 PRINT("1000baseSX"); 992 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 993 PRINT("1000baseSX-FDX"); 994 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 995 PRINT("auto"); 996 997 printf("\n"); 998 #undef ADD 999 #undef PRINT 1000 ifmedia_set(&sc->nge_ifmedia, 1001 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 1002 1003 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1004 | NGE_GPIO_GP4_OUT 1005 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 1006 | NGE_GPIO_GP3_OUTENB 1007 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 1008 1009 } else { 1010 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 1011 nge_free_jumbo_mem(sc); 1012 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1013 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1014 bus_release_resource(dev, NGE_RES, NGE_RID, 1015 sc->nge_res); 1016 error = ENXIO; 1017 goto fail; 1018 } 1019 } 1020 1021 /* 1022 * Call MI attach routine. 1023 */ 1024 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1025 callout_handle_init(&sc->nge_stat_ch); 1026 1027 fail: 1028 1029 splx(s); 1030 return(error); 1031 } 1032 1033 static int nge_detach(dev) 1034 device_t dev; 1035 { 1036 struct nge_softc *sc; 1037 struct ifnet *ifp; 1038 int s; 1039 1040 s = splimp(); 1041 1042 sc = device_get_softc(dev); 1043 ifp = &sc->arpcom.ac_if; 1044 1045 nge_reset(sc); 1046 nge_stop(sc); 1047 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1048 1049 bus_generic_detach(dev); 1050 if (!sc->nge_tbi) { 1051 device_delete_child(dev, sc->nge_miibus); 1052 } 1053 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1054 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1055 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 1056 1057 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 1058 nge_free_jumbo_mem(sc); 1059 1060 splx(s); 1061 1062 return(0); 1063 } 1064 1065 /* 1066 * Initialize the transmit descriptors. 1067 */ 1068 static int nge_list_tx_init(sc) 1069 struct nge_softc *sc; 1070 { 1071 struct nge_list_data *ld; 1072 struct nge_ring_data *cd; 1073 int i; 1074 1075 cd = &sc->nge_cdata; 1076 ld = sc->nge_ldata; 1077 1078 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1079 if (i == (NGE_TX_LIST_CNT - 1)) { 1080 ld->nge_tx_list[i].nge_nextdesc = 1081 &ld->nge_tx_list[0]; 1082 ld->nge_tx_list[i].nge_next = 1083 vtophys(&ld->nge_tx_list[0]); 1084 } else { 1085 ld->nge_tx_list[i].nge_nextdesc = 1086 &ld->nge_tx_list[i + 1]; 1087 ld->nge_tx_list[i].nge_next = 1088 vtophys(&ld->nge_tx_list[i + 1]); 1089 } 1090 ld->nge_tx_list[i].nge_mbuf = NULL; 1091 ld->nge_tx_list[i].nge_ptr = 0; 1092 ld->nge_tx_list[i].nge_ctl = 0; 1093 } 1094 1095 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1096 1097 return(0); 1098 } 1099 1100 1101 /* 1102 * Initialize the RX descriptors and allocate mbufs for them. Note that 1103 * we arrange the descriptors in a closed ring, so that the last descriptor 1104 * points back to the first. 1105 */ 1106 static int nge_list_rx_init(sc) 1107 struct nge_softc *sc; 1108 { 1109 struct nge_list_data *ld; 1110 struct nge_ring_data *cd; 1111 int i; 1112 1113 ld = sc->nge_ldata; 1114 cd = &sc->nge_cdata; 1115 1116 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1117 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1118 return(ENOBUFS); 1119 if (i == (NGE_RX_LIST_CNT - 1)) { 1120 ld->nge_rx_list[i].nge_nextdesc = 1121 &ld->nge_rx_list[0]; 1122 ld->nge_rx_list[i].nge_next = 1123 vtophys(&ld->nge_rx_list[0]); 1124 } else { 1125 ld->nge_rx_list[i].nge_nextdesc = 1126 &ld->nge_rx_list[i + 1]; 1127 ld->nge_rx_list[i].nge_next = 1128 vtophys(&ld->nge_rx_list[i + 1]); 1129 } 1130 } 1131 1132 cd->nge_rx_prod = 0; 1133 1134 return(0); 1135 } 1136 1137 /* 1138 * Initialize an RX descriptor and attach an MBUF cluster. 1139 */ 1140 static int nge_newbuf(sc, c, m) 1141 struct nge_softc *sc; 1142 struct nge_desc *c; 1143 struct mbuf *m; 1144 { 1145 struct mbuf *m_new = NULL; 1146 caddr_t *buf = NULL; 1147 1148 if (m == NULL) { 1149 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1150 if (m_new == NULL) { 1151 printf("nge%d: no memory for rx list " 1152 "-- packet dropped!\n", sc->nge_unit); 1153 return(ENOBUFS); 1154 } 1155 1156 /* Allocate the jumbo buffer */ 1157 buf = nge_jalloc(sc); 1158 if (buf == NULL) { 1159 #ifdef NGE_VERBOSE 1160 printf("nge%d: jumbo allocation failed " 1161 "-- packet dropped!\n", sc->nge_unit); 1162 #endif 1163 m_freem(m_new); 1164 return(ENOBUFS); 1165 } 1166 /* Attach the buffer to the mbuf */ 1167 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 1168 m_new->m_flags |= M_EXT; 1169 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 1170 m_new->m_len = NGE_MCLBYTES; 1171 m_new->m_ext.ext_free = nge_jfree; 1172 m_new->m_ext.ext_ref = nge_jref; 1173 } else { 1174 m_new = m; 1175 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES; 1176 m_new->m_data = m_new->m_ext.ext_buf; 1177 } 1178 1179 m_adj(m_new, sizeof(u_int64_t)); 1180 1181 c->nge_mbuf = m_new; 1182 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1183 c->nge_ctl = m_new->m_len; 1184 c->nge_extsts = 0; 1185 1186 return(0); 1187 } 1188 1189 static int nge_alloc_jumbo_mem(sc) 1190 struct nge_softc *sc; 1191 { 1192 caddr_t ptr; 1193 register int i; 1194 struct nge_jpool_entry *entry; 1195 1196 /* Grab a big chunk o' storage. */ 1197 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1198 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1199 1200 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1201 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1202 return(ENOBUFS); 1203 } 1204 1205 SLIST_INIT(&sc->nge_jfree_listhead); 1206 SLIST_INIT(&sc->nge_jinuse_listhead); 1207 1208 /* 1209 * Now divide it up into 9K pieces and save the addresses 1210 * in an array. 1211 */ 1212 ptr = sc->nge_cdata.nge_jumbo_buf; 1213 for (i = 0; i < NGE_JSLOTS; i++) { 1214 u_int64_t **aptr; 1215 aptr = (u_int64_t **)ptr; 1216 aptr[0] = (u_int64_t *)sc; 1217 ptr += sizeof(u_int64_t); 1218 sc->nge_cdata.nge_jslots[i].nge_buf = ptr; 1219 sc->nge_cdata.nge_jslots[i].nge_inuse = 0; 1220 ptr += NGE_MCLBYTES; 1221 entry = malloc(sizeof(struct nge_jpool_entry), 1222 M_DEVBUF, M_NOWAIT); 1223 if (entry == NULL) { 1224 printf("nge%d: no memory for jumbo " 1225 "buffer queue!\n", sc->nge_unit); 1226 return(ENOBUFS); 1227 } 1228 entry->slot = i; 1229 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1230 entry, jpool_entries); 1231 } 1232 1233 return(0); 1234 } 1235 1236 static void nge_free_jumbo_mem(sc) 1237 struct nge_softc *sc; 1238 { 1239 register int i; 1240 struct nge_jpool_entry *entry; 1241 1242 for (i = 0; i < NGE_JSLOTS; i++) { 1243 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1244 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1245 free(entry, M_DEVBUF); 1246 } 1247 1248 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1249 1250 return; 1251 } 1252 1253 /* 1254 * Allocate a jumbo buffer. 1255 */ 1256 static void *nge_jalloc(sc) 1257 struct nge_softc *sc; 1258 { 1259 struct nge_jpool_entry *entry; 1260 1261 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1262 1263 if (entry == NULL) { 1264 #ifdef NGE_VERBOSE 1265 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1266 #endif 1267 return(NULL); 1268 } 1269 1270 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1271 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1272 sc->nge_cdata.nge_jslots[entry->slot].nge_inuse = 1; 1273 return(sc->nge_cdata.nge_jslots[entry->slot].nge_buf); 1274 } 1275 1276 /* 1277 * Adjust usage count on a jumbo buffer. In general this doesn't 1278 * get used much because our jumbo buffers don't get passed around 1279 * a lot, but it's implemented for correctness. 1280 */ 1281 static void nge_jref(buf, size) 1282 caddr_t buf; 1283 u_int size; 1284 { 1285 struct nge_softc *sc; 1286 u_int64_t **aptr; 1287 register int i; 1288 1289 /* Extract the softc struct pointer. */ 1290 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 1291 sc = (struct nge_softc *)(aptr[0]); 1292 1293 if (sc == NULL) 1294 panic("nge_jref: can't find softc pointer!"); 1295 1296 if (size != NGE_MCLBYTES) 1297 panic("nge_jref: adjusting refcount of buf of wrong size!"); 1298 1299 /* calculate the slot this buffer belongs to */ 1300 1301 i = ((vm_offset_t)aptr 1302 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1303 1304 if ((i < 0) || (i >= NGE_JSLOTS)) 1305 panic("nge_jref: asked to reference buffer " 1306 "that we don't manage!"); 1307 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0) 1308 panic("nge_jref: buffer already free!"); 1309 else 1310 sc->nge_cdata.nge_jslots[i].nge_inuse++; 1311 1312 return; 1313 } 1314 1315 /* 1316 * Release a jumbo buffer. 1317 */ 1318 static void nge_jfree(buf, size) 1319 caddr_t buf; 1320 u_int size; 1321 { 1322 struct nge_softc *sc; 1323 u_int64_t **aptr; 1324 int i; 1325 struct nge_jpool_entry *entry; 1326 1327 /* Extract the softc struct pointer. */ 1328 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 1329 sc = (struct nge_softc *)(aptr[0]); 1330 1331 if (sc == NULL) 1332 panic("nge_jfree: can't find softc pointer!"); 1333 1334 if (size != NGE_MCLBYTES) 1335 panic("nge_jfree: freeing buffer of wrong size!"); 1336 1337 /* calculate the slot this buffer belongs to */ 1338 1339 i = ((vm_offset_t)aptr 1340 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1341 1342 if ((i < 0) || (i >= NGE_JSLOTS)) 1343 panic("nge_jfree: asked to free buffer that we don't manage!"); 1344 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0) 1345 panic("nge_jfree: buffer already free!"); 1346 else { 1347 sc->nge_cdata.nge_jslots[i].nge_inuse--; 1348 if(sc->nge_cdata.nge_jslots[i].nge_inuse == 0) { 1349 entry = SLIST_FIRST(&sc->nge_jinuse_listhead); 1350 if (entry == NULL) 1351 panic("nge_jfree: buffer not in use!"); 1352 entry->slot = i; 1353 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, 1354 jpool_entries); 1355 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1356 entry, jpool_entries); 1357 } 1358 } 1359 1360 return; 1361 } 1362 /* 1363 * A frame has been uploaded: pass the resulting mbuf chain up to 1364 * the higher level protocols. 1365 */ 1366 static void nge_rxeof(sc) 1367 struct nge_softc *sc; 1368 { 1369 struct ether_header *eh; 1370 struct mbuf *m; 1371 struct ifnet *ifp; 1372 struct nge_desc *cur_rx; 1373 int i, total_len = 0; 1374 u_int32_t rxstat; 1375 1376 ifp = &sc->arpcom.ac_if; 1377 i = sc->nge_cdata.nge_rx_prod; 1378 1379 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1380 struct mbuf *m0 = NULL; 1381 u_int32_t extsts; 1382 1383 #ifdef DEVICE_POLLING 1384 if (ifp->if_ipending & IFF_POLLING) { 1385 if (sc->rxcycles <= 0) 1386 break; 1387 sc->rxcycles--; 1388 } 1389 #endif /* DEVICE_POLLING */ 1390 1391 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1392 rxstat = cur_rx->nge_rxstat; 1393 extsts = cur_rx->nge_extsts; 1394 m = cur_rx->nge_mbuf; 1395 cur_rx->nge_mbuf = NULL; 1396 total_len = NGE_RXBYTES(cur_rx); 1397 NGE_INC(i, NGE_RX_LIST_CNT); 1398 /* 1399 * If an error occurs, update stats, clear the 1400 * status word and leave the mbuf cluster in place: 1401 * it should simply get re-used next time this descriptor 1402 * comes up in the ring. 1403 */ 1404 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1405 ifp->if_ierrors++; 1406 nge_newbuf(sc, cur_rx, m); 1407 continue; 1408 } 1409 1410 /* 1411 * Ok. NatSemi really screwed up here. This is the 1412 * only gigE chip I know of with alignment constraints 1413 * on receive buffers. RX buffers must be 64-bit aligned. 1414 */ 1415 #ifdef __i386__ 1416 /* 1417 * By popular demand, ignore the alignment problems 1418 * on the Intel x86 platform. The performance hit 1419 * incurred due to unaligned accesses is much smaller 1420 * than the hit produced by forcing buffer copies all 1421 * the time, especially with jumbo frames. We still 1422 * need to fix up the alignment everywhere else though. 1423 */ 1424 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1425 #endif 1426 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1427 total_len + ETHER_ALIGN, 0, ifp, NULL); 1428 nge_newbuf(sc, cur_rx, m); 1429 if (m0 == NULL) { 1430 printf("nge%d: no receive buffers " 1431 "available -- packet dropped!\n", 1432 sc->nge_unit); 1433 ifp->if_ierrors++; 1434 continue; 1435 } 1436 m_adj(m0, ETHER_ALIGN); 1437 m = m0; 1438 #ifdef __i386__ 1439 } else { 1440 m->m_pkthdr.rcvif = ifp; 1441 m->m_pkthdr.len = m->m_len = total_len; 1442 } 1443 #endif 1444 1445 ifp->if_ipackets++; 1446 eh = mtod(m, struct ether_header *); 1447 1448 /* Remove header from mbuf and pass it on. */ 1449 m_adj(m, sizeof(struct ether_header)); 1450 1451 /* Do IP checksum checking. */ 1452 if (extsts & NGE_RXEXTSTS_IPPKT) 1453 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1454 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1455 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1456 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1457 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1458 (extsts & NGE_RXEXTSTS_UDPPKT && 1459 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1460 m->m_pkthdr.csum_flags |= 1461 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1462 m->m_pkthdr.csum_data = 0xffff; 1463 } 1464 1465 /* 1466 * If we received a packet with a vlan tag, pass it 1467 * to vlan_input() instead of ether_input(). 1468 */ 1469 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1470 VLAN_INPUT_TAG(eh, m, extsts & NGE_RXEXTSTS_VTCI); 1471 continue; 1472 } 1473 1474 ether_input(ifp, eh, m); 1475 } 1476 1477 sc->nge_cdata.nge_rx_prod = i; 1478 1479 return; 1480 } 1481 1482 /* 1483 * A frame was downloaded to the chip. It's safe for us to clean up 1484 * the list buffers. 1485 */ 1486 1487 static void nge_txeof(sc) 1488 struct nge_softc *sc; 1489 { 1490 struct nge_desc *cur_tx = NULL; 1491 struct ifnet *ifp; 1492 u_int32_t idx; 1493 1494 ifp = &sc->arpcom.ac_if; 1495 1496 /* Clear the timeout timer. */ 1497 ifp->if_timer = 0; 1498 1499 /* 1500 * Go through our tx list and free mbufs for those 1501 * frames that have been transmitted. 1502 */ 1503 idx = sc->nge_cdata.nge_tx_cons; 1504 while (idx != sc->nge_cdata.nge_tx_prod) { 1505 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1506 1507 if (NGE_OWNDESC(cur_tx)) 1508 break; 1509 1510 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1511 sc->nge_cdata.nge_tx_cnt--; 1512 NGE_INC(idx, NGE_TX_LIST_CNT); 1513 continue; 1514 } 1515 1516 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1517 ifp->if_oerrors++; 1518 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1519 ifp->if_collisions++; 1520 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1521 ifp->if_collisions++; 1522 } 1523 1524 ifp->if_collisions += 1525 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1526 1527 ifp->if_opackets++; 1528 if (cur_tx->nge_mbuf != NULL) { 1529 m_freem(cur_tx->nge_mbuf); 1530 cur_tx->nge_mbuf = NULL; 1531 } 1532 1533 sc->nge_cdata.nge_tx_cnt--; 1534 NGE_INC(idx, NGE_TX_LIST_CNT); 1535 ifp->if_timer = 0; 1536 } 1537 1538 sc->nge_cdata.nge_tx_cons = idx; 1539 1540 if (cur_tx != NULL) 1541 ifp->if_flags &= ~IFF_OACTIVE; 1542 1543 return; 1544 } 1545 1546 static void nge_tick(xsc) 1547 void *xsc; 1548 { 1549 struct nge_softc *sc; 1550 struct mii_data *mii; 1551 struct ifnet *ifp; 1552 int s; 1553 1554 s = splimp(); 1555 1556 sc = xsc; 1557 ifp = &sc->arpcom.ac_if; 1558 1559 if (sc->nge_tbi) { 1560 if (!sc->nge_link) { 1561 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1562 & NGE_TBIBMSR_ANEG_DONE) { 1563 printf("nge%d: gigabit link up\n", 1564 sc->nge_unit); 1565 nge_miibus_statchg(sc->nge_miibus); 1566 sc->nge_link++; 1567 if (ifp->if_snd.ifq_head != NULL) 1568 nge_start(ifp); 1569 } 1570 } 1571 } else { 1572 mii = device_get_softc(sc->nge_miibus); 1573 mii_tick(mii); 1574 1575 if (!sc->nge_link) { 1576 if (mii->mii_media_status & IFM_ACTIVE && 1577 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1578 sc->nge_link++; 1579 if (IFM_SUBTYPE(mii->mii_media_active) 1580 == IFM_1000_TX) 1581 printf("nge%d: gigabit link up\n", 1582 sc->nge_unit); 1583 if (ifp->if_snd.ifq_head != NULL) 1584 nge_start(ifp); 1585 } 1586 } 1587 } 1588 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1589 1590 splx(s); 1591 1592 return; 1593 } 1594 1595 #ifdef DEVICE_POLLING 1596 static poll_handler_t nge_poll; 1597 1598 static void 1599 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1600 { 1601 struct nge_softc *sc = ifp->if_softc; 1602 1603 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1604 CSR_WRITE_4(sc, NGE_IER, 1); 1605 return; 1606 } 1607 1608 /* 1609 * On the nge, reading the status register also clears it. 1610 * So before returning to intr mode we must make sure that all 1611 * possible pending sources of interrupts have been served. 1612 * In practice this means run to completion the *eof routines, 1613 * and then call the interrupt routine 1614 */ 1615 sc->rxcycles = count; 1616 nge_rxeof(sc); 1617 nge_txeof(sc); 1618 if (ifp->if_snd.ifq_head != NULL) 1619 nge_start(ifp); 1620 1621 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1622 u_int32_t status; 1623 1624 /* Reading the ISR register clears all interrupts. */ 1625 status = CSR_READ_4(sc, NGE_ISR); 1626 1627 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1628 nge_rxeof(sc); 1629 1630 if (status & (NGE_ISR_RX_IDLE)) 1631 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1632 1633 if (status & NGE_ISR_SYSERR) { 1634 nge_reset(sc); 1635 nge_init(sc); 1636 } 1637 } 1638 } 1639 #endif /* DEVICE_POLLING */ 1640 1641 static void nge_intr(arg) 1642 void *arg; 1643 { 1644 struct nge_softc *sc; 1645 struct ifnet *ifp; 1646 u_int32_t status; 1647 1648 sc = arg; 1649 ifp = &sc->arpcom.ac_if; 1650 1651 #ifdef DEVICE_POLLING 1652 if (ifp->if_ipending & IFF_POLLING) 1653 return; 1654 if (ether_poll_register(nge_poll, ifp)) { /* ok, disable interrupts */ 1655 CSR_WRITE_4(sc, NGE_IER, 0); 1656 nge_poll(ifp, 0, 1); 1657 return; 1658 } 1659 #endif /* DEVICE_POLLING */ 1660 1661 /* Supress unwanted interrupts */ 1662 if (!(ifp->if_flags & IFF_UP)) { 1663 nge_stop(sc); 1664 return; 1665 } 1666 1667 /* Disable interrupts. */ 1668 CSR_WRITE_4(sc, NGE_IER, 0); 1669 1670 /* Data LED on for TBI mode */ 1671 if(sc->nge_tbi) 1672 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1673 | NGE_GPIO_GP3_OUT); 1674 1675 for (;;) { 1676 /* Reading the ISR register clears all interrupts. */ 1677 status = CSR_READ_4(sc, NGE_ISR); 1678 1679 if ((status & NGE_INTRS) == 0) 1680 break; 1681 1682 if ((status & NGE_ISR_TX_DESC_OK) || 1683 (status & NGE_ISR_TX_ERR) || 1684 (status & NGE_ISR_TX_OK) || 1685 (status & NGE_ISR_TX_IDLE)) 1686 nge_txeof(sc); 1687 1688 if ((status & NGE_ISR_RX_DESC_OK) || 1689 (status & NGE_ISR_RX_ERR) || 1690 (status & NGE_ISR_RX_OFLOW) || 1691 (status & NGE_ISR_RX_FIFO_OFLOW) || 1692 (status & NGE_ISR_RX_IDLE) || 1693 (status & NGE_ISR_RX_OK)) 1694 nge_rxeof(sc); 1695 1696 if ((status & NGE_ISR_RX_IDLE)) 1697 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1698 1699 if (status & NGE_ISR_SYSERR) { 1700 nge_reset(sc); 1701 ifp->if_flags &= ~IFF_RUNNING; 1702 nge_init(sc); 1703 } 1704 1705 #ifdef notyet 1706 /* mii_tick should only be called once per second */ 1707 if (status & NGE_ISR_PHY_INTR) { 1708 sc->nge_link = 0; 1709 nge_tick(sc); 1710 } 1711 #endif 1712 } 1713 1714 /* Re-enable interrupts. */ 1715 CSR_WRITE_4(sc, NGE_IER, 1); 1716 1717 if (ifp->if_snd.ifq_head != NULL) 1718 nge_start(ifp); 1719 1720 /* Data LED off for TBI mode */ 1721 1722 if(sc->nge_tbi) 1723 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1724 & ~NGE_GPIO_GP3_OUT); 1725 1726 return; 1727 } 1728 1729 /* 1730 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1731 * pointers to the fragment pointers. 1732 */ 1733 static int nge_encap(sc, m_head, txidx) 1734 struct nge_softc *sc; 1735 struct mbuf *m_head; 1736 u_int32_t *txidx; 1737 { 1738 struct nge_desc *f = NULL; 1739 struct mbuf *m; 1740 int frag, cur, cnt = 0; 1741 struct ifvlan *ifv = NULL; 1742 1743 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1744 m_head->m_pkthdr.rcvif != NULL && 1745 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1746 ifv = m_head->m_pkthdr.rcvif->if_softc; 1747 1748 /* 1749 * Start packing the mbufs in this chain into 1750 * the fragment pointers. Stop when we run out 1751 * of fragments or hit the end of the mbuf chain. 1752 */ 1753 m = m_head; 1754 cur = frag = *txidx; 1755 1756 for (m = m_head; m != NULL; m = m->m_next) { 1757 if (m->m_len != 0) { 1758 if ((NGE_TX_LIST_CNT - 1759 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1760 return(ENOBUFS); 1761 f = &sc->nge_ldata->nge_tx_list[frag]; 1762 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1763 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1764 if (cnt != 0) 1765 f->nge_ctl |= NGE_CMDSTS_OWN; 1766 cur = frag; 1767 NGE_INC(frag, NGE_TX_LIST_CNT); 1768 cnt++; 1769 } 1770 } 1771 1772 if (m != NULL) 1773 return(ENOBUFS); 1774 1775 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1776 if (m_head->m_pkthdr.csum_flags) { 1777 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1778 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1779 NGE_TXEXTSTS_IPCSUM; 1780 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1781 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1782 NGE_TXEXTSTS_TCPCSUM; 1783 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1784 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1785 NGE_TXEXTSTS_UDPCSUM; 1786 } 1787 1788 if (ifv != NULL) { 1789 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1790 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag); 1791 } 1792 1793 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1794 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1795 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1796 sc->nge_cdata.nge_tx_cnt += cnt; 1797 *txidx = frag; 1798 1799 return(0); 1800 } 1801 1802 /* 1803 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1804 * to the mbuf data regions directly in the transmit lists. We also save a 1805 * copy of the pointers since the transmit list fragment pointers are 1806 * physical addresses. 1807 */ 1808 1809 static void nge_start(ifp) 1810 struct ifnet *ifp; 1811 { 1812 struct nge_softc *sc; 1813 struct mbuf *m_head = NULL; 1814 u_int32_t idx; 1815 1816 sc = ifp->if_softc; 1817 1818 if (!sc->nge_link) 1819 return; 1820 1821 idx = sc->nge_cdata.nge_tx_prod; 1822 1823 if (ifp->if_flags & IFF_OACTIVE) 1824 return; 1825 1826 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1827 IF_DEQUEUE(&ifp->if_snd, m_head); 1828 if (m_head == NULL) 1829 break; 1830 1831 if (nge_encap(sc, m_head, &idx)) { 1832 IF_PREPEND(&ifp->if_snd, m_head); 1833 ifp->if_flags |= IFF_OACTIVE; 1834 break; 1835 } 1836 1837 /* 1838 * If there's a BPF listener, bounce a copy of this frame 1839 * to him. 1840 */ 1841 if (ifp->if_bpf) 1842 bpf_mtap(ifp, m_head); 1843 1844 } 1845 1846 /* Transmit */ 1847 sc->nge_cdata.nge_tx_prod = idx; 1848 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1849 1850 /* 1851 * Set a timeout in case the chip goes out to lunch. 1852 */ 1853 ifp->if_timer = 5; 1854 1855 return; 1856 } 1857 1858 static void nge_init(xsc) 1859 void *xsc; 1860 { 1861 struct nge_softc *sc = xsc; 1862 struct ifnet *ifp = &sc->arpcom.ac_if; 1863 struct mii_data *mii; 1864 int s; 1865 1866 if (ifp->if_flags & IFF_RUNNING) 1867 return; 1868 1869 s = splimp(); 1870 1871 /* 1872 * Cancel pending I/O and free all RX/TX buffers. 1873 */ 1874 nge_stop(sc); 1875 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1876 1877 if (sc->nge_tbi) { 1878 mii = NULL; 1879 } else { 1880 mii = device_get_softc(sc->nge_miibus); 1881 } 1882 1883 /* Set MAC address */ 1884 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1885 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1886 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1887 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1888 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1889 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1890 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1891 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1892 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1893 1894 /* Init circular RX list. */ 1895 if (nge_list_rx_init(sc) == ENOBUFS) { 1896 printf("nge%d: initialization failed: no " 1897 "memory for rx buffers\n", sc->nge_unit); 1898 nge_stop(sc); 1899 (void)splx(s); 1900 return; 1901 } 1902 1903 /* 1904 * Init tx descriptors. 1905 */ 1906 nge_list_tx_init(sc); 1907 1908 /* 1909 * For the NatSemi chip, we have to explicitly enable the 1910 * reception of ARP frames, as well as turn on the 'perfect 1911 * match' filter where we store the station address, otherwise 1912 * we won't receive unicasts meant for this host. 1913 */ 1914 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1915 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1916 1917 /* If we want promiscuous mode, set the allframes bit. */ 1918 if (ifp->if_flags & IFF_PROMISC) { 1919 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1920 } else { 1921 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1922 } 1923 1924 /* 1925 * Set the capture broadcast bit to capture broadcast frames. 1926 */ 1927 if (ifp->if_flags & IFF_BROADCAST) { 1928 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1929 } else { 1930 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1931 } 1932 1933 /* 1934 * Load the multicast filter. 1935 */ 1936 nge_setmulti(sc); 1937 1938 /* Turn the receive filter on */ 1939 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1940 1941 /* 1942 * Load the address of the RX and TX lists. 1943 */ 1944 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1945 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1946 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1947 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1948 1949 /* Set RX configuration */ 1950 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1951 /* 1952 * Enable hardware checksum validation for all IPv4 1953 * packets, do not reject packets with bad checksums. 1954 */ 1955 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1956 1957 /* 1958 * Tell the chip to detect and strip VLAN tag info from 1959 * received frames. The tag will be provided in the extsts 1960 * field in the RX descriptors. 1961 */ 1962 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1963 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1964 1965 /* Set TX configuration */ 1966 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1967 1968 /* 1969 * Enable TX IPv4 checksumming on a per-packet basis. 1970 */ 1971 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1972 1973 /* 1974 * Tell the chip to insert VLAN tags on a per-packet basis as 1975 * dictated by the code in the frame encapsulation routine. 1976 */ 1977 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1978 1979 /* Set full/half duplex mode. */ 1980 if (sc->nge_tbi) { 1981 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1982 == IFM_FDX) { 1983 NGE_SETBIT(sc, NGE_TX_CFG, 1984 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1985 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1986 } else { 1987 NGE_CLRBIT(sc, NGE_TX_CFG, 1988 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1989 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1990 } 1991 } else { 1992 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1993 NGE_SETBIT(sc, NGE_TX_CFG, 1994 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1995 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1996 } else { 1997 NGE_CLRBIT(sc, NGE_TX_CFG, 1998 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1999 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2000 } 2001 } 2002 2003 /* 2004 * Enable the delivery of PHY interrupts based on 2005 * link/speed/duplex status changes. Also enable the 2006 * extsts field in the DMA descriptors (needed for 2007 * TCP/IP checksum offload on transmit). 2008 */ 2009 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD| 2010 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 2011 2012 /* 2013 * Configure interrupt holdoff (moderation). We can 2014 * have the chip delay interrupt delivery for a certain 2015 * period. Units are in 100us, and the max setting 2016 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 2017 */ 2018 CSR_WRITE_4(sc, NGE_IHR, 0x01); 2019 2020 /* 2021 * Enable interrupts. 2022 */ 2023 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 2024 #ifdef DEVICE_POLLING 2025 /* 2026 * ... only enable interrupts if we are not polling, make sure 2027 * they are off otherwise. 2028 */ 2029 if (ifp->if_ipending & IFF_POLLING) 2030 CSR_WRITE_4(sc, NGE_IER, 0); 2031 else 2032 #endif /* DEVICE_POLLING */ 2033 CSR_WRITE_4(sc, NGE_IER, 1); 2034 2035 /* Enable receiver and transmitter. */ 2036 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2037 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 2038 2039 nge_ifmedia_upd(ifp); 2040 2041 ifp->if_flags |= IFF_RUNNING; 2042 ifp->if_flags &= ~IFF_OACTIVE; 2043 2044 (void)splx(s); 2045 2046 return; 2047 } 2048 2049 /* 2050 * Set media options. 2051 */ 2052 static int nge_ifmedia_upd(ifp) 2053 struct ifnet *ifp; 2054 { 2055 struct nge_softc *sc; 2056 struct mii_data *mii; 2057 2058 sc = ifp->if_softc; 2059 2060 if (sc->nge_tbi) { 2061 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 2062 == IFM_AUTO) { 2063 CSR_WRITE_4(sc, NGE_TBI_ANAR, 2064 CSR_READ_4(sc, NGE_TBI_ANAR) 2065 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 2066 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 2067 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 2068 | NGE_TBIBMCR_RESTART_ANEG); 2069 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 2070 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 2071 & IFM_GMASK) == IFM_FDX) { 2072 NGE_SETBIT(sc, NGE_TX_CFG, 2073 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2074 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2075 2076 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2077 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2078 } else { 2079 NGE_CLRBIT(sc, NGE_TX_CFG, 2080 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2081 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2082 2083 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2084 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2085 } 2086 2087 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 2088 & ~NGE_GPIO_GP3_OUT); 2089 } else { 2090 mii = device_get_softc(sc->nge_miibus); 2091 sc->nge_link = 0; 2092 if (mii->mii_instance) { 2093 struct mii_softc *miisc; 2094 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2095 miisc = LIST_NEXT(miisc, mii_list)) 2096 mii_phy_reset(miisc); 2097 } 2098 mii_mediachg(mii); 2099 } 2100 2101 return(0); 2102 } 2103 2104 /* 2105 * Report current media status. 2106 */ 2107 static void nge_ifmedia_sts(ifp, ifmr) 2108 struct ifnet *ifp; 2109 struct ifmediareq *ifmr; 2110 { 2111 struct nge_softc *sc; 2112 struct mii_data *mii; 2113 2114 sc = ifp->if_softc; 2115 2116 if (sc->nge_tbi) { 2117 ifmr->ifm_status = IFM_AVALID; 2118 ifmr->ifm_active = IFM_ETHER; 2119 2120 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2121 ifmr->ifm_status |= IFM_ACTIVE; 2122 } 2123 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 2124 ifmr->ifm_active |= IFM_LOOP; 2125 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2126 ifmr->ifm_active |= IFM_NONE; 2127 ifmr->ifm_status = 0; 2128 return; 2129 } 2130 ifmr->ifm_active |= IFM_1000_SX; 2131 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 2132 == IFM_AUTO) { 2133 ifmr->ifm_active |= IFM_AUTO; 2134 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2135 & NGE_TBIANAR_FDX) { 2136 ifmr->ifm_active |= IFM_FDX; 2137 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2138 & NGE_TBIANAR_HDX) { 2139 ifmr->ifm_active |= IFM_HDX; 2140 } 2141 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 2142 == IFM_FDX) 2143 ifmr->ifm_active |= IFM_FDX; 2144 else 2145 ifmr->ifm_active |= IFM_HDX; 2146 2147 } else { 2148 mii = device_get_softc(sc->nge_miibus); 2149 mii_pollstat(mii); 2150 ifmr->ifm_active = mii->mii_media_active; 2151 ifmr->ifm_status = mii->mii_media_status; 2152 } 2153 2154 return; 2155 } 2156 2157 static int nge_ioctl(ifp, command, data) 2158 struct ifnet *ifp; 2159 u_long command; 2160 caddr_t data; 2161 { 2162 struct nge_softc *sc = ifp->if_softc; 2163 struct ifreq *ifr = (struct ifreq *) data; 2164 struct mii_data *mii; 2165 int s, error = 0; 2166 2167 s = splimp(); 2168 2169 switch(command) { 2170 case SIOCSIFADDR: 2171 case SIOCGIFADDR: 2172 error = ether_ioctl(ifp, command, data); 2173 break; 2174 case SIOCSIFMTU: 2175 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 2176 error = EINVAL; 2177 else { 2178 ifp->if_mtu = ifr->ifr_mtu; 2179 /* 2180 * Workaround: if the MTU is larger than 2181 * 8152 (TX FIFO size minus 64 minus 18), turn off 2182 * TX checksum offloading. 2183 */ 2184 if (ifr->ifr_mtu >= 8152) 2185 ifp->if_hwassist = 0; 2186 else 2187 ifp->if_hwassist = NGE_CSUM_FEATURES; 2188 } 2189 break; 2190 case SIOCSIFFLAGS: 2191 if (ifp->if_flags & IFF_UP) { 2192 if (ifp->if_flags & IFF_RUNNING && 2193 ifp->if_flags & IFF_PROMISC && 2194 !(sc->nge_if_flags & IFF_PROMISC)) { 2195 NGE_SETBIT(sc, NGE_RXFILT_CTL, 2196 NGE_RXFILTCTL_ALLPHYS| 2197 NGE_RXFILTCTL_ALLMULTI); 2198 } else if (ifp->if_flags & IFF_RUNNING && 2199 !(ifp->if_flags & IFF_PROMISC) && 2200 sc->nge_if_flags & IFF_PROMISC) { 2201 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2202 NGE_RXFILTCTL_ALLPHYS); 2203 if (!(ifp->if_flags & IFF_ALLMULTI)) 2204 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2205 NGE_RXFILTCTL_ALLMULTI); 2206 } else { 2207 ifp->if_flags &= ~IFF_RUNNING; 2208 nge_init(sc); 2209 } 2210 } else { 2211 if (ifp->if_flags & IFF_RUNNING) 2212 nge_stop(sc); 2213 } 2214 sc->nge_if_flags = ifp->if_flags; 2215 error = 0; 2216 break; 2217 case SIOCADDMULTI: 2218 case SIOCDELMULTI: 2219 nge_setmulti(sc); 2220 error = 0; 2221 break; 2222 case SIOCGIFMEDIA: 2223 case SIOCSIFMEDIA: 2224 if (sc->nge_tbi) { 2225 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 2226 command); 2227 } else { 2228 mii = device_get_softc(sc->nge_miibus); 2229 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2230 command); 2231 } 2232 break; 2233 default: 2234 error = EINVAL; 2235 break; 2236 } 2237 2238 (void)splx(s); 2239 2240 return(error); 2241 } 2242 2243 static void nge_watchdog(ifp) 2244 struct ifnet *ifp; 2245 { 2246 struct nge_softc *sc; 2247 2248 sc = ifp->if_softc; 2249 2250 ifp->if_oerrors++; 2251 printf("nge%d: watchdog timeout\n", sc->nge_unit); 2252 2253 nge_stop(sc); 2254 nge_reset(sc); 2255 ifp->if_flags &= ~IFF_RUNNING; 2256 nge_init(sc); 2257 2258 if (ifp->if_snd.ifq_head != NULL) 2259 nge_start(ifp); 2260 2261 return; 2262 } 2263 2264 /* 2265 * Stop the adapter and free any mbufs allocated to the 2266 * RX and TX lists. 2267 */ 2268 static void nge_stop(sc) 2269 struct nge_softc *sc; 2270 { 2271 register int i; 2272 struct ifnet *ifp; 2273 struct ifmedia_entry *ifm; 2274 struct mii_data *mii; 2275 int mtmp, itmp; 2276 2277 ifp = &sc->arpcom.ac_if; 2278 ifp->if_timer = 0; 2279 if (sc->nge_tbi) { 2280 mii = NULL; 2281 } else { 2282 mii = device_get_softc(sc->nge_miibus); 2283 } 2284 2285 untimeout(nge_tick, sc, sc->nge_stat_ch); 2286 #ifdef DEVICE_POLLING 2287 ether_poll_deregister(ifp); 2288 #endif 2289 CSR_WRITE_4(sc, NGE_IER, 0); 2290 CSR_WRITE_4(sc, NGE_IMR, 0); 2291 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2292 DELAY(1000); 2293 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2294 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2295 2296 /* 2297 * Isolate/power down the PHY, but leave the media selection 2298 * unchanged so that things will be put back to normal when 2299 * we bring the interface back up. 2300 */ 2301 itmp = ifp->if_flags; 2302 ifp->if_flags |= IFF_UP; 2303 2304 if (sc->nge_tbi) 2305 ifm = sc->nge_ifmedia.ifm_cur; 2306 else 2307 ifm = mii->mii_media.ifm_cur; 2308 2309 mtmp = ifm->ifm_media; 2310 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2311 2312 if (!sc->nge_tbi) 2313 mii_mediachg(mii); 2314 ifm->ifm_media = mtmp; 2315 ifp->if_flags = itmp; 2316 2317 sc->nge_link = 0; 2318 2319 /* 2320 * Free data in the RX lists. 2321 */ 2322 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2323 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2324 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2325 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2326 } 2327 } 2328 bzero((char *)&sc->nge_ldata->nge_rx_list, 2329 sizeof(sc->nge_ldata->nge_rx_list)); 2330 2331 /* 2332 * Free the TX list buffers. 2333 */ 2334 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2335 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2336 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2337 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2338 } 2339 } 2340 2341 bzero((char *)&sc->nge_ldata->nge_tx_list, 2342 sizeof(sc->nge_ldata->nge_tx_list)); 2343 2344 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2345 2346 return; 2347 } 2348 2349 /* 2350 * Stop all chip I/O so that the kernel's probe routines don't 2351 * get confused by errant DMAs when rebooting. 2352 */ 2353 static void nge_shutdown(dev) 2354 device_t dev; 2355 { 2356 struct nge_softc *sc; 2357 2358 sc = device_get_softc(dev); 2359 2360 nge_reset(sc); 2361 nge_stop(sc); 2362 2363 return; 2364 } 2365