1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $ 34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.7 2004/03/14 15:36:51 joerg Exp $ 35 * 36 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $ 37 */ 38 39 /* 40 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 41 * for FreeBSD. Datasheets are available from: 42 * 43 * http://www.national.com/ds/DP/DP83820.pdf 44 * http://www.national.com/ds/DP/DP83821.pdf 45 * 46 * These chips are used on several low cost gigabit ethernet NICs 47 * sold by D-Link, Addtron, SMC and Asante. Both parts are 48 * virtually the same, except the 83820 is a 64-bit/32-bit part, 49 * while the 83821 is 32-bit only. 50 * 51 * Many cards also use National gigE transceivers, such as the 52 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 53 * contains a full register description that applies to all of these 54 * components: 55 * 56 * http://www.national.com/ds/DP/DP83861.pdf 57 * 58 * Written by Bill Paul <wpaul@bsdi.com> 59 * BSDi Open Source Solutions 60 */ 61 62 /* 63 * The NatSemi DP83820 and 83821 controllers are enhanced versions 64 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 65 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 66 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 67 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 68 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 69 * matching buffers, one perfect address filter buffer and interrupt 70 * moderation. The 83820 supports both 64-bit and 32-bit addressing 71 * and data transfers: the 64-bit support can be toggled on or off 72 * via software. This affects the size of certain fields in the DMA 73 * descriptors. 74 * 75 * There are two bugs/misfeatures in the 83820/83821 that I have 76 * discovered so far: 77 * 78 * - Receive buffers must be aligned on 64-bit boundaries, which means 79 * you must resort to copying data in order to fix up the payload 80 * alignment. 81 * 82 * - In order to transmit jumbo frames larger than 8170 bytes, you have 83 * to turn off transmit checksum offloading, because the chip can't 84 * compute the checksum on an outgoing frame unless it fits entirely 85 * within the TX FIFO, which is only 8192 bytes in size. If you have 86 * TX checksum offload enabled and you transmit attempt to transmit a 87 * frame larger than 8170 bytes, the transmitter will wedge. 88 * 89 * To work around the latter problem, TX checksum offload is disabled 90 * if the user selects an MTU larger than 8152 (8170 - 18). 91 */ 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/sockio.h> 96 #include <sys/mbuf.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 101 #include <net/if.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_types.h> 107 #include <net/vlan/if_vlan_var.h> 108 109 #include <net/bpf.h> 110 111 #include <vm/vm.h> /* for vtophys */ 112 #include <vm/pmap.h> /* for vtophys */ 113 #include <machine/clock.h> /* for DELAY */ 114 #include <machine/bus_pio.h> 115 #include <machine/bus_memio.h> 116 #include <machine/bus.h> 117 #include <machine/resource.h> 118 #include <sys/bus.h> 119 #include <sys/rman.h> 120 121 #include "../mii_layer/mii.h" 122 #include "../mii_layer/miivar.h" 123 124 #include <bus/pci/pcireg.h> 125 #include <bus/pci/pcivar.h> 126 127 #define NGE_USEIOSPACE 128 129 #include "if_ngereg.h" 130 131 132 /* "controller miibus0" required. See GENERIC if you get errors here. */ 133 #include "miibus_if.h" 134 135 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 136 137 /* 138 * Various supported device vendors/types and their names. 139 */ 140 static struct nge_type nge_devs[] = { 141 { NGE_VENDORID, NGE_DEVICEID, 142 "National Semiconductor Gigabit Ethernet" }, 143 { 0, 0, NULL } 144 }; 145 146 static int nge_probe (device_t); 147 static int nge_attach (device_t); 148 static int nge_detach (device_t); 149 150 static int nge_alloc_jumbo_mem (struct nge_softc *); 151 static void nge_free_jumbo_mem (struct nge_softc *); 152 static void *nge_jalloc (struct nge_softc *); 153 static void nge_jfree (caddr_t, u_int); 154 static void nge_jref (caddr_t, u_int); 155 156 static int nge_newbuf (struct nge_softc *, 157 struct nge_desc *, struct mbuf *); 158 static int nge_encap (struct nge_softc *, 159 struct mbuf *, u_int32_t *); 160 static void nge_rxeof (struct nge_softc *); 161 static void nge_txeof (struct nge_softc *); 162 static void nge_intr (void *); 163 static void nge_tick (void *); 164 static void nge_start (struct ifnet *); 165 static int nge_ioctl (struct ifnet *, u_long, caddr_t); 166 static void nge_init (void *); 167 static void nge_stop (struct nge_softc *); 168 static void nge_watchdog (struct ifnet *); 169 static void nge_shutdown (device_t); 170 static int nge_ifmedia_upd (struct ifnet *); 171 static void nge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 172 173 static void nge_delay (struct nge_softc *); 174 static void nge_eeprom_idle (struct nge_softc *); 175 static void nge_eeprom_putbyte (struct nge_softc *, int); 176 static void nge_eeprom_getword (struct nge_softc *, int, u_int16_t *); 177 static void nge_read_eeprom (struct nge_softc *, caddr_t, int, int, int); 178 179 static void nge_mii_sync (struct nge_softc *); 180 static void nge_mii_send (struct nge_softc *, u_int32_t, int); 181 static int nge_mii_readreg (struct nge_softc *, struct nge_mii_frame *); 182 static int nge_mii_writereg (struct nge_softc *, struct nge_mii_frame *); 183 184 static int nge_miibus_readreg (device_t, int, int); 185 static int nge_miibus_writereg (device_t, int, int, int); 186 static void nge_miibus_statchg (device_t); 187 188 static void nge_setmulti (struct nge_softc *); 189 static u_int32_t nge_crc (struct nge_softc *, caddr_t); 190 static void nge_reset (struct nge_softc *); 191 static int nge_list_rx_init (struct nge_softc *); 192 static int nge_list_tx_init (struct nge_softc *); 193 194 #ifdef NGE_USEIOSPACE 195 #define NGE_RES SYS_RES_IOPORT 196 #define NGE_RID NGE_PCI_LOIO 197 #else 198 #define NGE_RES SYS_RES_MEMORY 199 #define NGE_RID NGE_PCI_LOMEM 200 #endif 201 202 static device_method_t nge_methods[] = { 203 /* Device interface */ 204 DEVMETHOD(device_probe, nge_probe), 205 DEVMETHOD(device_attach, nge_attach), 206 DEVMETHOD(device_detach, nge_detach), 207 DEVMETHOD(device_shutdown, nge_shutdown), 208 209 /* bus interface */ 210 DEVMETHOD(bus_print_child, bus_generic_print_child), 211 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 212 213 /* MII interface */ 214 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 215 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 216 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 217 218 { 0, 0 } 219 }; 220 221 static driver_t nge_driver = { 222 "nge", 223 nge_methods, 224 sizeof(struct nge_softc) 225 }; 226 227 static devclass_t nge_devclass; 228 229 DECLARE_DUMMY_MODULE(if_nge); 230 MODULE_DEPEND(if_nge, miibus, 1, 1, 1); 231 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 232 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 233 234 #define NGE_SETBIT(sc, reg, x) \ 235 CSR_WRITE_4(sc, reg, \ 236 CSR_READ_4(sc, reg) | (x)) 237 238 #define NGE_CLRBIT(sc, reg, x) \ 239 CSR_WRITE_4(sc, reg, \ 240 CSR_READ_4(sc, reg) & ~(x)) 241 242 #define SIO_SET(x) \ 243 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x) 244 245 #define SIO_CLR(x) \ 246 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x) 247 248 static void nge_delay(sc) 249 struct nge_softc *sc; 250 { 251 int idx; 252 253 for (idx = (300 / 33) + 1; idx > 0; idx--) 254 CSR_READ_4(sc, NGE_CSR); 255 256 return; 257 } 258 259 static void nge_eeprom_idle(sc) 260 struct nge_softc *sc; 261 { 262 int i; 263 264 SIO_SET(NGE_MEAR_EE_CSEL); 265 nge_delay(sc); 266 SIO_SET(NGE_MEAR_EE_CLK); 267 nge_delay(sc); 268 269 for (i = 0; i < 25; i++) { 270 SIO_CLR(NGE_MEAR_EE_CLK); 271 nge_delay(sc); 272 SIO_SET(NGE_MEAR_EE_CLK); 273 nge_delay(sc); 274 } 275 276 SIO_CLR(NGE_MEAR_EE_CLK); 277 nge_delay(sc); 278 SIO_CLR(NGE_MEAR_EE_CSEL); 279 nge_delay(sc); 280 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 281 282 return; 283 } 284 285 /* 286 * Send a read command and address to the EEPROM, check for ACK. 287 */ 288 static void nge_eeprom_putbyte(sc, addr) 289 struct nge_softc *sc; 290 int addr; 291 { 292 int d, i; 293 294 d = addr | NGE_EECMD_READ; 295 296 /* 297 * Feed in each bit and stobe the clock. 298 */ 299 for (i = 0x400; i; i >>= 1) { 300 if (d & i) { 301 SIO_SET(NGE_MEAR_EE_DIN); 302 } else { 303 SIO_CLR(NGE_MEAR_EE_DIN); 304 } 305 nge_delay(sc); 306 SIO_SET(NGE_MEAR_EE_CLK); 307 nge_delay(sc); 308 SIO_CLR(NGE_MEAR_EE_CLK); 309 nge_delay(sc); 310 } 311 312 return; 313 } 314 315 /* 316 * Read a word of data stored in the EEPROM at address 'addr.' 317 */ 318 static void nge_eeprom_getword(sc, addr, dest) 319 struct nge_softc *sc; 320 int addr; 321 u_int16_t *dest; 322 { 323 int i; 324 u_int16_t word = 0; 325 326 /* Force EEPROM to idle state. */ 327 nge_eeprom_idle(sc); 328 329 /* Enter EEPROM access mode. */ 330 nge_delay(sc); 331 SIO_CLR(NGE_MEAR_EE_CLK); 332 nge_delay(sc); 333 SIO_SET(NGE_MEAR_EE_CSEL); 334 nge_delay(sc); 335 336 /* 337 * Send address of word we want to read. 338 */ 339 nge_eeprom_putbyte(sc, addr); 340 341 /* 342 * Start reading bits from EEPROM. 343 */ 344 for (i = 0x8000; i; i >>= 1) { 345 SIO_SET(NGE_MEAR_EE_CLK); 346 nge_delay(sc); 347 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 348 word |= i; 349 nge_delay(sc); 350 SIO_CLR(NGE_MEAR_EE_CLK); 351 nge_delay(sc); 352 } 353 354 /* Turn off EEPROM access mode. */ 355 nge_eeprom_idle(sc); 356 357 *dest = word; 358 359 return; 360 } 361 362 /* 363 * Read a sequence of words from the EEPROM. 364 */ 365 static void nge_read_eeprom(sc, dest, off, cnt, swap) 366 struct nge_softc *sc; 367 caddr_t dest; 368 int off; 369 int cnt; 370 int swap; 371 { 372 int i; 373 u_int16_t word = 0, *ptr; 374 375 for (i = 0; i < cnt; i++) { 376 nge_eeprom_getword(sc, off + i, &word); 377 ptr = (u_int16_t *)(dest + (i * 2)); 378 if (swap) 379 *ptr = ntohs(word); 380 else 381 *ptr = word; 382 } 383 384 return; 385 } 386 387 /* 388 * Sync the PHYs by setting data bit and strobing the clock 32 times. 389 */ 390 static void nge_mii_sync(sc) 391 struct nge_softc *sc; 392 { 393 int i; 394 395 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 396 397 for (i = 0; i < 32; i++) { 398 SIO_SET(NGE_MEAR_MII_CLK); 399 DELAY(1); 400 SIO_CLR(NGE_MEAR_MII_CLK); 401 DELAY(1); 402 } 403 404 return; 405 } 406 407 /* 408 * Clock a series of bits through the MII. 409 */ 410 static void nge_mii_send(sc, bits, cnt) 411 struct nge_softc *sc; 412 u_int32_t bits; 413 int cnt; 414 { 415 int i; 416 417 SIO_CLR(NGE_MEAR_MII_CLK); 418 419 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 420 if (bits & i) { 421 SIO_SET(NGE_MEAR_MII_DATA); 422 } else { 423 SIO_CLR(NGE_MEAR_MII_DATA); 424 } 425 DELAY(1); 426 SIO_CLR(NGE_MEAR_MII_CLK); 427 DELAY(1); 428 SIO_SET(NGE_MEAR_MII_CLK); 429 } 430 } 431 432 /* 433 * Read an PHY register through the MII. 434 */ 435 static int nge_mii_readreg(sc, frame) 436 struct nge_softc *sc; 437 struct nge_mii_frame *frame; 438 439 { 440 int i, ack, s; 441 442 s = splimp(); 443 444 /* 445 * Set up frame for RX. 446 */ 447 frame->mii_stdelim = NGE_MII_STARTDELIM; 448 frame->mii_opcode = NGE_MII_READOP; 449 frame->mii_turnaround = 0; 450 frame->mii_data = 0; 451 452 CSR_WRITE_4(sc, NGE_MEAR, 0); 453 454 /* 455 * Turn on data xmit. 456 */ 457 SIO_SET(NGE_MEAR_MII_DIR); 458 459 nge_mii_sync(sc); 460 461 /* 462 * Send command/address info. 463 */ 464 nge_mii_send(sc, frame->mii_stdelim, 2); 465 nge_mii_send(sc, frame->mii_opcode, 2); 466 nge_mii_send(sc, frame->mii_phyaddr, 5); 467 nge_mii_send(sc, frame->mii_regaddr, 5); 468 469 /* Idle bit */ 470 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 471 DELAY(1); 472 SIO_SET(NGE_MEAR_MII_CLK); 473 DELAY(1); 474 475 /* Turn off xmit. */ 476 SIO_CLR(NGE_MEAR_MII_DIR); 477 /* Check for ack */ 478 SIO_CLR(NGE_MEAR_MII_CLK); 479 DELAY(1); 480 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 481 SIO_SET(NGE_MEAR_MII_CLK); 482 DELAY(1); 483 484 /* 485 * Now try reading data bits. If the ack failed, we still 486 * need to clock through 16 cycles to keep the PHY(s) in sync. 487 */ 488 if (ack) { 489 for(i = 0; i < 16; i++) { 490 SIO_CLR(NGE_MEAR_MII_CLK); 491 DELAY(1); 492 SIO_SET(NGE_MEAR_MII_CLK); 493 DELAY(1); 494 } 495 goto fail; 496 } 497 498 for (i = 0x8000; i; i >>= 1) { 499 SIO_CLR(NGE_MEAR_MII_CLK); 500 DELAY(1); 501 if (!ack) { 502 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 503 frame->mii_data |= i; 504 DELAY(1); 505 } 506 SIO_SET(NGE_MEAR_MII_CLK); 507 DELAY(1); 508 } 509 510 fail: 511 512 SIO_CLR(NGE_MEAR_MII_CLK); 513 DELAY(1); 514 SIO_SET(NGE_MEAR_MII_CLK); 515 DELAY(1); 516 517 splx(s); 518 519 if (ack) 520 return(1); 521 return(0); 522 } 523 524 /* 525 * Write to a PHY register through the MII. 526 */ 527 static int nge_mii_writereg(sc, frame) 528 struct nge_softc *sc; 529 struct nge_mii_frame *frame; 530 531 { 532 int s; 533 534 s = splimp(); 535 /* 536 * Set up frame for TX. 537 */ 538 539 frame->mii_stdelim = NGE_MII_STARTDELIM; 540 frame->mii_opcode = NGE_MII_WRITEOP; 541 frame->mii_turnaround = NGE_MII_TURNAROUND; 542 543 /* 544 * Turn on data output. 545 */ 546 SIO_SET(NGE_MEAR_MII_DIR); 547 548 nge_mii_sync(sc); 549 550 nge_mii_send(sc, frame->mii_stdelim, 2); 551 nge_mii_send(sc, frame->mii_opcode, 2); 552 nge_mii_send(sc, frame->mii_phyaddr, 5); 553 nge_mii_send(sc, frame->mii_regaddr, 5); 554 nge_mii_send(sc, frame->mii_turnaround, 2); 555 nge_mii_send(sc, frame->mii_data, 16); 556 557 /* Idle bit. */ 558 SIO_SET(NGE_MEAR_MII_CLK); 559 DELAY(1); 560 SIO_CLR(NGE_MEAR_MII_CLK); 561 DELAY(1); 562 563 /* 564 * Turn off xmit. 565 */ 566 SIO_CLR(NGE_MEAR_MII_DIR); 567 568 splx(s); 569 570 return(0); 571 } 572 573 static int nge_miibus_readreg(dev, phy, reg) 574 device_t dev; 575 int phy, reg; 576 { 577 struct nge_softc *sc; 578 struct nge_mii_frame frame; 579 580 sc = device_get_softc(dev); 581 582 bzero((char *)&frame, sizeof(frame)); 583 584 frame.mii_phyaddr = phy; 585 frame.mii_regaddr = reg; 586 nge_mii_readreg(sc, &frame); 587 588 return(frame.mii_data); 589 } 590 591 static int nge_miibus_writereg(dev, phy, reg, data) 592 device_t dev; 593 int phy, reg, data; 594 { 595 struct nge_softc *sc; 596 struct nge_mii_frame frame; 597 598 sc = device_get_softc(dev); 599 600 bzero((char *)&frame, sizeof(frame)); 601 602 frame.mii_phyaddr = phy; 603 frame.mii_regaddr = reg; 604 frame.mii_data = data; 605 nge_mii_writereg(sc, &frame); 606 607 return(0); 608 } 609 610 static void nge_miibus_statchg(dev) 611 device_t dev; 612 { 613 int status; 614 struct nge_softc *sc; 615 struct mii_data *mii; 616 617 sc = device_get_softc(dev); 618 if (sc->nge_tbi) { 619 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 620 == IFM_AUTO) { 621 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 622 if (status == 0 || status & NGE_TBIANAR_FDX) { 623 NGE_SETBIT(sc, NGE_TX_CFG, 624 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 625 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 626 } else { 627 NGE_CLRBIT(sc, NGE_TX_CFG, 628 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 629 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 630 } 631 632 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 633 != IFM_FDX) { 634 NGE_CLRBIT(sc, NGE_TX_CFG, 635 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 636 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 637 } else { 638 NGE_SETBIT(sc, NGE_TX_CFG, 639 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 640 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 641 } 642 } else { 643 mii = device_get_softc(sc->nge_miibus); 644 645 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 646 NGE_SETBIT(sc, NGE_TX_CFG, 647 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 648 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 649 } else { 650 NGE_CLRBIT(sc, NGE_TX_CFG, 651 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 652 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 653 } 654 655 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 656 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 657 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 658 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 659 } else { 660 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 661 } 662 } 663 return; 664 } 665 666 static u_int32_t nge_crc(sc, addr) 667 struct nge_softc *sc; 668 caddr_t addr; 669 { 670 u_int32_t crc, carry; 671 int i, j; 672 u_int8_t c; 673 674 /* Compute CRC for the address value. */ 675 crc = 0xFFFFFFFF; /* initial value */ 676 677 for (i = 0; i < 6; i++) { 678 c = *(addr + i); 679 for (j = 0; j < 8; j++) { 680 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 681 crc <<= 1; 682 c >>= 1; 683 if (carry) 684 crc = (crc ^ 0x04c11db6) | carry; 685 } 686 } 687 688 /* 689 * return the filter bit position 690 */ 691 692 return((crc >> 21) & 0x00000FFF); 693 } 694 695 static void nge_setmulti(sc) 696 struct nge_softc *sc; 697 { 698 struct ifnet *ifp; 699 struct ifmultiaddr *ifma; 700 u_int32_t h = 0, i, filtsave; 701 int bit, index; 702 703 ifp = &sc->arpcom.ac_if; 704 705 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 706 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 707 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 708 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 709 return; 710 } 711 712 /* 713 * We have to explicitly enable the multicast hash table 714 * on the NatSemi chip if we want to use it, which we do. 715 * We also have to tell it that we don't want to use the 716 * hash table for matching unicast addresses. 717 */ 718 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 719 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 720 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 721 722 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 723 724 /* first, zot all the existing hash bits */ 725 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 726 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 727 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 728 } 729 730 /* 731 * From the 11 bits returned by the crc routine, the top 7 732 * bits represent the 16-bit word in the mcast hash table 733 * that needs to be updated, and the lower 4 bits represent 734 * which bit within that byte needs to be set. 735 */ 736 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 737 if (ifma->ifma_addr->sa_family != AF_LINK) 738 continue; 739 h = nge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 740 index = (h >> 4) & 0x7F; 741 bit = h & 0xF; 742 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 743 NGE_FILTADDR_MCAST_LO + (index * 2)); 744 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 745 } 746 747 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 748 749 return; 750 } 751 752 static void nge_reset(sc) 753 struct nge_softc *sc; 754 { 755 int i; 756 757 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 758 759 for (i = 0; i < NGE_TIMEOUT; i++) { 760 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 761 break; 762 } 763 764 if (i == NGE_TIMEOUT) 765 printf("nge%d: reset never completed\n", sc->nge_unit); 766 767 /* Wait a little while for the chip to get its brains in order. */ 768 DELAY(1000); 769 770 /* 771 * If this is a NetSemi chip, make sure to clear 772 * PME mode. 773 */ 774 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 775 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 776 777 return; 778 } 779 780 /* 781 * Probe for an NatSemi chip. Check the PCI vendor and device 782 * IDs against our list and return a device name if we find a match. 783 */ 784 static int nge_probe(dev) 785 device_t dev; 786 { 787 struct nge_type *t; 788 789 t = nge_devs; 790 791 while(t->nge_name != NULL) { 792 if ((pci_get_vendor(dev) == t->nge_vid) && 793 (pci_get_device(dev) == t->nge_did)) { 794 device_set_desc(dev, t->nge_name); 795 return(0); 796 } 797 t++; 798 } 799 800 return(ENXIO); 801 } 802 803 /* 804 * Attach the interface. Allocate softc structures, do ifmedia 805 * setup and ethernet/BPF attach. 806 */ 807 static int nge_attach(dev) 808 device_t dev; 809 { 810 int s; 811 u_char eaddr[ETHER_ADDR_LEN]; 812 u_int32_t command; 813 struct nge_softc *sc; 814 struct ifnet *ifp; 815 int unit, error = 0, rid; 816 const char *sep = ""; 817 818 s = splimp(); 819 820 sc = device_get_softc(dev); 821 unit = device_get_unit(dev); 822 bzero(sc, sizeof(struct nge_softc)); 823 824 /* 825 * Handle power management nonsense. 826 */ 827 828 829 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF; 830 if (command == 0x01) { 831 832 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4); 833 if (command & NGE_PSTATE_MASK) { 834 u_int32_t iobase, membase, irq; 835 836 /* Save important PCI config data. */ 837 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 838 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 839 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 840 841 /* Reset the power state. */ 842 printf("nge%d: chip is in D%d power mode " 843 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK); 844 command &= 0xFFFFFFFC; 845 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4); 846 847 /* Restore PCI config data. */ 848 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 849 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 850 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 851 } 852 } 853 854 /* 855 * Map control/status registers. 856 */ 857 command = pci_read_config(dev, PCIR_COMMAND, 4); 858 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 859 pci_write_config(dev, PCIR_COMMAND, command, 4); 860 command = pci_read_config(dev, PCIR_COMMAND, 4); 861 862 #ifdef NGE_USEIOSPACE 863 if (!(command & PCIM_CMD_PORTEN)) { 864 printf("nge%d: failed to enable I/O ports!\n", unit); 865 error = ENXIO;; 866 goto fail; 867 } 868 #else 869 if (!(command & PCIM_CMD_MEMEN)) { 870 printf("nge%d: failed to enable memory mapping!\n", unit); 871 error = ENXIO;; 872 goto fail; 873 } 874 #endif 875 876 rid = NGE_RID; 877 sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid, 878 0, ~0, 1, RF_ACTIVE); 879 880 if (sc->nge_res == NULL) { 881 printf("nge%d: couldn't map ports/memory\n", unit); 882 error = ENXIO; 883 goto fail; 884 } 885 886 sc->nge_btag = rman_get_bustag(sc->nge_res); 887 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 888 889 /* Allocate interrupt */ 890 rid = 0; 891 sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 892 RF_SHAREABLE | RF_ACTIVE); 893 894 if (sc->nge_irq == NULL) { 895 printf("nge%d: couldn't map interrupt\n", unit); 896 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 897 error = ENXIO; 898 goto fail; 899 } 900 901 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 902 nge_intr, sc, &sc->nge_intrhand); 903 904 if (error) { 905 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 906 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 907 printf("nge%d: couldn't set up irq\n", unit); 908 goto fail; 909 } 910 911 /* Reset the adapter. */ 912 nge_reset(sc); 913 914 /* 915 * Get station address from the EEPROM. 916 */ 917 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 918 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 919 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 920 921 /* 922 * A NatSemi chip was detected. Inform the world. 923 */ 924 printf("nge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 925 926 sc->nge_unit = unit; 927 928 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 929 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 930 931 if (sc->nge_ldata == NULL) { 932 printf("nge%d: no memory for list buffers!\n", unit); 933 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 934 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 935 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 936 error = ENXIO; 937 goto fail; 938 } 939 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 940 941 /* Try to allocate memory for jumbo buffers. */ 942 if (nge_alloc_jumbo_mem(sc)) { 943 printf("nge%d: jumbo buffer allocation failed\n", 944 sc->nge_unit); 945 contigfree(sc->nge_ldata, 946 sizeof(struct nge_list_data), M_DEVBUF); 947 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 948 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 949 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 950 error = ENXIO; 951 goto fail; 952 } 953 954 ifp = &sc->arpcom.ac_if; 955 ifp->if_softc = sc; 956 if_initname(ifp, "nge", unit); 957 ifp->if_mtu = ETHERMTU; 958 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 959 ifp->if_ioctl = nge_ioctl; 960 ifp->if_output = ether_output; 961 ifp->if_start = nge_start; 962 ifp->if_watchdog = nge_watchdog; 963 ifp->if_init = nge_init; 964 ifp->if_baudrate = 1000000000; 965 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 966 ifp->if_hwassist = NGE_CSUM_FEATURES; 967 ifp->if_capabilities = IFCAP_HWCSUM; 968 ifp->if_capenable = ifp->if_capabilities; 969 970 /* 971 * Do MII setup. 972 */ 973 if (mii_phy_probe(dev, &sc->nge_miibus, 974 nge_ifmedia_upd, nge_ifmedia_sts)) { 975 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 976 sc->nge_tbi = 1; 977 device_printf(dev, "Using TBI\n"); 978 979 sc->nge_miibus = dev; 980 981 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 982 nge_ifmedia_sts); 983 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 984 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 985 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 986 device_printf(dev, " "); 987 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 988 PRINT("1000baseSX"); 989 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 990 PRINT("1000baseSX-FDX"); 991 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 992 PRINT("auto"); 993 994 printf("\n"); 995 #undef ADD 996 #undef PRINT 997 ifmedia_set(&sc->nge_ifmedia, 998 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 999 1000 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1001 | NGE_GPIO_GP4_OUT 1002 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 1003 | NGE_GPIO_GP3_OUTENB 1004 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 1005 1006 } else { 1007 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 1008 nge_free_jumbo_mem(sc); 1009 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1010 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1011 bus_release_resource(dev, NGE_RES, NGE_RID, 1012 sc->nge_res); 1013 error = ENXIO; 1014 goto fail; 1015 } 1016 } 1017 1018 /* 1019 * Call MI attach routine. 1020 */ 1021 ether_ifattach(ifp, eaddr); 1022 callout_handle_init(&sc->nge_stat_ch); 1023 1024 fail: 1025 1026 splx(s); 1027 return(error); 1028 } 1029 1030 static int nge_detach(dev) 1031 device_t dev; 1032 { 1033 struct nge_softc *sc; 1034 struct ifnet *ifp; 1035 int s; 1036 1037 s = splimp(); 1038 1039 sc = device_get_softc(dev); 1040 ifp = &sc->arpcom.ac_if; 1041 1042 nge_reset(sc); 1043 nge_stop(sc); 1044 ether_ifdetach(ifp); 1045 1046 bus_generic_detach(dev); 1047 if (!sc->nge_tbi) { 1048 device_delete_child(dev, sc->nge_miibus); 1049 } 1050 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1051 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1052 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 1053 1054 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 1055 nge_free_jumbo_mem(sc); 1056 1057 splx(s); 1058 1059 return(0); 1060 } 1061 1062 /* 1063 * Initialize the transmit descriptors. 1064 */ 1065 static int nge_list_tx_init(sc) 1066 struct nge_softc *sc; 1067 { 1068 struct nge_list_data *ld; 1069 struct nge_ring_data *cd; 1070 int i; 1071 1072 cd = &sc->nge_cdata; 1073 ld = sc->nge_ldata; 1074 1075 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1076 if (i == (NGE_TX_LIST_CNT - 1)) { 1077 ld->nge_tx_list[i].nge_nextdesc = 1078 &ld->nge_tx_list[0]; 1079 ld->nge_tx_list[i].nge_next = 1080 vtophys(&ld->nge_tx_list[0]); 1081 } else { 1082 ld->nge_tx_list[i].nge_nextdesc = 1083 &ld->nge_tx_list[i + 1]; 1084 ld->nge_tx_list[i].nge_next = 1085 vtophys(&ld->nge_tx_list[i + 1]); 1086 } 1087 ld->nge_tx_list[i].nge_mbuf = NULL; 1088 ld->nge_tx_list[i].nge_ptr = 0; 1089 ld->nge_tx_list[i].nge_ctl = 0; 1090 } 1091 1092 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1093 1094 return(0); 1095 } 1096 1097 1098 /* 1099 * Initialize the RX descriptors and allocate mbufs for them. Note that 1100 * we arrange the descriptors in a closed ring, so that the last descriptor 1101 * points back to the first. 1102 */ 1103 static int nge_list_rx_init(sc) 1104 struct nge_softc *sc; 1105 { 1106 struct nge_list_data *ld; 1107 struct nge_ring_data *cd; 1108 int i; 1109 1110 ld = sc->nge_ldata; 1111 cd = &sc->nge_cdata; 1112 1113 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1114 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1115 return(ENOBUFS); 1116 if (i == (NGE_RX_LIST_CNT - 1)) { 1117 ld->nge_rx_list[i].nge_nextdesc = 1118 &ld->nge_rx_list[0]; 1119 ld->nge_rx_list[i].nge_next = 1120 vtophys(&ld->nge_rx_list[0]); 1121 } else { 1122 ld->nge_rx_list[i].nge_nextdesc = 1123 &ld->nge_rx_list[i + 1]; 1124 ld->nge_rx_list[i].nge_next = 1125 vtophys(&ld->nge_rx_list[i + 1]); 1126 } 1127 } 1128 1129 cd->nge_rx_prod = 0; 1130 1131 return(0); 1132 } 1133 1134 /* 1135 * Initialize an RX descriptor and attach an MBUF cluster. 1136 */ 1137 static int nge_newbuf(sc, c, m) 1138 struct nge_softc *sc; 1139 struct nge_desc *c; 1140 struct mbuf *m; 1141 { 1142 struct mbuf *m_new = NULL; 1143 caddr_t *buf = NULL; 1144 1145 if (m == NULL) { 1146 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1147 if (m_new == NULL) { 1148 printf("nge%d: no memory for rx list " 1149 "-- packet dropped!\n", sc->nge_unit); 1150 return(ENOBUFS); 1151 } 1152 1153 /* Allocate the jumbo buffer */ 1154 buf = nge_jalloc(sc); 1155 if (buf == NULL) { 1156 #ifdef NGE_VERBOSE 1157 printf("nge%d: jumbo allocation failed " 1158 "-- packet dropped!\n", sc->nge_unit); 1159 #endif 1160 m_freem(m_new); 1161 return(ENOBUFS); 1162 } 1163 /* Attach the buffer to the mbuf */ 1164 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 1165 m_new->m_flags |= M_EXT; 1166 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 1167 m_new->m_len = NGE_MCLBYTES; 1168 m_new->m_ext.ext_free = nge_jfree; 1169 m_new->m_ext.ext_ref = nge_jref; 1170 } else { 1171 m_new = m; 1172 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES; 1173 m_new->m_data = m_new->m_ext.ext_buf; 1174 } 1175 1176 m_adj(m_new, sizeof(u_int64_t)); 1177 1178 c->nge_mbuf = m_new; 1179 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1180 c->nge_ctl = m_new->m_len; 1181 c->nge_extsts = 0; 1182 1183 return(0); 1184 } 1185 1186 static int nge_alloc_jumbo_mem(sc) 1187 struct nge_softc *sc; 1188 { 1189 caddr_t ptr; 1190 int i; 1191 struct nge_jpool_entry *entry; 1192 1193 /* Grab a big chunk o' storage. */ 1194 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1195 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1196 1197 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1198 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1199 return(ENOBUFS); 1200 } 1201 1202 SLIST_INIT(&sc->nge_jfree_listhead); 1203 SLIST_INIT(&sc->nge_jinuse_listhead); 1204 1205 /* 1206 * Now divide it up into 9K pieces and save the addresses 1207 * in an array. 1208 */ 1209 ptr = sc->nge_cdata.nge_jumbo_buf; 1210 for (i = 0; i < NGE_JSLOTS; i++) { 1211 u_int64_t **aptr; 1212 aptr = (u_int64_t **)ptr; 1213 aptr[0] = (u_int64_t *)sc; 1214 ptr += sizeof(u_int64_t); 1215 sc->nge_cdata.nge_jslots[i].nge_buf = ptr; 1216 sc->nge_cdata.nge_jslots[i].nge_inuse = 0; 1217 ptr += NGE_MCLBYTES; 1218 entry = malloc(sizeof(struct nge_jpool_entry), 1219 M_DEVBUF, M_NOWAIT); 1220 if (entry == NULL) { 1221 printf("nge%d: no memory for jumbo " 1222 "buffer queue!\n", sc->nge_unit); 1223 return(ENOBUFS); 1224 } 1225 entry->slot = i; 1226 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1227 entry, jpool_entries); 1228 } 1229 1230 return(0); 1231 } 1232 1233 static void nge_free_jumbo_mem(sc) 1234 struct nge_softc *sc; 1235 { 1236 int i; 1237 struct nge_jpool_entry *entry; 1238 1239 for (i = 0; i < NGE_JSLOTS; i++) { 1240 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1241 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1242 free(entry, M_DEVBUF); 1243 } 1244 1245 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1246 1247 return; 1248 } 1249 1250 /* 1251 * Allocate a jumbo buffer. 1252 */ 1253 static void *nge_jalloc(sc) 1254 struct nge_softc *sc; 1255 { 1256 struct nge_jpool_entry *entry; 1257 1258 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1259 1260 if (entry == NULL) { 1261 #ifdef NGE_VERBOSE 1262 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1263 #endif 1264 return(NULL); 1265 } 1266 1267 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1268 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1269 sc->nge_cdata.nge_jslots[entry->slot].nge_inuse = 1; 1270 return(sc->nge_cdata.nge_jslots[entry->slot].nge_buf); 1271 } 1272 1273 /* 1274 * Adjust usage count on a jumbo buffer. In general this doesn't 1275 * get used much because our jumbo buffers don't get passed around 1276 * a lot, but it's implemented for correctness. 1277 */ 1278 static void nge_jref(buf, size) 1279 caddr_t buf; 1280 u_int size; 1281 { 1282 struct nge_softc *sc; 1283 u_int64_t **aptr; 1284 int i; 1285 1286 /* Extract the softc struct pointer. */ 1287 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 1288 sc = (struct nge_softc *)(aptr[0]); 1289 1290 if (sc == NULL) 1291 panic("nge_jref: can't find softc pointer!"); 1292 1293 if (size != NGE_MCLBYTES) 1294 panic("nge_jref: adjusting refcount of buf of wrong size!"); 1295 1296 /* calculate the slot this buffer belongs to */ 1297 1298 i = ((vm_offset_t)aptr 1299 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1300 1301 if ((i < 0) || (i >= NGE_JSLOTS)) 1302 panic("nge_jref: asked to reference buffer " 1303 "that we don't manage!"); 1304 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0) 1305 panic("nge_jref: buffer already free!"); 1306 else 1307 sc->nge_cdata.nge_jslots[i].nge_inuse++; 1308 1309 return; 1310 } 1311 1312 /* 1313 * Release a jumbo buffer. 1314 */ 1315 static void nge_jfree(buf, size) 1316 caddr_t buf; 1317 u_int size; 1318 { 1319 struct nge_softc *sc; 1320 u_int64_t **aptr; 1321 int i; 1322 struct nge_jpool_entry *entry; 1323 1324 /* Extract the softc struct pointer. */ 1325 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 1326 sc = (struct nge_softc *)(aptr[0]); 1327 1328 if (sc == NULL) 1329 panic("nge_jfree: can't find softc pointer!"); 1330 1331 if (size != NGE_MCLBYTES) 1332 panic("nge_jfree: freeing buffer of wrong size!"); 1333 1334 /* calculate the slot this buffer belongs to */ 1335 1336 i = ((vm_offset_t)aptr 1337 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1338 1339 if ((i < 0) || (i >= NGE_JSLOTS)) 1340 panic("nge_jfree: asked to free buffer that we don't manage!"); 1341 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0) 1342 panic("nge_jfree: buffer already free!"); 1343 else { 1344 sc->nge_cdata.nge_jslots[i].nge_inuse--; 1345 if(sc->nge_cdata.nge_jslots[i].nge_inuse == 0) { 1346 entry = SLIST_FIRST(&sc->nge_jinuse_listhead); 1347 if (entry == NULL) 1348 panic("nge_jfree: buffer not in use!"); 1349 entry->slot = i; 1350 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, 1351 jpool_entries); 1352 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1353 entry, jpool_entries); 1354 } 1355 } 1356 1357 return; 1358 } 1359 /* 1360 * A frame has been uploaded: pass the resulting mbuf chain up to 1361 * the higher level protocols. 1362 */ 1363 static void nge_rxeof(sc) 1364 struct nge_softc *sc; 1365 { 1366 struct ether_header *eh; 1367 struct mbuf *m; 1368 struct ifnet *ifp; 1369 struct nge_desc *cur_rx; 1370 int i, total_len = 0; 1371 u_int32_t rxstat; 1372 1373 ifp = &sc->arpcom.ac_if; 1374 i = sc->nge_cdata.nge_rx_prod; 1375 1376 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1377 struct mbuf *m0 = NULL; 1378 u_int32_t extsts; 1379 1380 #ifdef DEVICE_POLLING 1381 if (ifp->if_ipending & IFF_POLLING) { 1382 if (sc->rxcycles <= 0) 1383 break; 1384 sc->rxcycles--; 1385 } 1386 #endif /* DEVICE_POLLING */ 1387 1388 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1389 rxstat = cur_rx->nge_rxstat; 1390 extsts = cur_rx->nge_extsts; 1391 m = cur_rx->nge_mbuf; 1392 cur_rx->nge_mbuf = NULL; 1393 total_len = NGE_RXBYTES(cur_rx); 1394 NGE_INC(i, NGE_RX_LIST_CNT); 1395 /* 1396 * If an error occurs, update stats, clear the 1397 * status word and leave the mbuf cluster in place: 1398 * it should simply get re-used next time this descriptor 1399 * comes up in the ring. 1400 */ 1401 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1402 ifp->if_ierrors++; 1403 nge_newbuf(sc, cur_rx, m); 1404 continue; 1405 } 1406 1407 /* 1408 * Ok. NatSemi really screwed up here. This is the 1409 * only gigE chip I know of with alignment constraints 1410 * on receive buffers. RX buffers must be 64-bit aligned. 1411 */ 1412 #ifdef __i386__ 1413 /* 1414 * By popular demand, ignore the alignment problems 1415 * on the Intel x86 platform. The performance hit 1416 * incurred due to unaligned accesses is much smaller 1417 * than the hit produced by forcing buffer copies all 1418 * the time, especially with jumbo frames. We still 1419 * need to fix up the alignment everywhere else though. 1420 */ 1421 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1422 #endif 1423 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1424 total_len + ETHER_ALIGN, 0, ifp, NULL); 1425 nge_newbuf(sc, cur_rx, m); 1426 if (m0 == NULL) { 1427 printf("nge%d: no receive buffers " 1428 "available -- packet dropped!\n", 1429 sc->nge_unit); 1430 ifp->if_ierrors++; 1431 continue; 1432 } 1433 m_adj(m0, ETHER_ALIGN); 1434 m = m0; 1435 #ifdef __i386__ 1436 } else { 1437 m->m_pkthdr.rcvif = ifp; 1438 m->m_pkthdr.len = m->m_len = total_len; 1439 } 1440 #endif 1441 1442 ifp->if_ipackets++; 1443 eh = mtod(m, struct ether_header *); 1444 1445 /* Remove header from mbuf and pass it on. */ 1446 m_adj(m, sizeof(struct ether_header)); 1447 1448 /* Do IP checksum checking. */ 1449 if (extsts & NGE_RXEXTSTS_IPPKT) 1450 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1451 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1452 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1453 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1454 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1455 (extsts & NGE_RXEXTSTS_UDPPKT && 1456 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1457 m->m_pkthdr.csum_flags |= 1458 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1459 m->m_pkthdr.csum_data = 0xffff; 1460 } 1461 1462 /* 1463 * If we received a packet with a vlan tag, pass it 1464 * to vlan_input() instead of ether_input(). 1465 */ 1466 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1467 VLAN_INPUT_TAG(eh, m, extsts & NGE_RXEXTSTS_VTCI); 1468 continue; 1469 } 1470 1471 ether_input(ifp, eh, m); 1472 } 1473 1474 sc->nge_cdata.nge_rx_prod = i; 1475 1476 return; 1477 } 1478 1479 /* 1480 * A frame was downloaded to the chip. It's safe for us to clean up 1481 * the list buffers. 1482 */ 1483 1484 static void nge_txeof(sc) 1485 struct nge_softc *sc; 1486 { 1487 struct nge_desc *cur_tx = NULL; 1488 struct ifnet *ifp; 1489 u_int32_t idx; 1490 1491 ifp = &sc->arpcom.ac_if; 1492 1493 /* Clear the timeout timer. */ 1494 ifp->if_timer = 0; 1495 1496 /* 1497 * Go through our tx list and free mbufs for those 1498 * frames that have been transmitted. 1499 */ 1500 idx = sc->nge_cdata.nge_tx_cons; 1501 while (idx != sc->nge_cdata.nge_tx_prod) { 1502 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1503 1504 if (NGE_OWNDESC(cur_tx)) 1505 break; 1506 1507 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1508 sc->nge_cdata.nge_tx_cnt--; 1509 NGE_INC(idx, NGE_TX_LIST_CNT); 1510 continue; 1511 } 1512 1513 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1514 ifp->if_oerrors++; 1515 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1516 ifp->if_collisions++; 1517 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1518 ifp->if_collisions++; 1519 } 1520 1521 ifp->if_collisions += 1522 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1523 1524 ifp->if_opackets++; 1525 if (cur_tx->nge_mbuf != NULL) { 1526 m_freem(cur_tx->nge_mbuf); 1527 cur_tx->nge_mbuf = NULL; 1528 } 1529 1530 sc->nge_cdata.nge_tx_cnt--; 1531 NGE_INC(idx, NGE_TX_LIST_CNT); 1532 ifp->if_timer = 0; 1533 } 1534 1535 sc->nge_cdata.nge_tx_cons = idx; 1536 1537 if (cur_tx != NULL) 1538 ifp->if_flags &= ~IFF_OACTIVE; 1539 1540 return; 1541 } 1542 1543 static void nge_tick(xsc) 1544 void *xsc; 1545 { 1546 struct nge_softc *sc; 1547 struct mii_data *mii; 1548 struct ifnet *ifp; 1549 int s; 1550 1551 s = splimp(); 1552 1553 sc = xsc; 1554 ifp = &sc->arpcom.ac_if; 1555 1556 if (sc->nge_tbi) { 1557 if (!sc->nge_link) { 1558 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1559 & NGE_TBIBMSR_ANEG_DONE) { 1560 printf("nge%d: gigabit link up\n", 1561 sc->nge_unit); 1562 nge_miibus_statchg(sc->nge_miibus); 1563 sc->nge_link++; 1564 if (ifp->if_snd.ifq_head != NULL) 1565 nge_start(ifp); 1566 } 1567 } 1568 } else { 1569 mii = device_get_softc(sc->nge_miibus); 1570 mii_tick(mii); 1571 1572 if (!sc->nge_link) { 1573 if (mii->mii_media_status & IFM_ACTIVE && 1574 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1575 sc->nge_link++; 1576 if (IFM_SUBTYPE(mii->mii_media_active) 1577 == IFM_1000_TX) 1578 printf("nge%d: gigabit link up\n", 1579 sc->nge_unit); 1580 if (ifp->if_snd.ifq_head != NULL) 1581 nge_start(ifp); 1582 } 1583 } 1584 } 1585 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1586 1587 splx(s); 1588 1589 return; 1590 } 1591 1592 #ifdef DEVICE_POLLING 1593 static poll_handler_t nge_poll; 1594 1595 static void 1596 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1597 { 1598 struct nge_softc *sc = ifp->if_softc; 1599 1600 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1601 CSR_WRITE_4(sc, NGE_IER, 1); 1602 return; 1603 } 1604 1605 /* 1606 * On the nge, reading the status register also clears it. 1607 * So before returning to intr mode we must make sure that all 1608 * possible pending sources of interrupts have been served. 1609 * In practice this means run to completion the *eof routines, 1610 * and then call the interrupt routine 1611 */ 1612 sc->rxcycles = count; 1613 nge_rxeof(sc); 1614 nge_txeof(sc); 1615 if (ifp->if_snd.ifq_head != NULL) 1616 nge_start(ifp); 1617 1618 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1619 u_int32_t status; 1620 1621 /* Reading the ISR register clears all interrupts. */ 1622 status = CSR_READ_4(sc, NGE_ISR); 1623 1624 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1625 nge_rxeof(sc); 1626 1627 if (status & (NGE_ISR_RX_IDLE)) 1628 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1629 1630 if (status & NGE_ISR_SYSERR) { 1631 nge_reset(sc); 1632 nge_init(sc); 1633 } 1634 } 1635 } 1636 #endif /* DEVICE_POLLING */ 1637 1638 static void nge_intr(arg) 1639 void *arg; 1640 { 1641 struct nge_softc *sc; 1642 struct ifnet *ifp; 1643 u_int32_t status; 1644 1645 sc = arg; 1646 ifp = &sc->arpcom.ac_if; 1647 1648 #ifdef DEVICE_POLLING 1649 if (ifp->if_ipending & IFF_POLLING) 1650 return; 1651 if (ether_poll_register(nge_poll, ifp)) { /* ok, disable interrupts */ 1652 CSR_WRITE_4(sc, NGE_IER, 0); 1653 nge_poll(ifp, 0, 1); 1654 return; 1655 } 1656 #endif /* DEVICE_POLLING */ 1657 1658 /* Supress unwanted interrupts */ 1659 if (!(ifp->if_flags & IFF_UP)) { 1660 nge_stop(sc); 1661 return; 1662 } 1663 1664 /* Disable interrupts. */ 1665 CSR_WRITE_4(sc, NGE_IER, 0); 1666 1667 /* Data LED on for TBI mode */ 1668 if(sc->nge_tbi) 1669 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1670 | NGE_GPIO_GP3_OUT); 1671 1672 for (;;) { 1673 /* Reading the ISR register clears all interrupts. */ 1674 status = CSR_READ_4(sc, NGE_ISR); 1675 1676 if ((status & NGE_INTRS) == 0) 1677 break; 1678 1679 if ((status & NGE_ISR_TX_DESC_OK) || 1680 (status & NGE_ISR_TX_ERR) || 1681 (status & NGE_ISR_TX_OK) || 1682 (status & NGE_ISR_TX_IDLE)) 1683 nge_txeof(sc); 1684 1685 if ((status & NGE_ISR_RX_DESC_OK) || 1686 (status & NGE_ISR_RX_ERR) || 1687 (status & NGE_ISR_RX_OFLOW) || 1688 (status & NGE_ISR_RX_FIFO_OFLOW) || 1689 (status & NGE_ISR_RX_IDLE) || 1690 (status & NGE_ISR_RX_OK)) 1691 nge_rxeof(sc); 1692 1693 if ((status & NGE_ISR_RX_IDLE)) 1694 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1695 1696 if (status & NGE_ISR_SYSERR) { 1697 nge_reset(sc); 1698 ifp->if_flags &= ~IFF_RUNNING; 1699 nge_init(sc); 1700 } 1701 1702 #ifdef notyet 1703 /* mii_tick should only be called once per second */ 1704 if (status & NGE_ISR_PHY_INTR) { 1705 sc->nge_link = 0; 1706 nge_tick(sc); 1707 } 1708 #endif 1709 } 1710 1711 /* Re-enable interrupts. */ 1712 CSR_WRITE_4(sc, NGE_IER, 1); 1713 1714 if (ifp->if_snd.ifq_head != NULL) 1715 nge_start(ifp); 1716 1717 /* Data LED off for TBI mode */ 1718 1719 if(sc->nge_tbi) 1720 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1721 & ~NGE_GPIO_GP3_OUT); 1722 1723 return; 1724 } 1725 1726 /* 1727 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1728 * pointers to the fragment pointers. 1729 */ 1730 static int nge_encap(sc, m_head, txidx) 1731 struct nge_softc *sc; 1732 struct mbuf *m_head; 1733 u_int32_t *txidx; 1734 { 1735 struct nge_desc *f = NULL; 1736 struct mbuf *m; 1737 int frag, cur, cnt = 0; 1738 struct ifvlan *ifv = NULL; 1739 1740 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1741 m_head->m_pkthdr.rcvif != NULL && 1742 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1743 ifv = m_head->m_pkthdr.rcvif->if_softc; 1744 1745 /* 1746 * Start packing the mbufs in this chain into 1747 * the fragment pointers. Stop when we run out 1748 * of fragments or hit the end of the mbuf chain. 1749 */ 1750 m = m_head; 1751 cur = frag = *txidx; 1752 1753 for (m = m_head; m != NULL; m = m->m_next) { 1754 if (m->m_len != 0) { 1755 if ((NGE_TX_LIST_CNT - 1756 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1757 return(ENOBUFS); 1758 f = &sc->nge_ldata->nge_tx_list[frag]; 1759 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1760 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1761 if (cnt != 0) 1762 f->nge_ctl |= NGE_CMDSTS_OWN; 1763 cur = frag; 1764 NGE_INC(frag, NGE_TX_LIST_CNT); 1765 cnt++; 1766 } 1767 } 1768 1769 if (m != NULL) 1770 return(ENOBUFS); 1771 1772 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1773 if (m_head->m_pkthdr.csum_flags) { 1774 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1775 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1776 NGE_TXEXTSTS_IPCSUM; 1777 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1778 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1779 NGE_TXEXTSTS_TCPCSUM; 1780 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1781 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1782 NGE_TXEXTSTS_UDPCSUM; 1783 } 1784 1785 if (ifv != NULL) { 1786 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1787 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag); 1788 } 1789 1790 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1791 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1792 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1793 sc->nge_cdata.nge_tx_cnt += cnt; 1794 *txidx = frag; 1795 1796 return(0); 1797 } 1798 1799 /* 1800 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1801 * to the mbuf data regions directly in the transmit lists. We also save a 1802 * copy of the pointers since the transmit list fragment pointers are 1803 * physical addresses. 1804 */ 1805 1806 static void nge_start(ifp) 1807 struct ifnet *ifp; 1808 { 1809 struct nge_softc *sc; 1810 struct mbuf *m_head = NULL; 1811 u_int32_t idx; 1812 1813 sc = ifp->if_softc; 1814 1815 if (!sc->nge_link) 1816 return; 1817 1818 idx = sc->nge_cdata.nge_tx_prod; 1819 1820 if (ifp->if_flags & IFF_OACTIVE) 1821 return; 1822 1823 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1824 IF_DEQUEUE(&ifp->if_snd, m_head); 1825 if (m_head == NULL) 1826 break; 1827 1828 if (nge_encap(sc, m_head, &idx)) { 1829 IF_PREPEND(&ifp->if_snd, m_head); 1830 ifp->if_flags |= IFF_OACTIVE; 1831 break; 1832 } 1833 1834 /* 1835 * If there's a BPF listener, bounce a copy of this frame 1836 * to him. 1837 */ 1838 if (ifp->if_bpf) 1839 bpf_mtap(ifp, m_head); 1840 1841 } 1842 1843 /* Transmit */ 1844 sc->nge_cdata.nge_tx_prod = idx; 1845 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1846 1847 /* 1848 * Set a timeout in case the chip goes out to lunch. 1849 */ 1850 ifp->if_timer = 5; 1851 1852 return; 1853 } 1854 1855 static void nge_init(xsc) 1856 void *xsc; 1857 { 1858 struct nge_softc *sc = xsc; 1859 struct ifnet *ifp = &sc->arpcom.ac_if; 1860 struct mii_data *mii; 1861 int s; 1862 1863 if (ifp->if_flags & IFF_RUNNING) 1864 return; 1865 1866 s = splimp(); 1867 1868 /* 1869 * Cancel pending I/O and free all RX/TX buffers. 1870 */ 1871 nge_stop(sc); 1872 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1873 1874 if (sc->nge_tbi) { 1875 mii = NULL; 1876 } else { 1877 mii = device_get_softc(sc->nge_miibus); 1878 } 1879 1880 /* Set MAC address */ 1881 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1882 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1883 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1884 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1885 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1886 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1887 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1888 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1889 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1890 1891 /* Init circular RX list. */ 1892 if (nge_list_rx_init(sc) == ENOBUFS) { 1893 printf("nge%d: initialization failed: no " 1894 "memory for rx buffers\n", sc->nge_unit); 1895 nge_stop(sc); 1896 (void)splx(s); 1897 return; 1898 } 1899 1900 /* 1901 * Init tx descriptors. 1902 */ 1903 nge_list_tx_init(sc); 1904 1905 /* 1906 * For the NatSemi chip, we have to explicitly enable the 1907 * reception of ARP frames, as well as turn on the 'perfect 1908 * match' filter where we store the station address, otherwise 1909 * we won't receive unicasts meant for this host. 1910 */ 1911 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1912 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1913 1914 /* If we want promiscuous mode, set the allframes bit. */ 1915 if (ifp->if_flags & IFF_PROMISC) { 1916 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1917 } else { 1918 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1919 } 1920 1921 /* 1922 * Set the capture broadcast bit to capture broadcast frames. 1923 */ 1924 if (ifp->if_flags & IFF_BROADCAST) { 1925 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1926 } else { 1927 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1928 } 1929 1930 /* 1931 * Load the multicast filter. 1932 */ 1933 nge_setmulti(sc); 1934 1935 /* Turn the receive filter on */ 1936 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1937 1938 /* 1939 * Load the address of the RX and TX lists. 1940 */ 1941 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1942 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1943 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1944 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1945 1946 /* Set RX configuration */ 1947 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1948 /* 1949 * Enable hardware checksum validation for all IPv4 1950 * packets, do not reject packets with bad checksums. 1951 */ 1952 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1953 1954 /* 1955 * Tell the chip to detect and strip VLAN tag info from 1956 * received frames. The tag will be provided in the extsts 1957 * field in the RX descriptors. 1958 */ 1959 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1960 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1961 1962 /* Set TX configuration */ 1963 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1964 1965 /* 1966 * Enable TX IPv4 checksumming on a per-packet basis. 1967 */ 1968 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1969 1970 /* 1971 * Tell the chip to insert VLAN tags on a per-packet basis as 1972 * dictated by the code in the frame encapsulation routine. 1973 */ 1974 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1975 1976 /* Set full/half duplex mode. */ 1977 if (sc->nge_tbi) { 1978 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1979 == IFM_FDX) { 1980 NGE_SETBIT(sc, NGE_TX_CFG, 1981 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1982 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1983 } else { 1984 NGE_CLRBIT(sc, NGE_TX_CFG, 1985 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1986 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1987 } 1988 } else { 1989 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1990 NGE_SETBIT(sc, NGE_TX_CFG, 1991 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1992 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1993 } else { 1994 NGE_CLRBIT(sc, NGE_TX_CFG, 1995 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1996 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1997 } 1998 } 1999 2000 /* 2001 * Enable the delivery of PHY interrupts based on 2002 * link/speed/duplex status changes. Also enable the 2003 * extsts field in the DMA descriptors (needed for 2004 * TCP/IP checksum offload on transmit). 2005 */ 2006 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD| 2007 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 2008 2009 /* 2010 * Configure interrupt holdoff (moderation). We can 2011 * have the chip delay interrupt delivery for a certain 2012 * period. Units are in 100us, and the max setting 2013 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 2014 */ 2015 CSR_WRITE_4(sc, NGE_IHR, 0x01); 2016 2017 /* 2018 * Enable interrupts. 2019 */ 2020 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 2021 #ifdef DEVICE_POLLING 2022 /* 2023 * ... only enable interrupts if we are not polling, make sure 2024 * they are off otherwise. 2025 */ 2026 if (ifp->if_ipending & IFF_POLLING) 2027 CSR_WRITE_4(sc, NGE_IER, 0); 2028 else 2029 #endif /* DEVICE_POLLING */ 2030 CSR_WRITE_4(sc, NGE_IER, 1); 2031 2032 /* Enable receiver and transmitter. */ 2033 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2034 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 2035 2036 nge_ifmedia_upd(ifp); 2037 2038 ifp->if_flags |= IFF_RUNNING; 2039 ifp->if_flags &= ~IFF_OACTIVE; 2040 2041 (void)splx(s); 2042 2043 return; 2044 } 2045 2046 /* 2047 * Set media options. 2048 */ 2049 static int nge_ifmedia_upd(ifp) 2050 struct ifnet *ifp; 2051 { 2052 struct nge_softc *sc; 2053 struct mii_data *mii; 2054 2055 sc = ifp->if_softc; 2056 2057 if (sc->nge_tbi) { 2058 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 2059 == IFM_AUTO) { 2060 CSR_WRITE_4(sc, NGE_TBI_ANAR, 2061 CSR_READ_4(sc, NGE_TBI_ANAR) 2062 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 2063 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 2064 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 2065 | NGE_TBIBMCR_RESTART_ANEG); 2066 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 2067 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 2068 & IFM_GMASK) == IFM_FDX) { 2069 NGE_SETBIT(sc, NGE_TX_CFG, 2070 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2071 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2072 2073 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2074 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2075 } else { 2076 NGE_CLRBIT(sc, NGE_TX_CFG, 2077 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2078 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2079 2080 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2081 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2082 } 2083 2084 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 2085 & ~NGE_GPIO_GP3_OUT); 2086 } else { 2087 mii = device_get_softc(sc->nge_miibus); 2088 sc->nge_link = 0; 2089 if (mii->mii_instance) { 2090 struct mii_softc *miisc; 2091 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2092 miisc = LIST_NEXT(miisc, mii_list)) 2093 mii_phy_reset(miisc); 2094 } 2095 mii_mediachg(mii); 2096 } 2097 2098 return(0); 2099 } 2100 2101 /* 2102 * Report current media status. 2103 */ 2104 static void nge_ifmedia_sts(ifp, ifmr) 2105 struct ifnet *ifp; 2106 struct ifmediareq *ifmr; 2107 { 2108 struct nge_softc *sc; 2109 struct mii_data *mii; 2110 2111 sc = ifp->if_softc; 2112 2113 if (sc->nge_tbi) { 2114 ifmr->ifm_status = IFM_AVALID; 2115 ifmr->ifm_active = IFM_ETHER; 2116 2117 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2118 ifmr->ifm_status |= IFM_ACTIVE; 2119 } 2120 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 2121 ifmr->ifm_active |= IFM_LOOP; 2122 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2123 ifmr->ifm_active |= IFM_NONE; 2124 ifmr->ifm_status = 0; 2125 return; 2126 } 2127 ifmr->ifm_active |= IFM_1000_SX; 2128 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 2129 == IFM_AUTO) { 2130 ifmr->ifm_active |= IFM_AUTO; 2131 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2132 & NGE_TBIANAR_FDX) { 2133 ifmr->ifm_active |= IFM_FDX; 2134 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2135 & NGE_TBIANAR_HDX) { 2136 ifmr->ifm_active |= IFM_HDX; 2137 } 2138 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 2139 == IFM_FDX) 2140 ifmr->ifm_active |= IFM_FDX; 2141 else 2142 ifmr->ifm_active |= IFM_HDX; 2143 2144 } else { 2145 mii = device_get_softc(sc->nge_miibus); 2146 mii_pollstat(mii); 2147 ifmr->ifm_active = mii->mii_media_active; 2148 ifmr->ifm_status = mii->mii_media_status; 2149 } 2150 2151 return; 2152 } 2153 2154 static int nge_ioctl(ifp, command, data) 2155 struct ifnet *ifp; 2156 u_long command; 2157 caddr_t data; 2158 { 2159 struct nge_softc *sc = ifp->if_softc; 2160 struct ifreq *ifr = (struct ifreq *) data; 2161 struct mii_data *mii; 2162 int s, error = 0; 2163 2164 s = splimp(); 2165 2166 switch(command) { 2167 case SIOCSIFADDR: 2168 case SIOCGIFADDR: 2169 error = ether_ioctl(ifp, command, data); 2170 break; 2171 case SIOCSIFMTU: 2172 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 2173 error = EINVAL; 2174 else { 2175 ifp->if_mtu = ifr->ifr_mtu; 2176 /* 2177 * Workaround: if the MTU is larger than 2178 * 8152 (TX FIFO size minus 64 minus 18), turn off 2179 * TX checksum offloading. 2180 */ 2181 if (ifr->ifr_mtu >= 8152) 2182 ifp->if_hwassist = 0; 2183 else 2184 ifp->if_hwassist = NGE_CSUM_FEATURES; 2185 } 2186 break; 2187 case SIOCSIFFLAGS: 2188 if (ifp->if_flags & IFF_UP) { 2189 if (ifp->if_flags & IFF_RUNNING && 2190 ifp->if_flags & IFF_PROMISC && 2191 !(sc->nge_if_flags & IFF_PROMISC)) { 2192 NGE_SETBIT(sc, NGE_RXFILT_CTL, 2193 NGE_RXFILTCTL_ALLPHYS| 2194 NGE_RXFILTCTL_ALLMULTI); 2195 } else if (ifp->if_flags & IFF_RUNNING && 2196 !(ifp->if_flags & IFF_PROMISC) && 2197 sc->nge_if_flags & IFF_PROMISC) { 2198 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2199 NGE_RXFILTCTL_ALLPHYS); 2200 if (!(ifp->if_flags & IFF_ALLMULTI)) 2201 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2202 NGE_RXFILTCTL_ALLMULTI); 2203 } else { 2204 ifp->if_flags &= ~IFF_RUNNING; 2205 nge_init(sc); 2206 } 2207 } else { 2208 if (ifp->if_flags & IFF_RUNNING) 2209 nge_stop(sc); 2210 } 2211 sc->nge_if_flags = ifp->if_flags; 2212 error = 0; 2213 break; 2214 case SIOCADDMULTI: 2215 case SIOCDELMULTI: 2216 nge_setmulti(sc); 2217 error = 0; 2218 break; 2219 case SIOCGIFMEDIA: 2220 case SIOCSIFMEDIA: 2221 if (sc->nge_tbi) { 2222 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 2223 command); 2224 } else { 2225 mii = device_get_softc(sc->nge_miibus); 2226 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2227 command); 2228 } 2229 break; 2230 default: 2231 error = EINVAL; 2232 break; 2233 } 2234 2235 (void)splx(s); 2236 2237 return(error); 2238 } 2239 2240 static void nge_watchdog(ifp) 2241 struct ifnet *ifp; 2242 { 2243 struct nge_softc *sc; 2244 2245 sc = ifp->if_softc; 2246 2247 ifp->if_oerrors++; 2248 printf("nge%d: watchdog timeout\n", sc->nge_unit); 2249 2250 nge_stop(sc); 2251 nge_reset(sc); 2252 ifp->if_flags &= ~IFF_RUNNING; 2253 nge_init(sc); 2254 2255 if (ifp->if_snd.ifq_head != NULL) 2256 nge_start(ifp); 2257 2258 return; 2259 } 2260 2261 /* 2262 * Stop the adapter and free any mbufs allocated to the 2263 * RX and TX lists. 2264 */ 2265 static void nge_stop(sc) 2266 struct nge_softc *sc; 2267 { 2268 int i; 2269 struct ifnet *ifp; 2270 struct ifmedia_entry *ifm; 2271 struct mii_data *mii; 2272 int mtmp, itmp; 2273 2274 ifp = &sc->arpcom.ac_if; 2275 ifp->if_timer = 0; 2276 if (sc->nge_tbi) { 2277 mii = NULL; 2278 } else { 2279 mii = device_get_softc(sc->nge_miibus); 2280 } 2281 2282 untimeout(nge_tick, sc, sc->nge_stat_ch); 2283 #ifdef DEVICE_POLLING 2284 ether_poll_deregister(ifp); 2285 #endif 2286 CSR_WRITE_4(sc, NGE_IER, 0); 2287 CSR_WRITE_4(sc, NGE_IMR, 0); 2288 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2289 DELAY(1000); 2290 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2291 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2292 2293 /* 2294 * Isolate/power down the PHY, but leave the media selection 2295 * unchanged so that things will be put back to normal when 2296 * we bring the interface back up. 2297 */ 2298 itmp = ifp->if_flags; 2299 ifp->if_flags |= IFF_UP; 2300 2301 if (sc->nge_tbi) 2302 ifm = sc->nge_ifmedia.ifm_cur; 2303 else 2304 ifm = mii->mii_media.ifm_cur; 2305 2306 mtmp = ifm->ifm_media; 2307 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2308 2309 if (!sc->nge_tbi) 2310 mii_mediachg(mii); 2311 ifm->ifm_media = mtmp; 2312 ifp->if_flags = itmp; 2313 2314 sc->nge_link = 0; 2315 2316 /* 2317 * Free data in the RX lists. 2318 */ 2319 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2320 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2321 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2322 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2323 } 2324 } 2325 bzero((char *)&sc->nge_ldata->nge_rx_list, 2326 sizeof(sc->nge_ldata->nge_rx_list)); 2327 2328 /* 2329 * Free the TX list buffers. 2330 */ 2331 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2332 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2333 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2334 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2335 } 2336 } 2337 2338 bzero((char *)&sc->nge_ldata->nge_tx_list, 2339 sizeof(sc->nge_ldata->nge_tx_list)); 2340 2341 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2342 2343 return; 2344 } 2345 2346 /* 2347 * Stop all chip I/O so that the kernel's probe routines don't 2348 * get confused by errant DMAs when rebooting. 2349 */ 2350 static void nge_shutdown(dev) 2351 device_t dev; 2352 { 2353 struct nge_softc *sc; 2354 2355 sc = device_get_softc(dev); 2356 2357 nge_reset(sc); 2358 nge_stop(sc); 2359 2360 return; 2361 } 2362