1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/cdefs.h> 21 __FBSDID("$FreeBSD$"); 22 23 /*- 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/sysctl.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/endian.h> 41 #include <sys/firmware.h> 42 43 #if defined(__DragonFly__) 44 /* empty */ 45 #else 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #endif 49 #include <sys/rman.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_var.h> 54 #include <net/if_arp.h> 55 #include <net/ethernet.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 60 #include <netproto/802_11/ieee80211_var.h> 61 #include <netproto/802_11/ieee80211_radiotap.h> 62 #include <netproto/802_11/ieee80211_regdomain.h> 63 #include <netproto/802_11/ieee80211_ratectl.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/in_var.h> 68 #include <netinet/ip.h> 69 #include <netinet/if_ether.h> 70 71 #include <dev/netif/ral/rt2661reg.h> 72 #include <dev/netif/ral/rt2661var.h> 73 74 #define RAL_DEBUG 75 #ifdef RAL_DEBUG 76 #define DPRINTF(sc, fmt, ...) do { \ 77 if (sc->sc_debug > 0) \ 78 kprintf(fmt, __VA_ARGS__); \ 79 } while (0) 80 #define DPRINTFN(sc, n, fmt, ...) do { \ 81 if (sc->sc_debug >= (n)) \ 82 kprintf(fmt, __VA_ARGS__); \ 83 } while (0) 84 #else 85 #define DPRINTF(sc, fmt, ...) 86 #define DPRINTFN(sc, n, fmt, ...) 87 #endif 88 89 static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *, 90 const char [IFNAMSIZ], int, enum ieee80211_opmode, 91 int, const uint8_t [IEEE80211_ADDR_LEN], 92 const uint8_t [IEEE80211_ADDR_LEN]); 93 static void rt2661_vap_delete(struct ieee80211vap *); 94 static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 95 int); 96 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 97 struct rt2661_tx_ring *, int); 98 static void rt2661_reset_tx_ring(struct rt2661_softc *, 99 struct rt2661_tx_ring *); 100 static void rt2661_free_tx_ring(struct rt2661_softc *, 101 struct rt2661_tx_ring *); 102 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 103 struct rt2661_rx_ring *, int); 104 static void rt2661_reset_rx_ring(struct rt2661_softc *, 105 struct rt2661_rx_ring *); 106 static void rt2661_free_rx_ring(struct rt2661_softc *, 107 struct rt2661_rx_ring *); 108 static int rt2661_newstate(struct ieee80211vap *, 109 enum ieee80211_state, int); 110 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 111 static void rt2661_rx_intr(struct rt2661_softc *); 112 static void rt2661_tx_intr(struct rt2661_softc *); 113 static void rt2661_tx_dma_intr(struct rt2661_softc *, 114 struct rt2661_tx_ring *); 115 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 116 static void rt2661_mcu_wakeup(struct rt2661_softc *); 117 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 118 static void rt2661_scan_start(struct ieee80211com *); 119 static void rt2661_scan_end(struct ieee80211com *); 120 static void rt2661_set_channel(struct ieee80211com *); 121 static void rt2661_setup_tx_desc(struct rt2661_softc *, 122 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 123 int, const bus_dma_segment_t *, int, int); 124 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 125 struct ieee80211_node *, int); 126 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 127 struct ieee80211_node *); 128 static int rt2661_transmit(struct ieee80211com *, struct mbuf *); 129 static void rt2661_start(struct rt2661_softc *); 130 static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *, 131 const struct ieee80211_bpf_params *); 132 static void rt2661_watchdog(void *); 133 static void rt2661_parent(struct ieee80211com *); 134 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 135 uint8_t); 136 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 137 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 138 uint32_t); 139 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 140 uint16_t); 141 static void rt2661_select_antenna(struct rt2661_softc *); 142 static void rt2661_enable_mrr(struct rt2661_softc *); 143 static void rt2661_set_txpreamble(struct rt2661_softc *); 144 static void rt2661_set_basicrates(struct rt2661_softc *, 145 const struct ieee80211_rateset *); 146 static void rt2661_select_band(struct rt2661_softc *, 147 struct ieee80211_channel *); 148 static void rt2661_set_chan(struct rt2661_softc *, 149 struct ieee80211_channel *); 150 static void rt2661_set_bssid(struct rt2661_softc *, 151 const uint8_t *); 152 static void rt2661_set_macaddr(struct rt2661_softc *, 153 const uint8_t *); 154 static void rt2661_update_promisc(struct ieee80211com *); 155 static int rt2661_wme_update(struct ieee80211com *) __unused; 156 static void rt2661_update_slot(struct ieee80211com *); 157 static const char *rt2661_get_rf(int); 158 static void rt2661_read_eeprom(struct rt2661_softc *, 159 uint8_t macaddr[IEEE80211_ADDR_LEN]); 160 static int rt2661_bbp_init(struct rt2661_softc *); 161 static void rt2661_init_locked(struct rt2661_softc *); 162 static void rt2661_init(void *); 163 static void rt2661_stop_locked(struct rt2661_softc *); 164 static void rt2661_stop(void *); 165 static int rt2661_load_microcode(struct rt2661_softc *); 166 #ifdef notyet 167 static void rt2661_rx_tune(struct rt2661_softc *); 168 static void rt2661_radar_start(struct rt2661_softc *); 169 static int rt2661_radar_stop(struct rt2661_softc *); 170 #endif 171 static int rt2661_prepare_beacon(struct rt2661_softc *, 172 struct ieee80211vap *); 173 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 174 static void rt2661_enable_tsf(struct rt2661_softc *); 175 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 176 177 static const struct { 178 uint32_t reg; 179 uint32_t val; 180 } rt2661_def_mac[] = { 181 RT2661_DEF_MAC 182 }; 183 184 static const struct { 185 uint8_t reg; 186 uint8_t val; 187 } rt2661_def_bbp[] = { 188 RT2661_DEF_BBP 189 }; 190 191 static const struct rfprog { 192 uint8_t chan; 193 uint32_t r1, r2, r3, r4; 194 } rt2661_rf5225_1[] = { 195 RT2661_RF5225_1 196 }, rt2661_rf5225_2[] = { 197 RT2661_RF5225_2 198 }; 199 200 int 201 rt2661_attach(device_t dev, int id) 202 { 203 struct rt2661_softc *sc = device_get_softc(dev); 204 struct ieee80211com *ic = &sc->sc_ic; 205 uint32_t val; 206 uint8_t bands[IEEE80211_MODE_BYTES]; 207 int error, ac, ntries; 208 209 sc->sc_id = id; 210 sc->sc_dev = dev; 211 212 #if defined(__DragonFly__) 213 lockinit(&sc->sc_mtx, device_get_nameunit(dev), 0, LK_CANRECURSE); 214 #else 215 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 216 MTX_DEF | MTX_RECURSE); 217 #endif 218 219 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 220 mbufq_init(&sc->sc_snd, ifqmaxlen); 221 222 /* wait for NIC to initialize */ 223 for (ntries = 0; ntries < 1000; ntries++) { 224 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 225 break; 226 DELAY(1000); 227 } 228 if (ntries == 1000) { 229 device_printf(sc->sc_dev, 230 "timeout waiting for NIC to initialize\n"); 231 error = EIO; 232 goto fail1; 233 } 234 235 /* retrieve RF rev. no and various other things from EEPROM */ 236 rt2661_read_eeprom(sc, ic->ic_macaddr); 237 238 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 239 rt2661_get_rf(sc->rf_rev)); 240 241 /* 242 * Allocate Tx and Rx rings. 243 */ 244 for (ac = 0; ac < 4; ac++) { 245 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 246 RT2661_TX_RING_COUNT); 247 if (error != 0) { 248 device_printf(sc->sc_dev, 249 "could not allocate Tx ring %d\n", ac); 250 goto fail2; 251 } 252 } 253 254 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 255 if (error != 0) { 256 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 257 goto fail2; 258 } 259 260 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 261 if (error != 0) { 262 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 263 goto fail3; 264 } 265 266 ic->ic_softc = sc; 267 ic->ic_name = device_get_nameunit(dev); 268 ic->ic_opmode = IEEE80211_M_STA; 269 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 270 271 /* set device capabilities */ 272 ic->ic_caps = 273 IEEE80211_C_STA /* station mode */ 274 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 275 | IEEE80211_C_HOSTAP /* hostap mode */ 276 | IEEE80211_C_MONITOR /* monitor mode */ 277 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 278 | IEEE80211_C_WDS /* 4-address traffic works */ 279 | IEEE80211_C_MBSS /* mesh point link mode */ 280 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 281 | IEEE80211_C_SHSLOT /* short slot time supported */ 282 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 283 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 284 #ifdef notyet 285 | IEEE80211_C_TXFRAG /* handle tx frags */ 286 | IEEE80211_C_WME /* 802.11e */ 287 #endif 288 ; 289 290 memset(bands, 0, sizeof(bands)); 291 setbit(bands, IEEE80211_MODE_11B); 292 setbit(bands, IEEE80211_MODE_11G); 293 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) 294 setbit(bands, IEEE80211_MODE_11A); 295 ieee80211_init_channels(ic, NULL, bands); 296 297 ieee80211_ifattach(ic); 298 #if 0 299 ic->ic_wme.wme_update = rt2661_wme_update; 300 #endif 301 ic->ic_scan_start = rt2661_scan_start; 302 ic->ic_scan_end = rt2661_scan_end; 303 ic->ic_set_channel = rt2661_set_channel; 304 ic->ic_updateslot = rt2661_update_slot; 305 ic->ic_update_promisc = rt2661_update_promisc; 306 ic->ic_raw_xmit = rt2661_raw_xmit; 307 ic->ic_transmit = rt2661_transmit; 308 ic->ic_parent = rt2661_parent; 309 ic->ic_vap_create = rt2661_vap_create; 310 ic->ic_vap_delete = rt2661_vap_delete; 311 312 ieee80211_radiotap_attach(ic, 313 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 314 RT2661_TX_RADIOTAP_PRESENT, 315 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 316 RT2661_RX_RADIOTAP_PRESENT); 317 318 #ifdef RAL_DEBUG 319 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 320 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 321 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 322 #endif 323 if (bootverbose) 324 ieee80211_announce(ic); 325 326 return 0; 327 328 fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 329 fail2: while (--ac >= 0) 330 rt2661_free_tx_ring(sc, &sc->txq[ac]); 331 #if defined(__DragonFly__) 332 fail1: lockuninit(&sc->sc_mtx); 333 #else 334 fail1: mtx_destroy(&sc->sc_mtx); 335 #endif 336 return error; 337 } 338 339 int 340 rt2661_detach(void *xsc) 341 { 342 struct rt2661_softc *sc = xsc; 343 struct ieee80211com *ic = &sc->sc_ic; 344 345 RAL_LOCK(sc); 346 rt2661_stop_locked(sc); 347 RAL_UNLOCK(sc); 348 349 ieee80211_ifdetach(ic); 350 mbufq_drain(&sc->sc_snd); 351 352 rt2661_free_tx_ring(sc, &sc->txq[0]); 353 rt2661_free_tx_ring(sc, &sc->txq[1]); 354 rt2661_free_tx_ring(sc, &sc->txq[2]); 355 rt2661_free_tx_ring(sc, &sc->txq[3]); 356 rt2661_free_tx_ring(sc, &sc->mgtq); 357 rt2661_free_rx_ring(sc, &sc->rxq); 358 359 #if defined(__DragonFly__) 360 lockuninit(&sc->sc_mtx); 361 #else 362 mtx_destroy(&sc->sc_mtx); 363 #endif 364 365 return 0; 366 } 367 368 static struct ieee80211vap * 369 rt2661_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 370 enum ieee80211_opmode opmode, int flags, 371 const uint8_t bssid[IEEE80211_ADDR_LEN], 372 const uint8_t mac[IEEE80211_ADDR_LEN]) 373 { 374 struct rt2661_softc *sc = ic->ic_softc; 375 struct rt2661_vap *rvp; 376 struct ieee80211vap *vap; 377 378 switch (opmode) { 379 case IEEE80211_M_STA: 380 case IEEE80211_M_IBSS: 381 case IEEE80211_M_AHDEMO: 382 case IEEE80211_M_MONITOR: 383 case IEEE80211_M_HOSTAP: 384 case IEEE80211_M_MBSS: 385 /* XXXRP: TBD */ 386 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 387 device_printf(sc->sc_dev, "only 1 vap supported\n"); 388 return NULL; 389 } 390 if (opmode == IEEE80211_M_STA) 391 flags |= IEEE80211_CLONE_NOBEACONS; 392 break; 393 case IEEE80211_M_WDS: 394 if (TAILQ_EMPTY(&ic->ic_vaps) || 395 ic->ic_opmode != IEEE80211_M_HOSTAP) { 396 device_printf(sc->sc_dev, 397 "wds only supported in ap mode\n"); 398 return NULL; 399 } 400 /* 401 * Silently remove any request for a unique 402 * bssid; WDS vap's always share the local 403 * mac address. 404 */ 405 flags &= ~IEEE80211_CLONE_BSSID; 406 break; 407 default: 408 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 409 return NULL; 410 } 411 rvp = kmalloc(sizeof(struct rt2661_vap), M_80211_VAP, M_WAITOK | M_ZERO); 412 vap = &rvp->ral_vap; 413 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 414 415 /* override state transition machine */ 416 rvp->ral_newstate = vap->iv_newstate; 417 vap->iv_newstate = rt2661_newstate; 418 #if 0 419 vap->iv_update_beacon = rt2661_beacon_update; 420 #endif 421 422 ieee80211_ratectl_init(vap); 423 /* complete setup */ 424 ieee80211_vap_attach(vap, ieee80211_media_change, 425 ieee80211_media_status, mac); 426 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 427 ic->ic_opmode = opmode; 428 return vap; 429 } 430 431 static void 432 rt2661_vap_delete(struct ieee80211vap *vap) 433 { 434 struct rt2661_vap *rvp = RT2661_VAP(vap); 435 436 ieee80211_ratectl_deinit(vap); 437 ieee80211_vap_detach(vap); 438 kfree(rvp, M_80211_VAP); 439 } 440 441 void 442 rt2661_shutdown(void *xsc) 443 { 444 struct rt2661_softc *sc = xsc; 445 446 rt2661_stop(sc); 447 } 448 449 void 450 rt2661_suspend(void *xsc) 451 { 452 struct rt2661_softc *sc = xsc; 453 454 rt2661_stop(sc); 455 } 456 457 void 458 rt2661_resume(void *xsc) 459 { 460 struct rt2661_softc *sc = xsc; 461 462 if (sc->sc_ic.ic_nrunning > 0) 463 rt2661_init(sc); 464 } 465 466 static void 467 rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 468 { 469 if (error != 0) 470 return; 471 472 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 473 474 *(bus_addr_t *)arg = segs[0].ds_addr; 475 } 476 477 static int 478 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 479 int count) 480 { 481 int i, error; 482 483 ring->count = count; 484 ring->queued = 0; 485 ring->cur = ring->next = ring->stat = 0; 486 487 #if defined(__DragonFly__) 488 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 489 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 490 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, 491 0, &ring->desc_dmat); 492 #else 493 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 494 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 495 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, 496 0, NULL, NULL, &ring->desc_dmat); 497 #endif 498 if (error != 0) { 499 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 500 goto fail; 501 } 502 503 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 504 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 505 if (error != 0) { 506 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 507 goto fail; 508 } 509 510 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 511 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 512 0); 513 if (error != 0) { 514 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 515 goto fail; 516 } 517 518 ring->data = kmalloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 519 M_INTWAIT | M_ZERO); 520 if (ring->data == NULL) { 521 device_printf(sc->sc_dev, "could not allocate soft data\n"); 522 error = ENOMEM; 523 goto fail; 524 } 525 526 #if defined(__DragonFly__) 527 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 528 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 529 RT2661_MAX_SCATTER, MCLBYTES, 0, &ring->data_dmat); 530 #else 531 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 532 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 533 RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 534 #endif 535 if (error != 0) { 536 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 537 goto fail; 538 } 539 540 for (i = 0; i < count; i++) { 541 error = bus_dmamap_create(ring->data_dmat, 0, 542 &ring->data[i].map); 543 if (error != 0) { 544 device_printf(sc->sc_dev, "could not create DMA map\n"); 545 goto fail; 546 } 547 } 548 549 return 0; 550 551 fail: rt2661_free_tx_ring(sc, ring); 552 return error; 553 } 554 555 static void 556 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 557 { 558 struct rt2661_tx_desc *desc; 559 struct rt2661_tx_data *data; 560 int i; 561 562 for (i = 0; i < ring->count; i++) { 563 desc = &ring->desc[i]; 564 data = &ring->data[i]; 565 566 if (data->m != NULL) { 567 bus_dmamap_sync(ring->data_dmat, data->map, 568 BUS_DMASYNC_POSTWRITE); 569 bus_dmamap_unload(ring->data_dmat, data->map); 570 m_freem(data->m); 571 data->m = NULL; 572 } 573 574 if (data->ni != NULL) { 575 ieee80211_free_node(data->ni); 576 data->ni = NULL; 577 } 578 579 desc->flags = 0; 580 } 581 582 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 583 584 ring->queued = 0; 585 ring->cur = ring->next = ring->stat = 0; 586 } 587 588 static void 589 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 590 { 591 struct rt2661_tx_data *data; 592 int i; 593 594 if (ring->desc != NULL) { 595 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 596 BUS_DMASYNC_POSTWRITE); 597 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 598 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 599 } 600 601 if (ring->desc_dmat != NULL) 602 bus_dma_tag_destroy(ring->desc_dmat); 603 604 if (ring->data != NULL) { 605 for (i = 0; i < ring->count; i++) { 606 data = &ring->data[i]; 607 608 if (data->m != NULL) { 609 bus_dmamap_sync(ring->data_dmat, data->map, 610 BUS_DMASYNC_POSTWRITE); 611 bus_dmamap_unload(ring->data_dmat, data->map); 612 m_freem(data->m); 613 } 614 615 if (data->ni != NULL) 616 ieee80211_free_node(data->ni); 617 618 if (data->map != NULL) 619 bus_dmamap_destroy(ring->data_dmat, data->map); 620 } 621 622 kfree(ring->data, M_DEVBUF); 623 } 624 625 if (ring->data_dmat != NULL) 626 bus_dma_tag_destroy(ring->data_dmat); 627 } 628 629 static int 630 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 631 int count) 632 { 633 struct rt2661_rx_desc *desc; 634 struct rt2661_rx_data *data; 635 bus_addr_t physaddr; 636 int i, error; 637 638 ring->count = count; 639 ring->cur = ring->next = 0; 640 641 #if defined(__DragonFly__) 642 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 643 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 644 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, 645 0, &ring->desc_dmat); 646 #else 647 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 648 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 649 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, 650 0, NULL, NULL, &ring->desc_dmat); 651 #endif 652 if (error != 0) { 653 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 654 goto fail; 655 } 656 657 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 658 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 659 if (error != 0) { 660 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 661 goto fail; 662 } 663 664 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 665 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 666 0); 667 if (error != 0) { 668 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 669 goto fail; 670 } 671 672 ring->data = kmalloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 673 M_INTWAIT | M_ZERO); 674 if (ring->data == NULL) { 675 device_printf(sc->sc_dev, "could not allocate soft data\n"); 676 error = ENOMEM; 677 goto fail; 678 } 679 680 /* 681 * Pre-allocate Rx buffers and populate Rx ring. 682 */ 683 #if defined(__DragonFly__) 684 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 685 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 686 1, MCLBYTES, 0, &ring->data_dmat); 687 #else 688 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 689 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 690 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 691 #endif 692 if (error != 0) { 693 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 694 goto fail; 695 } 696 697 for (i = 0; i < count; i++) { 698 desc = &sc->rxq.desc[i]; 699 data = &sc->rxq.data[i]; 700 701 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 702 if (error != 0) { 703 device_printf(sc->sc_dev, "could not create DMA map\n"); 704 goto fail; 705 } 706 707 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 708 if (data->m == NULL) { 709 device_printf(sc->sc_dev, 710 "could not allocate rx mbuf\n"); 711 error = ENOMEM; 712 goto fail; 713 } 714 715 error = bus_dmamap_load(ring->data_dmat, data->map, 716 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 717 &physaddr, 0); 718 if (error != 0) { 719 device_printf(sc->sc_dev, 720 "could not load rx buf DMA map"); 721 goto fail; 722 } 723 724 desc->flags = htole32(RT2661_RX_BUSY); 725 desc->physaddr = htole32(physaddr); 726 } 727 728 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 729 730 return 0; 731 732 fail: rt2661_free_rx_ring(sc, ring); 733 return error; 734 } 735 736 static void 737 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 738 { 739 int i; 740 741 for (i = 0; i < ring->count; i++) 742 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 743 744 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 745 746 ring->cur = ring->next = 0; 747 } 748 749 static void 750 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 751 { 752 struct rt2661_rx_data *data; 753 int i; 754 755 if (ring->desc != NULL) { 756 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 757 BUS_DMASYNC_POSTWRITE); 758 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 759 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 760 } 761 762 if (ring->desc_dmat != NULL) 763 bus_dma_tag_destroy(ring->desc_dmat); 764 765 if (ring->data != NULL) { 766 for (i = 0; i < ring->count; i++) { 767 data = &ring->data[i]; 768 769 if (data->m != NULL) { 770 bus_dmamap_sync(ring->data_dmat, data->map, 771 BUS_DMASYNC_POSTREAD); 772 bus_dmamap_unload(ring->data_dmat, data->map); 773 m_freem(data->m); 774 } 775 776 if (data->map != NULL) 777 bus_dmamap_destroy(ring->data_dmat, data->map); 778 } 779 780 kfree(ring->data, M_DEVBUF); 781 } 782 783 if (ring->data_dmat != NULL) 784 bus_dma_tag_destroy(ring->data_dmat); 785 } 786 787 static int 788 rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 789 { 790 struct rt2661_vap *rvp = RT2661_VAP(vap); 791 struct ieee80211com *ic = vap->iv_ic; 792 struct rt2661_softc *sc = ic->ic_softc; 793 int error; 794 795 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 796 uint32_t tmp; 797 798 /* abort TSF synchronization */ 799 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 800 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 801 } 802 803 error = rvp->ral_newstate(vap, nstate, arg); 804 805 if (error == 0 && nstate == IEEE80211_S_RUN) { 806 struct ieee80211_node *ni = vap->iv_bss; 807 808 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 809 rt2661_enable_mrr(sc); 810 rt2661_set_txpreamble(sc); 811 rt2661_set_basicrates(sc, &ni->ni_rates); 812 rt2661_set_bssid(sc, ni->ni_bssid); 813 } 814 815 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 816 vap->iv_opmode == IEEE80211_M_IBSS || 817 vap->iv_opmode == IEEE80211_M_MBSS) { 818 error = rt2661_prepare_beacon(sc, vap); 819 if (error != 0) 820 return error; 821 } 822 if (vap->iv_opmode != IEEE80211_M_MONITOR) 823 rt2661_enable_tsf_sync(sc); 824 else 825 rt2661_enable_tsf(sc); 826 } 827 return error; 828 } 829 830 /* 831 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 832 * 93C66). 833 */ 834 static uint16_t 835 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 836 { 837 uint32_t tmp; 838 uint16_t val; 839 int n; 840 841 /* clock C once before the first command */ 842 RT2661_EEPROM_CTL(sc, 0); 843 844 RT2661_EEPROM_CTL(sc, RT2661_S); 845 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 846 RT2661_EEPROM_CTL(sc, RT2661_S); 847 848 /* write start bit (1) */ 849 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 850 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 851 852 /* write READ opcode (10) */ 853 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 854 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 855 RT2661_EEPROM_CTL(sc, RT2661_S); 856 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 857 858 /* write address (A5-A0 or A7-A0) */ 859 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 860 for (; n >= 0; n--) { 861 RT2661_EEPROM_CTL(sc, RT2661_S | 862 (((addr >> n) & 1) << RT2661_SHIFT_D)); 863 RT2661_EEPROM_CTL(sc, RT2661_S | 864 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 865 } 866 867 RT2661_EEPROM_CTL(sc, RT2661_S); 868 869 /* read data Q15-Q0 */ 870 val = 0; 871 for (n = 15; n >= 0; n--) { 872 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 873 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 874 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 875 RT2661_EEPROM_CTL(sc, RT2661_S); 876 } 877 878 RT2661_EEPROM_CTL(sc, 0); 879 880 /* clear Chip Select and clock C */ 881 RT2661_EEPROM_CTL(sc, RT2661_S); 882 RT2661_EEPROM_CTL(sc, 0); 883 RT2661_EEPROM_CTL(sc, RT2661_C); 884 885 return val; 886 } 887 888 static void 889 rt2661_tx_intr(struct rt2661_softc *sc) 890 { 891 struct rt2661_tx_ring *txq; 892 struct rt2661_tx_data *data; 893 uint32_t val; 894 int error, qid, retrycnt; 895 struct ieee80211vap *vap; 896 897 for (;;) { 898 struct ieee80211_node *ni; 899 struct mbuf *m; 900 901 val = RAL_READ(sc, RT2661_STA_CSR4); 902 if (!(val & RT2661_TX_STAT_VALID)) 903 break; 904 905 /* retrieve the queue in which this frame was sent */ 906 qid = RT2661_TX_QID(val); 907 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 908 909 /* retrieve rate control algorithm context */ 910 data = &txq->data[txq->stat]; 911 m = data->m; 912 data->m = NULL; 913 ni = data->ni; 914 data->ni = NULL; 915 916 /* if no frame has been sent, ignore */ 917 if (ni == NULL) 918 continue; 919 else 920 vap = ni->ni_vap; 921 922 switch (RT2661_TX_RESULT(val)) { 923 case RT2661_TX_SUCCESS: 924 retrycnt = RT2661_TX_RETRYCNT(val); 925 926 DPRINTFN(sc, 10, "data frame sent successfully after " 927 "%d retries\n", retrycnt); 928 if (data->rix != IEEE80211_FIXED_RATE_NONE) 929 ieee80211_ratectl_tx_complete(vap, ni, 930 IEEE80211_RATECTL_TX_SUCCESS, 931 &retrycnt, NULL); 932 error = 0; 933 break; 934 935 case RT2661_TX_RETRY_FAIL: 936 retrycnt = RT2661_TX_RETRYCNT(val); 937 938 DPRINTFN(sc, 9, "%s\n", 939 "sending data frame failed (too much retries)"); 940 if (data->rix != IEEE80211_FIXED_RATE_NONE) 941 ieee80211_ratectl_tx_complete(vap, ni, 942 IEEE80211_RATECTL_TX_FAILURE, 943 &retrycnt, NULL); 944 error = 1; 945 break; 946 947 default: 948 /* other failure */ 949 device_printf(sc->sc_dev, 950 "sending data frame failed 0x%08x\n", val); 951 error = 1; 952 } 953 954 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat); 955 956 txq->queued--; 957 if (++txq->stat >= txq->count) /* faster than % count */ 958 txq->stat = 0; 959 960 ieee80211_tx_complete(ni, m, error); 961 } 962 963 sc->sc_tx_timer = 0; 964 965 rt2661_start(sc); 966 } 967 968 static void 969 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 970 { 971 struct rt2661_tx_desc *desc; 972 struct rt2661_tx_data *data; 973 974 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 975 976 for (;;) { 977 desc = &txq->desc[txq->next]; 978 data = &txq->data[txq->next]; 979 980 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 981 !(le32toh(desc->flags) & RT2661_TX_VALID)) 982 break; 983 984 bus_dmamap_sync(txq->data_dmat, data->map, 985 BUS_DMASYNC_POSTWRITE); 986 bus_dmamap_unload(txq->data_dmat, data->map); 987 988 /* descriptor is no longer valid */ 989 desc->flags &= ~htole32(RT2661_TX_VALID); 990 991 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next); 992 993 if (++txq->next >= txq->count) /* faster than % count */ 994 txq->next = 0; 995 } 996 997 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 998 } 999 1000 static void 1001 rt2661_rx_intr(struct rt2661_softc *sc) 1002 { 1003 struct ieee80211com *ic = &sc->sc_ic; 1004 struct rt2661_rx_desc *desc; 1005 struct rt2661_rx_data *data; 1006 bus_addr_t physaddr; 1007 struct ieee80211_frame *wh; 1008 struct ieee80211_node *ni; 1009 struct mbuf *mnew, *m; 1010 int error; 1011 1012 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1013 BUS_DMASYNC_POSTREAD); 1014 1015 for (;;) { 1016 int8_t rssi, nf; 1017 1018 desc = &sc->rxq.desc[sc->rxq.cur]; 1019 data = &sc->rxq.data[sc->rxq.cur]; 1020 1021 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1022 break; 1023 1024 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1025 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1026 /* 1027 * This should not happen since we did not request 1028 * to receive those frames when we filled TXRX_CSR0. 1029 */ 1030 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", 1031 le32toh(desc->flags)); 1032 #if defined(__DragonFly__) 1033 /* not implemented */ 1034 #else 1035 counter_u64_add(ic->ic_ierrors, 1); 1036 #endif 1037 goto skip; 1038 } 1039 1040 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1041 #if defined(__DragonFly__) 1042 /* not implemented */ 1043 #else 1044 counter_u64_add(ic->ic_ierrors, 1); 1045 #endif 1046 goto skip; 1047 } 1048 1049 /* 1050 * Try to allocate a new mbuf for this ring element and load it 1051 * before processing the current mbuf. If the ring element 1052 * cannot be loaded, drop the received packet and reuse the old 1053 * mbuf. In the unlikely case that the old mbuf can't be 1054 * reloaded either, explicitly panic. 1055 */ 1056 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1057 if (mnew == NULL) { 1058 #if defined(__DragonFly__) 1059 /* not implemented */ 1060 #else 1061 counter_u64_add(ic->ic_ierrors, 1); 1062 #endif 1063 goto skip; 1064 } 1065 1066 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1067 BUS_DMASYNC_POSTREAD); 1068 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1069 1070 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1071 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1072 &physaddr, 0); 1073 if (error != 0) { 1074 m_freem(mnew); 1075 1076 /* try to reload the old mbuf */ 1077 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1078 mtod(data->m, void *), MCLBYTES, 1079 rt2661_dma_map_addr, &physaddr, 0); 1080 if (error != 0) { 1081 /* very unlikely that it will fail... */ 1082 panic("%s: could not load old rx mbuf", 1083 device_get_name(sc->sc_dev)); 1084 } 1085 #if defined(__DragonFly__) 1086 /* not implemented */ 1087 #else 1088 counter_u64_add(ic->ic_ierrors, 1); 1089 #endif 1090 goto skip; 1091 } 1092 1093 /* 1094 * New mbuf successfully loaded, update Rx ring and continue 1095 * processing. 1096 */ 1097 m = data->m; 1098 data->m = mnew; 1099 desc->physaddr = htole32(physaddr); 1100 1101 /* finalize mbuf */ 1102 m->m_pkthdr.len = m->m_len = 1103 (le32toh(desc->flags) >> 16) & 0xfff; 1104 1105 rssi = rt2661_get_rssi(sc, desc->rssi); 1106 /* Error happened during RSSI conversion. */ 1107 if (rssi < 0) 1108 rssi = -30; /* XXX ignored by net80211 */ 1109 nf = RT2661_NOISE_FLOOR; 1110 1111 if (ieee80211_radiotap_active(ic)) { 1112 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1113 uint32_t tsf_lo, tsf_hi; 1114 1115 /* get timestamp (low and high 32 bits) */ 1116 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1117 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1118 1119 tap->wr_tsf = 1120 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1121 tap->wr_flags = 0; 1122 tap->wr_rate = ieee80211_plcp2rate(desc->rate, 1123 (desc->flags & htole32(RT2661_RX_OFDM)) ? 1124 IEEE80211_T_OFDM : IEEE80211_T_CCK); 1125 tap->wr_antsignal = nf + rssi; 1126 tap->wr_antnoise = nf; 1127 } 1128 sc->sc_flags |= RAL_INPUT_RUNNING; 1129 RAL_UNLOCK(sc); 1130 wh = mtod(m, struct ieee80211_frame *); 1131 1132 /* send the frame to the 802.11 layer */ 1133 ni = ieee80211_find_rxnode(ic, 1134 (struct ieee80211_frame_min *)wh); 1135 if (ni != NULL) { 1136 (void) ieee80211_input(ni, m, rssi, nf); 1137 ieee80211_free_node(ni); 1138 } else 1139 (void) ieee80211_input_all(ic, m, rssi, nf); 1140 1141 RAL_LOCK(sc); 1142 sc->sc_flags &= ~RAL_INPUT_RUNNING; 1143 1144 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1145 1146 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur); 1147 1148 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1149 } 1150 1151 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1152 BUS_DMASYNC_PREWRITE); 1153 } 1154 1155 /* ARGSUSED */ 1156 static void 1157 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1158 { 1159 /* do nothing */ 1160 } 1161 1162 static void 1163 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1164 { 1165 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1166 1167 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1168 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1169 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1170 1171 /* send wakeup command to MCU */ 1172 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1173 } 1174 1175 static void 1176 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1177 { 1178 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1179 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1180 } 1181 1182 void 1183 rt2661_intr(void *arg) 1184 { 1185 struct rt2661_softc *sc = arg; 1186 uint32_t r1, r2; 1187 1188 RAL_LOCK(sc); 1189 1190 /* disable MAC and MCU interrupts */ 1191 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1192 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1193 1194 /* don't re-enable interrupts if we're shutting down */ 1195 if (!(sc->sc_flags & RAL_RUNNING)) { 1196 RAL_UNLOCK(sc); 1197 return; 1198 } 1199 1200 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1201 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1202 1203 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1204 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1205 1206 if (r1 & RT2661_MGT_DONE) 1207 rt2661_tx_dma_intr(sc, &sc->mgtq); 1208 1209 if (r1 & RT2661_RX_DONE) 1210 rt2661_rx_intr(sc); 1211 1212 if (r1 & RT2661_TX0_DMA_DONE) 1213 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1214 1215 if (r1 & RT2661_TX1_DMA_DONE) 1216 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1217 1218 if (r1 & RT2661_TX2_DMA_DONE) 1219 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1220 1221 if (r1 & RT2661_TX3_DMA_DONE) 1222 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1223 1224 if (r1 & RT2661_TX_DONE) 1225 rt2661_tx_intr(sc); 1226 1227 if (r2 & RT2661_MCU_CMD_DONE) 1228 rt2661_mcu_cmd_intr(sc); 1229 1230 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1231 rt2661_mcu_beacon_expire(sc); 1232 1233 if (r2 & RT2661_MCU_WAKEUP) 1234 rt2661_mcu_wakeup(sc); 1235 1236 /* re-enable MAC and MCU interrupts */ 1237 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1238 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1239 1240 RAL_UNLOCK(sc); 1241 } 1242 1243 static uint8_t 1244 rt2661_plcp_signal(int rate) 1245 { 1246 switch (rate) { 1247 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1248 case 12: return 0xb; 1249 case 18: return 0xf; 1250 case 24: return 0xa; 1251 case 36: return 0xe; 1252 case 48: return 0x9; 1253 case 72: return 0xd; 1254 case 96: return 0x8; 1255 case 108: return 0xc; 1256 1257 /* CCK rates (NB: not IEEE std, device-specific) */ 1258 case 2: return 0x0; 1259 case 4: return 0x1; 1260 case 11: return 0x2; 1261 case 22: return 0x3; 1262 } 1263 return 0xff; /* XXX unsupported/unknown rate */ 1264 } 1265 1266 static void 1267 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1268 uint32_t flags, uint16_t xflags, int len, int rate, 1269 const bus_dma_segment_t *segs, int nsegs, int ac) 1270 { 1271 struct ieee80211com *ic = &sc->sc_ic; 1272 uint16_t plcp_length; 1273 int i, remainder; 1274 1275 desc->flags = htole32(flags); 1276 desc->flags |= htole32(len << 16); 1277 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1278 1279 desc->xflags = htole16(xflags); 1280 desc->xflags |= htole16(nsegs << 13); 1281 1282 desc->wme = htole16( 1283 RT2661_QID(ac) | 1284 RT2661_AIFSN(2) | 1285 RT2661_LOGCWMIN(4) | 1286 RT2661_LOGCWMAX(10)); 1287 1288 /* 1289 * Remember in which queue this frame was sent. This field is driver 1290 * private data only. It will be made available by the NIC in STA_CSR4 1291 * on Tx interrupts. 1292 */ 1293 desc->qid = ac; 1294 1295 /* setup PLCP fields */ 1296 desc->plcp_signal = rt2661_plcp_signal(rate); 1297 desc->plcp_service = 4; 1298 1299 len += IEEE80211_CRC_LEN; 1300 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1301 desc->flags |= htole32(RT2661_TX_OFDM); 1302 1303 plcp_length = len & 0xfff; 1304 desc->plcp_length_hi = plcp_length >> 6; 1305 desc->plcp_length_lo = plcp_length & 0x3f; 1306 } else { 1307 plcp_length = howmany(16 * len, rate); 1308 if (rate == 22) { 1309 remainder = (16 * len) % 22; 1310 if (remainder != 0 && remainder < 7) 1311 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1312 } 1313 desc->plcp_length_hi = plcp_length >> 8; 1314 desc->plcp_length_lo = plcp_length & 0xff; 1315 1316 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1317 desc->plcp_signal |= 0x08; 1318 } 1319 1320 /* RT2x61 supports scatter with up to 5 segments */ 1321 for (i = 0; i < nsegs; i++) { 1322 desc->addr[i] = htole32(segs[i].ds_addr); 1323 desc->len [i] = htole16(segs[i].ds_len); 1324 } 1325 } 1326 1327 static int 1328 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1329 struct ieee80211_node *ni) 1330 { 1331 struct ieee80211vap *vap = ni->ni_vap; 1332 struct ieee80211com *ic = ni->ni_ic; 1333 struct rt2661_tx_desc *desc; 1334 struct rt2661_tx_data *data; 1335 struct ieee80211_frame *wh; 1336 struct ieee80211_key *k; 1337 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1338 uint16_t dur; 1339 uint32_t flags = 0; /* XXX HWSEQ */ 1340 int nsegs, rate, error; 1341 1342 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1343 data = &sc->mgtq.data[sc->mgtq.cur]; 1344 1345 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate; 1346 1347 wh = mtod(m0, struct ieee80211_frame *); 1348 1349 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1350 k = ieee80211_crypto_encap(ni, m0); 1351 if (k == NULL) { 1352 m_freem(m0); 1353 return ENOBUFS; 1354 } 1355 } 1356 1357 #if defined(__DragonFly__) 1358 error = bus_dmamap_load_mbuf_segment(sc->mgtq.data_dmat, data->map, m0, 1359 segs, 1, &nsegs, BUS_DMA_NOWAIT); 1360 #else 1361 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0, 1362 segs, &nsegs, 0); 1363 #endif 1364 if (error != 0) { 1365 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1366 error); 1367 m_freem(m0); 1368 return error; 1369 } 1370 1371 if (ieee80211_radiotap_active_vap(vap)) { 1372 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1373 1374 tap->wt_flags = 0; 1375 tap->wt_rate = rate; 1376 1377 ieee80211_radiotap_tx(vap, m0); 1378 } 1379 1380 data->m = m0; 1381 data->ni = ni; 1382 /* management frames are not taken into account for amrr */ 1383 data->rix = IEEE80211_FIXED_RATE_NONE; 1384 1385 wh = mtod(m0, struct ieee80211_frame *); 1386 1387 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1388 flags |= RT2661_TX_NEED_ACK; 1389 1390 dur = ieee80211_ack_duration(ic->ic_rt, 1391 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1392 *(uint16_t *)wh->i_dur = htole16(dur); 1393 1394 /* tell hardware to add timestamp in probe responses */ 1395 if ((wh->i_fc[0] & 1396 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1397 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1398 flags |= RT2661_TX_TIMESTAMP; 1399 } 1400 1401 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1402 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1403 1404 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1405 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1406 BUS_DMASYNC_PREWRITE); 1407 1408 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", 1409 m0->m_pkthdr.len, sc->mgtq.cur, rate); 1410 1411 /* kick mgt */ 1412 sc->mgtq.queued++; 1413 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1414 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1415 1416 return 0; 1417 } 1418 1419 static int 1420 rt2661_sendprot(struct rt2661_softc *sc, int ac, 1421 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1422 { 1423 struct ieee80211com *ic = ni->ni_ic; 1424 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1425 const struct ieee80211_frame *wh; 1426 struct rt2661_tx_desc *desc; 1427 struct rt2661_tx_data *data; 1428 struct mbuf *mprot; 1429 int protrate, ackrate, pktlen, flags, isshort, error; 1430 uint16_t dur; 1431 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1432 int nsegs; 1433 1434 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1435 ("protection %d", prot)); 1436 1437 wh = mtod(m, const struct ieee80211_frame *); 1438 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1439 1440 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1441 ackrate = ieee80211_ack_rate(ic->ic_rt, rate); 1442 1443 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1444 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) 1445 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1446 flags = RT2661_TX_MORE_FRAG; 1447 if (prot == IEEE80211_PROT_RTSCTS) { 1448 /* NB: CTS is the same size as an ACK */ 1449 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1450 flags |= RT2661_TX_NEED_ACK; 1451 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1452 } else { 1453 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1454 } 1455 if (mprot == NULL) { 1456 /* XXX stat + msg */ 1457 return ENOBUFS; 1458 } 1459 1460 data = &txq->data[txq->cur]; 1461 desc = &txq->desc[txq->cur]; 1462 1463 #if defined(__DragonFly__) 1464 error = bus_dmamap_load_mbuf_segment(txq->data_dmat, data->map, mprot, 1465 segs, 1, &nsegs, BUS_DMA_NOWAIT); 1466 #else 1467 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs, 1468 &nsegs, 0); 1469 #endif 1470 if (error != 0) { 1471 device_printf(sc->sc_dev, 1472 "could not map mbuf (error %d)\n", error); 1473 m_freem(mprot); 1474 return error; 1475 } 1476 1477 data->m = mprot; 1478 data->ni = ieee80211_ref_node(ni); 1479 /* ctl frames are not taken into account for amrr */ 1480 data->rix = IEEE80211_FIXED_RATE_NONE; 1481 1482 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len, 1483 protrate, segs, 1, ac); 1484 1485 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1486 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1487 1488 txq->queued++; 1489 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1490 1491 return 0; 1492 } 1493 1494 static int 1495 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1496 struct ieee80211_node *ni, int ac) 1497 { 1498 struct ieee80211vap *vap = ni->ni_vap; 1499 struct ieee80211com *ic = &sc->sc_ic; 1500 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1501 struct rt2661_tx_desc *desc; 1502 struct rt2661_tx_data *data; 1503 struct ieee80211_frame *wh; 1504 const struct ieee80211_txparam *tp; 1505 struct ieee80211_key *k; 1506 const struct chanAccParams *cap; 1507 struct mbuf *mnew; 1508 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1509 uint16_t dur; 1510 uint32_t flags; 1511 int error, nsegs, rate, noack = 0; 1512 1513 wh = mtod(m0, struct ieee80211_frame *); 1514 1515 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1516 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1517 rate = tp->mcastrate; 1518 } else if (m0->m_flags & M_EAPOL) { 1519 rate = tp->mgmtrate; 1520 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1521 rate = tp->ucastrate; 1522 } else { 1523 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1524 rate = ni->ni_txrate; 1525 } 1526 rate &= IEEE80211_RATE_VAL; 1527 1528 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1529 cap = &ic->ic_wme.wme_chanParams; 1530 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1531 } 1532 1533 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1534 k = ieee80211_crypto_encap(ni, m0); 1535 if (k == NULL) { 1536 m_freem(m0); 1537 return ENOBUFS; 1538 } 1539 1540 /* packet header may have moved, reset our local pointer */ 1541 wh = mtod(m0, struct ieee80211_frame *); 1542 } 1543 1544 flags = 0; 1545 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1546 int prot = IEEE80211_PROT_NONE; 1547 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1548 prot = IEEE80211_PROT_RTSCTS; 1549 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1550 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1551 prot = ic->ic_protmode; 1552 if (prot != IEEE80211_PROT_NONE) { 1553 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate); 1554 if (error) { 1555 m_freem(m0); 1556 return error; 1557 } 1558 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1559 } 1560 } 1561 1562 data = &txq->data[txq->cur]; 1563 desc = &txq->desc[txq->cur]; 1564 1565 #if defined(__DragonFly__) 1566 error = bus_dmamap_load_mbuf_segment(txq->data_dmat, data->map, m0, 1567 segs, 1, &nsegs, BUS_DMA_NOWAIT); 1568 #else 1569 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs, 1570 &nsegs, 0); 1571 #endif 1572 if (error != 0 && error != EFBIG) { 1573 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1574 error); 1575 m_freem(m0); 1576 return error; 1577 } 1578 if (error != 0) { 1579 mnew = m_defrag(m0, M_NOWAIT); 1580 if (mnew == NULL) { 1581 device_printf(sc->sc_dev, 1582 "could not defragment mbuf\n"); 1583 m_freem(m0); 1584 return ENOBUFS; 1585 } 1586 m0 = mnew; 1587 1588 #if defined(__DragonFly__) 1589 error = bus_dmamap_load_mbuf_segment(txq->data_dmat, data->map, 1590 m0, segs, 1, &nsegs, BUS_DMA_NOWAIT); 1591 #else 1592 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, 1593 segs, &nsegs, 0); 1594 #endif 1595 if (error != 0) { 1596 device_printf(sc->sc_dev, 1597 "could not map mbuf (error %d)\n", error); 1598 m_freem(m0); 1599 return error; 1600 } 1601 1602 /* packet header have moved, reset our local pointer */ 1603 wh = mtod(m0, struct ieee80211_frame *); 1604 } 1605 1606 if (ieee80211_radiotap_active_vap(vap)) { 1607 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1608 1609 tap->wt_flags = 0; 1610 tap->wt_rate = rate; 1611 1612 ieee80211_radiotap_tx(vap, m0); 1613 } 1614 1615 data->m = m0; 1616 data->ni = ni; 1617 1618 /* remember link conditions for rate adaptation algorithm */ 1619 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { 1620 data->rix = ni->ni_txrate; 1621 /* XXX probably need last rssi value and not avg */ 1622 data->rssi = ic->ic_node_getrssi(ni); 1623 } else 1624 data->rix = IEEE80211_FIXED_RATE_NONE; 1625 1626 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1627 flags |= RT2661_TX_NEED_ACK; 1628 1629 dur = ieee80211_ack_duration(ic->ic_rt, 1630 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1631 *(uint16_t *)wh->i_dur = htole16(dur); 1632 } 1633 1634 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1635 nsegs, ac); 1636 1637 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1638 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1639 1640 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", 1641 m0->m_pkthdr.len, txq->cur, rate); 1642 1643 /* kick Tx */ 1644 txq->queued++; 1645 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1646 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1647 1648 return 0; 1649 } 1650 1651 static int 1652 rt2661_transmit(struct ieee80211com *ic, struct mbuf *m) 1653 { 1654 struct rt2661_softc *sc = ic->ic_softc; 1655 int error; 1656 1657 RAL_LOCK(sc); 1658 if ((sc->sc_flags & RAL_RUNNING) == 0) { 1659 RAL_UNLOCK(sc); 1660 return (ENXIO); 1661 } 1662 error = mbufq_enqueue(&sc->sc_snd, m); 1663 if (error) { 1664 RAL_UNLOCK(sc); 1665 return (error); 1666 } 1667 rt2661_start(sc); 1668 RAL_UNLOCK(sc); 1669 1670 return (0); 1671 } 1672 1673 static void 1674 rt2661_start(struct rt2661_softc *sc) 1675 { 1676 struct mbuf *m; 1677 struct ieee80211_node *ni; 1678 int ac; 1679 1680 RAL_LOCK_ASSERT(sc); 1681 1682 /* prevent management frames from being sent if we're not ready */ 1683 if (!(sc->sc_flags & RAL_RUNNING) || sc->sc_invalid) 1684 return; 1685 1686 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1687 ac = M_WME_GETAC(m); 1688 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1689 /* there is no place left in this ring */ 1690 mbufq_prepend(&sc->sc_snd, m); 1691 break; 1692 } 1693 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1694 if (rt2661_tx_data(sc, m, ni, ac) != 0) { 1695 ieee80211_free_node(ni); 1696 if_inc_counter(ni->ni_vap->iv_ifp, 1697 IFCOUNTER_OERRORS, 1); 1698 break; 1699 } 1700 sc->sc_tx_timer = 5; 1701 } 1702 } 1703 1704 static int 1705 rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1706 const struct ieee80211_bpf_params *params) 1707 { 1708 struct ieee80211com *ic = ni->ni_ic; 1709 struct rt2661_softc *sc = ic->ic_softc; 1710 1711 RAL_LOCK(sc); 1712 1713 /* prevent management frames from being sent if we're not ready */ 1714 if (!(sc->sc_flags & RAL_RUNNING)) { 1715 RAL_UNLOCK(sc); 1716 m_freem(m); 1717 return ENETDOWN; 1718 } 1719 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1720 RAL_UNLOCK(sc); 1721 m_freem(m); 1722 return ENOBUFS; /* XXX */ 1723 } 1724 1725 /* 1726 * Legacy path; interpret frame contents to decide 1727 * precisely how to send the frame. 1728 * XXX raw path 1729 */ 1730 if (rt2661_tx_mgt(sc, m, ni) != 0) 1731 goto bad; 1732 sc->sc_tx_timer = 5; 1733 1734 RAL_UNLOCK(sc); 1735 1736 return 0; 1737 bad: 1738 RAL_UNLOCK(sc); 1739 return EIO; /* XXX */ 1740 } 1741 1742 static void 1743 rt2661_watchdog(void *arg) 1744 { 1745 struct rt2661_softc *sc = (struct rt2661_softc *)arg; 1746 1747 RAL_LOCK_ASSERT(sc); 1748 1749 KASSERT(sc->sc_flags & RAL_RUNNING, ("not running")); 1750 1751 if (sc->sc_invalid) /* card ejected */ 1752 return; 1753 1754 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1755 device_printf(sc->sc_dev, "device timeout\n"); 1756 rt2661_init_locked(sc); 1757 #if defined(__DragonFly__) 1758 /* not implemented */ 1759 #else 1760 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1761 #endif 1762 /* NB: callout is reset in rt2661_init() */ 1763 return; 1764 } 1765 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 1766 } 1767 1768 static void 1769 rt2661_parent(struct ieee80211com *ic) 1770 { 1771 struct rt2661_softc *sc = ic->ic_softc; 1772 int startall = 0; 1773 1774 RAL_LOCK(sc); 1775 if (ic->ic_nrunning > 0) { 1776 if ((sc->sc_flags & RAL_RUNNING) == 0) { 1777 rt2661_init_locked(sc); 1778 startall = 1; 1779 } else 1780 rt2661_update_promisc(ic); 1781 } else if (sc->sc_flags & RAL_RUNNING) 1782 rt2661_stop_locked(sc); 1783 RAL_UNLOCK(sc); 1784 if (startall) 1785 ieee80211_start_all(ic); 1786 } 1787 1788 static void 1789 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1790 { 1791 uint32_t tmp; 1792 int ntries; 1793 1794 for (ntries = 0; ntries < 100; ntries++) { 1795 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1796 break; 1797 DELAY(1); 1798 } 1799 if (ntries == 100) { 1800 device_printf(sc->sc_dev, "could not write to BBP\n"); 1801 return; 1802 } 1803 1804 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1805 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1806 1807 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); 1808 } 1809 1810 static uint8_t 1811 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1812 { 1813 uint32_t val; 1814 int ntries; 1815 1816 for (ntries = 0; ntries < 100; ntries++) { 1817 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1818 break; 1819 DELAY(1); 1820 } 1821 if (ntries == 100) { 1822 device_printf(sc->sc_dev, "could not read from BBP\n"); 1823 return 0; 1824 } 1825 1826 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1827 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1828 1829 for (ntries = 0; ntries < 100; ntries++) { 1830 val = RAL_READ(sc, RT2661_PHY_CSR3); 1831 if (!(val & RT2661_BBP_BUSY)) 1832 return val & 0xff; 1833 DELAY(1); 1834 } 1835 1836 device_printf(sc->sc_dev, "could not read from BBP\n"); 1837 return 0; 1838 } 1839 1840 static void 1841 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1842 { 1843 uint32_t tmp; 1844 int ntries; 1845 1846 for (ntries = 0; ntries < 100; ntries++) { 1847 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 1848 break; 1849 DELAY(1); 1850 } 1851 if (ntries == 100) { 1852 device_printf(sc->sc_dev, "could not write to RF\n"); 1853 return; 1854 } 1855 1856 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 1857 (reg & 3); 1858 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 1859 1860 /* remember last written value in sc */ 1861 sc->rf_regs[reg] = val; 1862 1863 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff); 1864 } 1865 1866 static int 1867 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 1868 { 1869 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 1870 return EIO; /* there is already a command pending */ 1871 1872 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 1873 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 1874 1875 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 1876 1877 return 0; 1878 } 1879 1880 static void 1881 rt2661_select_antenna(struct rt2661_softc *sc) 1882 { 1883 uint8_t bbp4, bbp77; 1884 uint32_t tmp; 1885 1886 bbp4 = rt2661_bbp_read(sc, 4); 1887 bbp77 = rt2661_bbp_read(sc, 77); 1888 1889 /* TBD */ 1890 1891 /* make sure Rx is disabled before switching antenna */ 1892 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 1893 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 1894 1895 rt2661_bbp_write(sc, 4, bbp4); 1896 rt2661_bbp_write(sc, 77, bbp77); 1897 1898 /* restore Rx filter */ 1899 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 1900 } 1901 1902 /* 1903 * Enable multi-rate retries for frames sent at OFDM rates. 1904 * In 802.11b/g mode, allow fallback to CCK rates. 1905 */ 1906 static void 1907 rt2661_enable_mrr(struct rt2661_softc *sc) 1908 { 1909 struct ieee80211com *ic = &sc->sc_ic; 1910 uint32_t tmp; 1911 1912 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1913 1914 tmp &= ~RT2661_MRR_CCK_FALLBACK; 1915 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 1916 tmp |= RT2661_MRR_CCK_FALLBACK; 1917 tmp |= RT2661_MRR_ENABLED; 1918 1919 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1920 } 1921 1922 static void 1923 rt2661_set_txpreamble(struct rt2661_softc *sc) 1924 { 1925 struct ieee80211com *ic = &sc->sc_ic; 1926 uint32_t tmp; 1927 1928 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1929 1930 tmp &= ~RT2661_SHORT_PREAMBLE; 1931 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1932 tmp |= RT2661_SHORT_PREAMBLE; 1933 1934 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1935 } 1936 1937 static void 1938 rt2661_set_basicrates(struct rt2661_softc *sc, 1939 const struct ieee80211_rateset *rs) 1940 { 1941 struct ieee80211com *ic = &sc->sc_ic; 1942 uint32_t mask = 0; 1943 uint8_t rate; 1944 int i; 1945 1946 for (i = 0; i < rs->rs_nrates; i++) { 1947 rate = rs->rs_rates[i]; 1948 1949 if (!(rate & IEEE80211_RATE_BASIC)) 1950 continue; 1951 1952 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 1953 IEEE80211_RV(rate)); 1954 } 1955 1956 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 1957 1958 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask); 1959 } 1960 1961 /* 1962 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 1963 * driver. 1964 */ 1965 static void 1966 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 1967 { 1968 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 1969 uint32_t tmp; 1970 1971 /* update all BBP registers that depend on the band */ 1972 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 1973 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 1974 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1975 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 1976 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 1977 } 1978 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1979 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1980 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 1981 } 1982 1983 rt2661_bbp_write(sc, 17, bbp17); 1984 rt2661_bbp_write(sc, 96, bbp96); 1985 rt2661_bbp_write(sc, 104, bbp104); 1986 1987 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1988 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1989 rt2661_bbp_write(sc, 75, 0x80); 1990 rt2661_bbp_write(sc, 86, 0x80); 1991 rt2661_bbp_write(sc, 88, 0x80); 1992 } 1993 1994 rt2661_bbp_write(sc, 35, bbp35); 1995 rt2661_bbp_write(sc, 97, bbp97); 1996 rt2661_bbp_write(sc, 98, bbp98); 1997 1998 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 1999 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2000 if (IEEE80211_IS_CHAN_2GHZ(c)) 2001 tmp |= RT2661_PA_PE_2GHZ; 2002 else 2003 tmp |= RT2661_PA_PE_5GHZ; 2004 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2005 } 2006 2007 static void 2008 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2009 { 2010 struct ieee80211com *ic = &sc->sc_ic; 2011 const struct rfprog *rfprog; 2012 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2013 int8_t power; 2014 u_int i, chan; 2015 2016 chan = ieee80211_chan2ieee(ic, c); 2017 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); 2018 2019 /* select the appropriate RF settings based on what EEPROM says */ 2020 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2021 2022 /* find the settings for this channel (we know it exists) */ 2023 for (i = 0; rfprog[i].chan != chan; i++); 2024 2025 power = sc->txpow[i]; 2026 if (power < 0) { 2027 bbp94 += power; 2028 power = 0; 2029 } else if (power > 31) { 2030 bbp94 += power - 31; 2031 power = 31; 2032 } 2033 2034 /* 2035 * If we are switching from the 2GHz band to the 5GHz band or 2036 * vice-versa, BBP registers need to be reprogrammed. 2037 */ 2038 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2039 rt2661_select_band(sc, c); 2040 rt2661_select_antenna(sc); 2041 } 2042 sc->sc_curchan = c; 2043 2044 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2045 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2046 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2047 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2048 2049 DELAY(200); 2050 2051 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2052 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2053 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2054 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2055 2056 DELAY(200); 2057 2058 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2059 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2060 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2061 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2062 2063 /* enable smart mode for MIMO-capable RFs */ 2064 bbp3 = rt2661_bbp_read(sc, 3); 2065 2066 bbp3 &= ~RT2661_SMART_MODE; 2067 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2068 bbp3 |= RT2661_SMART_MODE; 2069 2070 rt2661_bbp_write(sc, 3, bbp3); 2071 2072 if (bbp94 != RT2661_BBPR94_DEFAULT) 2073 rt2661_bbp_write(sc, 94, bbp94); 2074 2075 /* 5GHz radio needs a 1ms delay here */ 2076 if (IEEE80211_IS_CHAN_5GHZ(c)) 2077 DELAY(1000); 2078 } 2079 2080 static void 2081 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2082 { 2083 uint32_t tmp; 2084 2085 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2086 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2087 2088 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2089 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2090 } 2091 2092 static void 2093 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2094 { 2095 uint32_t tmp; 2096 2097 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2098 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2099 2100 tmp = addr[4] | addr[5] << 8; 2101 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2102 } 2103 2104 static void 2105 rt2661_update_promisc(struct ieee80211com *ic) 2106 { 2107 struct rt2661_softc *sc = ic->ic_softc; 2108 uint32_t tmp; 2109 2110 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2111 2112 tmp &= ~RT2661_DROP_NOT_TO_ME; 2113 if (ic->ic_promisc == 0) 2114 tmp |= RT2661_DROP_NOT_TO_ME; 2115 2116 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2117 2118 DPRINTF(sc, "%s promiscuous mode\n", 2119 (ic->ic_promisc > 0) ? "entering" : "leaving"); 2120 } 2121 2122 /* 2123 * Update QoS (802.11e) settings for each h/w Tx ring. 2124 */ 2125 static int 2126 rt2661_wme_update(struct ieee80211com *ic) 2127 { 2128 struct rt2661_softc *sc = ic->ic_softc; 2129 const struct wmeParams *wmep; 2130 2131 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2132 2133 /* XXX: not sure about shifts. */ 2134 /* XXX: the reference driver plays with AC_VI settings too. */ 2135 2136 /* update TxOp */ 2137 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2138 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2139 wmep[WME_AC_BK].wmep_txopLimit); 2140 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2141 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2142 wmep[WME_AC_VO].wmep_txopLimit); 2143 2144 /* update CWmin */ 2145 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2146 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2147 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2148 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2149 wmep[WME_AC_VO].wmep_logcwmin); 2150 2151 /* update CWmax */ 2152 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2153 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2154 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2155 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2156 wmep[WME_AC_VO].wmep_logcwmax); 2157 2158 /* update Aifsn */ 2159 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2160 wmep[WME_AC_BE].wmep_aifsn << 12 | 2161 wmep[WME_AC_BK].wmep_aifsn << 8 | 2162 wmep[WME_AC_VI].wmep_aifsn << 4 | 2163 wmep[WME_AC_VO].wmep_aifsn); 2164 2165 return 0; 2166 } 2167 2168 static void 2169 rt2661_update_slot(struct ieee80211com *ic) 2170 { 2171 struct rt2661_softc *sc = ic->ic_softc; 2172 uint8_t slottime; 2173 uint32_t tmp; 2174 2175 slottime = IEEE80211_GET_SLOTTIME(ic); 2176 2177 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2178 tmp = (tmp & ~0xff) | slottime; 2179 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2180 } 2181 2182 static const char * 2183 rt2661_get_rf(int rev) 2184 { 2185 switch (rev) { 2186 case RT2661_RF_5225: return "RT5225"; 2187 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2188 case RT2661_RF_2527: return "RT2527"; 2189 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2190 default: return "unknown"; 2191 } 2192 } 2193 2194 static void 2195 rt2661_read_eeprom(struct rt2661_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2196 { 2197 uint16_t val; 2198 int i; 2199 2200 /* read MAC address */ 2201 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2202 macaddr[0] = val & 0xff; 2203 macaddr[1] = val >> 8; 2204 2205 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2206 macaddr[2] = val & 0xff; 2207 macaddr[3] = val >> 8; 2208 2209 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2210 macaddr[4] = val & 0xff; 2211 macaddr[5] = val >> 8; 2212 2213 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2214 /* XXX: test if different from 0xffff? */ 2215 sc->rf_rev = (val >> 11) & 0x1f; 2216 sc->hw_radio = (val >> 10) & 0x1; 2217 sc->rx_ant = (val >> 4) & 0x3; 2218 sc->tx_ant = (val >> 2) & 0x3; 2219 sc->nb_ant = val & 0x3; 2220 2221 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev); 2222 2223 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2224 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2225 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2226 2227 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2228 sc->ext_2ghz_lna, sc->ext_5ghz_lna); 2229 2230 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2231 if ((val & 0xff) != 0xff) 2232 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2233 2234 /* Only [-10, 10] is valid */ 2235 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10) 2236 sc->rssi_2ghz_corr = 0; 2237 2238 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2239 if ((val & 0xff) != 0xff) 2240 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2241 2242 /* Only [-10, 10] is valid */ 2243 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2244 sc->rssi_5ghz_corr = 0; 2245 2246 /* adjust RSSI correction for external low-noise amplifier */ 2247 if (sc->ext_2ghz_lna) 2248 sc->rssi_2ghz_corr -= 14; 2249 if (sc->ext_5ghz_lna) 2250 sc->rssi_5ghz_corr -= 14; 2251 2252 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2253 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr); 2254 2255 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2256 if ((val >> 8) != 0xff) 2257 sc->rfprog = (val >> 8) & 0x3; 2258 if ((val & 0xff) != 0xff) 2259 sc->rffreq = val & 0xff; 2260 2261 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq); 2262 2263 /* read Tx power for all a/b/g channels */ 2264 for (i = 0; i < 19; i++) { 2265 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2266 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2267 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2268 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]); 2269 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2270 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2271 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]); 2272 } 2273 2274 /* read vendor-specific BBP values */ 2275 for (i = 0; i < 16; i++) { 2276 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2277 if (val == 0 || val == 0xffff) 2278 continue; /* skip invalid entries */ 2279 sc->bbp_prom[i].reg = val >> 8; 2280 sc->bbp_prom[i].val = val & 0xff; 2281 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2282 sc->bbp_prom[i].val); 2283 } 2284 } 2285 2286 static int 2287 rt2661_bbp_init(struct rt2661_softc *sc) 2288 { 2289 int i, ntries; 2290 uint8_t val; 2291 2292 /* wait for BBP to be ready */ 2293 for (ntries = 0; ntries < 100; ntries++) { 2294 val = rt2661_bbp_read(sc, 0); 2295 if (val != 0 && val != 0xff) 2296 break; 2297 DELAY(100); 2298 } 2299 if (ntries == 100) { 2300 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2301 return EIO; 2302 } 2303 2304 /* initialize BBP registers to default values */ 2305 for (i = 0; i < nitems(rt2661_def_bbp); i++) { 2306 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2307 rt2661_def_bbp[i].val); 2308 } 2309 2310 /* write vendor-specific BBP values (from EEPROM) */ 2311 for (i = 0; i < 16; i++) { 2312 if (sc->bbp_prom[i].reg == 0) 2313 continue; 2314 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2315 } 2316 2317 return 0; 2318 } 2319 2320 static void 2321 rt2661_init_locked(struct rt2661_softc *sc) 2322 { 2323 struct ieee80211com *ic = &sc->sc_ic; 2324 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2325 uint32_t tmp, sta[3]; 2326 int i, error, ntries; 2327 2328 RAL_LOCK_ASSERT(sc); 2329 2330 if ((sc->sc_flags & RAL_FW_LOADED) == 0) { 2331 error = rt2661_load_microcode(sc); 2332 if (error != 0) { 2333 device_printf(sc->sc_dev, 2334 "%s: could not load 8051 microcode, error %d\n", 2335 __func__, error); 2336 return; 2337 } 2338 sc->sc_flags |= RAL_FW_LOADED; 2339 } 2340 2341 rt2661_stop_locked(sc); 2342 2343 /* initialize Tx rings */ 2344 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2345 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2346 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2347 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2348 2349 /* initialize Mgt ring */ 2350 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2351 2352 /* initialize Rx ring */ 2353 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2354 2355 /* initialize Tx rings sizes */ 2356 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2357 RT2661_TX_RING_COUNT << 24 | 2358 RT2661_TX_RING_COUNT << 16 | 2359 RT2661_TX_RING_COUNT << 8 | 2360 RT2661_TX_RING_COUNT); 2361 2362 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2363 RT2661_TX_DESC_WSIZE << 16 | 2364 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2365 RT2661_MGT_RING_COUNT); 2366 2367 /* initialize Rx rings */ 2368 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2369 RT2661_RX_DESC_BACK << 16 | 2370 RT2661_RX_DESC_WSIZE << 8 | 2371 RT2661_RX_RING_COUNT); 2372 2373 /* XXX: some magic here */ 2374 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2375 2376 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2377 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2378 2379 /* load base address of Rx ring */ 2380 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2381 2382 /* initialize MAC registers to default values */ 2383 for (i = 0; i < nitems(rt2661_def_mac); i++) 2384 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2385 2386 rt2661_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 2387 2388 /* set host ready */ 2389 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2390 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2391 2392 /* wait for BBP/RF to wakeup */ 2393 for (ntries = 0; ntries < 1000; ntries++) { 2394 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2395 break; 2396 DELAY(1000); 2397 } 2398 if (ntries == 1000) { 2399 kprintf("timeout waiting for BBP/RF to wakeup\n"); 2400 rt2661_stop_locked(sc); 2401 return; 2402 } 2403 2404 if (rt2661_bbp_init(sc) != 0) { 2405 rt2661_stop_locked(sc); 2406 return; 2407 } 2408 2409 /* select default channel */ 2410 sc->sc_curchan = ic->ic_curchan; 2411 rt2661_select_band(sc, sc->sc_curchan); 2412 rt2661_select_antenna(sc); 2413 rt2661_set_chan(sc, sc->sc_curchan); 2414 2415 /* update Rx filter */ 2416 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2417 2418 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2419 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2420 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2421 RT2661_DROP_ACKCTS; 2422 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 2423 ic->ic_opmode != IEEE80211_M_MBSS) 2424 tmp |= RT2661_DROP_TODS; 2425 if (ic->ic_promisc == 0) 2426 tmp |= RT2661_DROP_NOT_TO_ME; 2427 } 2428 2429 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2430 2431 /* clear STA registers */ 2432 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, nitems(sta)); 2433 2434 /* initialize ASIC */ 2435 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2436 2437 /* clear any pending interrupt */ 2438 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2439 2440 /* enable interrupts */ 2441 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2442 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2443 2444 /* kick Rx */ 2445 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2446 2447 sc->sc_flags |= RAL_RUNNING; 2448 2449 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 2450 } 2451 2452 static void 2453 rt2661_init(void *priv) 2454 { 2455 struct rt2661_softc *sc = priv; 2456 struct ieee80211com *ic = &sc->sc_ic; 2457 2458 RAL_LOCK(sc); 2459 rt2661_init_locked(sc); 2460 RAL_UNLOCK(sc); 2461 2462 if (sc->sc_flags & RAL_RUNNING) 2463 ieee80211_start_all(ic); /* start all vap's */ 2464 } 2465 2466 static void 2467 rt2661_stop_locked(struct rt2661_softc *sc) 2468 { 2469 volatile int *flags = &sc->sc_flags; 2470 uint32_t tmp; 2471 2472 #if defined(__DragonFly__) 2473 while (*flags & RAL_INPUT_RUNNING) 2474 lksleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10); 2475 #else 2476 while (*flags & RAL_INPUT_RUNNING) 2477 msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10); 2478 #endif 2479 2480 callout_stop(&sc->watchdog_ch); 2481 sc->sc_tx_timer = 0; 2482 2483 if (sc->sc_flags & RAL_RUNNING) { 2484 sc->sc_flags &= ~RAL_RUNNING; 2485 2486 /* abort Tx (for all 5 Tx rings) */ 2487 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2488 2489 /* disable Rx (value remains after reset!) */ 2490 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2491 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2492 2493 /* reset ASIC */ 2494 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2495 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2496 2497 /* disable interrupts */ 2498 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2499 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2500 2501 /* clear any pending interrupt */ 2502 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2503 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2504 2505 /* reset Tx and Rx rings */ 2506 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2507 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2508 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2509 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2510 rt2661_reset_tx_ring(sc, &sc->mgtq); 2511 rt2661_reset_rx_ring(sc, &sc->rxq); 2512 } 2513 } 2514 2515 static void 2516 rt2661_stop(void *priv) 2517 { 2518 struct rt2661_softc *sc = priv; 2519 2520 RAL_LOCK(sc); 2521 rt2661_stop_locked(sc); 2522 RAL_UNLOCK(sc); 2523 } 2524 2525 static int 2526 rt2661_load_microcode(struct rt2661_softc *sc) 2527 { 2528 const struct firmware *fp; 2529 const char *imagename; 2530 int ntries, error; 2531 2532 RAL_LOCK_ASSERT(sc); 2533 2534 switch (sc->sc_id) { 2535 case 0x0301: imagename = "rt2561sfw"; break; 2536 case 0x0302: imagename = "rt2561fw"; break; 2537 case 0x0401: imagename = "rt2661fw"; break; 2538 default: 2539 device_printf(sc->sc_dev, "%s: unexpected pci device id 0x%x, " 2540 "don't know how to retrieve firmware\n", 2541 __func__, sc->sc_id); 2542 return EINVAL; 2543 } 2544 RAL_UNLOCK(sc); 2545 fp = firmware_get(imagename); 2546 RAL_LOCK(sc); 2547 if (fp == NULL) { 2548 device_printf(sc->sc_dev, 2549 "%s: unable to retrieve firmware image %s\n", 2550 __func__, imagename); 2551 return EINVAL; 2552 } 2553 2554 /* 2555 * Load 8051 microcode into NIC. 2556 */ 2557 /* reset 8051 */ 2558 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2559 2560 /* cancel any pending Host to MCU command */ 2561 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2562 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2563 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2564 2565 /* write 8051's microcode */ 2566 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2567 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize); 2568 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2569 2570 /* kick 8051's ass */ 2571 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2572 2573 /* wait for 8051 to initialize */ 2574 for (ntries = 0; ntries < 500; ntries++) { 2575 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2576 break; 2577 DELAY(100); 2578 } 2579 if (ntries == 500) { 2580 device_printf(sc->sc_dev, 2581 "%s: timeout waiting for MCU to initialize\n", __func__); 2582 error = EIO; 2583 } else 2584 error = 0; 2585 2586 firmware_put(fp, FIRMWARE_UNLOAD); 2587 return error; 2588 } 2589 2590 #ifdef notyet 2591 /* 2592 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2593 * false CCA count. This function is called periodically (every seconds) when 2594 * in the RUN state. Values taken from the reference driver. 2595 */ 2596 static void 2597 rt2661_rx_tune(struct rt2661_softc *sc) 2598 { 2599 uint8_t bbp17; 2600 uint16_t cca; 2601 int lo, hi, dbm; 2602 2603 /* 2604 * Tuning range depends on operating band and on the presence of an 2605 * external low-noise amplifier. 2606 */ 2607 lo = 0x20; 2608 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2609 lo += 0x08; 2610 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2611 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2612 lo += 0x10; 2613 hi = lo + 0x20; 2614 2615 /* retrieve false CCA count since last call (clear on read) */ 2616 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2617 2618 if (dbm >= -35) { 2619 bbp17 = 0x60; 2620 } else if (dbm >= -58) { 2621 bbp17 = hi; 2622 } else if (dbm >= -66) { 2623 bbp17 = lo + 0x10; 2624 } else if (dbm >= -74) { 2625 bbp17 = lo + 0x08; 2626 } else { 2627 /* RSSI < -74dBm, tune using false CCA count */ 2628 2629 bbp17 = sc->bbp17; /* current value */ 2630 2631 hi -= 2 * (-74 - dbm); 2632 if (hi < lo) 2633 hi = lo; 2634 2635 if (bbp17 > hi) { 2636 bbp17 = hi; 2637 2638 } else if (cca > 512) { 2639 if (++bbp17 > hi) 2640 bbp17 = hi; 2641 } else if (cca < 100) { 2642 if (--bbp17 < lo) 2643 bbp17 = lo; 2644 } 2645 } 2646 2647 if (bbp17 != sc->bbp17) { 2648 rt2661_bbp_write(sc, 17, bbp17); 2649 sc->bbp17 = bbp17; 2650 } 2651 } 2652 2653 /* 2654 * Enter/Leave radar detection mode. 2655 * This is for 802.11h additional regulatory domains. 2656 */ 2657 static void 2658 rt2661_radar_start(struct rt2661_softc *sc) 2659 { 2660 uint32_t tmp; 2661 2662 /* disable Rx */ 2663 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2664 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2665 2666 rt2661_bbp_write(sc, 82, 0x20); 2667 rt2661_bbp_write(sc, 83, 0x00); 2668 rt2661_bbp_write(sc, 84, 0x40); 2669 2670 /* save current BBP registers values */ 2671 sc->bbp18 = rt2661_bbp_read(sc, 18); 2672 sc->bbp21 = rt2661_bbp_read(sc, 21); 2673 sc->bbp22 = rt2661_bbp_read(sc, 22); 2674 sc->bbp16 = rt2661_bbp_read(sc, 16); 2675 sc->bbp17 = rt2661_bbp_read(sc, 17); 2676 sc->bbp64 = rt2661_bbp_read(sc, 64); 2677 2678 rt2661_bbp_write(sc, 18, 0xff); 2679 rt2661_bbp_write(sc, 21, 0x3f); 2680 rt2661_bbp_write(sc, 22, 0x3f); 2681 rt2661_bbp_write(sc, 16, 0xbd); 2682 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2683 rt2661_bbp_write(sc, 64, 0x21); 2684 2685 /* restore Rx filter */ 2686 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2687 } 2688 2689 static int 2690 rt2661_radar_stop(struct rt2661_softc *sc) 2691 { 2692 uint8_t bbp66; 2693 2694 /* read radar detection result */ 2695 bbp66 = rt2661_bbp_read(sc, 66); 2696 2697 /* restore BBP registers values */ 2698 rt2661_bbp_write(sc, 16, sc->bbp16); 2699 rt2661_bbp_write(sc, 17, sc->bbp17); 2700 rt2661_bbp_write(sc, 18, sc->bbp18); 2701 rt2661_bbp_write(sc, 21, sc->bbp21); 2702 rt2661_bbp_write(sc, 22, sc->bbp22); 2703 rt2661_bbp_write(sc, 64, sc->bbp64); 2704 2705 return bbp66 == 1; 2706 } 2707 #endif 2708 2709 static int 2710 rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap) 2711 { 2712 struct ieee80211com *ic = vap->iv_ic; 2713 struct rt2661_tx_desc desc; 2714 struct mbuf *m0; 2715 int rate; 2716 2717 if ((m0 = ieee80211_beacon_alloc(vap->iv_bss))== NULL) { 2718 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2719 return ENOBUFS; 2720 } 2721 2722 /* send beacons at the lowest available rate */ 2723 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2; 2724 2725 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2726 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2727 2728 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2729 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2730 2731 /* copy beacon header and payload into NIC memory */ 2732 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2733 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2734 2735 m_freem(m0); 2736 2737 return 0; 2738 } 2739 2740 /* 2741 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2742 * and HostAP operating modes. 2743 */ 2744 static void 2745 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2746 { 2747 struct ieee80211com *ic = &sc->sc_ic; 2748 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2749 uint32_t tmp; 2750 2751 if (vap->iv_opmode != IEEE80211_M_STA) { 2752 /* 2753 * Change default 16ms TBTT adjustment to 8ms. 2754 * Must be done before enabling beacon generation. 2755 */ 2756 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2757 } 2758 2759 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2760 2761 /* set beacon interval (in 1/16ms unit) */ 2762 tmp |= vap->iv_bss->ni_intval * 16; 2763 2764 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2765 if (vap->iv_opmode == IEEE80211_M_STA) 2766 tmp |= RT2661_TSF_MODE(1); 2767 else 2768 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2769 2770 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2771 } 2772 2773 static void 2774 rt2661_enable_tsf(struct rt2661_softc *sc) 2775 { 2776 RAL_WRITE(sc, RT2661_TXRX_CSR9, 2777 (RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000) 2778 | RT2661_TSF_TICKING | RT2661_TSF_MODE(2)); 2779 } 2780 2781 /* 2782 * Retrieve the "Received Signal Strength Indicator" from the raw values 2783 * contained in Rx descriptors. The computation depends on which band the 2784 * frame was received. Correction values taken from the reference driver. 2785 */ 2786 static int 2787 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2788 { 2789 int lna, agc, rssi; 2790 2791 lna = (raw >> 5) & 0x3; 2792 agc = raw & 0x1f; 2793 2794 if (lna == 0) { 2795 /* 2796 * No mapping available. 2797 * 2798 * NB: Since RSSI is relative to noise floor, -1 is 2799 * adequate for caller to know error happened. 2800 */ 2801 return -1; 2802 } 2803 2804 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 2805 2806 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2807 rssi += sc->rssi_2ghz_corr; 2808 2809 if (lna == 1) 2810 rssi -= 64; 2811 else if (lna == 2) 2812 rssi -= 74; 2813 else if (lna == 3) 2814 rssi -= 90; 2815 } else { 2816 rssi += sc->rssi_5ghz_corr; 2817 2818 if (lna == 1) 2819 rssi -= 64; 2820 else if (lna == 2) 2821 rssi -= 86; 2822 else if (lna == 3) 2823 rssi -= 100; 2824 } 2825 return rssi; 2826 } 2827 2828 static void 2829 rt2661_scan_start(struct ieee80211com *ic) 2830 { 2831 struct rt2661_softc *sc = ic->ic_softc; 2832 uint32_t tmp; 2833 2834 /* abort TSF synchronization */ 2835 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 2836 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff); 2837 rt2661_set_bssid(sc, ieee80211broadcastaddr); 2838 } 2839 2840 static void 2841 rt2661_scan_end(struct ieee80211com *ic) 2842 { 2843 struct rt2661_softc *sc = ic->ic_softc; 2844 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2845 2846 rt2661_enable_tsf_sync(sc); 2847 /* XXX keep local copy */ 2848 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid); 2849 } 2850 2851 static void 2852 rt2661_set_channel(struct ieee80211com *ic) 2853 { 2854 struct rt2661_softc *sc = ic->ic_softc; 2855 2856 RAL_LOCK(sc); 2857 rt2661_set_chan(sc, ic->ic_curchan); 2858 RAL_UNLOCK(sc); 2859 2860 } 2861