1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 */ 37 38 /* 39 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Networking Software Engineer 43 * Wind River Systems 44 */ 45 46 /* 47 * This driver is designed to support RealTek's next generation of 48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 49 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 50 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 51 * 52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 53 * with the older 8139 family, however it also supports a special 54 * C+ mode of operation that provides several new performance enhancing 55 * features. These include: 56 * 57 * o Descriptor based DMA mechanism. Each descriptor represents 58 * a single packet fragment. Data buffers may be aligned on 59 * any byte boundary. 60 * 61 * o 64-bit DMA 62 * 63 * o TCP/IP checksum offload for both RX and TX 64 * 65 * o High and normal priority transmit DMA rings 66 * 67 * o VLAN tag insertion and extraction 68 * 69 * o TCP large send (segmentation offload) 70 * 71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 72 * programming API is fairly straightforward. The RX filtering, EEPROM 73 * access and PHY access is the same as it is on the older 8139 series 74 * chips. 75 * 76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 77 * same programming API and feature set as the 8139C+ with the following 78 * differences and additions: 79 * 80 * o 1000Mbps mode 81 * 82 * o Jumbo frames 83 * 84 * o GMII and TBI ports/registers for interfacing with copper 85 * or fiber PHYs 86 * 87 * o RX and TX DMA rings can have up to 1024 descriptors 88 * (the 8139C+ allows a maximum of 64) 89 * 90 * o Slight differences in register layout from the 8139C+ 91 * 92 * The TX start and timer interrupt registers are at different locations 93 * on the 8169 than they are on the 8139C+. Also, the status word in the 94 * RX descriptor has a slightly different bit layout. The 8169 does not 95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 96 * copper gigE PHY. 97 * 98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 99 * (the 'S' stands for 'single-chip'). These devices have the same 100 * programming API as the older 8169, but also have some vendor-specific 101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 103 * 104 * This driver takes advantage of the RX and TX checksum offload and 105 * VLAN tag insertion/extraction features. It also implements TX 106 * interrupt moderation using the timer interrupt registers, which 107 * significantly reduces TX interrupt load. There is also support 108 * for jumbo frames, however the 8169/8169S/8110S can not transmit 109 * jumbo frames larger than 7440, so the max MTU possible with this 110 * driver is 7422 bytes. 111 */ 112 113 #define _IP_VHL 114 115 #include "opt_ifpoll.h" 116 117 #include <sys/param.h> 118 #include <sys/bus.h> 119 #include <sys/endian.h> 120 #include <sys/kernel.h> 121 #include <sys/in_cksum.h> 122 #include <sys/interrupt.h> 123 #include <sys/malloc.h> 124 #include <sys/mbuf.h> 125 #include <sys/rman.h> 126 #include <sys/serialize.h> 127 #include <sys/socket.h> 128 #include <sys/sockio.h> 129 #include <sys/sysctl.h> 130 131 #include <net/bpf.h> 132 #include <net/ethernet.h> 133 #include <net/if.h> 134 #include <net/ifq_var.h> 135 #include <net/if_arp.h> 136 #include <net/if_dl.h> 137 #include <net/if_media.h> 138 #include <net/if_poll.h> 139 #include <net/if_types.h> 140 #include <net/vlan/if_vlan_var.h> 141 #include <net/vlan/if_vlan_ether.h> 142 143 #include <netinet/ip.h> 144 145 #include <dev/netif/mii_layer/mii.h> 146 #include <dev/netif/mii_layer/miivar.h> 147 148 #include <bus/pci/pcidevs.h> 149 #include <bus/pci/pcireg.h> 150 #include <bus/pci/pcivar.h> 151 152 /* "device miibus" required. See GENERIC if you get errors here. */ 153 #include "miibus_if.h" 154 155 #include <dev/netif/re/if_rereg.h> 156 #include <dev/netif/re/if_revar.h> 157 158 /* 159 * Various supported device vendors/types and their names. 160 */ 161 static const struct re_type { 162 uint16_t re_vid; 163 uint16_t re_did; 164 const char *re_name; 165 } re_devs[] = { 166 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, 167 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 168 169 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, 170 "RealTek 8139C+ 10/100BaseTX" }, 171 172 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, 173 "RealTek 810x PCIe 10/100baseTX" }, 174 175 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, 176 "RealTek 8111/8168 PCIe Gigabit Ethernet" }, 177 178 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 179 "RealTek 8110/8169 Gigabit Ethernet" }, 180 181 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, 182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 183 184 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, 185 "Corega CG-LAPCIGT Gigabit Ethernet" }, 186 187 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, 188 "Linksys EG1032 Gigabit Ethernet" }, 189 190 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, 191 "US Robotics 997902 Gigabit Ethernet" }, 192 193 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322, 194 "TTTech MC322 Gigabit Ethernet" }, 195 196 { 0, 0, NULL } 197 }; 198 199 static const struct re_hwrev re_hwrevs[] = { 200 { RE_HWREV_8139CPLUS, RE_MACVER_UNKN, ETHERMTU, 201 RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE }, 202 203 { RE_HWREV_8169, RE_MACVER_UNKN, ETHERMTU, 204 RE_C_HWCSUM | RE_C_8169 }, 205 206 { RE_HWREV_8110S, RE_MACVER_03, RE_MTU_6K, 207 RE_C_HWCSUM | RE_C_8169 }, 208 209 { RE_HWREV_8169S, RE_MACVER_03, RE_MTU_6K, 210 RE_C_HWCSUM | RE_C_8169 }, 211 212 { RE_HWREV_8169SB, RE_MACVER_04, RE_MTU_6K, 213 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 214 215 { RE_HWREV_8169SC1, RE_MACVER_05, RE_MTU_6K, 216 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 217 218 { RE_HWREV_8169SC2, RE_MACVER_06, RE_MTU_6K, 219 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 220 221 { RE_HWREV_8168B1, RE_MACVER_21, RE_MTU_6K, 222 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT }, 223 224 { RE_HWREV_8168B2, RE_MACVER_23, RE_MTU_6K, 225 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 226 227 { RE_HWREV_8168B3, RE_MACVER_23, RE_MTU_6K, 228 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 229 230 { RE_HWREV_8168C, RE_MACVER_29, RE_MTU_6K, 231 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 232 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 233 234 { RE_HWREV_8168CP, RE_MACVER_2B, RE_MTU_6K, 235 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 236 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 237 238 { RE_HWREV_8168D, RE_MACVER_2A, RE_MTU_9K, 239 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 240 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 241 242 { RE_HWREV_8168DP, RE_MACVER_2D, RE_MTU_9K, 243 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 244 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 245 246 { RE_HWREV_8168E, RE_MACVER_UNKN, RE_MTU_9K, 247 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 248 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 249 250 { RE_HWREV_8168F, RE_MACVER_UNKN, RE_MTU_9K, 251 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 252 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 253 254 { RE_HWREV_8111F, RE_MACVER_UNKN, RE_MTU_9K, 255 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 256 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 257 258 { RE_HWREV_8100E, RE_MACVER_UNKN, ETHERMTU, 259 RE_C_HWCSUM | RE_C_FASTE }, 260 261 { RE_HWREV_8101E1, RE_MACVER_16, ETHERMTU, 262 RE_C_HWCSUM | RE_C_FASTE }, 263 264 { RE_HWREV_8101E2, RE_MACVER_16, ETHERMTU, 265 RE_C_HWCSUM | RE_C_FASTE }, 266 267 { RE_HWREV_8102E, RE_MACVER_15, ETHERMTU, 268 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 269 RE_C_FASTE }, 270 271 { RE_HWREV_8102EL, RE_MACVER_15, ETHERMTU, 272 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 273 RE_C_FASTE }, 274 275 { RE_HWREV_8105E, RE_MACVER_UNKN, ETHERMTU, 276 RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | RE_C_AUTOPAD | 277 RE_C_STOP_RXTX | RE_C_FASTE }, 278 279 { RE_HWREV_NULL, 0, 0, 0 } 280 }; 281 282 static int re_probe(device_t); 283 static int re_attach(device_t); 284 static int re_detach(device_t); 285 static int re_suspend(device_t); 286 static int re_resume(device_t); 287 static void re_shutdown(device_t); 288 289 static int re_allocmem(device_t); 290 static void re_freemem(device_t); 291 static void re_freebufmem(struct re_softc *, int, int); 292 static int re_encap(struct re_softc *, struct mbuf **, int *); 293 static int re_newbuf_std(struct re_softc *, int, int); 294 static int re_newbuf_jumbo(struct re_softc *, int, int); 295 static void re_setup_rxdesc(struct re_softc *, int); 296 static int re_rx_list_init(struct re_softc *); 297 static int re_tx_list_init(struct re_softc *); 298 static int re_rxeof(struct re_softc *); 299 static int re_txeof(struct re_softc *); 300 static int re_tx_collect(struct re_softc *); 301 static void re_intr(void *); 302 static void re_tick(void *); 303 static void re_tick_serialized(void *); 304 305 static void re_start(struct ifnet *, struct ifaltq_subque *); 306 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 307 static void re_init(void *); 308 static void re_stop(struct re_softc *); 309 static void re_watchdog(struct ifnet *); 310 static int re_ifmedia_upd(struct ifnet *); 311 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 312 313 static void re_eeprom_putbyte(struct re_softc *, int); 314 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 315 static void re_read_eeprom(struct re_softc *, caddr_t, int, int); 316 static void re_get_eewidth(struct re_softc *); 317 318 static int re_gmii_readreg(device_t, int, int); 319 static int re_gmii_writereg(device_t, int, int, int); 320 321 static int re_miibus_readreg(device_t, int, int); 322 static int re_miibus_writereg(device_t, int, int, int); 323 static void re_miibus_statchg(device_t); 324 325 static void re_setmulti(struct re_softc *); 326 static void re_reset(struct re_softc *, int); 327 static void re_get_eaddr(struct re_softc *, uint8_t *); 328 329 static void re_setup_hw_im(struct re_softc *); 330 static void re_setup_sim_im(struct re_softc *); 331 static void re_disable_hw_im(struct re_softc *); 332 static void re_disable_sim_im(struct re_softc *); 333 static void re_config_imtype(struct re_softc *, int); 334 static void re_setup_intr(struct re_softc *, int, int); 335 336 static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *); 337 static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS); 338 static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS); 339 static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS); 340 static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS); 341 342 static int re_jpool_alloc(struct re_softc *); 343 static void re_jpool_free(struct re_softc *); 344 static struct re_jbuf *re_jbuf_alloc(struct re_softc *); 345 static void re_jbuf_free(void *); 346 static void re_jbuf_ref(void *); 347 348 #ifdef RE_DIAG 349 static int re_diag(struct re_softc *); 350 #endif 351 352 #ifdef IFPOLL_ENABLE 353 static void re_npoll(struct ifnet *, struct ifpoll_info *); 354 static void re_npoll_compat(struct ifnet *, void *, int); 355 #endif 356 357 static device_method_t re_methods[] = { 358 /* Device interface */ 359 DEVMETHOD(device_probe, re_probe), 360 DEVMETHOD(device_attach, re_attach), 361 DEVMETHOD(device_detach, re_detach), 362 DEVMETHOD(device_suspend, re_suspend), 363 DEVMETHOD(device_resume, re_resume), 364 DEVMETHOD(device_shutdown, re_shutdown), 365 366 /* bus interface */ 367 DEVMETHOD(bus_print_child, bus_generic_print_child), 368 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 369 370 /* MII interface */ 371 DEVMETHOD(miibus_readreg, re_miibus_readreg), 372 DEVMETHOD(miibus_writereg, re_miibus_writereg), 373 DEVMETHOD(miibus_statchg, re_miibus_statchg), 374 375 DEVMETHOD_END 376 }; 377 378 static driver_t re_driver = { 379 "re", 380 re_methods, 381 sizeof(struct re_softc) 382 }; 383 384 static devclass_t re_devclass; 385 386 DECLARE_DUMMY_MODULE(if_re); 387 MODULE_DEPEND(if_re, miibus, 1, 1, 1); 388 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, NULL, NULL); 389 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, NULL, NULL); 390 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, NULL, NULL); 391 392 static int re_rx_desc_count = RE_RX_DESC_CNT_DEF; 393 static int re_tx_desc_count = RE_TX_DESC_CNT_DEF; 394 static int re_msi_enable = 0; 395 396 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count); 397 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count); 398 TUNABLE_INT("hw.re.msi.enable", &re_msi_enable); 399 400 #define EE_SET(x) \ 401 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 402 403 #define EE_CLR(x) \ 404 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 405 406 static __inline void 407 re_free_rxchain(struct re_softc *sc) 408 { 409 if (sc->re_head != NULL) { 410 m_freem(sc->re_head); 411 sc->re_head = sc->re_tail = NULL; 412 } 413 } 414 415 /* 416 * Send a read command and address to the EEPROM, check for ACK. 417 */ 418 static void 419 re_eeprom_putbyte(struct re_softc *sc, int addr) 420 { 421 int d, i; 422 423 d = addr | (RE_9346_READ << sc->re_eewidth); 424 425 /* 426 * Feed in each bit and strobe the clock. 427 */ 428 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) { 429 if (d & i) 430 EE_SET(RE_EE_DATAIN); 431 else 432 EE_CLR(RE_EE_DATAIN); 433 DELAY(100); 434 EE_SET(RE_EE_CLK); 435 DELAY(150); 436 EE_CLR(RE_EE_CLK); 437 DELAY(100); 438 } 439 } 440 441 /* 442 * Read a word of data stored in the EEPROM at address 'addr.' 443 */ 444 static void 445 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 446 { 447 int i; 448 uint16_t word = 0; 449 450 /* 451 * Send address of word we want to read. 452 */ 453 re_eeprom_putbyte(sc, addr); 454 455 /* 456 * Start reading bits from EEPROM. 457 */ 458 for (i = 0x8000; i != 0; i >>= 1) { 459 EE_SET(RE_EE_CLK); 460 DELAY(100); 461 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 462 word |= i; 463 EE_CLR(RE_EE_CLK); 464 DELAY(100); 465 } 466 467 *dest = word; 468 } 469 470 /* 471 * Read a sequence of words from the EEPROM. 472 */ 473 static void 474 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt) 475 { 476 int i; 477 uint16_t word = 0, *ptr; 478 479 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 480 DELAY(100); 481 482 for (i = 0; i < cnt; i++) { 483 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL); 484 re_eeprom_getword(sc, off + i, &word); 485 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL); 486 ptr = (uint16_t *)(dest + (i * 2)); 487 *ptr = word; 488 } 489 490 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 491 } 492 493 static void 494 re_get_eewidth(struct re_softc *sc) 495 { 496 uint16_t re_did = 0; 497 498 sc->re_eewidth = 6; 499 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 500 if (re_did != 0x8129) 501 sc->re_eewidth = 8; 502 } 503 504 static int 505 re_gmii_readreg(device_t dev, int phy, int reg) 506 { 507 struct re_softc *sc = device_get_softc(dev); 508 u_int32_t rval; 509 int i; 510 511 if (phy != 1) 512 return(0); 513 514 /* Let the rgephy driver read the GMEDIASTAT register */ 515 516 if (reg == RE_GMEDIASTAT) 517 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 518 519 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 520 DELAY(1000); 521 522 for (i = 0; i < RE_TIMEOUT; i++) { 523 rval = CSR_READ_4(sc, RE_PHYAR); 524 if (rval & RE_PHYAR_BUSY) 525 break; 526 DELAY(100); 527 } 528 529 if (i == RE_TIMEOUT) { 530 device_printf(dev, "PHY read failed\n"); 531 return(0); 532 } 533 534 return(rval & RE_PHYAR_PHYDATA); 535 } 536 537 static int 538 re_gmii_writereg(device_t dev, int phy, int reg, int data) 539 { 540 struct re_softc *sc = device_get_softc(dev); 541 uint32_t rval; 542 int i; 543 544 CSR_WRITE_4(sc, RE_PHYAR, 545 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 546 DELAY(1000); 547 548 for (i = 0; i < RE_TIMEOUT; i++) { 549 rval = CSR_READ_4(sc, RE_PHYAR); 550 if ((rval & RE_PHYAR_BUSY) == 0) 551 break; 552 DELAY(100); 553 } 554 555 if (i == RE_TIMEOUT) 556 device_printf(dev, "PHY write failed\n"); 557 558 return(0); 559 } 560 561 static int 562 re_miibus_readreg(device_t dev, int phy, int reg) 563 { 564 struct re_softc *sc = device_get_softc(dev); 565 uint16_t rval = 0; 566 uint16_t re8139_reg = 0; 567 568 if (!RE_IS_8139CP(sc)) { 569 rval = re_gmii_readreg(dev, phy, reg); 570 return(rval); 571 } 572 573 /* Pretend the internal PHY is only at address 0 */ 574 if (phy) 575 return(0); 576 577 switch(reg) { 578 case MII_BMCR: 579 re8139_reg = RE_BMCR; 580 break; 581 case MII_BMSR: 582 re8139_reg = RE_BMSR; 583 break; 584 case MII_ANAR: 585 re8139_reg = RE_ANAR; 586 break; 587 case MII_ANER: 588 re8139_reg = RE_ANER; 589 break; 590 case MII_ANLPAR: 591 re8139_reg = RE_LPAR; 592 break; 593 case MII_PHYIDR1: 594 case MII_PHYIDR2: 595 return(0); 596 /* 597 * Allow the rlphy driver to read the media status 598 * register. If we have a link partner which does not 599 * support NWAY, this is the register which will tell 600 * us the results of parallel detection. 601 */ 602 case RE_MEDIASTAT: 603 return(CSR_READ_1(sc, RE_MEDIASTAT)); 604 default: 605 device_printf(dev, "bad phy register\n"); 606 return(0); 607 } 608 rval = CSR_READ_2(sc, re8139_reg); 609 if (re8139_reg == RE_BMCR) { 610 /* 8139C+ has different bit layout. */ 611 rval &= ~(BMCR_LOOP | BMCR_ISO); 612 } 613 return(rval); 614 } 615 616 static int 617 re_miibus_writereg(device_t dev, int phy, int reg, int data) 618 { 619 struct re_softc *sc= device_get_softc(dev); 620 u_int16_t re8139_reg = 0; 621 622 if (!RE_IS_8139CP(sc)) 623 return(re_gmii_writereg(dev, phy, reg, data)); 624 625 /* Pretend the internal PHY is only at address 0 */ 626 if (phy) 627 return(0); 628 629 switch(reg) { 630 case MII_BMCR: 631 re8139_reg = RE_BMCR; 632 /* 8139C+ has different bit layout. */ 633 data &= ~(BMCR_LOOP | BMCR_ISO); 634 break; 635 case MII_BMSR: 636 re8139_reg = RE_BMSR; 637 break; 638 case MII_ANAR: 639 re8139_reg = RE_ANAR; 640 break; 641 case MII_ANER: 642 re8139_reg = RE_ANER; 643 break; 644 case MII_ANLPAR: 645 re8139_reg = RE_LPAR; 646 break; 647 case MII_PHYIDR1: 648 case MII_PHYIDR2: 649 return(0); 650 default: 651 device_printf(dev, "bad phy register\n"); 652 return(0); 653 } 654 CSR_WRITE_2(sc, re8139_reg, data); 655 return(0); 656 } 657 658 static void 659 re_miibus_statchg(device_t dev) 660 { 661 } 662 663 /* 664 * Program the 64-bit multicast hash filter. 665 */ 666 static void 667 re_setmulti(struct re_softc *sc) 668 { 669 struct ifnet *ifp = &sc->arpcom.ac_if; 670 int h = 0; 671 uint32_t hashes[2] = { 0, 0 }; 672 struct ifmultiaddr *ifma; 673 uint32_t rxfilt; 674 int mcnt = 0; 675 676 rxfilt = CSR_READ_4(sc, RE_RXCFG); 677 678 /* Set the individual bit to receive frames for this host only. */ 679 rxfilt |= RE_RXCFG_RX_INDIV; 680 /* Set capture broadcast bit to capture broadcast frames. */ 681 rxfilt |= RE_RXCFG_RX_BROAD; 682 683 rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI); 684 if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) { 685 rxfilt |= RE_RXCFG_RX_MULTI; 686 687 /* If we want promiscuous mode, set the allframes bit. */ 688 if (ifp->if_flags & IFF_PROMISC) 689 rxfilt |= RE_RXCFG_RX_ALLPHYS; 690 691 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 692 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 693 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 694 return; 695 } 696 697 /* first, zot all the existing hash bits */ 698 CSR_WRITE_4(sc, RE_MAR0, 0); 699 CSR_WRITE_4(sc, RE_MAR4, 0); 700 701 /* now program new ones */ 702 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 703 if (ifma->ifma_addr->sa_family != AF_LINK) 704 continue; 705 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 706 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 707 if (h < 32) 708 hashes[0] |= (1 << h); 709 else 710 hashes[1] |= (1 << (h - 32)); 711 mcnt++; 712 } 713 714 if (mcnt) 715 rxfilt |= RE_RXCFG_RX_MULTI; 716 else 717 rxfilt &= ~RE_RXCFG_RX_MULTI; 718 719 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 720 721 /* 722 * For some unfathomable reason, RealTek decided to reverse 723 * the order of the multicast hash registers in the PCI Express 724 * parts. This means we have to write the hash pattern in reverse 725 * order for those devices. 726 */ 727 if (sc->re_caps & RE_C_PCIE) { 728 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[1])); 729 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[0])); 730 } else { 731 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 732 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 733 } 734 } 735 736 static void 737 re_reset(struct re_softc *sc, int running) 738 { 739 int i; 740 741 if ((sc->re_caps & RE_C_STOP_RXTX) && running) { 742 CSR_WRITE_1(sc, RE_COMMAND, 743 RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB); 744 DELAY(100); 745 } 746 747 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 748 749 for (i = 0; i < RE_TIMEOUT; i++) { 750 DELAY(10); 751 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 752 break; 753 } 754 if (i == RE_TIMEOUT) 755 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 756 } 757 758 #ifdef RE_DIAG 759 /* 760 * The following routine is designed to test for a defect on some 761 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 762 * lines connected to the bus, however for a 32-bit only card, they 763 * should be pulled high. The result of this defect is that the 764 * NIC will not work right if you plug it into a 64-bit slot: DMA 765 * operations will be done with 64-bit transfers, which will fail 766 * because the 64-bit data lines aren't connected. 767 * 768 * There's no way to work around this (short of talking a soldering 769 * iron to the board), however we can detect it. The method we use 770 * here is to put the NIC into digital loopback mode, set the receiver 771 * to promiscuous mode, and then try to send a frame. We then compare 772 * the frame data we sent to what was received. If the data matches, 773 * then the NIC is working correctly, otherwise we know the user has 774 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 775 * slot. In the latter case, there's no way the NIC can work correctly, 776 * so we print out a message on the console and abort the device attach. 777 */ 778 779 static int 780 re_diag(struct re_softc *sc) 781 { 782 struct ifnet *ifp = &sc->arpcom.ac_if; 783 struct mbuf *m0; 784 struct ether_header *eh; 785 struct re_desc *cur_rx; 786 uint16_t status; 787 int total_len, i, error = 0, phyaddr; 788 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 789 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 790 char ethstr[2][ETHER_ADDRSTRLEN + 1]; 791 792 /* Allocate a single mbuf */ 793 794 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 795 if (m0 == NULL) 796 return(ENOBUFS); 797 798 /* 799 * Initialize the NIC in test mode. This sets the chip up 800 * so that it can send and receive frames, but performs the 801 * following special functions: 802 * - Puts receiver in promiscuous mode 803 * - Enables digital loopback mode 804 * - Leaves interrupts turned off 805 */ 806 807 ifp->if_flags |= IFF_PROMISC; 808 sc->re_flags |= RE_F_TESTMODE; 809 re_init(sc); 810 sc->re_flags |= RE_F_LINKED; 811 if (!RE_IS_8139CP(sc)) 812 phyaddr = 1; 813 else 814 phyaddr = 0; 815 816 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET); 817 for (i = 0; i < RE_TIMEOUT; i++) { 818 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR); 819 if (!(status & BMCR_RESET)) 820 break; 821 } 822 823 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP); 824 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG); 825 826 DELAY(100000); 827 828 /* Put some data in the mbuf */ 829 830 eh = mtod(m0, struct ether_header *); 831 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 832 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 833 eh->ether_type = htons(ETHERTYPE_IP); 834 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 835 836 /* 837 * Queue the packet, start transmission. 838 * Note: ifq_handoff() ultimately calls re_start() for us. 839 */ 840 841 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 842 error = ifq_handoff(ifp, m0, NULL); 843 if (error) { 844 m0 = NULL; 845 goto done; 846 } 847 m0 = NULL; 848 849 /* Wait for it to propagate through the chip */ 850 851 DELAY(100000); 852 for (i = 0; i < RE_TIMEOUT; i++) { 853 status = CSR_READ_2(sc, RE_ISR); 854 CSR_WRITE_2(sc, RE_ISR, status); 855 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 856 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 857 break; 858 DELAY(10); 859 } 860 861 if (i == RE_TIMEOUT) { 862 if_printf(ifp, "diagnostic failed to receive packet " 863 "in loopback mode\n"); 864 error = EIO; 865 goto done; 866 } 867 868 /* 869 * The packet should have been dumped into the first 870 * entry in the RX DMA ring. Grab it from there. 871 */ 872 873 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, sc->re_ldata.re_rx_dmamap[0], 874 BUS_DMASYNC_POSTREAD); 875 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 876 sc->re_ldata.re_rx_dmamap[0]); 877 878 m0 = sc->re_ldata.re_rx_mbuf[0]; 879 sc->re_ldata.re_rx_mbuf[0] = NULL; 880 eh = mtod(m0, struct ether_header *); 881 882 cur_rx = &sc->re_ldata.re_rx_list[0]; 883 total_len = RE_RXBYTES(cur_rx); 884 885 if (total_len != ETHER_MIN_LEN) { 886 if_printf(ifp, "diagnostic failed, received short packet\n"); 887 error = EIO; 888 goto done; 889 } 890 891 /* Test that the received packet data matches what we sent. */ 892 893 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 894 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 895 be16toh(eh->ether_type) != ETHERTYPE_IP) { 896 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 897 if_printf(ifp, "expected TX data: %s/%s/0x%x\n", 898 kether_ntoa(dst, ethstr[0]), kether_ntoa(src, ethstr[1]), ETHERTYPE_IP); 899 if_printf(ifp, "received RX data: %s/%s/0x%x\n", 900 kether_ntoa(eh->ether_dhost, ethstr[0]), 901 kether_ntoa(eh->ether_shost, ethstr[1]), 902 ntohs(eh->ether_type)); 903 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 904 "into a 64-bit PCI slot.\n"); 905 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 906 "for proper operation.\n"); 907 if_printf(ifp, "Read the re(4) man page for more details.\n"); 908 error = EIO; 909 } 910 911 done: 912 /* Turn interface off, release resources */ 913 914 sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE); 915 ifp->if_flags &= ~IFF_PROMISC; 916 re_stop(sc); 917 if (m0 != NULL) 918 m_freem(m0); 919 920 return (error); 921 } 922 #endif /* RE_DIAG */ 923 924 /* 925 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 926 * IDs against our list and return a device name if we find a match. 927 */ 928 static int 929 re_probe(device_t dev) 930 { 931 const struct re_type *t; 932 const struct re_hwrev *hw_rev; 933 struct re_softc *sc; 934 int rid; 935 uint32_t hwrev, macmode, txcfg; 936 uint16_t vendor, product; 937 938 vendor = pci_get_vendor(dev); 939 product = pci_get_device(dev); 940 941 /* 942 * Only attach to rev.3 of the Linksys EG1032 adapter. 943 * Rev.2 is supported by sk(4). 944 */ 945 if (vendor == PCI_VENDOR_LINKSYS && 946 product == PCI_PRODUCT_LINKSYS_EG1032 && 947 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3) 948 return ENXIO; 949 950 if (vendor == PCI_VENDOR_REALTEK && 951 product == PCI_PRODUCT_REALTEK_RT8139 && 952 pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) { 953 /* Poor 8139 */ 954 return ENXIO; 955 } 956 957 for (t = re_devs; t->re_name != NULL; t++) { 958 if (product == t->re_did && vendor == t->re_vid) 959 break; 960 } 961 962 /* 963 * Check if we found a RealTek device. 964 */ 965 if (t->re_name == NULL) 966 return ENXIO; 967 968 /* 969 * Temporarily map the I/O space so we can read the chip ID register. 970 */ 971 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 972 rid = RE_PCI_LOIO; 973 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 974 RF_ACTIVE); 975 if (sc->re_res == NULL) { 976 device_printf(dev, "couldn't map ports/memory\n"); 977 kfree(sc, M_TEMP); 978 return ENXIO; 979 } 980 981 sc->re_btag = rman_get_bustag(sc->re_res); 982 sc->re_bhandle = rman_get_bushandle(sc->re_res); 983 984 txcfg = CSR_READ_4(sc, RE_TXCFG); 985 hwrev = txcfg & RE_TXCFG_HWREV; 986 macmode = txcfg & RE_TXCFG_MACMODE; 987 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 988 kfree(sc, M_TEMP); 989 990 /* 991 * and continue matching for the specific chip... 992 */ 993 for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) { 994 if (hw_rev->re_hwrev == hwrev) { 995 sc = device_get_softc(dev); 996 997 sc->re_hwrev = hw_rev->re_hwrev; 998 sc->re_macver = hw_rev->re_macver; 999 sc->re_caps = hw_rev->re_caps; 1000 sc->re_maxmtu = hw_rev->re_maxmtu; 1001 1002 /* 1003 * Apply chip property fixup 1004 */ 1005 switch (sc->re_hwrev) { 1006 case RE_HWREV_8101E1: 1007 case RE_HWREV_8101E2: 1008 if (macmode == 0) 1009 sc->re_macver = RE_MACVER_11; 1010 else if (macmode == 0x200000) 1011 sc->re_macver = RE_MACVER_12; 1012 break; 1013 case RE_HWREV_8102E: 1014 case RE_HWREV_8102EL: 1015 if (macmode == 0) 1016 sc->re_macver = RE_MACVER_13; 1017 else if (macmode == 0x100000) 1018 sc->re_macver = RE_MACVER_14; 1019 break; 1020 case RE_HWREV_8168B2: 1021 case RE_HWREV_8168B3: 1022 if (macmode == 0) 1023 sc->re_macver = RE_MACVER_22; 1024 break; 1025 case RE_HWREV_8168C: 1026 if (macmode == 0) 1027 sc->re_macver = RE_MACVER_24; 1028 else if (macmode == 0x200000) 1029 sc->re_macver = RE_MACVER_25; 1030 else if (macmode == 0x300000) 1031 sc->re_macver = RE_MACVER_27; 1032 break; 1033 case RE_HWREV_8168CP: 1034 if (macmode == 0) 1035 sc->re_macver = RE_MACVER_26; 1036 else if (macmode == 0x100000) 1037 sc->re_macver = RE_MACVER_28; 1038 break; 1039 case RE_HWREV_8168DP: 1040 if (macmode == 0) 1041 sc->re_macver = RE_MACVER_2B; 1042 else if (macmode == 0x200000) 1043 sc->re_macver = RE_MACVER_2C; 1044 break; 1045 case RE_HWREV_8168E: 1046 if (macmode == 0x100000) 1047 sc->re_macver = RE_MACVER_2E; 1048 else if (macmode == 0x200000) 1049 sc->re_macver = RE_MACVER_2F; 1050 break; 1051 case RE_HWREV_8168F: 1052 case RE_HWREV_8111F: 1053 if (macmode == 0x000000) 1054 sc->re_macver = RE_MACVER_30; 1055 else if (macmode == 0x100000) 1056 sc->re_macver = RE_MACVER_31; 1057 break; 1058 } 1059 if (pci_is_pcie(dev)) 1060 sc->re_caps |= RE_C_PCIE; 1061 1062 device_set_desc(dev, t->re_name); 1063 return 0; 1064 } 1065 } 1066 1067 if (bootverbose) { 1068 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n", 1069 hwrev, macmode); 1070 } 1071 return ENXIO; 1072 } 1073 1074 static int 1075 re_allocmem(device_t dev) 1076 { 1077 struct re_softc *sc = device_get_softc(dev); 1078 bus_dmamem_t dmem; 1079 int error, i; 1080 1081 /* 1082 * Allocate list data 1083 */ 1084 sc->re_ldata.re_tx_mbuf = 1085 kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *), 1086 M_DEVBUF, M_ZERO | M_WAITOK); 1087 1088 sc->re_ldata.re_rx_mbuf = 1089 kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *), 1090 M_DEVBUF, M_ZERO | M_WAITOK); 1091 1092 sc->re_ldata.re_rx_paddr = 1093 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t), 1094 M_DEVBUF, M_ZERO | M_WAITOK); 1095 1096 sc->re_ldata.re_tx_dmamap = 1097 kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t), 1098 M_DEVBUF, M_ZERO | M_WAITOK); 1099 1100 sc->re_ldata.re_rx_dmamap = 1101 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t), 1102 M_DEVBUF, M_ZERO | M_WAITOK); 1103 1104 /* 1105 * Allocate the parent bus DMA tag appropriate for PCI. 1106 */ 1107 error = bus_dma_tag_create(NULL, /* parent */ 1108 1, 0, /* alignment, boundary */ 1109 BUS_SPACE_MAXADDR, /* lowaddr */ 1110 BUS_SPACE_MAXADDR, /* highaddr */ 1111 NULL, NULL, /* filter, filterarg */ 1112 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 1113 0, /* nsegments */ 1114 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1115 0, /* flags */ 1116 &sc->re_parent_tag); 1117 if (error) { 1118 device_printf(dev, "could not allocate parent dma tag\n"); 1119 return error; 1120 } 1121 1122 /* Allocate TX descriptor list. */ 1123 error = bus_dmamem_coherent(sc->re_parent_tag, 1124 RE_RING_ALIGN, 0, 1125 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1126 RE_TX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1127 &dmem); 1128 if (error) { 1129 device_printf(dev, "could not allocate TX ring\n"); 1130 return error; 1131 } 1132 sc->re_ldata.re_tx_list_tag = dmem.dmem_tag; 1133 sc->re_ldata.re_tx_list_map = dmem.dmem_map; 1134 sc->re_ldata.re_tx_list = dmem.dmem_addr; 1135 sc->re_ldata.re_tx_list_addr = dmem.dmem_busaddr; 1136 1137 /* Allocate RX descriptor list. */ 1138 error = bus_dmamem_coherent(sc->re_parent_tag, 1139 RE_RING_ALIGN, 0, 1140 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1141 RE_RX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1142 &dmem); 1143 if (error) { 1144 device_printf(dev, "could not allocate RX ring\n"); 1145 return error; 1146 } 1147 sc->re_ldata.re_rx_list_tag = dmem.dmem_tag; 1148 sc->re_ldata.re_rx_list_map = dmem.dmem_map; 1149 sc->re_ldata.re_rx_list = dmem.dmem_addr; 1150 sc->re_ldata.re_rx_list_addr = dmem.dmem_busaddr; 1151 1152 /* Allocate maps for TX mbufs. */ 1153 error = bus_dma_tag_create(sc->re_parent_tag, 1154 1, 0, 1155 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1156 NULL, NULL, 1157 RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES, 1158 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1159 &sc->re_ldata.re_tx_mtag); 1160 if (error) { 1161 device_printf(dev, "could not allocate TX buf dma tag\n"); 1162 return(error); 1163 } 1164 1165 /* Create DMA maps for TX buffers */ 1166 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 1167 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag, 1168 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1169 &sc->re_ldata.re_tx_dmamap[i]); 1170 if (error) { 1171 device_printf(dev, "can't create DMA map for TX buf\n"); 1172 re_freebufmem(sc, i, 0); 1173 return(error); 1174 } 1175 } 1176 1177 /* Allocate maps for RX mbufs. */ 1178 error = bus_dma_tag_create(sc->re_parent_tag, 1179 RE_RXBUF_ALIGN, 0, 1180 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1181 NULL, NULL, 1182 MCLBYTES, 1, MCLBYTES, 1183 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED, 1184 &sc->re_ldata.re_rx_mtag); 1185 if (error) { 1186 device_printf(dev, "could not allocate RX buf dma tag\n"); 1187 return(error); 1188 } 1189 1190 /* Create spare DMA map for RX */ 1191 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, BUS_DMA_WAITOK, 1192 &sc->re_ldata.re_rx_spare); 1193 if (error) { 1194 device_printf(dev, "can't create spare DMA map for RX\n"); 1195 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1196 sc->re_ldata.re_rx_mtag = NULL; 1197 return error; 1198 } 1199 1200 /* Create DMA maps for RX buffers */ 1201 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1202 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, 1203 BUS_DMA_WAITOK, &sc->re_ldata.re_rx_dmamap[i]); 1204 if (error) { 1205 device_printf(dev, "can't create DMA map for RX buf\n"); 1206 re_freebufmem(sc, sc->re_tx_desc_cnt, i); 1207 return(error); 1208 } 1209 } 1210 1211 /* Create jumbo buffer pool for RX if required */ 1212 if (sc->re_caps & RE_C_CONTIGRX) { 1213 error = re_jpool_alloc(sc); 1214 if (error) { 1215 re_jpool_free(sc); 1216 /* Disable jumbo frame support */ 1217 sc->re_maxmtu = ETHERMTU; 1218 } 1219 } 1220 return(0); 1221 } 1222 1223 static void 1224 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt) 1225 { 1226 int i; 1227 1228 /* Destroy all the RX and TX buffer maps */ 1229 if (sc->re_ldata.re_tx_mtag) { 1230 for (i = 0; i < tx_cnt; i++) { 1231 bus_dmamap_destroy(sc->re_ldata.re_tx_mtag, 1232 sc->re_ldata.re_tx_dmamap[i]); 1233 } 1234 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag); 1235 sc->re_ldata.re_tx_mtag = NULL; 1236 } 1237 1238 if (sc->re_ldata.re_rx_mtag) { 1239 for (i = 0; i < rx_cnt; i++) { 1240 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1241 sc->re_ldata.re_rx_dmamap[i]); 1242 } 1243 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1244 sc->re_ldata.re_rx_spare); 1245 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1246 sc->re_ldata.re_rx_mtag = NULL; 1247 } 1248 } 1249 1250 static void 1251 re_freemem(device_t dev) 1252 { 1253 struct re_softc *sc = device_get_softc(dev); 1254 1255 /* Unload and free the RX DMA ring memory and map */ 1256 if (sc->re_ldata.re_rx_list_tag) { 1257 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1258 sc->re_ldata.re_rx_list_map); 1259 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1260 sc->re_ldata.re_rx_list, 1261 sc->re_ldata.re_rx_list_map); 1262 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1263 } 1264 1265 /* Unload and free the TX DMA ring memory and map */ 1266 if (sc->re_ldata.re_tx_list_tag) { 1267 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1268 sc->re_ldata.re_tx_list_map); 1269 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1270 sc->re_ldata.re_tx_list, 1271 sc->re_ldata.re_tx_list_map); 1272 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1273 } 1274 1275 /* Free RX/TX buf DMA stuffs */ 1276 re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt); 1277 1278 /* Unload and free the stats buffer and map */ 1279 if (sc->re_ldata.re_stag) { 1280 bus_dmamap_unload(sc->re_ldata.re_stag, sc->re_ldata.re_smap); 1281 bus_dmamem_free(sc->re_ldata.re_stag, 1282 sc->re_ldata.re_stats, 1283 sc->re_ldata.re_smap); 1284 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1285 } 1286 1287 if (sc->re_caps & RE_C_CONTIGRX) 1288 re_jpool_free(sc); 1289 1290 if (sc->re_parent_tag) 1291 bus_dma_tag_destroy(sc->re_parent_tag); 1292 1293 if (sc->re_ldata.re_tx_mbuf != NULL) 1294 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF); 1295 if (sc->re_ldata.re_rx_mbuf != NULL) 1296 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF); 1297 if (sc->re_ldata.re_rx_paddr != NULL) 1298 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF); 1299 if (sc->re_ldata.re_tx_dmamap != NULL) 1300 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF); 1301 if (sc->re_ldata.re_rx_dmamap != NULL) 1302 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF); 1303 } 1304 1305 /* 1306 * Attach the interface. Allocate softc structures, do ifmedia 1307 * setup and ethernet/BPF attach. 1308 */ 1309 static int 1310 re_attach(device_t dev) 1311 { 1312 struct re_softc *sc = device_get_softc(dev); 1313 struct ifnet *ifp; 1314 uint8_t eaddr[ETHER_ADDR_LEN]; 1315 int error = 0, qlen, msi_enable; 1316 u_int irq_flags; 1317 1318 callout_init(&sc->re_timer); 1319 sc->re_dev = dev; 1320 1321 if (RE_IS_8139CP(sc)) { 1322 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP; 1323 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP; 1324 } else { 1325 sc->re_rx_desc_cnt = re_rx_desc_count; 1326 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX) 1327 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX; 1328 1329 sc->re_tx_desc_cnt = re_tx_desc_count; 1330 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX) 1331 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX; 1332 } 1333 1334 qlen = RE_IFQ_MAXLEN; 1335 if (sc->re_tx_desc_cnt > qlen) 1336 qlen = sc->re_tx_desc_cnt; 1337 1338 sc->re_rxbuf_size = MCLBYTES; 1339 sc->re_newbuf = re_newbuf_std; 1340 1341 sc->re_tx_time = 5; /* 125us */ 1342 sc->re_rx_time = 2; /* 50us */ 1343 if (sc->re_caps & RE_C_PCIE) 1344 sc->re_sim_time = 75; /* 75us */ 1345 else 1346 sc->re_sim_time = 125; /* 125us */ 1347 if (!RE_IS_8139CP(sc)) { 1348 /* simulated interrupt moderation */ 1349 sc->re_imtype = RE_IMTYPE_SIM; 1350 } else { 1351 sc->re_imtype = RE_IMTYPE_NONE; 1352 } 1353 re_config_imtype(sc, sc->re_imtype); 1354 1355 sysctl_ctx_init(&sc->re_sysctl_ctx); 1356 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx, 1357 SYSCTL_STATIC_CHILDREN(_hw), 1358 OID_AUTO, 1359 device_get_nameunit(dev), 1360 CTLFLAG_RD, 0, ""); 1361 if (sc->re_sysctl_tree == NULL) { 1362 device_printf(dev, "can't add sysctl node\n"); 1363 error = ENXIO; 1364 goto fail; 1365 } 1366 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1367 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1368 "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt, 1369 0, "RX desc count"); 1370 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1371 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1372 "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt, 1373 0, "TX desc count"); 1374 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1375 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1376 OID_AUTO, "sim_time", 1377 CTLTYPE_INT | CTLFLAG_RW, 1378 sc, 0, re_sysctl_simtime, "I", 1379 "Simulated interrupt moderation time (usec)."); 1380 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1381 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1382 OID_AUTO, "imtype", 1383 CTLTYPE_INT | CTLFLAG_RW, 1384 sc, 0, re_sysctl_imtype, "I", 1385 "Interrupt moderation type -- " 1386 "0:disable, 1:simulated, " 1387 "2:hardware(if supported)"); 1388 if (sc->re_caps & RE_C_HWIM) { 1389 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1390 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1391 OID_AUTO, "hw_rxtime", 1392 CTLTYPE_INT | CTLFLAG_RW, 1393 sc, 0, re_sysctl_rxtime, "I", 1394 "Hardware interrupt moderation time " 1395 "(unit: 25usec)."); 1396 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1397 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1398 OID_AUTO, "hw_txtime", 1399 CTLTYPE_INT | CTLFLAG_RW, 1400 sc, 0, re_sysctl_txtime, "I", 1401 "Hardware interrupt moderation time " 1402 "(unit: 25usec)."); 1403 } 1404 1405 #ifndef BURN_BRIDGES 1406 /* 1407 * Handle power management nonsense. 1408 */ 1409 1410 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1411 uint32_t membase, irq; 1412 1413 /* Save important PCI config data. */ 1414 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1415 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1416 1417 /* Reset the power state. */ 1418 device_printf(dev, "chip is in D%d power mode " 1419 "-- setting to D0\n", pci_get_powerstate(dev)); 1420 1421 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1422 1423 /* Restore PCI config data. */ 1424 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1425 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1426 } 1427 #endif 1428 /* 1429 * Map control/status registers. 1430 */ 1431 pci_enable_busmaster(dev); 1432 1433 if (pci_is_pcie(dev)) { 1434 sc->re_res_rid = PCIR_BAR(2); 1435 sc->re_res_type = SYS_RES_MEMORY; 1436 } else { 1437 sc->re_res_rid = PCIR_BAR(0); 1438 sc->re_res_type = SYS_RES_IOPORT; 1439 } 1440 sc->re_res = bus_alloc_resource_any(dev, sc->re_res_type, 1441 &sc->re_res_rid, RF_ACTIVE); 1442 if (sc->re_res == NULL) { 1443 device_printf(dev, "couldn't map IO\n"); 1444 error = ENXIO; 1445 goto fail; 1446 } 1447 1448 sc->re_btag = rman_get_bustag(sc->re_res); 1449 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1450 1451 /* 1452 * Allocate interrupt 1453 */ 1454 if (pci_is_pcie(dev)) 1455 msi_enable = re_msi_enable; 1456 else 1457 msi_enable = 0; 1458 sc->re_irq_type = pci_alloc_1intr(dev, msi_enable, 1459 &sc->re_irq_rid, &irq_flags); 1460 1461 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->re_irq_rid, 1462 irq_flags); 1463 if (sc->re_irq == NULL) { 1464 device_printf(dev, "couldn't map interrupt\n"); 1465 error = ENXIO; 1466 goto fail; 1467 } 1468 1469 /* Reset the adapter. */ 1470 re_reset(sc, 0); 1471 1472 if (RE_IS_8139CP(sc)) { 1473 sc->re_bus_speed = 33; /* XXX */ 1474 } else if (sc->re_caps & RE_C_PCIE) { 1475 sc->re_bus_speed = 125; 1476 } else { 1477 uint8_t cfg2; 1478 1479 cfg2 = CSR_READ_1(sc, RE_CFG2); 1480 switch (cfg2 & RE_CFG2_PCICLK_MASK) { 1481 case RE_CFG2_PCICLK_33MHZ: 1482 sc->re_bus_speed = 33; 1483 break; 1484 case RE_CFG2_PCICLK_66MHZ: 1485 sc->re_bus_speed = 66; 1486 break; 1487 default: 1488 device_printf(dev, "unknown bus speed, assume 33MHz\n"); 1489 sc->re_bus_speed = 33; 1490 break; 1491 } 1492 if (cfg2 & RE_CFG2_PCI64) 1493 sc->re_caps |= RE_C_PCI64; 1494 } 1495 device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; " 1496 "PCI%s %dMHz\n", 1497 sc->re_hwrev, sc->re_macver, 1498 (sc->re_caps & RE_C_PCIE) ? 1499 "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"), 1500 sc->re_bus_speed); 1501 1502 /* 1503 * NOTE: 1504 * DO NOT try to adjust config1 and config5 which was spotted in 1505 * Realtek's Linux drivers. It will _permanently_ damage certain 1506 * cards EEPROM, e.g. one of my 8168B (0x38000000) card ... 1507 */ 1508 1509 re_get_eaddr(sc, eaddr); 1510 1511 if (!RE_IS_8139CP(sc)) { 1512 /* Set RX length mask */ 1513 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1514 sc->re_txstart = RE_GTXSTART; 1515 } else { 1516 /* Set RX length mask */ 1517 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1518 sc->re_txstart = RE_TXSTART; 1519 } 1520 1521 /* Allocate DMA stuffs */ 1522 error = re_allocmem(dev); 1523 if (error) 1524 goto fail; 1525 1526 /* 1527 * Apply some magic PCI settings from Realtek ... 1528 */ 1529 if (RE_IS_8169(sc)) { 1530 CSR_WRITE_1(sc, 0x82, 1); 1531 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1); 1532 } 1533 pci_write_config(dev, PCIR_LATTIMER, 0x40, 1); 1534 1535 if (sc->re_caps & RE_C_MAC2) { 1536 /* 1537 * Following part is extracted from Realtek BSD driver v176. 1538 * However, this does _not_ make much/any sense: 1539 * 8168C's PCI Express device control is located at 0x78, 1540 * so the reading from 0x79 (higher part of 0x78) and setting 1541 * the 4~6bits intend to enlarge the "max read request size" 1542 * (we will do it). The content of the rest part of this 1543 * register is not meaningful to other PCI registers, so 1544 * writing the value to 0x54 could be completely wrong. 1545 * 0x80 is the lower part of PCI Express device status, non- 1546 * reserved bits are RW1C, writing 0 to them will not have 1547 * any effect at all. 1548 */ 1549 #ifdef foo 1550 uint8_t val; 1551 1552 val = pci_read_config(dev, 0x79, 1); 1553 val = (val & ~0x70) | 0x50; 1554 pci_write_config(dev, 0x54, val, 1); 1555 pci_write_config(dev, 0x80, 0, 1); 1556 #endif 1557 } 1558 1559 /* 1560 * Apply some PHY fixup from Realtek ... 1561 */ 1562 if (sc->re_hwrev == RE_HWREV_8110S) { 1563 CSR_WRITE_1(sc, 0x82, 1); 1564 re_miibus_writereg(dev, 1, 0xb, 0); 1565 } 1566 if (sc->re_caps & RE_C_PHYPMGT) { 1567 /* Power up PHY */ 1568 re_miibus_writereg(dev, 1, 0x1f, 0); 1569 re_miibus_writereg(dev, 1, 0xe, 0); 1570 } 1571 1572 /* Do MII setup */ 1573 if (mii_phy_probe(dev, &sc->re_miibus, 1574 re_ifmedia_upd, re_ifmedia_sts)) { 1575 device_printf(dev, "MII without any phy!\n"); 1576 error = ENXIO; 1577 goto fail; 1578 } 1579 1580 ifp = &sc->arpcom.ac_if; 1581 ifp->if_softc = sc; 1582 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1583 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1584 ifp->if_ioctl = re_ioctl; 1585 ifp->if_start = re_start; 1586 #ifdef IFPOLL_ENABLE 1587 ifp->if_npoll = re_npoll; 1588 #endif 1589 ifp->if_watchdog = re_watchdog; 1590 ifp->if_init = re_init; 1591 if (!RE_IS_8139CP(sc)) /* XXX */ 1592 ifp->if_baudrate = 1000000000; 1593 else 1594 ifp->if_baudrate = 100000000; 1595 ifq_set_maxlen(&ifp->if_snd, qlen); 1596 ifq_set_ready(&ifp->if_snd); 1597 1598 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1599 if (sc->re_caps & RE_C_HWCSUM) 1600 ifp->if_capabilities |= IFCAP_HWCSUM; 1601 1602 ifp->if_capenable = ifp->if_capabilities; 1603 if (ifp->if_capabilities & IFCAP_HWCSUM) { 1604 /* 1605 * RTL8168/8111C generates wrong IP checksummed frame if the 1606 * packet has IP options so disable TX IP checksum offloading. 1607 */ 1608 if (sc->re_hwrev == RE_HWREV_8168CP || 1609 sc->re_hwrev == RE_HWREV_8168C) 1610 sc->re_hwassist = CSUM_TCP | CSUM_UDP; 1611 else 1612 sc->re_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1613 } 1614 ifp->if_hwassist = sc->re_hwassist; 1615 1616 /* 1617 * Call MI attach routine. 1618 */ 1619 ether_ifattach(ifp, eaddr, NULL); 1620 1621 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->re_irq)); 1622 1623 #ifdef IFPOLL_ENABLE 1624 ifpoll_compat_setup(&sc->re_npoll, 1625 &sc->re_sysctl_ctx, sc->re_sysctl_tree, device_get_unit(dev), 1626 ifp->if_serializer); 1627 #endif 1628 1629 #ifdef RE_DIAG 1630 /* 1631 * Perform hardware diagnostic on the original RTL8169. 1632 * Some 32-bit cards were incorrectly wired and would 1633 * malfunction if plugged into a 64-bit slot. 1634 */ 1635 if (sc->re_hwrev == RE_HWREV_8169) { 1636 lwkt_serialize_enter(ifp->if_serializer); 1637 error = re_diag(sc); 1638 lwkt_serialize_exit(ifp->if_serializer); 1639 1640 if (error) { 1641 device_printf(dev, "hardware diagnostic failure\n"); 1642 ether_ifdetach(ifp); 1643 goto fail; 1644 } 1645 } 1646 #endif /* RE_DIAG */ 1647 1648 /* Hook interrupt last to avoid having to lock softc */ 1649 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc, 1650 &sc->re_intrhand, ifp->if_serializer); 1651 1652 if (error) { 1653 device_printf(dev, "couldn't set up irq\n"); 1654 ether_ifdetach(ifp); 1655 goto fail; 1656 } 1657 1658 fail: 1659 if (error) 1660 re_detach(dev); 1661 1662 return (error); 1663 } 1664 1665 /* 1666 * Shutdown hardware and free up resources. This can be called any 1667 * time after the mutex has been initialized. It is called in both 1668 * the error case in attach and the normal detach case so it needs 1669 * to be careful about only freeing resources that have actually been 1670 * allocated. 1671 */ 1672 static int 1673 re_detach(device_t dev) 1674 { 1675 struct re_softc *sc = device_get_softc(dev); 1676 struct ifnet *ifp = &sc->arpcom.ac_if; 1677 1678 /* These should only be active if attach succeeded */ 1679 if (device_is_attached(dev)) { 1680 lwkt_serialize_enter(ifp->if_serializer); 1681 re_stop(sc); 1682 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1683 lwkt_serialize_exit(ifp->if_serializer); 1684 1685 ether_ifdetach(ifp); 1686 } 1687 if (sc->re_miibus) 1688 device_delete_child(dev, sc->re_miibus); 1689 bus_generic_detach(dev); 1690 1691 if (sc->re_sysctl_tree != NULL) 1692 sysctl_ctx_free(&sc->re_sysctl_ctx); 1693 1694 if (sc->re_irq) 1695 bus_release_resource(dev, SYS_RES_IRQ, sc->re_irq_rid, 1696 sc->re_irq); 1697 1698 if (sc->re_irq_type == PCI_INTR_TYPE_MSI) 1699 pci_release_msi(dev); 1700 1701 if (sc->re_res) { 1702 bus_release_resource(dev, sc->re_res_type, sc->re_res_rid, 1703 sc->re_res); 1704 } 1705 1706 /* Free DMA stuffs */ 1707 re_freemem(dev); 1708 1709 return(0); 1710 } 1711 1712 static void 1713 re_setup_rxdesc(struct re_softc *sc, int idx) 1714 { 1715 bus_addr_t paddr; 1716 uint32_t cmdstat; 1717 struct re_desc *d; 1718 1719 paddr = sc->re_ldata.re_rx_paddr[idx]; 1720 d = &sc->re_ldata.re_rx_list[idx]; 1721 1722 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr)); 1723 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr)); 1724 1725 cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN; 1726 if (idx == (sc->re_rx_desc_cnt - 1)) 1727 cmdstat |= RE_RDESC_CMD_EOR; 1728 d->re_cmdstat = htole32(cmdstat); 1729 } 1730 1731 static int 1732 re_newbuf_std(struct re_softc *sc, int idx, int init) 1733 { 1734 bus_dma_segment_t seg; 1735 bus_dmamap_t map; 1736 struct mbuf *m; 1737 int error, nsegs; 1738 1739 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1740 if (m == NULL) { 1741 error = ENOBUFS; 1742 1743 if (init) { 1744 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n"); 1745 return error; 1746 } else { 1747 goto back; 1748 } 1749 } 1750 m->m_len = m->m_pkthdr.len = MCLBYTES; 1751 1752 /* 1753 * NOTE: 1754 * re(4) chips need address of the receive buffer to be 8-byte 1755 * aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1756 */ 1757 1758 error = bus_dmamap_load_mbuf_segment(sc->re_ldata.re_rx_mtag, 1759 sc->re_ldata.re_rx_spare, m, 1760 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 1761 if (error) { 1762 m_freem(m); 1763 if (init) { 1764 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 1765 return error; 1766 } else { 1767 goto back; 1768 } 1769 } 1770 1771 if (!init) { 1772 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, 1773 sc->re_ldata.re_rx_dmamap[idx], 1774 BUS_DMASYNC_POSTREAD); 1775 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 1776 sc->re_ldata.re_rx_dmamap[idx]); 1777 } 1778 sc->re_ldata.re_rx_mbuf[idx] = m; 1779 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr; 1780 1781 map = sc->re_ldata.re_rx_dmamap[idx]; 1782 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare; 1783 sc->re_ldata.re_rx_spare = map; 1784 back: 1785 re_setup_rxdesc(sc, idx); 1786 return error; 1787 } 1788 1789 static int 1790 re_newbuf_jumbo(struct re_softc *sc, int idx, int init) 1791 { 1792 struct mbuf *m; 1793 struct re_jbuf *jbuf; 1794 int error = 0; 1795 1796 MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA); 1797 if (m == NULL) { 1798 error = ENOBUFS; 1799 if (init) { 1800 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n"); 1801 return error; 1802 } else { 1803 goto back; 1804 } 1805 } 1806 1807 jbuf = re_jbuf_alloc(sc); 1808 if (jbuf == NULL) { 1809 m_freem(m); 1810 1811 error = ENOBUFS; 1812 if (init) { 1813 if_printf(&sc->arpcom.ac_if, "jpool is empty\n"); 1814 return error; 1815 } else { 1816 goto back; 1817 } 1818 } 1819 1820 m->m_ext.ext_arg = jbuf; 1821 m->m_ext.ext_buf = jbuf->re_buf; 1822 m->m_ext.ext_free = re_jbuf_free; 1823 m->m_ext.ext_ref = re_jbuf_ref; 1824 m->m_ext.ext_size = sc->re_rxbuf_size; 1825 1826 m->m_data = m->m_ext.ext_buf; 1827 m->m_flags |= M_EXT; 1828 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1829 1830 /* 1831 * NOTE: 1832 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer 1833 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1834 */ 1835 1836 sc->re_ldata.re_rx_mbuf[idx] = m; 1837 sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr; 1838 back: 1839 re_setup_rxdesc(sc, idx); 1840 return error; 1841 } 1842 1843 static int 1844 re_tx_list_init(struct re_softc *sc) 1845 { 1846 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 1847 1848 sc->re_ldata.re_tx_prodidx = 0; 1849 sc->re_ldata.re_tx_considx = 0; 1850 sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt; 1851 1852 return(0); 1853 } 1854 1855 static int 1856 re_rx_list_init(struct re_softc *sc) 1857 { 1858 int i, error; 1859 1860 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc)); 1861 1862 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1863 error = sc->re_newbuf(sc, i, 1); 1864 if (error) 1865 return(error); 1866 } 1867 1868 sc->re_ldata.re_rx_prodidx = 0; 1869 sc->re_head = sc->re_tail = NULL; 1870 1871 return(0); 1872 } 1873 1874 #define RE_IP4_PACKET 0x1 1875 #define RE_TCP_PACKET 0x2 1876 #define RE_UDP_PACKET 0x4 1877 1878 static __inline uint8_t 1879 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl) 1880 { 1881 uint8_t packet_type = 0; 1882 1883 if (sc->re_caps & RE_C_MAC2) { 1884 if (rxctrl & RE_RDESC_CTL_PROTOIP4) 1885 packet_type |= RE_IP4_PACKET; 1886 } else { 1887 if (rxstat & RE_RDESC_STAT_PROTOID) 1888 packet_type |= RE_IP4_PACKET; 1889 } 1890 if (RE_TCPPKT(rxstat)) 1891 packet_type |= RE_TCP_PACKET; 1892 else if (RE_UDPPKT(rxstat)) 1893 packet_type |= RE_UDP_PACKET; 1894 return packet_type; 1895 } 1896 1897 /* 1898 * RX handler for C+ and 8169. For the gigE chips, we support 1899 * the reception of jumbo frames that have been fragmented 1900 * across multiple 2K mbuf cluster buffers. 1901 */ 1902 static int 1903 re_rxeof(struct re_softc *sc) 1904 { 1905 struct ifnet *ifp = &sc->arpcom.ac_if; 1906 struct mbuf *m; 1907 struct re_desc *cur_rx; 1908 uint32_t rxstat, rxctrl; 1909 int i, total_len, rx = 0; 1910 1911 for (i = sc->re_ldata.re_rx_prodidx; 1912 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) { 1913 cur_rx = &sc->re_ldata.re_rx_list[i]; 1914 m = sc->re_ldata.re_rx_mbuf[i]; 1915 total_len = RE_RXBYTES(cur_rx); 1916 rxstat = le32toh(cur_rx->re_cmdstat); 1917 rxctrl = le32toh(cur_rx->re_control); 1918 1919 rx = 1; 1920 1921 #ifdef INVARIANTS 1922 if (sc->re_flags & RE_F_USE_JPOOL) 1923 KKASSERT(rxstat & RE_RDESC_STAT_EOF); 1924 #endif 1925 1926 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1927 if (sc->re_flags & RE_F_DROP_RXFRAG) { 1928 re_setup_rxdesc(sc, i); 1929 continue; 1930 } 1931 1932 if (sc->re_newbuf(sc, i, 0)) { 1933 /* Drop upcoming fragments */ 1934 sc->re_flags |= RE_F_DROP_RXFRAG; 1935 continue; 1936 } 1937 1938 m->m_len = MCLBYTES; 1939 if (sc->re_head == NULL) { 1940 sc->re_head = sc->re_tail = m; 1941 } else { 1942 sc->re_tail->m_next = m; 1943 sc->re_tail = m; 1944 } 1945 continue; 1946 } else if (sc->re_flags & RE_F_DROP_RXFRAG) { 1947 /* 1948 * Last fragment of a multi-fragment packet. 1949 * 1950 * Since error already happened, this fragment 1951 * must be dropped as well as the fragment chain. 1952 */ 1953 re_setup_rxdesc(sc, i); 1954 re_free_rxchain(sc); 1955 sc->re_flags &= ~RE_F_DROP_RXFRAG; 1956 continue; 1957 } 1958 1959 /* 1960 * NOTE: for the 8139C+, the frame length field 1961 * is always 12 bits in size, but for the gigE chips, 1962 * it is 13 bits (since the max RX frame length is 16K). 1963 * Unfortunately, all 32 bits in the status word 1964 * were already used, so to make room for the extra 1965 * length bit, RealTek took out the 'frame alignment 1966 * error' bit and shifted the other status bits 1967 * over one slot. The OWN, EOR, FS and LS bits are 1968 * still in the same places. We have already extracted 1969 * the frame length and checked the OWN bit, so rather 1970 * than using an alternate bit mapping, we shift the 1971 * status bits one space to the right so we can evaluate 1972 * them using the 8169 status as though it was in the 1973 * same format as that of the 8139C+. 1974 */ 1975 if (!RE_IS_8139CP(sc)) 1976 rxstat >>= 1; 1977 1978 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 1979 IFNET_STAT_INC(ifp, ierrors, 1); 1980 /* 1981 * If this is part of a multi-fragment packet, 1982 * discard all the pieces. 1983 */ 1984 re_free_rxchain(sc); 1985 re_setup_rxdesc(sc, i); 1986 continue; 1987 } 1988 1989 /* 1990 * If allocating a replacement mbuf fails, 1991 * reload the current one. 1992 */ 1993 1994 if (sc->re_newbuf(sc, i, 0)) { 1995 IFNET_STAT_INC(ifp, ierrors, 1); 1996 continue; 1997 } 1998 1999 if (sc->re_head != NULL) { 2000 m->m_len = total_len % MCLBYTES; 2001 /* 2002 * Special case: if there's 4 bytes or less 2003 * in this buffer, the mbuf can be discarded: 2004 * the last 4 bytes is the CRC, which we don't 2005 * care about anyway. 2006 */ 2007 if (m->m_len <= ETHER_CRC_LEN) { 2008 sc->re_tail->m_len -= 2009 (ETHER_CRC_LEN - m->m_len); 2010 m_freem(m); 2011 } else { 2012 m->m_len -= ETHER_CRC_LEN; 2013 sc->re_tail->m_next = m; 2014 } 2015 m = sc->re_head; 2016 sc->re_head = sc->re_tail = NULL; 2017 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2018 } else { 2019 m->m_pkthdr.len = m->m_len = 2020 (total_len - ETHER_CRC_LEN); 2021 } 2022 2023 IFNET_STAT_INC(ifp, ipackets, 1); 2024 m->m_pkthdr.rcvif = ifp; 2025 2026 /* Do RX checksumming if enabled */ 2027 2028 if (ifp->if_capenable & IFCAP_RXCSUM) { 2029 uint8_t packet_type; 2030 2031 packet_type = re_packet_type(sc, rxstat, rxctrl); 2032 2033 /* Check IP header checksum */ 2034 if (packet_type & RE_IP4_PACKET) { 2035 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2036 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 2037 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2038 } 2039 2040 /* Check TCP/UDP checksum */ 2041 if (((packet_type & RE_TCP_PACKET) && 2042 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 2043 ((packet_type & RE_UDP_PACKET) && 2044 (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) { 2045 m->m_pkthdr.csum_flags |= 2046 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 2047 CSUM_FRAG_NOT_CHECKED; 2048 m->m_pkthdr.csum_data = 0xffff; 2049 } 2050 } 2051 2052 if (rxctrl & RE_RDESC_CTL_HASTAG) { 2053 m->m_flags |= M_VLANTAG; 2054 m->m_pkthdr.ether_vlantag = 2055 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA)); 2056 } 2057 ifp->if_input(ifp, m); 2058 } 2059 2060 sc->re_ldata.re_rx_prodidx = i; 2061 2062 return rx; 2063 } 2064 2065 #undef RE_IP4_PACKET 2066 #undef RE_TCP_PACKET 2067 #undef RE_UDP_PACKET 2068 2069 static int 2070 re_tx_collect(struct re_softc *sc) 2071 { 2072 struct ifnet *ifp = &sc->arpcom.ac_if; 2073 uint32_t txstat; 2074 int idx, tx = 0; 2075 2076 for (idx = sc->re_ldata.re_tx_considx; 2077 sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt; 2078 RE_TXDESC_INC(sc, idx)) { 2079 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 2080 if (txstat & RE_TDESC_CMD_OWN) 2081 break; 2082 2083 tx = 1; 2084 2085 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0; 2086 2087 /* 2088 * We only stash mbufs in the last descriptor 2089 * in a fragment chain, which also happens to 2090 * be the only place where the TX status bits 2091 * are valid. 2092 */ 2093 if (txstat & RE_TDESC_CMD_EOF) { 2094 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2095 sc->re_ldata.re_tx_dmamap[idx]); 2096 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 2097 sc->re_ldata.re_tx_mbuf[idx] = NULL; 2098 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 2099 RE_TDESC_STAT_COLCNT)) 2100 IFNET_STAT_INC(ifp, collisions, 1); 2101 if (txstat & RE_TDESC_STAT_TXERRSUM) 2102 IFNET_STAT_INC(ifp, oerrors, 1); 2103 else 2104 IFNET_STAT_INC(ifp, opackets, 1); 2105 } 2106 sc->re_ldata.re_tx_free++; 2107 } 2108 sc->re_ldata.re_tx_considx = idx; 2109 2110 return tx; 2111 } 2112 2113 static int 2114 re_txeof(struct re_softc *sc) 2115 { 2116 struct ifnet *ifp = &sc->arpcom.ac_if; 2117 int tx; 2118 2119 tx = re_tx_collect(sc); 2120 2121 /* There is enough free TX descs */ 2122 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE) 2123 ifq_clr_oactive(&ifp->if_snd); 2124 2125 /* 2126 * Some chips will ignore a second TX request issued while an 2127 * existing transmission is in progress. If the transmitter goes 2128 * idle but there are still packets waiting to be sent, we need 2129 * to restart the channel here to flush them out. This only seems 2130 * to be required with the PCIe devices. 2131 */ 2132 if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt) 2133 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2134 else 2135 ifp->if_timer = 0; 2136 2137 return tx; 2138 } 2139 2140 static void 2141 re_tick(void *xsc) 2142 { 2143 struct re_softc *sc = xsc; 2144 2145 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2146 re_tick_serialized(xsc); 2147 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2148 } 2149 2150 static void 2151 re_tick_serialized(void *xsc) 2152 { 2153 struct re_softc *sc = xsc; 2154 struct ifnet *ifp = &sc->arpcom.ac_if; 2155 struct mii_data *mii; 2156 2157 ASSERT_SERIALIZED(ifp->if_serializer); 2158 2159 mii = device_get_softc(sc->re_miibus); 2160 mii_tick(mii); 2161 if (sc->re_flags & RE_F_LINKED) { 2162 if (!(mii->mii_media_status & IFM_ACTIVE)) 2163 sc->re_flags &= ~RE_F_LINKED; 2164 } else { 2165 if (mii->mii_media_status & IFM_ACTIVE && 2166 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2167 sc->re_flags |= RE_F_LINKED; 2168 if (!ifq_is_empty(&ifp->if_snd)) 2169 if_devstart(ifp); 2170 } 2171 } 2172 2173 callout_reset(&sc->re_timer, hz, re_tick, sc); 2174 } 2175 2176 #ifdef IFPOLL_ENABLE 2177 2178 static void 2179 re_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 2180 { 2181 struct re_softc *sc = ifp->if_softc; 2182 2183 ASSERT_SERIALIZED(ifp->if_serializer); 2184 2185 if (sc->re_npoll.ifpc_stcount-- == 0) { 2186 uint16_t status; 2187 2188 sc->re_npoll.ifpc_stcount = sc->re_npoll.ifpc_stfrac; 2189 2190 status = CSR_READ_2(sc, RE_ISR); 2191 if (status == 0xffff) 2192 return; 2193 if (status) 2194 CSR_WRITE_2(sc, RE_ISR, status); 2195 2196 /* 2197 * XXX check behaviour on receiver stalls. 2198 */ 2199 2200 if (status & RE_ISR_SYSTEM_ERR) 2201 re_init(sc); 2202 } 2203 2204 sc->rxcycles = count; 2205 re_rxeof(sc); 2206 re_txeof(sc); 2207 2208 if (!ifq_is_empty(&ifp->if_snd)) 2209 if_devstart(ifp); 2210 } 2211 2212 static void 2213 re_npoll(struct ifnet *ifp, struct ifpoll_info *info) 2214 { 2215 struct re_softc *sc = ifp->if_softc; 2216 2217 ASSERT_SERIALIZED(ifp->if_serializer); 2218 2219 if (info != NULL) { 2220 int cpuid = sc->re_npoll.ifpc_cpuid; 2221 2222 info->ifpi_rx[cpuid].poll_func = re_npoll_compat; 2223 info->ifpi_rx[cpuid].arg = NULL; 2224 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 2225 2226 if (ifp->if_flags & IFF_RUNNING) 2227 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2228 ifq_set_cpuid(&ifp->if_snd, cpuid); 2229 } else { 2230 if (ifp->if_flags & IFF_RUNNING) 2231 re_setup_intr(sc, 1, sc->re_imtype); 2232 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->re_irq)); 2233 } 2234 } 2235 #endif /* IFPOLL_ENABLE */ 2236 2237 static void 2238 re_intr(void *arg) 2239 { 2240 struct re_softc *sc = arg; 2241 struct ifnet *ifp = &sc->arpcom.ac_if; 2242 uint16_t status; 2243 int rx, tx; 2244 2245 ASSERT_SERIALIZED(ifp->if_serializer); 2246 2247 if ((sc->re_flags & RE_F_SUSPENDED) || 2248 (ifp->if_flags & IFF_RUNNING) == 0) 2249 return; 2250 2251 rx = tx = 0; 2252 2253 status = CSR_READ_2(sc, RE_ISR); 2254 /* If the card has gone away the read returns 0xffff. */ 2255 if (status == 0xffff) 2256 goto reload; 2257 if (status) 2258 CSR_WRITE_2(sc, RE_ISR, status); 2259 2260 if ((status & sc->re_intrs) == 0) 2261 goto reload; 2262 2263 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR)) 2264 rx |= re_rxeof(sc); 2265 2266 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR)) 2267 tx |= re_txeof(sc); 2268 2269 if (status & RE_ISR_SYSTEM_ERR) 2270 re_init(sc); 2271 2272 if (status & RE_ISR_LINKCHG) { 2273 callout_stop(&sc->re_timer); 2274 re_tick_serialized(sc); 2275 } 2276 2277 reload: 2278 if (sc->re_imtype == RE_IMTYPE_SIM) { 2279 if ((sc->re_flags & RE_F_TIMER_INTR)) { 2280 if ((tx | rx) == 0) { 2281 /* 2282 * Nothing needs to be processed, fallback 2283 * to use TX/RX interrupts. 2284 */ 2285 re_setup_intr(sc, 1, RE_IMTYPE_NONE); 2286 2287 /* 2288 * Recollect, mainly to avoid the possible 2289 * race introduced by changing interrupt 2290 * masks. 2291 */ 2292 re_rxeof(sc); 2293 tx = re_txeof(sc); 2294 } else { 2295 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 2296 } 2297 } else if (tx | rx) { 2298 /* 2299 * Assume that using simulated interrupt moderation 2300 * (hardware timer based) could reduce the interript 2301 * rate. 2302 */ 2303 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 2304 } 2305 } 2306 2307 if (tx && !ifq_is_empty(&ifp->if_snd)) 2308 if_devstart(ifp); 2309 } 2310 2311 static int 2312 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0) 2313 { 2314 struct mbuf *m = *m_head; 2315 bus_dma_segment_t segs[RE_MAXSEGS]; 2316 bus_dmamap_t map; 2317 int error, maxsegs, idx, i, nsegs; 2318 struct re_desc *d, *tx_ring; 2319 uint32_t cmd_csum, ctl_csum, vlantag; 2320 2321 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE, 2322 ("not enough free TX desc")); 2323 2324 map = sc->re_ldata.re_tx_dmamap[*idx0]; 2325 2326 /* 2327 * Set up checksum offload. Note: checksum offload bits must 2328 * appear in all descriptors of a multi-descriptor transmit 2329 * attempt. (This is according to testing done with an 8169 2330 * chip. I'm not sure if this is a requirement or a bug.) 2331 */ 2332 cmd_csum = ctl_csum = 0; 2333 if (m->m_pkthdr.csum_flags & CSUM_IP) { 2334 cmd_csum |= RE_TDESC_CMD_IPCSUM; 2335 ctl_csum |= RE_TDESC_CTL_IPCSUM; 2336 } 2337 if (m->m_pkthdr.csum_flags & CSUM_TCP) { 2338 cmd_csum |= RE_TDESC_CMD_TCPCSUM; 2339 ctl_csum |= RE_TDESC_CTL_TCPCSUM; 2340 } 2341 if (m->m_pkthdr.csum_flags & CSUM_UDP) { 2342 cmd_csum |= RE_TDESC_CMD_UDPCSUM; 2343 ctl_csum |= RE_TDESC_CTL_UDPCSUM; 2344 } 2345 2346 /* For MAC2 chips, csum flags are set on re_control */ 2347 if (sc->re_caps & RE_C_MAC2) 2348 cmd_csum = 0; 2349 else 2350 ctl_csum = 0; 2351 2352 if ((sc->re_caps & RE_C_AUTOPAD) == 0) { 2353 /* 2354 * With some of the RealTek chips, using the checksum offload 2355 * support in conjunction with the autopadding feature results 2356 * in the transmission of corrupt frames. For example, if we 2357 * need to send a really small IP fragment that's less than 60 2358 * bytes in size, and IP header checksumming is enabled, the 2359 * resulting ethernet frame that appears on the wire will 2360 * have garbled payload. To work around this, if TX checksum 2361 * offload is enabled, we always manually pad short frames out 2362 * to the minimum ethernet frame size. 2363 * 2364 * Note: this appears unnecessary for TCP, and doing it for TCP 2365 * with PCIe adapters seems to result in bad checksums. 2366 */ 2367 if ((m->m_pkthdr.csum_flags & 2368 (CSUM_DELAY_IP | CSUM_DELAY_DATA)) && 2369 (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 && 2370 m->m_pkthdr.len < RE_MIN_FRAMELEN) { 2371 error = m_devpad(m, RE_MIN_FRAMELEN); 2372 if (error) 2373 goto back; 2374 } 2375 } 2376 2377 vlantag = 0; 2378 if (m->m_flags & M_VLANTAG) { 2379 vlantag = htobe16(m->m_pkthdr.ether_vlantag) | 2380 RE_TDESC_CTL_INSTAG; 2381 } 2382 2383 maxsegs = sc->re_ldata.re_tx_free; 2384 if (maxsegs > RE_MAXSEGS) 2385 maxsegs = RE_MAXSEGS; 2386 2387 error = bus_dmamap_load_mbuf_defrag(sc->re_ldata.re_tx_mtag, map, 2388 m_head, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 2389 if (error) 2390 goto back; 2391 2392 m = *m_head; 2393 bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE); 2394 2395 /* 2396 * Map the segment array into descriptors. We also keep track 2397 * of the end of the ring and set the end-of-ring bits as needed, 2398 * and we set the ownership bits in all except the very first 2399 * descriptor, whose ownership bits will be turned on later. 2400 */ 2401 tx_ring = sc->re_ldata.re_tx_list; 2402 idx = *idx0; 2403 i = 0; 2404 for (;;) { 2405 uint32_t cmdstat; 2406 2407 d = &tx_ring[idx]; 2408 2409 cmdstat = segs[i].ds_len; 2410 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 2411 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 2412 if (i == 0) 2413 cmdstat |= RE_TDESC_CMD_SOF; 2414 else 2415 cmdstat |= RE_TDESC_CMD_OWN; 2416 if (idx == (sc->re_tx_desc_cnt - 1)) 2417 cmdstat |= RE_TDESC_CMD_EOR; 2418 d->re_cmdstat = htole32(cmdstat | cmd_csum); 2419 d->re_control = htole32(ctl_csum | vlantag); 2420 2421 i++; 2422 if (i == nsegs) 2423 break; 2424 RE_TXDESC_INC(sc, idx); 2425 } 2426 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 2427 2428 /* Transfer ownership of packet to the chip. */ 2429 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2430 if (*idx0 != idx) 2431 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2432 2433 /* 2434 * Insure that the map for this transmission 2435 * is placed at the array index of the last descriptor 2436 * in this chain. 2437 */ 2438 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx]; 2439 sc->re_ldata.re_tx_dmamap[idx] = map; 2440 2441 sc->re_ldata.re_tx_mbuf[idx] = m; 2442 sc->re_ldata.re_tx_free -= nsegs; 2443 2444 RE_TXDESC_INC(sc, idx); 2445 *idx0 = idx; 2446 back: 2447 if (error) { 2448 m_freem(*m_head); 2449 *m_head = NULL; 2450 } 2451 return error; 2452 } 2453 2454 /* 2455 * Main transmit routine for C+ and gigE NICs. 2456 */ 2457 2458 static void 2459 re_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 2460 { 2461 struct re_softc *sc = ifp->if_softc; 2462 struct mbuf *m_head; 2463 int idx, need_trans, oactive, error; 2464 2465 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 2466 ASSERT_SERIALIZED(ifp->if_serializer); 2467 2468 if ((sc->re_flags & RE_F_LINKED) == 0) { 2469 ifq_purge(&ifp->if_snd); 2470 return; 2471 } 2472 2473 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 2474 return; 2475 2476 idx = sc->re_ldata.re_tx_prodidx; 2477 2478 need_trans = 0; 2479 oactive = 0; 2480 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 2481 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2482 if (!oactive) { 2483 if (re_tx_collect(sc)) { 2484 oactive = 1; 2485 continue; 2486 } 2487 } 2488 ifq_set_oactive(&ifp->if_snd); 2489 break; 2490 } 2491 2492 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2493 if (m_head == NULL) 2494 break; 2495 2496 error = re_encap(sc, &m_head, &idx); 2497 if (error) { 2498 /* m_head is freed by re_encap(), if we reach here */ 2499 IFNET_STAT_INC(ifp, oerrors, 1); 2500 2501 if (error == EFBIG && !oactive) { 2502 if (re_tx_collect(sc)) { 2503 oactive = 1; 2504 continue; 2505 } 2506 } 2507 ifq_set_oactive(&ifp->if_snd); 2508 break; 2509 } 2510 2511 oactive = 0; 2512 need_trans = 1; 2513 2514 /* 2515 * If there's a BPF listener, bounce a copy of this frame 2516 * to him. 2517 */ 2518 ETHER_BPF_MTAP(ifp, m_head); 2519 } 2520 2521 /* 2522 * If sc->re_ldata.re_tx_mbuf[idx] is not NULL it is possible 2523 * for OACTIVE to not be properly set when we also do not 2524 * have sufficient free tx descriptors, leaving packet in 2525 * ifp->if_snd. This can cause if_start_dispatch() to loop 2526 * infinitely so make sure OACTIVE is set properly. 2527 */ 2528 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2529 if (!ifq_is_oactive(&ifp->if_snd)) { 2530 if_printf(ifp, "Debug: OACTIVE was not set when " 2531 "re_tx_free was below minimum!\n"); 2532 ifq_set_oactive(&ifp->if_snd); 2533 } 2534 } 2535 if (!need_trans) 2536 return; 2537 2538 sc->re_ldata.re_tx_prodidx = idx; 2539 2540 /* 2541 * RealTek put the TX poll request register in a different 2542 * location on the 8169 gigE chip. I don't know why. 2543 */ 2544 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2545 2546 /* 2547 * Set a timeout in case the chip goes out to lunch. 2548 */ 2549 ifp->if_timer = 5; 2550 } 2551 2552 static void 2553 re_init(void *xsc) 2554 { 2555 struct re_softc *sc = xsc; 2556 struct ifnet *ifp = &sc->arpcom.ac_if; 2557 struct mii_data *mii; 2558 int error, framelen; 2559 2560 ASSERT_SERIALIZED(ifp->if_serializer); 2561 2562 mii = device_get_softc(sc->re_miibus); 2563 2564 /* 2565 * Cancel pending I/O and free all RX/TX buffers. 2566 */ 2567 re_stop(sc); 2568 2569 if (sc->re_caps & RE_C_CONTIGRX) { 2570 if (ifp->if_mtu > ETHERMTU) { 2571 KKASSERT(sc->re_ldata.re_jbuf != NULL); 2572 sc->re_flags |= RE_F_USE_JPOOL; 2573 sc->re_rxbuf_size = RE_FRAMELEN_MAX; 2574 sc->re_newbuf = re_newbuf_jumbo; 2575 } else { 2576 sc->re_flags &= ~RE_F_USE_JPOOL; 2577 sc->re_rxbuf_size = MCLBYTES; 2578 sc->re_newbuf = re_newbuf_std; 2579 } 2580 } 2581 2582 /* 2583 * Adjust max read request size according to MTU; mainly to 2584 * improve TX performance for common case (ETHERMTU) on GigE 2585 * NICs. However, this could _not_ be done on 10/100 only 2586 * NICs; their DMA engines will malfunction using non-default 2587 * max read request size. 2588 */ 2589 if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) { 2590 if (ifp->if_mtu > ETHERMTU) { 2591 /* 2592 * 512 seems to be the only value that works 2593 * reliably with jumbo frame 2594 */ 2595 pcie_set_max_readrq(sc->re_dev, 2596 PCIEM_DEVCTL_MAX_READRQ_512); 2597 } else { 2598 pcie_set_max_readrq(sc->re_dev, 2599 PCIEM_DEVCTL_MAX_READRQ_4096); 2600 } 2601 } 2602 2603 /* 2604 * Enable C+ RX and TX mode, as well as VLAN stripping and 2605 * RX checksum offload. We must configure the C+ register 2606 * before all others. 2607 */ 2608 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 2609 RE_CPLUSCMD_PCI_MRW | 2610 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 2611 RE_CPLUSCMD_VLANSTRIP : 0) | 2612 (ifp->if_capenable & IFCAP_RXCSUM ? 2613 RE_CPLUSCMD_RXCSUM_ENB : 0)); 2614 2615 /* 2616 * Init our MAC address. Even though the chipset 2617 * documentation doesn't mention it, we need to enter "Config 2618 * register write enable" mode to modify the ID registers. 2619 */ 2620 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 2621 CSR_WRITE_4(sc, RE_IDR0, 2622 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0]))); 2623 CSR_WRITE_2(sc, RE_IDR4, 2624 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4]))); 2625 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 2626 2627 /* 2628 * For C+ mode, initialize the RX descriptors and mbufs. 2629 */ 2630 error = re_rx_list_init(sc); 2631 if (error) { 2632 re_stop(sc); 2633 return; 2634 } 2635 error = re_tx_list_init(sc); 2636 if (error) { 2637 re_stop(sc); 2638 return; 2639 } 2640 2641 /* 2642 * Load the addresses of the RX and TX lists into the chip. 2643 */ 2644 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2645 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2646 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2647 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2648 2649 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2650 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2651 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2652 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2653 2654 /* 2655 * Enable transmit and receive. 2656 */ 2657 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2658 2659 /* 2660 * Set the initial TX and RX configuration. 2661 */ 2662 if (sc->re_flags & RE_F_TESTMODE) { 2663 if (!RE_IS_8139CP(sc)) 2664 CSR_WRITE_4(sc, RE_TXCFG, 2665 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 2666 else 2667 CSR_WRITE_4(sc, RE_TXCFG, 2668 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 2669 } else 2670 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 2671 2672 framelen = RE_FRAMELEN(ifp->if_mtu); 2673 if (framelen < MCLBYTES) 2674 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128)); 2675 else 2676 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128)); 2677 2678 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 2679 2680 /* 2681 * Program the multicast filter, if necessary. 2682 */ 2683 re_setmulti(sc); 2684 2685 #ifdef IFPOLL_ENABLE 2686 /* 2687 * Disable interrupts if we are polling. 2688 */ 2689 if (ifp->if_flags & IFF_NPOLLING) 2690 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2691 else /* otherwise ... */ 2692 #endif /* IFPOLL_ENABLE */ 2693 /* 2694 * Enable interrupts. 2695 */ 2696 if (sc->re_flags & RE_F_TESTMODE) 2697 CSR_WRITE_2(sc, RE_IMR, 0); 2698 else 2699 re_setup_intr(sc, 1, sc->re_imtype); 2700 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs); 2701 2702 /* Start RX/TX process. */ 2703 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 2704 2705 #ifdef notdef 2706 /* Enable receiver and transmitter. */ 2707 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2708 #endif 2709 2710 /* 2711 * For 8169 gigE NICs, set the max allowed RX packet 2712 * size so we can receive jumbo frames. 2713 */ 2714 if (!RE_IS_8139CP(sc)) { 2715 if (sc->re_caps & RE_C_CONTIGRX) 2716 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size); 2717 else 2718 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2719 } 2720 2721 if (sc->re_flags & RE_F_TESTMODE) 2722 return; 2723 2724 mii_mediachg(mii); 2725 2726 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2727 2728 ifp->if_flags |= IFF_RUNNING; 2729 ifq_clr_oactive(&ifp->if_snd); 2730 2731 callout_reset(&sc->re_timer, hz, re_tick, sc); 2732 } 2733 2734 /* 2735 * Set media options. 2736 */ 2737 static int 2738 re_ifmedia_upd(struct ifnet *ifp) 2739 { 2740 struct re_softc *sc = ifp->if_softc; 2741 struct mii_data *mii; 2742 2743 ASSERT_SERIALIZED(ifp->if_serializer); 2744 2745 mii = device_get_softc(sc->re_miibus); 2746 mii_mediachg(mii); 2747 2748 return(0); 2749 } 2750 2751 /* 2752 * Report current media status. 2753 */ 2754 static void 2755 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2756 { 2757 struct re_softc *sc = ifp->if_softc; 2758 struct mii_data *mii; 2759 2760 ASSERT_SERIALIZED(ifp->if_serializer); 2761 2762 mii = device_get_softc(sc->re_miibus); 2763 2764 mii_pollstat(mii); 2765 ifmr->ifm_active = mii->mii_media_active; 2766 ifmr->ifm_status = mii->mii_media_status; 2767 } 2768 2769 static int 2770 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2771 { 2772 struct re_softc *sc = ifp->if_softc; 2773 struct ifreq *ifr = (struct ifreq *) data; 2774 struct mii_data *mii; 2775 int error = 0, mask; 2776 2777 ASSERT_SERIALIZED(ifp->if_serializer); 2778 2779 switch(command) { 2780 case SIOCSIFMTU: 2781 if (ifr->ifr_mtu > sc->re_maxmtu) { 2782 error = EINVAL; 2783 } else if (ifp->if_mtu != ifr->ifr_mtu) { 2784 ifp->if_mtu = ifr->ifr_mtu; 2785 if (ifp->if_flags & IFF_RUNNING) 2786 ifp->if_init(sc); 2787 } 2788 break; 2789 2790 case SIOCSIFFLAGS: 2791 if (ifp->if_flags & IFF_UP) { 2792 if (ifp->if_flags & IFF_RUNNING) { 2793 if ((ifp->if_flags ^ sc->re_if_flags) & 2794 (IFF_PROMISC | IFF_ALLMULTI)) 2795 re_setmulti(sc); 2796 } else { 2797 re_init(sc); 2798 } 2799 } else if (ifp->if_flags & IFF_RUNNING) { 2800 re_stop(sc); 2801 } 2802 sc->re_if_flags = ifp->if_flags; 2803 break; 2804 2805 case SIOCADDMULTI: 2806 case SIOCDELMULTI: 2807 re_setmulti(sc); 2808 break; 2809 2810 case SIOCGIFMEDIA: 2811 case SIOCSIFMEDIA: 2812 mii = device_get_softc(sc->re_miibus); 2813 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2814 break; 2815 2816 case SIOCSIFCAP: 2817 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & 2818 ifp->if_capabilities; 2819 ifp->if_capenable ^= mask; 2820 2821 if (mask & IFCAP_HWCSUM) { 2822 if (ifp->if_capenable & IFCAP_TXCSUM) 2823 ifp->if_hwassist = sc->re_hwassist; 2824 else 2825 ifp->if_hwassist = 0; 2826 } 2827 if (mask && (ifp->if_flags & IFF_RUNNING)) 2828 re_init(sc); 2829 break; 2830 2831 default: 2832 error = ether_ioctl(ifp, command, data); 2833 break; 2834 } 2835 return(error); 2836 } 2837 2838 static void 2839 re_watchdog(struct ifnet *ifp) 2840 { 2841 struct re_softc *sc = ifp->if_softc; 2842 2843 ASSERT_SERIALIZED(ifp->if_serializer); 2844 2845 if_printf(ifp, "watchdog timeout\n"); 2846 2847 IFNET_STAT_INC(ifp, oerrors, 1); 2848 2849 re_txeof(sc); 2850 re_rxeof(sc); 2851 2852 re_init(sc); 2853 2854 if (!ifq_is_empty(&ifp->if_snd)) 2855 if_devstart(ifp); 2856 } 2857 2858 /* 2859 * Stop the adapter and free any mbufs allocated to the 2860 * RX and TX lists. 2861 */ 2862 static void 2863 re_stop(struct re_softc *sc) 2864 { 2865 struct ifnet *ifp = &sc->arpcom.ac_if; 2866 int i; 2867 2868 ASSERT_SERIALIZED(ifp->if_serializer); 2869 2870 /* Reset the adapter. */ 2871 re_reset(sc, ifp->if_flags & IFF_RUNNING); 2872 2873 ifp->if_timer = 0; 2874 callout_stop(&sc->re_timer); 2875 2876 ifp->if_flags &= ~IFF_RUNNING; 2877 ifq_clr_oactive(&ifp->if_snd); 2878 sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED); 2879 2880 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2881 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2882 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 2883 2884 re_free_rxchain(sc); 2885 2886 /* Free the TX list buffers. */ 2887 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 2888 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2889 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2890 sc->re_ldata.re_tx_dmamap[i]); 2891 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2892 sc->re_ldata.re_tx_mbuf[i] = NULL; 2893 } 2894 } 2895 2896 /* Free the RX list buffers. */ 2897 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 2898 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2899 if ((sc->re_flags & RE_F_USE_JPOOL) == 0) { 2900 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 2901 sc->re_ldata.re_rx_dmamap[i]); 2902 } 2903 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2904 sc->re_ldata.re_rx_mbuf[i] = NULL; 2905 } 2906 } 2907 } 2908 2909 /* 2910 * Device suspend routine. Stop the interface and save some PCI 2911 * settings in case the BIOS doesn't restore them properly on 2912 * resume. 2913 */ 2914 static int 2915 re_suspend(device_t dev) 2916 { 2917 #ifndef BURN_BRIDGES 2918 int i; 2919 #endif 2920 struct re_softc *sc = device_get_softc(dev); 2921 struct ifnet *ifp = &sc->arpcom.ac_if; 2922 2923 lwkt_serialize_enter(ifp->if_serializer); 2924 2925 re_stop(sc); 2926 2927 #ifndef BURN_BRIDGES 2928 for (i = 0; i < 5; i++) 2929 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2930 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2931 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2932 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2933 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2934 #endif 2935 2936 sc->re_flags |= RE_F_SUSPENDED; 2937 2938 lwkt_serialize_exit(ifp->if_serializer); 2939 2940 return (0); 2941 } 2942 2943 /* 2944 * Device resume routine. Restore some PCI settings in case the BIOS 2945 * doesn't, re-enable busmastering, and restart the interface if 2946 * appropriate. 2947 */ 2948 static int 2949 re_resume(device_t dev) 2950 { 2951 struct re_softc *sc = device_get_softc(dev); 2952 struct ifnet *ifp = &sc->arpcom.ac_if; 2953 #ifndef BURN_BRIDGES 2954 int i; 2955 #endif 2956 2957 lwkt_serialize_enter(ifp->if_serializer); 2958 2959 #ifndef BURN_BRIDGES 2960 /* better way to do this? */ 2961 for (i = 0; i < 5; i++) 2962 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2963 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2964 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2965 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2966 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2967 2968 /* reenable busmastering */ 2969 pci_enable_busmaster(dev); 2970 pci_enable_io(dev, SYS_RES_IOPORT); 2971 #endif 2972 2973 /* reinitialize interface if necessary */ 2974 if (ifp->if_flags & IFF_UP) 2975 re_init(sc); 2976 2977 sc->re_flags &= ~RE_F_SUSPENDED; 2978 2979 lwkt_serialize_exit(ifp->if_serializer); 2980 2981 return (0); 2982 } 2983 2984 /* 2985 * Stop all chip I/O so that the kernel's probe routines don't 2986 * get confused by errant DMAs when rebooting. 2987 */ 2988 static void 2989 re_shutdown(device_t dev) 2990 { 2991 struct re_softc *sc = device_get_softc(dev); 2992 struct ifnet *ifp = &sc->arpcom.ac_if; 2993 2994 lwkt_serialize_enter(ifp->if_serializer); 2995 re_stop(sc); 2996 lwkt_serialize_exit(ifp->if_serializer); 2997 } 2998 2999 static int 3000 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS) 3001 { 3002 struct re_softc *sc = arg1; 3003 3004 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time); 3005 } 3006 3007 static int 3008 re_sysctl_txtime(SYSCTL_HANDLER_ARGS) 3009 { 3010 struct re_softc *sc = arg1; 3011 3012 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time); 3013 } 3014 3015 static int 3016 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime) 3017 { 3018 struct re_softc *sc = arg1; 3019 struct ifnet *ifp = &sc->arpcom.ac_if; 3020 int error, v; 3021 3022 lwkt_serialize_enter(ifp->if_serializer); 3023 3024 v = *hwtime; 3025 error = sysctl_handle_int(oidp, &v, 0, req); 3026 if (error || req->newptr == NULL) 3027 goto back; 3028 3029 if (v <= 0) { 3030 error = EINVAL; 3031 goto back; 3032 } 3033 3034 if (v != *hwtime) { 3035 *hwtime = v; 3036 3037 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) == 3038 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW) 3039 re_setup_hw_im(sc); 3040 } 3041 back: 3042 lwkt_serialize_exit(ifp->if_serializer); 3043 return error; 3044 } 3045 3046 static int 3047 re_sysctl_simtime(SYSCTL_HANDLER_ARGS) 3048 { 3049 struct re_softc *sc = arg1; 3050 struct ifnet *ifp = &sc->arpcom.ac_if; 3051 int error, v; 3052 3053 lwkt_serialize_enter(ifp->if_serializer); 3054 3055 v = sc->re_sim_time; 3056 error = sysctl_handle_int(oidp, &v, 0, req); 3057 if (error || req->newptr == NULL) 3058 goto back; 3059 3060 if (v <= 0) { 3061 error = EINVAL; 3062 goto back; 3063 } 3064 3065 if (v != sc->re_sim_time) { 3066 sc->re_sim_time = v; 3067 3068 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) == 3069 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) { 3070 #ifdef foo 3071 int reg; 3072 3073 /* 3074 * Following code causes various strange 3075 * performance problems. Hmm ... 3076 */ 3077 CSR_WRITE_2(sc, RE_IMR, 0); 3078 if (!RE_IS_8139CP(sc)) 3079 reg = RE_TIMERINT_8169; 3080 else 3081 reg = RE_TIMERINT; 3082 CSR_WRITE_4(sc, reg, 0); 3083 CSR_READ_4(sc, reg); /* flush */ 3084 3085 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3086 re_setup_sim_im(sc); 3087 #else 3088 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 3089 DELAY(10); 3090 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 3091 #endif 3092 } 3093 } 3094 back: 3095 lwkt_serialize_exit(ifp->if_serializer); 3096 return error; 3097 } 3098 3099 static int 3100 re_sysctl_imtype(SYSCTL_HANDLER_ARGS) 3101 { 3102 struct re_softc *sc = arg1; 3103 struct ifnet *ifp = &sc->arpcom.ac_if; 3104 int error, v; 3105 3106 lwkt_serialize_enter(ifp->if_serializer); 3107 3108 v = sc->re_imtype; 3109 error = sysctl_handle_int(oidp, &v, 0, req); 3110 if (error || req->newptr == NULL) 3111 goto back; 3112 3113 if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) { 3114 error = EINVAL; 3115 goto back; 3116 } 3117 if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) { 3118 /* Can't do hardware interrupt moderation */ 3119 error = EOPNOTSUPP; 3120 goto back; 3121 } 3122 3123 if (v != sc->re_imtype) { 3124 sc->re_imtype = v; 3125 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) == 3126 IFF_RUNNING) 3127 re_setup_intr(sc, 1, sc->re_imtype); 3128 } 3129 back: 3130 lwkt_serialize_exit(ifp->if_serializer); 3131 return error; 3132 } 3133 3134 static void 3135 re_setup_hw_im(struct re_softc *sc) 3136 { 3137 KKASSERT(sc->re_caps & RE_C_HWIM); 3138 3139 /* 3140 * Interrupt moderation 3141 * 3142 * 0xABCD 3143 * A - unknown (maybe TX related) 3144 * B - TX timer (unit: 25us) 3145 * C - unknown (maybe RX related) 3146 * D - RX timer (unit: 25us) 3147 * 3148 * 3149 * re(4)'s interrupt moderation is actually controlled by 3150 * two variables, like most other NICs (bge, bce etc.) 3151 * o timer 3152 * o number of packets [P] 3153 * 3154 * The logic relationship between these two variables is 3155 * similar to other NICs too: 3156 * if (timer expire || packets > [P]) 3157 * Interrupt is delivered 3158 * 3159 * Currently we only know how to set 'timer', but not 3160 * 'number of packets', which should be ~30, as far as I 3161 * tested (sink ~900Kpps, interrupt rate is 30KHz) 3162 */ 3163 CSR_WRITE_2(sc, RE_IM, 3164 RE_IM_RXTIME(sc->re_rx_time) | 3165 RE_IM_TXTIME(sc->re_tx_time) | 3166 RE_IM_MAGIC); 3167 } 3168 3169 static void 3170 re_disable_hw_im(struct re_softc *sc) 3171 { 3172 if (sc->re_caps & RE_C_HWIM) 3173 CSR_WRITE_2(sc, RE_IM, 0); 3174 } 3175 3176 static void 3177 re_setup_sim_im(struct re_softc *sc) 3178 { 3179 if (!RE_IS_8139CP(sc)) { 3180 uint32_t ticks; 3181 3182 /* 3183 * Datasheet says tick decreases at bus speed, 3184 * but it seems the clock runs a little bit 3185 * faster, so we do some compensation here. 3186 */ 3187 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5; 3188 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks); 3189 } else { 3190 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */ 3191 } 3192 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 3193 sc->re_flags |= RE_F_TIMER_INTR; 3194 } 3195 3196 static void 3197 re_disable_sim_im(struct re_softc *sc) 3198 { 3199 if (!RE_IS_8139CP(sc)) 3200 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0); 3201 else 3202 CSR_WRITE_4(sc, RE_TIMERINT, 0); 3203 sc->re_flags &= ~RE_F_TIMER_INTR; 3204 } 3205 3206 static void 3207 re_config_imtype(struct re_softc *sc, int imtype) 3208 { 3209 switch (imtype) { 3210 case RE_IMTYPE_HW: 3211 KKASSERT(sc->re_caps & RE_C_HWIM); 3212 /* FALL THROUGH */ 3213 case RE_IMTYPE_NONE: 3214 sc->re_intrs = RE_INTRS; 3215 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW | 3216 RE_ISR_RX_OVERRUN; 3217 sc->re_tx_ack = RE_ISR_TX_OK; 3218 break; 3219 3220 case RE_IMTYPE_SIM: 3221 sc->re_intrs = RE_INTRS_TIMER; 3222 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED; 3223 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; 3224 break; 3225 3226 default: 3227 panic("%s: unknown imtype %d", 3228 sc->arpcom.ac_if.if_xname, imtype); 3229 } 3230 } 3231 3232 static void 3233 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype) 3234 { 3235 re_config_imtype(sc, imtype); 3236 3237 if (enable_intrs) 3238 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3239 else 3240 CSR_WRITE_2(sc, RE_IMR, 0); 3241 3242 sc->re_npoll.ifpc_stcount = 0; 3243 3244 switch (imtype) { 3245 case RE_IMTYPE_NONE: 3246 re_disable_sim_im(sc); 3247 re_disable_hw_im(sc); 3248 break; 3249 3250 case RE_IMTYPE_HW: 3251 KKASSERT(sc->re_caps & RE_C_HWIM); 3252 re_disable_sim_im(sc); 3253 re_setup_hw_im(sc); 3254 break; 3255 3256 case RE_IMTYPE_SIM: 3257 re_disable_hw_im(sc); 3258 re_setup_sim_im(sc); 3259 break; 3260 3261 default: 3262 panic("%s: unknown imtype %d", 3263 sc->arpcom.ac_if.if_xname, imtype); 3264 } 3265 } 3266 3267 static void 3268 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr) 3269 { 3270 int i; 3271 3272 if (sc->re_macver == RE_MACVER_11 || 3273 sc->re_macver == RE_MACVER_12 || 3274 sc->re_macver == RE_MACVER_30 || 3275 sc->re_macver == RE_MACVER_31) { 3276 uint16_t re_did; 3277 3278 re_get_eewidth(sc); 3279 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 3280 if (re_did == 0x8128) { 3281 uint16_t as[ETHER_ADDR_LEN / 2]; 3282 int eaddr_off; 3283 3284 if (sc->re_macver == RE_MACVER_30 || 3285 sc->re_macver == RE_MACVER_31) 3286 eaddr_off = RE_EE_EADDR1; 3287 else 3288 eaddr_off = RE_EE_EADDR0; 3289 3290 /* 3291 * Get station address from the EEPROM. 3292 */ 3293 re_read_eeprom(sc, (caddr_t)as, eaddr_off, 3); 3294 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 3295 as[i] = le16toh(as[i]); 3296 bcopy(as, eaddr, ETHER_ADDR_LEN); 3297 return; 3298 } 3299 } 3300 3301 /* 3302 * Get station address from IDRx. 3303 */ 3304 for (i = 0; i < ETHER_ADDR_LEN; ++i) 3305 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i); 3306 } 3307 3308 static int 3309 re_jpool_alloc(struct re_softc *sc) 3310 { 3311 struct re_list_data *ldata = &sc->re_ldata; 3312 struct re_jbuf *jbuf; 3313 bus_addr_t paddr; 3314 bus_size_t jpool_size; 3315 bus_dmamem_t dmem; 3316 caddr_t buf; 3317 int i, error; 3318 3319 lwkt_serialize_init(&ldata->re_jbuf_serializer); 3320 3321 ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc), 3322 M_DEVBUF, M_WAITOK | M_ZERO); 3323 3324 jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE; 3325 3326 error = bus_dmamem_coherent(sc->re_parent_tag, 3327 RE_RXBUF_ALIGN, 0, 3328 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3329 jpool_size, BUS_DMA_WAITOK, &dmem); 3330 if (error) { 3331 device_printf(sc->re_dev, "could not allocate jumbo memory\n"); 3332 return error; 3333 } 3334 ldata->re_jpool_tag = dmem.dmem_tag; 3335 ldata->re_jpool_map = dmem.dmem_map; 3336 ldata->re_jpool = dmem.dmem_addr; 3337 paddr = dmem.dmem_busaddr; 3338 3339 /* ..and split it into 9KB chunks */ 3340 SLIST_INIT(&ldata->re_jbuf_free); 3341 3342 buf = ldata->re_jpool; 3343 for (i = 0; i < RE_JBUF_COUNT(sc); i++) { 3344 jbuf = &ldata->re_jbuf[i]; 3345 3346 jbuf->re_sc = sc; 3347 jbuf->re_inuse = 0; 3348 jbuf->re_slot = i; 3349 jbuf->re_buf = buf; 3350 jbuf->re_paddr = paddr; 3351 3352 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3353 3354 buf += RE_JBUF_SIZE; 3355 paddr += RE_JBUF_SIZE; 3356 } 3357 return 0; 3358 } 3359 3360 static void 3361 re_jpool_free(struct re_softc *sc) 3362 { 3363 struct re_list_data *ldata = &sc->re_ldata; 3364 3365 if (ldata->re_jpool_tag != NULL) { 3366 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map); 3367 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool, 3368 ldata->re_jpool_map); 3369 bus_dma_tag_destroy(ldata->re_jpool_tag); 3370 ldata->re_jpool_tag = NULL; 3371 } 3372 3373 if (ldata->re_jbuf != NULL) { 3374 kfree(ldata->re_jbuf, M_DEVBUF); 3375 ldata->re_jbuf = NULL; 3376 } 3377 } 3378 3379 static struct re_jbuf * 3380 re_jbuf_alloc(struct re_softc *sc) 3381 { 3382 struct re_list_data *ldata = &sc->re_ldata; 3383 struct re_jbuf *jbuf; 3384 3385 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3386 3387 jbuf = SLIST_FIRST(&ldata->re_jbuf_free); 3388 if (jbuf != NULL) { 3389 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link); 3390 jbuf->re_inuse = 1; 3391 } 3392 3393 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3394 3395 return jbuf; 3396 } 3397 3398 static void 3399 re_jbuf_free(void *arg) 3400 { 3401 struct re_jbuf *jbuf = arg; 3402 struct re_softc *sc = jbuf->re_sc; 3403 struct re_list_data *ldata = &sc->re_ldata; 3404 3405 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3406 panic("%s: free wrong jumbo buffer", 3407 sc->arpcom.ac_if.if_xname); 3408 } else if (jbuf->re_inuse == 0) { 3409 panic("%s: jumbo buffer already freed", 3410 sc->arpcom.ac_if.if_xname); 3411 } 3412 3413 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3414 atomic_subtract_int(&jbuf->re_inuse, 1); 3415 if (jbuf->re_inuse == 0) 3416 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3417 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3418 } 3419 3420 static void 3421 re_jbuf_ref(void *arg) 3422 { 3423 struct re_jbuf *jbuf = arg; 3424 struct re_softc *sc = jbuf->re_sc; 3425 struct re_list_data *ldata = &sc->re_ldata; 3426 3427 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3428 panic("%s: ref wrong jumbo buffer", 3429 sc->arpcom.ac_if.if_xname); 3430 } else if (jbuf->re_inuse == 0) { 3431 panic("%s: jumbo buffer already freed", 3432 sc->arpcom.ac_if.if_xname); 3433 } 3434 atomic_add_int(&jbuf->re_inuse, 1); 3435 } 3436