1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.99 2008/10/30 11:27:40 sephe Exp $ 37 */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7440, so the max MTU possible with this 111 * driver is 7422 bytes. 112 */ 113 114 #define _IP_VHL 115 116 #include "opt_polling.h" 117 118 #include <sys/param.h> 119 #include <sys/bus.h> 120 #include <sys/endian.h> 121 #include <sys/kernel.h> 122 #include <sys/in_cksum.h> 123 #include <sys/interrupt.h> 124 #include <sys/malloc.h> 125 #include <sys/mbuf.h> 126 #include <sys/rman.h> 127 #include <sys/serialize.h> 128 #include <sys/socket.h> 129 #include <sys/sockio.h> 130 #include <sys/sysctl.h> 131 132 #include <net/bpf.h> 133 #include <net/ethernet.h> 134 #include <net/if.h> 135 #include <net/ifq_var.h> 136 #include <net/if_arp.h> 137 #include <net/if_dl.h> 138 #include <net/if_media.h> 139 #include <net/if_types.h> 140 #include <net/vlan/if_vlan_var.h> 141 #include <net/vlan/if_vlan_ether.h> 142 143 #include <netinet/ip.h> 144 145 #include <dev/netif/mii_layer/mii.h> 146 #include <dev/netif/mii_layer/miivar.h> 147 148 #include <bus/pci/pcidevs.h> 149 #include <bus/pci/pcireg.h> 150 #include <bus/pci/pcivar.h> 151 152 /* "device miibus" required. See GENERIC if you get errors here. */ 153 #include "miibus_if.h" 154 155 #include <dev/netif/re/if_rereg.h> 156 #include <dev/netif/re/if_revar.h> 157 158 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 159 160 /* 161 * Various supported device vendors/types and their names. 162 */ 163 static const struct re_type { 164 uint16_t re_vid; 165 uint16_t re_did; 166 const char *re_name; 167 } re_devs[] = { 168 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, 172 "RealTek 8139C+ 10/100BaseTX" }, 173 174 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, 175 "RealTek 810x PCIe 10/100baseTX" }, 176 177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, 178 "RealTek 8111/8168 PCIe Gigabit Ethernet" }, 179 180 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 181 "RealTek 8110/8169 Gigabit Ethernet" }, 182 183 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, 184 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 185 186 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, 187 "Corega CG-LAPCIGT Gigabit Ethernet" }, 188 189 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, 190 "Linksys EG1032 Gigabit Ethernet" }, 191 192 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, 193 "US Robotics 997902 Gigabit Ethernet" }, 194 195 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322, 196 "TTTech MC322 Gigabit Ethernet" }, 197 198 { 0, 0, NULL } 199 }; 200 201 static const struct re_hwrev re_hwrevs[] = { 202 { RE_HWREV_8139CPLUS, RE_MACVER_UNKN, ETHERMTU, 203 RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE }, 204 205 { RE_HWREV_8169, RE_MACVER_UNKN, ETHERMTU, 206 RE_C_HWCSUM | RE_C_8169 }, 207 208 { RE_HWREV_8110S, RE_MACVER_03, RE_MTU_6K, 209 RE_C_HWCSUM | RE_C_8169 }, 210 211 { RE_HWREV_8169S, RE_MACVER_03, RE_MTU_6K, 212 RE_C_HWCSUM | RE_C_8169 }, 213 214 { RE_HWREV_8169SB, RE_MACVER_04, RE_MTU_6K, 215 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 216 217 { RE_HWREV_8169SC1, RE_MACVER_05, RE_MTU_6K, 218 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 219 220 { RE_HWREV_8169SC2, RE_MACVER_06, RE_MTU_6K, 221 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 222 223 { RE_HWREV_8168B1, RE_MACVER_21, RE_MTU_6K, 224 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT }, 225 226 { RE_HWREV_8168B2, RE_MACVER_23, RE_MTU_6K, 227 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 228 229 { RE_HWREV_8168B3, RE_MACVER_23, RE_MTU_6K, 230 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 231 232 { RE_HWREV_8168C, RE_MACVER_29, RE_MTU_6K, 233 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 234 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 235 236 { RE_HWREV_8168CP, RE_MACVER_2B, RE_MTU_6K, 237 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 238 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 239 240 { RE_HWREV_8168D, RE_MACVER_2A, RE_MTU_9K, 241 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 242 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 243 244 { RE_HWREV_8100E, RE_MACVER_UNKN, ETHERMTU, 245 RE_C_HWCSUM | RE_C_FASTE }, 246 247 { RE_HWREV_8101E1, RE_MACVER_16, ETHERMTU, 248 RE_C_HWCSUM | RE_C_FASTE }, 249 250 { RE_HWREV_8101E2, RE_MACVER_16, ETHERMTU, 251 RE_C_HWCSUM | RE_C_FASTE }, 252 253 { RE_HWREV_8102E, RE_MACVER_15, ETHERMTU, 254 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 255 RE_C_FASTE }, 256 257 { RE_HWREV_8102EL, RE_MACVER_15, ETHERMTU, 258 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 259 RE_C_FASTE }, 260 261 { RE_HWREV_NULL, 0, 0, 0 } 262 }; 263 264 static int re_probe(device_t); 265 static int re_attach(device_t); 266 static int re_detach(device_t); 267 static int re_suspend(device_t); 268 static int re_resume(device_t); 269 static void re_shutdown(device_t); 270 271 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int); 272 static void re_dma_map_desc(void *, bus_dma_segment_t *, int, 273 bus_size_t, int); 274 static int re_allocmem(device_t); 275 static void re_freemem(device_t); 276 static void re_freebufmem(struct re_softc *, int, int); 277 static int re_encap(struct re_softc *, struct mbuf **, int *); 278 static int re_newbuf_std(struct re_softc *, int, int); 279 static int re_newbuf_jumbo(struct re_softc *, int, int); 280 static void re_setup_rxdesc(struct re_softc *, int); 281 static int re_rx_list_init(struct re_softc *); 282 static int re_tx_list_init(struct re_softc *); 283 static int re_rxeof(struct re_softc *); 284 static int re_txeof(struct re_softc *); 285 static int re_tx_collect(struct re_softc *); 286 static void re_intr(void *); 287 static void re_tick(void *); 288 static void re_tick_serialized(void *); 289 290 static void re_start(struct ifnet *); 291 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 292 static void re_init(void *); 293 static void re_stop(struct re_softc *); 294 static void re_watchdog(struct ifnet *); 295 static int re_ifmedia_upd(struct ifnet *); 296 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 297 298 static void re_eeprom_putbyte(struct re_softc *, int); 299 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 300 static void re_read_eeprom(struct re_softc *, caddr_t, int, int); 301 static void re_get_eewidth(struct re_softc *); 302 303 static int re_gmii_readreg(device_t, int, int); 304 static int re_gmii_writereg(device_t, int, int, int); 305 306 static int re_miibus_readreg(device_t, int, int); 307 static int re_miibus_writereg(device_t, int, int, int); 308 static void re_miibus_statchg(device_t); 309 310 static void re_setmulti(struct re_softc *); 311 static void re_reset(struct re_softc *, int); 312 static void re_get_eaddr(struct re_softc *, uint8_t *); 313 314 static void re_setup_hw_im(struct re_softc *); 315 static void re_setup_sim_im(struct re_softc *); 316 static void re_disable_hw_im(struct re_softc *); 317 static void re_disable_sim_im(struct re_softc *); 318 static void re_config_imtype(struct re_softc *, int); 319 static void re_setup_intr(struct re_softc *, int, int); 320 321 static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *); 322 static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS); 323 static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS); 324 static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS); 325 static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS); 326 327 static int re_jpool_alloc(struct re_softc *); 328 static void re_jpool_free(struct re_softc *); 329 static struct re_jbuf *re_jbuf_alloc(struct re_softc *); 330 static void re_jbuf_free(void *); 331 static void re_jbuf_ref(void *); 332 333 #ifdef RE_DIAG 334 static int re_diag(struct re_softc *); 335 #endif 336 337 #ifdef DEVICE_POLLING 338 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 339 #endif 340 341 static device_method_t re_methods[] = { 342 /* Device interface */ 343 DEVMETHOD(device_probe, re_probe), 344 DEVMETHOD(device_attach, re_attach), 345 DEVMETHOD(device_detach, re_detach), 346 DEVMETHOD(device_suspend, re_suspend), 347 DEVMETHOD(device_resume, re_resume), 348 DEVMETHOD(device_shutdown, re_shutdown), 349 350 /* bus interface */ 351 DEVMETHOD(bus_print_child, bus_generic_print_child), 352 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 353 354 /* MII interface */ 355 DEVMETHOD(miibus_readreg, re_miibus_readreg), 356 DEVMETHOD(miibus_writereg, re_miibus_writereg), 357 DEVMETHOD(miibus_statchg, re_miibus_statchg), 358 359 { 0, 0 } 360 }; 361 362 static driver_t re_driver = { 363 "re", 364 re_methods, 365 sizeof(struct re_softc) 366 }; 367 368 static devclass_t re_devclass; 369 370 DECLARE_DUMMY_MODULE(if_re); 371 MODULE_DEPEND(if_re, miibus, 1, 1, 1); 372 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0); 373 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0); 374 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 375 376 static int re_rx_desc_count = RE_RX_DESC_CNT_DEF; 377 static int re_tx_desc_count = RE_TX_DESC_CNT_DEF; 378 379 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count); 380 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count); 381 382 #define EE_SET(x) \ 383 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 384 385 #define EE_CLR(x) \ 386 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 387 388 static __inline void 389 re_free_rxchain(struct re_softc *sc) 390 { 391 if (sc->re_head != NULL) { 392 m_freem(sc->re_head); 393 sc->re_head = sc->re_tail = NULL; 394 } 395 } 396 397 /* 398 * Send a read command and address to the EEPROM, check for ACK. 399 */ 400 static void 401 re_eeprom_putbyte(struct re_softc *sc, int addr) 402 { 403 int d, i; 404 405 d = addr | (RE_9346_READ << sc->re_eewidth); 406 407 /* 408 * Feed in each bit and strobe the clock. 409 */ 410 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) { 411 if (d & i) 412 EE_SET(RE_EE_DATAIN); 413 else 414 EE_CLR(RE_EE_DATAIN); 415 DELAY(100); 416 EE_SET(RE_EE_CLK); 417 DELAY(150); 418 EE_CLR(RE_EE_CLK); 419 DELAY(100); 420 } 421 } 422 423 /* 424 * Read a word of data stored in the EEPROM at address 'addr.' 425 */ 426 static void 427 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 428 { 429 int i; 430 uint16_t word = 0; 431 432 /* 433 * Send address of word we want to read. 434 */ 435 re_eeprom_putbyte(sc, addr); 436 437 /* 438 * Start reading bits from EEPROM. 439 */ 440 for (i = 0x8000; i != 0; i >>= 1) { 441 EE_SET(RE_EE_CLK); 442 DELAY(100); 443 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 444 word |= i; 445 EE_CLR(RE_EE_CLK); 446 DELAY(100); 447 } 448 449 *dest = word; 450 } 451 452 /* 453 * Read a sequence of words from the EEPROM. 454 */ 455 static void 456 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt) 457 { 458 int i; 459 uint16_t word = 0, *ptr; 460 461 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 462 DELAY(100); 463 464 for (i = 0; i < cnt; i++) { 465 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL); 466 re_eeprom_getword(sc, off + i, &word); 467 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL); 468 ptr = (uint16_t *)(dest + (i * 2)); 469 *ptr = word; 470 } 471 472 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 473 } 474 475 static void 476 re_get_eewidth(struct re_softc *sc) 477 { 478 uint16_t re_did = 0; 479 480 sc->re_eewidth = 6; 481 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 482 if (re_did != 0x8129) 483 sc->re_eewidth = 8; 484 } 485 486 static int 487 re_gmii_readreg(device_t dev, int phy, int reg) 488 { 489 struct re_softc *sc = device_get_softc(dev); 490 u_int32_t rval; 491 int i; 492 493 if (phy != 1) 494 return(0); 495 496 /* Let the rgephy driver read the GMEDIASTAT register */ 497 498 if (reg == RE_GMEDIASTAT) 499 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 500 501 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 502 DELAY(1000); 503 504 for (i = 0; i < RE_TIMEOUT; i++) { 505 rval = CSR_READ_4(sc, RE_PHYAR); 506 if (rval & RE_PHYAR_BUSY) 507 break; 508 DELAY(100); 509 } 510 511 if (i == RE_TIMEOUT) { 512 device_printf(dev, "PHY read failed\n"); 513 return(0); 514 } 515 516 return(rval & RE_PHYAR_PHYDATA); 517 } 518 519 static int 520 re_gmii_writereg(device_t dev, int phy, int reg, int data) 521 { 522 struct re_softc *sc = device_get_softc(dev); 523 uint32_t rval; 524 int i; 525 526 CSR_WRITE_4(sc, RE_PHYAR, 527 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 528 DELAY(1000); 529 530 for (i = 0; i < RE_TIMEOUT; i++) { 531 rval = CSR_READ_4(sc, RE_PHYAR); 532 if ((rval & RE_PHYAR_BUSY) == 0) 533 break; 534 DELAY(100); 535 } 536 537 if (i == RE_TIMEOUT) 538 device_printf(dev, "PHY write failed\n"); 539 540 return(0); 541 } 542 543 static int 544 re_miibus_readreg(device_t dev, int phy, int reg) 545 { 546 struct re_softc *sc = device_get_softc(dev); 547 uint16_t rval = 0; 548 uint16_t re8139_reg = 0; 549 550 if (!RE_IS_8139CP(sc)) { 551 rval = re_gmii_readreg(dev, phy, reg); 552 return(rval); 553 } 554 555 /* Pretend the internal PHY is only at address 0 */ 556 if (phy) 557 return(0); 558 559 switch(reg) { 560 case MII_BMCR: 561 re8139_reg = RE_BMCR; 562 break; 563 case MII_BMSR: 564 re8139_reg = RE_BMSR; 565 break; 566 case MII_ANAR: 567 re8139_reg = RE_ANAR; 568 break; 569 case MII_ANER: 570 re8139_reg = RE_ANER; 571 break; 572 case MII_ANLPAR: 573 re8139_reg = RE_LPAR; 574 break; 575 case MII_PHYIDR1: 576 case MII_PHYIDR2: 577 return(0); 578 /* 579 * Allow the rlphy driver to read the media status 580 * register. If we have a link partner which does not 581 * support NWAY, this is the register which will tell 582 * us the results of parallel detection. 583 */ 584 case RE_MEDIASTAT: 585 return(CSR_READ_1(sc, RE_MEDIASTAT)); 586 default: 587 device_printf(dev, "bad phy register\n"); 588 return(0); 589 } 590 rval = CSR_READ_2(sc, re8139_reg); 591 if (re8139_reg == RE_BMCR) { 592 /* 8139C+ has different bit layout. */ 593 rval &= ~(BMCR_LOOP | BMCR_ISO); 594 } 595 return(rval); 596 } 597 598 static int 599 re_miibus_writereg(device_t dev, int phy, int reg, int data) 600 { 601 struct re_softc *sc= device_get_softc(dev); 602 u_int16_t re8139_reg = 0; 603 604 if (!RE_IS_8139CP(sc)) 605 return(re_gmii_writereg(dev, phy, reg, data)); 606 607 /* Pretend the internal PHY is only at address 0 */ 608 if (phy) 609 return(0); 610 611 switch(reg) { 612 case MII_BMCR: 613 re8139_reg = RE_BMCR; 614 /* 8139C+ has different bit layout. */ 615 data &= ~(BMCR_LOOP | BMCR_ISO); 616 break; 617 case MII_BMSR: 618 re8139_reg = RE_BMSR; 619 break; 620 case MII_ANAR: 621 re8139_reg = RE_ANAR; 622 break; 623 case MII_ANER: 624 re8139_reg = RE_ANER; 625 break; 626 case MII_ANLPAR: 627 re8139_reg = RE_LPAR; 628 break; 629 case MII_PHYIDR1: 630 case MII_PHYIDR2: 631 return(0); 632 default: 633 device_printf(dev, "bad phy register\n"); 634 return(0); 635 } 636 CSR_WRITE_2(sc, re8139_reg, data); 637 return(0); 638 } 639 640 static void 641 re_miibus_statchg(device_t dev) 642 { 643 } 644 645 /* 646 * Program the 64-bit multicast hash filter. 647 */ 648 static void 649 re_setmulti(struct re_softc *sc) 650 { 651 struct ifnet *ifp = &sc->arpcom.ac_if; 652 int h = 0; 653 uint32_t hashes[2] = { 0, 0 }; 654 struct ifmultiaddr *ifma; 655 uint32_t rxfilt; 656 int mcnt = 0; 657 658 rxfilt = CSR_READ_4(sc, RE_RXCFG); 659 660 /* Set the individual bit to receive frames for this host only. */ 661 rxfilt |= RE_RXCFG_RX_INDIV; 662 /* Set capture broadcast bit to capture broadcast frames. */ 663 rxfilt |= RE_RXCFG_RX_BROAD; 664 665 rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI); 666 if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) { 667 rxfilt |= RE_RXCFG_RX_MULTI; 668 669 /* If we want promiscuous mode, set the allframes bit. */ 670 if (ifp->if_flags & IFF_PROMISC) 671 rxfilt |= RE_RXCFG_RX_ALLPHYS; 672 673 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 674 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 675 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 676 return; 677 } 678 679 /* first, zot all the existing hash bits */ 680 CSR_WRITE_4(sc, RE_MAR0, 0); 681 CSR_WRITE_4(sc, RE_MAR4, 0); 682 683 /* now program new ones */ 684 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 685 if (ifma->ifma_addr->sa_family != AF_LINK) 686 continue; 687 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 688 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 689 if (h < 32) 690 hashes[0] |= (1 << h); 691 else 692 hashes[1] |= (1 << (h - 32)); 693 mcnt++; 694 } 695 696 if (mcnt) 697 rxfilt |= RE_RXCFG_RX_MULTI; 698 else 699 rxfilt &= ~RE_RXCFG_RX_MULTI; 700 701 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 702 703 /* 704 * For some unfathomable reason, RealTek decided to reverse 705 * the order of the multicast hash registers in the PCI Express 706 * parts. This means we have to write the hash pattern in reverse 707 * order for those devices. 708 */ 709 if (sc->re_caps & RE_C_PCIE) { 710 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[0])); 711 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[1])); 712 } else { 713 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 714 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 715 } 716 } 717 718 static void 719 re_reset(struct re_softc *sc, int running) 720 { 721 int i; 722 723 if ((sc->re_caps & RE_C_STOP_RXTX) && running) { 724 CSR_WRITE_1(sc, RE_COMMAND, 725 RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB); 726 DELAY(100); 727 } 728 729 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 730 731 for (i = 0; i < RE_TIMEOUT; i++) { 732 DELAY(10); 733 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 734 break; 735 } 736 if (i == RE_TIMEOUT) 737 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 738 } 739 740 #ifdef RE_DIAG 741 /* 742 * The following routine is designed to test for a defect on some 743 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 744 * lines connected to the bus, however for a 32-bit only card, they 745 * should be pulled high. The result of this defect is that the 746 * NIC will not work right if you plug it into a 64-bit slot: DMA 747 * operations will be done with 64-bit transfers, which will fail 748 * because the 64-bit data lines aren't connected. 749 * 750 * There's no way to work around this (short of talking a soldering 751 * iron to the board), however we can detect it. The method we use 752 * here is to put the NIC into digital loopback mode, set the receiver 753 * to promiscuous mode, and then try to send a frame. We then compare 754 * the frame data we sent to what was received. If the data matches, 755 * then the NIC is working correctly, otherwise we know the user has 756 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 757 * slot. In the latter case, there's no way the NIC can work correctly, 758 * so we print out a message on the console and abort the device attach. 759 */ 760 761 static int 762 re_diag(struct re_softc *sc) 763 { 764 struct ifnet *ifp = &sc->arpcom.ac_if; 765 struct mbuf *m0; 766 struct ether_header *eh; 767 struct re_desc *cur_rx; 768 uint16_t status; 769 uint32_t rxstat; 770 int total_len, i, error = 0, phyaddr; 771 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 772 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 773 774 /* Allocate a single mbuf */ 775 776 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 777 if (m0 == NULL) 778 return(ENOBUFS); 779 780 /* 781 * Initialize the NIC in test mode. This sets the chip up 782 * so that it can send and receive frames, but performs the 783 * following special functions: 784 * - Puts receiver in promiscuous mode 785 * - Enables digital loopback mode 786 * - Leaves interrupts turned off 787 */ 788 789 ifp->if_flags |= IFF_PROMISC; 790 sc->re_flags |= RE_F_TESTMODE; 791 re_init(sc); 792 sc->re_flags |= RE_F_LINKED; 793 if (!RE_IS_8139CP(sc)) 794 phyaddr = 1; 795 else 796 phyaddr = 0; 797 798 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET); 799 for (i = 0; i < RE_TIMEOUT; i++) { 800 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR); 801 if (!(status & BMCR_RESET)) 802 break; 803 } 804 805 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP); 806 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG); 807 808 DELAY(100000); 809 810 /* Put some data in the mbuf */ 811 812 eh = mtod(m0, struct ether_header *); 813 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 814 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 815 eh->ether_type = htons(ETHERTYPE_IP); 816 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 817 818 /* 819 * Queue the packet, start transmission. 820 * Note: ifq_handoff() ultimately calls re_start() for us. 821 */ 822 823 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 824 error = ifq_handoff(ifp, m0, NULL); 825 if (error) { 826 m0 = NULL; 827 goto done; 828 } 829 m0 = NULL; 830 831 /* Wait for it to propagate through the chip */ 832 833 DELAY(100000); 834 for (i = 0; i < RE_TIMEOUT; i++) { 835 status = CSR_READ_2(sc, RE_ISR); 836 CSR_WRITE_2(sc, RE_ISR, status); 837 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 838 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 839 break; 840 DELAY(10); 841 } 842 843 if (i == RE_TIMEOUT) { 844 if_printf(ifp, "diagnostic failed to receive packet " 845 "in loopback mode\n"); 846 error = EIO; 847 goto done; 848 } 849 850 /* 851 * The packet should have been dumped into the first 852 * entry in the RX DMA ring. Grab it from there. 853 */ 854 855 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 856 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 857 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, sc->re_ldata.re_rx_dmamap[0], 858 BUS_DMASYNC_POSTREAD); 859 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 860 sc->re_ldata.re_rx_dmamap[0]); 861 862 m0 = sc->re_ldata.re_rx_mbuf[0]; 863 sc->re_ldata.re_rx_mbuf[0] = NULL; 864 eh = mtod(m0, struct ether_header *); 865 866 cur_rx = &sc->re_ldata.re_rx_list[0]; 867 total_len = RE_RXBYTES(cur_rx); 868 rxstat = le32toh(cur_rx->re_cmdstat); 869 870 if (total_len != ETHER_MIN_LEN) { 871 if_printf(ifp, "diagnostic failed, received short packet\n"); 872 error = EIO; 873 goto done; 874 } 875 876 /* Test that the received packet data matches what we sent. */ 877 878 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 879 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 880 be16toh(eh->ether_type) != ETHERTYPE_IP) { 881 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 882 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 883 dst, ":", src, ":", ETHERTYPE_IP); 884 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 885 eh->ether_dhost, ":", eh->ether_shost, ":", 886 ntohs(eh->ether_type)); 887 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 888 "into a 64-bit PCI slot.\n"); 889 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 890 "for proper operation.\n"); 891 if_printf(ifp, "Read the re(4) man page for more details.\n"); 892 error = EIO; 893 } 894 895 done: 896 /* Turn interface off, release resources */ 897 898 sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE); 899 ifp->if_flags &= ~IFF_PROMISC; 900 re_stop(sc); 901 if (m0 != NULL) 902 m_freem(m0); 903 904 return (error); 905 } 906 #endif /* RE_DIAG */ 907 908 /* 909 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 910 * IDs against our list and return a device name if we find a match. 911 */ 912 static int 913 re_probe(device_t dev) 914 { 915 const struct re_type *t; 916 const struct re_hwrev *hw_rev; 917 struct re_softc *sc; 918 int rid; 919 uint32_t hwrev, macmode, txcfg; 920 uint16_t vendor, product; 921 922 vendor = pci_get_vendor(dev); 923 product = pci_get_device(dev); 924 925 /* 926 * Only attach to rev.3 of the Linksys EG1032 adapter. 927 * Rev.2 is supported by sk(4). 928 */ 929 if (vendor == PCI_VENDOR_LINKSYS && 930 product == PCI_PRODUCT_LINKSYS_EG1032 && 931 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3) 932 return ENXIO; 933 934 if (vendor == PCI_VENDOR_REALTEK && 935 product == PCI_PRODUCT_REALTEK_RT8139 && 936 pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) { 937 /* Poor 8139 */ 938 return ENXIO; 939 } 940 941 for (t = re_devs; t->re_name != NULL; t++) { 942 if (product == t->re_did && vendor == t->re_vid) 943 break; 944 } 945 946 /* 947 * Check if we found a RealTek device. 948 */ 949 if (t->re_name == NULL) 950 return ENXIO; 951 952 /* 953 * Temporarily map the I/O space so we can read the chip ID register. 954 */ 955 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 956 rid = RE_PCI_LOIO; 957 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 958 RF_ACTIVE); 959 if (sc->re_res == NULL) { 960 device_printf(dev, "couldn't map ports/memory\n"); 961 kfree(sc, M_TEMP); 962 return ENXIO; 963 } 964 965 sc->re_btag = rman_get_bustag(sc->re_res); 966 sc->re_bhandle = rman_get_bushandle(sc->re_res); 967 968 txcfg = CSR_READ_4(sc, RE_TXCFG); 969 hwrev = txcfg & RE_TXCFG_HWREV; 970 macmode = txcfg & RE_TXCFG_MACMODE; 971 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 972 kfree(sc, M_TEMP); 973 974 /* 975 * and continue matching for the specific chip... 976 */ 977 for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) { 978 if (hw_rev->re_hwrev == hwrev) { 979 sc = device_get_softc(dev); 980 981 sc->re_hwrev = hw_rev->re_hwrev; 982 sc->re_macver = hw_rev->re_macver; 983 sc->re_caps = hw_rev->re_caps; 984 sc->re_maxmtu = hw_rev->re_maxmtu; 985 986 /* 987 * Apply chip property fixup 988 */ 989 switch (sc->re_hwrev) { 990 case RE_HWREV_8101E1: 991 case RE_HWREV_8101E2: 992 if (macmode == 0) 993 sc->re_macver = RE_MACVER_11; 994 else if (macmode == 0x200000) 995 sc->re_macver = RE_MACVER_12; 996 break; 997 case RE_HWREV_8102E: 998 case RE_HWREV_8102EL: 999 if (macmode == 0) 1000 sc->re_macver = RE_MACVER_13; 1001 else if (macmode == 0x100000) 1002 sc->re_macver = RE_MACVER_14; 1003 break; 1004 case RE_HWREV_8168B2: 1005 case RE_HWREV_8168B3: 1006 if (macmode == 0) 1007 sc->re_macver = RE_MACVER_22; 1008 break; 1009 case RE_HWREV_8168C: 1010 if (macmode == 0) 1011 sc->re_macver = RE_MACVER_24; 1012 else if (macmode == 0x200000) 1013 sc->re_macver = RE_MACVER_25; 1014 else if (macmode == 0x300000) 1015 sc->re_macver = RE_MACVER_27; 1016 break; 1017 case RE_HWREV_8168CP: 1018 if (macmode == 0) 1019 sc->re_macver = RE_MACVER_26; 1020 else if (macmode == 0x100000) 1021 sc->re_macver = RE_MACVER_28; 1022 break; 1023 } 1024 if (pci_is_pcie(dev)) 1025 sc->re_caps |= RE_C_PCIE; 1026 1027 device_set_desc(dev, t->re_name); 1028 return 0; 1029 } 1030 } 1031 1032 if (bootverbose) { 1033 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n", 1034 hwrev, macmode); 1035 } 1036 return ENXIO; 1037 } 1038 1039 static void 1040 re_dma_map_desc(void *xarg, bus_dma_segment_t *segs, int nsegs, 1041 bus_size_t mapsize, int error) 1042 { 1043 struct re_dmaload_arg *arg = xarg; 1044 int i; 1045 1046 if (error) 1047 return; 1048 1049 if (nsegs > arg->re_nsegs) { 1050 arg->re_nsegs = 0; 1051 return; 1052 } 1053 1054 arg->re_nsegs = nsegs; 1055 for (i = 0; i < nsegs; ++i) 1056 arg->re_segs[i] = segs[i]; 1057 } 1058 1059 /* 1060 * Map a single buffer address. 1061 */ 1062 1063 static void 1064 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1065 { 1066 uint32_t *addr; 1067 1068 if (error) 1069 return; 1070 1071 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1072 addr = arg; 1073 *addr = segs->ds_addr; 1074 } 1075 1076 static int 1077 re_allocmem(device_t dev) 1078 { 1079 struct re_softc *sc = device_get_softc(dev); 1080 int error, i; 1081 1082 /* 1083 * Allocate list data 1084 */ 1085 sc->re_ldata.re_tx_mbuf = 1086 kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *), 1087 M_DEVBUF, M_ZERO | M_WAITOK); 1088 1089 sc->re_ldata.re_rx_mbuf = 1090 kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *), 1091 M_DEVBUF, M_ZERO | M_WAITOK); 1092 1093 sc->re_ldata.re_rx_paddr = 1094 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t), 1095 M_DEVBUF, M_ZERO | M_WAITOK); 1096 1097 sc->re_ldata.re_tx_dmamap = 1098 kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t), 1099 M_DEVBUF, M_ZERO | M_WAITOK); 1100 1101 sc->re_ldata.re_rx_dmamap = 1102 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t), 1103 M_DEVBUF, M_ZERO | M_WAITOK); 1104 1105 /* 1106 * Allocate the parent bus DMA tag appropriate for PCI. 1107 */ 1108 error = bus_dma_tag_create(NULL, /* parent */ 1109 1, 0, /* alignment, boundary */ 1110 BUS_SPACE_MAXADDR, /* lowaddr */ 1111 BUS_SPACE_MAXADDR, /* highaddr */ 1112 NULL, NULL, /* filter, filterarg */ 1113 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 1114 0, /* nsegments */ 1115 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1116 0, /* flags */ 1117 &sc->re_parent_tag); 1118 if (error) { 1119 device_printf(dev, "could not allocate parent dma tag\n"); 1120 return error; 1121 } 1122 1123 /* Allocate tag for TX descriptor list. */ 1124 error = bus_dma_tag_create(sc->re_parent_tag, 1125 RE_RING_ALIGN, 0, 1126 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1127 NULL, NULL, 1128 RE_TX_LIST_SZ(sc), 1, RE_TX_LIST_SZ(sc), 1129 0, &sc->re_ldata.re_tx_list_tag); 1130 if (error) { 1131 device_printf(dev, "could not allocate TX ring dma tag\n"); 1132 return(error); 1133 } 1134 1135 /* Allocate DMA'able memory for the TX ring */ 1136 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag, 1137 (void **)&sc->re_ldata.re_tx_list, 1138 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1139 &sc->re_ldata.re_tx_list_map); 1140 if (error) { 1141 device_printf(dev, "could not allocate TX ring\n"); 1142 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1143 sc->re_ldata.re_tx_list_tag = NULL; 1144 return(error); 1145 } 1146 1147 /* Load the map for the TX ring. */ 1148 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag, 1149 sc->re_ldata.re_tx_list_map, 1150 sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc), 1151 re_dma_map_addr, &sc->re_ldata.re_tx_list_addr, 1152 BUS_DMA_NOWAIT); 1153 if (error) { 1154 device_printf(dev, "could not get address of TX ring\n"); 1155 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1156 sc->re_ldata.re_tx_list, 1157 sc->re_ldata.re_tx_list_map); 1158 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1159 sc->re_ldata.re_tx_list_tag = NULL; 1160 return(error); 1161 } 1162 1163 /* Allocate tag for RX descriptor list. */ 1164 error = bus_dma_tag_create(sc->re_parent_tag, 1165 RE_RING_ALIGN, 0, 1166 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1167 NULL, NULL, 1168 RE_RX_LIST_SZ(sc), 1, RE_RX_LIST_SZ(sc), 1169 0, &sc->re_ldata.re_rx_list_tag); 1170 if (error) { 1171 device_printf(dev, "could not allocate RX ring dma tag\n"); 1172 return(error); 1173 } 1174 1175 /* Allocate DMA'able memory for the RX ring */ 1176 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag, 1177 (void **)&sc->re_ldata.re_rx_list, 1178 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1179 &sc->re_ldata.re_rx_list_map); 1180 if (error) { 1181 device_printf(dev, "could not allocate RX ring\n"); 1182 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1183 sc->re_ldata.re_rx_list_tag = NULL; 1184 return(error); 1185 } 1186 1187 /* Load the map for the RX ring. */ 1188 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag, 1189 sc->re_ldata.re_rx_list_map, 1190 sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc), 1191 re_dma_map_addr, &sc->re_ldata.re_rx_list_addr, 1192 BUS_DMA_NOWAIT); 1193 if (error) { 1194 device_printf(dev, "could not get address of RX ring\n"); 1195 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1196 sc->re_ldata.re_rx_list, 1197 sc->re_ldata.re_rx_list_map); 1198 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1199 sc->re_ldata.re_rx_list_tag = NULL; 1200 return(error); 1201 } 1202 1203 /* Allocate maps for TX mbufs. */ 1204 error = bus_dma_tag_create(sc->re_parent_tag, 1205 1, 0, 1206 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1207 NULL, NULL, 1208 RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES, 1209 BUS_DMA_ALLOCNOW, 1210 &sc->re_ldata.re_tx_mtag); 1211 if (error) { 1212 device_printf(dev, "could not allocate TX buf dma tag\n"); 1213 return(error); 1214 } 1215 1216 /* Create DMA maps for TX buffers */ 1217 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 1218 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag, 0, 1219 &sc->re_ldata.re_tx_dmamap[i]); 1220 if (error) { 1221 device_printf(dev, "can't create DMA map for TX buf\n"); 1222 re_freebufmem(sc, i, 0); 1223 return(error); 1224 } 1225 } 1226 1227 /* Allocate maps for RX mbufs. */ 1228 error = bus_dma_tag_create(sc->re_parent_tag, 1229 RE_RXBUF_ALIGN, 0, 1230 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1231 NULL, NULL, 1232 MCLBYTES, 1, MCLBYTES, 1233 BUS_DMA_ALLOCNOW, 1234 &sc->re_ldata.re_rx_mtag); 1235 if (error) { 1236 device_printf(dev, "could not allocate RX buf dma tag\n"); 1237 return(error); 1238 } 1239 1240 /* Create spare DMA map for RX */ 1241 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, 0, 1242 &sc->re_ldata.re_rx_spare); 1243 if (error) { 1244 device_printf(dev, "can't create spare DMA map for RX\n"); 1245 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1246 sc->re_ldata.re_rx_mtag = NULL; 1247 return error; 1248 } 1249 1250 /* Create DMA maps for RX buffers */ 1251 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1252 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, 0, 1253 &sc->re_ldata.re_rx_dmamap[i]); 1254 if (error) { 1255 device_printf(dev, "can't create DMA map for RX buf\n"); 1256 re_freebufmem(sc, sc->re_tx_desc_cnt, i); 1257 return(error); 1258 } 1259 } 1260 1261 /* Create jumbo buffer pool for RX if required */ 1262 if (sc->re_caps & RE_C_CONTIGRX) { 1263 error = re_jpool_alloc(sc); 1264 if (error) { 1265 re_jpool_free(sc); 1266 /* Disable jumbo frame support */ 1267 sc->re_maxmtu = ETHERMTU; 1268 } 1269 } 1270 return(0); 1271 } 1272 1273 static void 1274 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt) 1275 { 1276 int i; 1277 1278 /* Destroy all the RX and TX buffer maps */ 1279 if (sc->re_ldata.re_tx_mtag) { 1280 for (i = 0; i < tx_cnt; i++) { 1281 bus_dmamap_destroy(sc->re_ldata.re_tx_mtag, 1282 sc->re_ldata.re_tx_dmamap[i]); 1283 } 1284 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag); 1285 sc->re_ldata.re_tx_mtag = NULL; 1286 } 1287 1288 if (sc->re_ldata.re_rx_mtag) { 1289 for (i = 0; i < rx_cnt; i++) { 1290 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1291 sc->re_ldata.re_rx_dmamap[i]); 1292 } 1293 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1294 sc->re_ldata.re_rx_spare); 1295 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1296 sc->re_ldata.re_rx_mtag = NULL; 1297 } 1298 } 1299 1300 static void 1301 re_freemem(device_t dev) 1302 { 1303 struct re_softc *sc = device_get_softc(dev); 1304 1305 /* Unload and free the RX DMA ring memory and map */ 1306 if (sc->re_ldata.re_rx_list_tag) { 1307 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1308 sc->re_ldata.re_rx_list_map); 1309 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1310 sc->re_ldata.re_rx_list, 1311 sc->re_ldata.re_rx_list_map); 1312 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1313 } 1314 1315 /* Unload and free the TX DMA ring memory and map */ 1316 if (sc->re_ldata.re_tx_list_tag) { 1317 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1318 sc->re_ldata.re_tx_list_map); 1319 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1320 sc->re_ldata.re_tx_list, 1321 sc->re_ldata.re_tx_list_map); 1322 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1323 } 1324 1325 /* Free RX/TX buf DMA stuffs */ 1326 re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt); 1327 1328 /* Unload and free the stats buffer and map */ 1329 if (sc->re_ldata.re_stag) { 1330 bus_dmamap_unload(sc->re_ldata.re_stag, 1331 sc->re_ldata.re_rx_list_map); 1332 bus_dmamem_free(sc->re_ldata.re_stag, 1333 sc->re_ldata.re_stats, 1334 sc->re_ldata.re_smap); 1335 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1336 } 1337 1338 if (sc->re_caps & RE_C_CONTIGRX) 1339 re_jpool_free(sc); 1340 1341 if (sc->re_parent_tag) 1342 bus_dma_tag_destroy(sc->re_parent_tag); 1343 1344 if (sc->re_ldata.re_tx_mbuf != NULL) 1345 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF); 1346 if (sc->re_ldata.re_rx_mbuf != NULL) 1347 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF); 1348 if (sc->re_ldata.re_rx_paddr != NULL) 1349 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF); 1350 if (sc->re_ldata.re_tx_dmamap != NULL) 1351 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF); 1352 if (sc->re_ldata.re_rx_dmamap != NULL) 1353 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF); 1354 } 1355 1356 /* 1357 * Attach the interface. Allocate softc structures, do ifmedia 1358 * setup and ethernet/BPF attach. 1359 */ 1360 static int 1361 re_attach(device_t dev) 1362 { 1363 struct re_softc *sc = device_get_softc(dev); 1364 struct ifnet *ifp; 1365 uint8_t eaddr[ETHER_ADDR_LEN]; 1366 int error = 0, rid, qlen; 1367 1368 callout_init(&sc->re_timer); 1369 sc->re_dev = dev; 1370 1371 if (RE_IS_8139CP(sc)) { 1372 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP; 1373 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP; 1374 } else { 1375 sc->re_rx_desc_cnt = re_rx_desc_count; 1376 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX) 1377 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX; 1378 1379 sc->re_tx_desc_cnt = re_tx_desc_count; 1380 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX) 1381 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX; 1382 } 1383 1384 qlen = RE_IFQ_MAXLEN; 1385 if (sc->re_tx_desc_cnt > qlen) 1386 qlen = sc->re_tx_desc_cnt; 1387 1388 sc->re_rxbuf_size = MCLBYTES; 1389 sc->re_newbuf = re_newbuf_std; 1390 1391 sc->re_tx_time = 5; /* 125us */ 1392 sc->re_rx_time = 2; /* 50us */ 1393 if (sc->re_caps & RE_C_PCIE) 1394 sc->re_sim_time = 75; /* 75us */ 1395 else 1396 sc->re_sim_time = 125; /* 125us */ 1397 if (!RE_IS_8139CP(sc)) { 1398 /* simulated interrupt moderation */ 1399 sc->re_imtype = RE_IMTYPE_SIM; 1400 } else { 1401 sc->re_imtype = RE_IMTYPE_NONE; 1402 } 1403 re_config_imtype(sc, sc->re_imtype); 1404 1405 sysctl_ctx_init(&sc->re_sysctl_ctx); 1406 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx, 1407 SYSCTL_STATIC_CHILDREN(_hw), 1408 OID_AUTO, 1409 device_get_nameunit(dev), 1410 CTLFLAG_RD, 0, ""); 1411 if (sc->re_sysctl_tree == NULL) { 1412 device_printf(dev, "can't add sysctl node\n"); 1413 error = ENXIO; 1414 goto fail; 1415 } 1416 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1417 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1418 "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt, 1419 0, "RX desc count"); 1420 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1421 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1422 "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt, 1423 0, "TX desc count"); 1424 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1425 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1426 OID_AUTO, "sim_time", 1427 CTLTYPE_INT | CTLFLAG_RW, 1428 sc, 0, re_sysctl_simtime, "I", 1429 "Simulated interrupt moderation time (usec)."); 1430 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1431 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1432 OID_AUTO, "imtype", 1433 CTLTYPE_INT | CTLFLAG_RW, 1434 sc, 0, re_sysctl_imtype, "I", 1435 "Interrupt moderation type -- " 1436 "0:disable, 1:simulated, " 1437 "2:hardware(if supported)"); 1438 if (sc->re_caps & RE_C_HWIM) { 1439 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1440 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1441 OID_AUTO, "hw_rxtime", 1442 CTLTYPE_INT | CTLFLAG_RW, 1443 sc, 0, re_sysctl_rxtime, "I", 1444 "Hardware interrupt moderation time " 1445 "(unit: 25usec)."); 1446 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1447 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1448 OID_AUTO, "hw_txtime", 1449 CTLTYPE_INT | CTLFLAG_RW, 1450 sc, 0, re_sysctl_txtime, "I", 1451 "Hardware interrupt moderation time " 1452 "(unit: 25usec)."); 1453 } 1454 1455 #ifndef BURN_BRIDGES 1456 /* 1457 * Handle power management nonsense. 1458 */ 1459 1460 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1461 uint32_t membase, irq; 1462 1463 /* Save important PCI config data. */ 1464 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1465 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1466 1467 /* Reset the power state. */ 1468 device_printf(dev, "chip is in D%d power mode " 1469 "-- setting to D0\n", pci_get_powerstate(dev)); 1470 1471 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1472 1473 /* Restore PCI config data. */ 1474 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1475 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1476 } 1477 #endif 1478 /* 1479 * Map control/status registers. 1480 */ 1481 pci_enable_busmaster(dev); 1482 1483 rid = RE_PCI_LOIO; 1484 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1485 RF_ACTIVE); 1486 1487 if (sc->re_res == NULL) { 1488 device_printf(dev, "couldn't map ports\n"); 1489 error = ENXIO; 1490 goto fail; 1491 } 1492 1493 sc->re_btag = rman_get_bustag(sc->re_res); 1494 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1495 1496 /* Allocate interrupt */ 1497 rid = 0; 1498 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1499 RF_SHAREABLE | RF_ACTIVE); 1500 1501 if (sc->re_irq == NULL) { 1502 device_printf(dev, "couldn't map interrupt\n"); 1503 error = ENXIO; 1504 goto fail; 1505 } 1506 1507 /* Reset the adapter. */ 1508 re_reset(sc, 0); 1509 1510 if (RE_IS_8139CP(sc)) { 1511 sc->re_bus_speed = 33; /* XXX */ 1512 } else if (sc->re_caps & RE_C_PCIE) { 1513 sc->re_bus_speed = 125; 1514 } else { 1515 uint8_t cfg2; 1516 1517 cfg2 = CSR_READ_1(sc, RE_CFG2); 1518 switch (cfg2 & RE_CFG2_PCICLK_MASK) { 1519 case RE_CFG2_PCICLK_33MHZ: 1520 sc->re_bus_speed = 33; 1521 break; 1522 case RE_CFG2_PCICLK_66MHZ: 1523 sc->re_bus_speed = 66; 1524 break; 1525 default: 1526 device_printf(dev, "unknown bus speed, assume 33MHz\n"); 1527 sc->re_bus_speed = 33; 1528 break; 1529 } 1530 if (cfg2 & RE_CFG2_PCI64) 1531 sc->re_caps |= RE_C_PCI64; 1532 } 1533 device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; " 1534 "PCI%s %dMHz\n", 1535 sc->re_hwrev, sc->re_macver, 1536 (sc->re_caps & RE_C_PCIE) ? 1537 "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"), 1538 sc->re_bus_speed); 1539 1540 /* 1541 * NOTE: 1542 * DO NOT try to adjust config1 and config5 which was spotted in 1543 * Realtek's Linux drivers. It will _permanently_ damage certain 1544 * cards EEPROM, e.g. one of my 8168B (0x38000000) card ... 1545 */ 1546 1547 re_get_eaddr(sc, eaddr); 1548 1549 if (!RE_IS_8139CP(sc)) { 1550 /* Set RX length mask */ 1551 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1552 sc->re_txstart = RE_GTXSTART; 1553 } else { 1554 /* Set RX length mask */ 1555 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1556 sc->re_txstart = RE_TXSTART; 1557 } 1558 1559 /* Allocate DMA stuffs */ 1560 error = re_allocmem(dev); 1561 if (error) 1562 goto fail; 1563 1564 /* 1565 * Apply some magic PCI settings from Realtek ... 1566 */ 1567 if (RE_IS_8169(sc)) { 1568 CSR_WRITE_1(sc, 0x82, 1); 1569 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1); 1570 } 1571 pci_write_config(dev, PCIR_LATTIMER, 0x40, 1); 1572 1573 if (sc->re_caps & RE_C_MAC2) { 1574 /* 1575 * Following part is extracted from Realtek BSD driver v176. 1576 * However, this does _not_ make much/any sense: 1577 * 8168C's PCI Express device control is located at 0x78, 1578 * so the reading from 0x79 (higher part of 0x78) and setting 1579 * the 4~6bits intend to enlarge the "max read request size" 1580 * (we will do it). The content of the rest part of this 1581 * register is not meaningful to other PCI registers, so 1582 * writing the value to 0x54 could be completely wrong. 1583 * 0x80 is the lower part of PCI Express device status, non- 1584 * reserved bits are RW1C, writing 0 to them will not have 1585 * any effect at all. 1586 */ 1587 #ifdef foo 1588 uint8_t val; 1589 1590 val = pci_read_config(dev, 0x79, 1); 1591 val = (val & ~0x70) | 0x50; 1592 pci_write_config(dev, 0x54, val, 1); 1593 pci_write_config(dev, 0x80, 0, 1); 1594 #endif 1595 } 1596 1597 /* 1598 * Apply some PHY fixup from Realtek ... 1599 */ 1600 if (sc->re_hwrev == RE_HWREV_8110S) { 1601 CSR_WRITE_1(sc, 0x82, 1); 1602 re_miibus_writereg(dev, 1, 0xb, 0); 1603 } 1604 if (sc->re_caps & RE_C_PHYPMGT) { 1605 /* Power up PHY */ 1606 re_miibus_writereg(dev, 1, 0x1f, 0); 1607 re_miibus_writereg(dev, 1, 0xe, 0); 1608 } 1609 1610 /* Do MII setup */ 1611 if (mii_phy_probe(dev, &sc->re_miibus, 1612 re_ifmedia_upd, re_ifmedia_sts)) { 1613 device_printf(dev, "MII without any phy!\n"); 1614 error = ENXIO; 1615 goto fail; 1616 } 1617 1618 ifp = &sc->arpcom.ac_if; 1619 ifp->if_softc = sc; 1620 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1621 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1622 ifp->if_ioctl = re_ioctl; 1623 ifp->if_start = re_start; 1624 #ifdef DEVICE_POLLING 1625 ifp->if_poll = re_poll; 1626 #endif 1627 ifp->if_watchdog = re_watchdog; 1628 ifp->if_init = re_init; 1629 if (!RE_IS_8139CP(sc)) /* XXX */ 1630 ifp->if_baudrate = 1000000000; 1631 else 1632 ifp->if_baudrate = 100000000; 1633 ifq_set_maxlen(&ifp->if_snd, qlen); 1634 ifq_set_ready(&ifp->if_snd); 1635 1636 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1637 if (sc->re_caps & RE_C_HWCSUM) 1638 ifp->if_capabilities |= IFCAP_HWCSUM; 1639 1640 ifp->if_capenable = ifp->if_capabilities; 1641 if (ifp->if_capabilities & IFCAP_HWCSUM) 1642 ifp->if_hwassist = RE_CSUM_FEATURES; 1643 else 1644 ifp->if_hwassist = 0; 1645 1646 /* 1647 * Call MI attach routine. 1648 */ 1649 ether_ifattach(ifp, eaddr, NULL); 1650 1651 #ifdef RE_DIAG 1652 /* 1653 * Perform hardware diagnostic on the original RTL8169. 1654 * Some 32-bit cards were incorrectly wired and would 1655 * malfunction if plugged into a 64-bit slot. 1656 */ 1657 if (sc->re_hwrev == RE_HWREV_8169) { 1658 lwkt_serialize_enter(ifp->if_serializer); 1659 error = re_diag(sc); 1660 lwkt_serialize_exit(ifp->if_serializer); 1661 1662 if (error) { 1663 device_printf(dev, "hardware diagnostic failure\n"); 1664 ether_ifdetach(ifp); 1665 goto fail; 1666 } 1667 } 1668 #endif /* RE_DIAG */ 1669 1670 /* Hook interrupt last to avoid having to lock softc */ 1671 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc, 1672 &sc->re_intrhand, ifp->if_serializer); 1673 1674 if (error) { 1675 device_printf(dev, "couldn't set up irq\n"); 1676 ether_ifdetach(ifp); 1677 goto fail; 1678 } 1679 1680 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->re_irq)); 1681 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 1682 1683 fail: 1684 if (error) 1685 re_detach(dev); 1686 1687 return (error); 1688 } 1689 1690 /* 1691 * Shutdown hardware and free up resources. This can be called any 1692 * time after the mutex has been initialized. It is called in both 1693 * the error case in attach and the normal detach case so it needs 1694 * to be careful about only freeing resources that have actually been 1695 * allocated. 1696 */ 1697 static int 1698 re_detach(device_t dev) 1699 { 1700 struct re_softc *sc = device_get_softc(dev); 1701 struct ifnet *ifp = &sc->arpcom.ac_if; 1702 1703 /* These should only be active if attach succeeded */ 1704 if (device_is_attached(dev)) { 1705 lwkt_serialize_enter(ifp->if_serializer); 1706 re_stop(sc); 1707 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1708 lwkt_serialize_exit(ifp->if_serializer); 1709 1710 ether_ifdetach(ifp); 1711 } 1712 if (sc->re_miibus) 1713 device_delete_child(dev, sc->re_miibus); 1714 bus_generic_detach(dev); 1715 1716 if (sc->re_sysctl_tree != NULL) 1717 sysctl_ctx_free(&sc->re_sysctl_ctx); 1718 1719 if (sc->re_irq) 1720 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq); 1721 if (sc->re_res) { 1722 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, 1723 sc->re_res); 1724 } 1725 1726 /* Free DMA stuffs */ 1727 re_freemem(dev); 1728 1729 return(0); 1730 } 1731 1732 static void 1733 re_setup_rxdesc(struct re_softc *sc, int idx) 1734 { 1735 bus_addr_t paddr; 1736 uint32_t cmdstat; 1737 struct re_desc *d; 1738 1739 paddr = sc->re_ldata.re_rx_paddr[idx]; 1740 d = &sc->re_ldata.re_rx_list[idx]; 1741 1742 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr)); 1743 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr)); 1744 1745 cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN; 1746 if (idx == (sc->re_rx_desc_cnt - 1)) 1747 cmdstat |= RE_RDESC_CMD_EOR; 1748 d->re_cmdstat = htole32(cmdstat); 1749 } 1750 1751 static int 1752 re_newbuf_std(struct re_softc *sc, int idx, int init) 1753 { 1754 struct re_dmaload_arg arg; 1755 bus_dma_segment_t seg; 1756 bus_dmamap_t map; 1757 struct mbuf *m; 1758 int error; 1759 1760 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1761 if (m == NULL) { 1762 error = ENOBUFS; 1763 1764 if (init) { 1765 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n"); 1766 return error; 1767 } else { 1768 goto back; 1769 } 1770 } 1771 m->m_len = m->m_pkthdr.len = MCLBYTES; 1772 1773 /* 1774 * NOTE: 1775 * re(4) chips need address of the receive buffer to be 8-byte 1776 * aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1777 */ 1778 1779 arg.re_nsegs = 1; 1780 arg.re_segs = &seg; 1781 error = bus_dmamap_load_mbuf(sc->re_ldata.re_rx_mtag, 1782 sc->re_ldata.re_rx_spare, m, 1783 re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1784 if (error || arg.re_nsegs == 0) { 1785 if (!error) { 1786 if_printf(&sc->arpcom.ac_if, "too many segments?!\n"); 1787 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 1788 sc->re_ldata.re_rx_spare); 1789 error = EFBIG; 1790 } 1791 m_freem(m); 1792 1793 if (init) { 1794 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 1795 return error; 1796 } else { 1797 goto back; 1798 } 1799 } 1800 1801 if (!init) { 1802 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, 1803 sc->re_ldata.re_rx_dmamap[idx], 1804 BUS_DMASYNC_POSTREAD); 1805 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 1806 sc->re_ldata.re_rx_dmamap[idx]); 1807 } 1808 sc->re_ldata.re_rx_mbuf[idx] = m; 1809 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr; 1810 1811 map = sc->re_ldata.re_rx_dmamap[idx]; 1812 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare; 1813 sc->re_ldata.re_rx_spare = map; 1814 back: 1815 re_setup_rxdesc(sc, idx); 1816 return error; 1817 } 1818 1819 static int 1820 re_newbuf_jumbo(struct re_softc *sc, int idx, int init) 1821 { 1822 struct mbuf *m; 1823 struct re_jbuf *jbuf; 1824 int error = 0; 1825 1826 MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA); 1827 if (m == NULL) { 1828 error = ENOBUFS; 1829 if (init) { 1830 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n"); 1831 return error; 1832 } else { 1833 goto back; 1834 } 1835 } 1836 1837 jbuf = re_jbuf_alloc(sc); 1838 if (jbuf == NULL) { 1839 m_freem(m); 1840 1841 error = ENOBUFS; 1842 if (init) { 1843 if_printf(&sc->arpcom.ac_if, "jpool is empty\n"); 1844 return error; 1845 } else { 1846 goto back; 1847 } 1848 } 1849 1850 m->m_ext.ext_arg = jbuf; 1851 m->m_ext.ext_buf = jbuf->re_buf; 1852 m->m_ext.ext_free = re_jbuf_free; 1853 m->m_ext.ext_ref = re_jbuf_ref; 1854 m->m_ext.ext_size = sc->re_rxbuf_size; 1855 1856 m->m_data = m->m_ext.ext_buf; 1857 m->m_flags |= M_EXT; 1858 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1859 1860 /* 1861 * NOTE: 1862 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer 1863 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1864 */ 1865 1866 sc->re_ldata.re_rx_mbuf[idx] = m; 1867 sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr; 1868 back: 1869 re_setup_rxdesc(sc, idx); 1870 return error; 1871 } 1872 1873 static int 1874 re_tx_list_init(struct re_softc *sc) 1875 { 1876 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 1877 1878 /* Flush the TX descriptors */ 1879 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1880 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 1881 1882 sc->re_ldata.re_tx_prodidx = 0; 1883 sc->re_ldata.re_tx_considx = 0; 1884 sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt; 1885 1886 return(0); 1887 } 1888 1889 static int 1890 re_rx_list_init(struct re_softc *sc) 1891 { 1892 int i, error; 1893 1894 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc)); 1895 1896 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1897 error = sc->re_newbuf(sc, i, 1); 1898 if (error) 1899 return(error); 1900 } 1901 1902 /* Flush the RX descriptors */ 1903 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1904 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); 1905 1906 sc->re_ldata.re_rx_prodidx = 0; 1907 sc->re_head = sc->re_tail = NULL; 1908 1909 return(0); 1910 } 1911 1912 #define RE_IP4_PACKET 0x1 1913 #define RE_TCP_PACKET 0x2 1914 #define RE_UDP_PACKET 0x4 1915 1916 static __inline uint8_t 1917 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl) 1918 { 1919 uint8_t packet_type = 0; 1920 1921 if (sc->re_caps & RE_C_MAC2) { 1922 if (rxctrl & RE_RDESC_CTL_PROTOIP4) 1923 packet_type |= RE_IP4_PACKET; 1924 } else { 1925 if (rxstat & RE_RDESC_STAT_PROTOID) 1926 packet_type |= RE_IP4_PACKET; 1927 } 1928 if (RE_TCPPKT(rxstat)) 1929 packet_type |= RE_TCP_PACKET; 1930 else if (RE_UDPPKT(rxstat)) 1931 packet_type |= RE_UDP_PACKET; 1932 return packet_type; 1933 } 1934 1935 /* 1936 * RX handler for C+ and 8169. For the gigE chips, we support 1937 * the reception of jumbo frames that have been fragmented 1938 * across multiple 2K mbuf cluster buffers. 1939 */ 1940 static int 1941 re_rxeof(struct re_softc *sc) 1942 { 1943 struct ifnet *ifp = &sc->arpcom.ac_if; 1944 struct mbuf *m; 1945 struct re_desc *cur_rx; 1946 uint32_t rxstat, rxctrl; 1947 int i, total_len, rx = 0; 1948 struct mbuf_chain chain[MAXCPU]; 1949 1950 /* Invalidate the descriptor memory */ 1951 1952 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1953 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 1954 1955 ether_input_chain_init(chain); 1956 1957 for (i = sc->re_ldata.re_rx_prodidx; 1958 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) { 1959 cur_rx = &sc->re_ldata.re_rx_list[i]; 1960 m = sc->re_ldata.re_rx_mbuf[i]; 1961 total_len = RE_RXBYTES(cur_rx); 1962 rxstat = le32toh(cur_rx->re_cmdstat); 1963 rxctrl = le32toh(cur_rx->re_control); 1964 1965 rx = 1; 1966 1967 #ifdef INVARIANTS 1968 if (sc->re_flags & RE_F_USE_JPOOL) 1969 KKASSERT(rxstat & RE_RDESC_STAT_EOF); 1970 #endif 1971 1972 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1973 if (sc->re_flags & RE_F_DROP_RXFRAG) { 1974 re_setup_rxdesc(sc, i); 1975 continue; 1976 } 1977 1978 if (sc->re_newbuf(sc, i, 0)) { 1979 /* Drop upcoming fragments */ 1980 sc->re_flags |= RE_F_DROP_RXFRAG; 1981 continue; 1982 } 1983 1984 m->m_len = MCLBYTES; 1985 if (sc->re_head == NULL) { 1986 sc->re_head = sc->re_tail = m; 1987 } else { 1988 sc->re_tail->m_next = m; 1989 sc->re_tail = m; 1990 } 1991 continue; 1992 } else if (sc->re_flags & RE_F_DROP_RXFRAG) { 1993 /* 1994 * Last fragment of a multi-fragment packet. 1995 * 1996 * Since error already happened, this fragment 1997 * must be dropped as well as the fragment chain. 1998 */ 1999 re_setup_rxdesc(sc, i); 2000 re_free_rxchain(sc); 2001 sc->re_flags &= ~RE_F_DROP_RXFRAG; 2002 continue; 2003 } 2004 2005 /* 2006 * NOTE: for the 8139C+, the frame length field 2007 * is always 12 bits in size, but for the gigE chips, 2008 * it is 13 bits (since the max RX frame length is 16K). 2009 * Unfortunately, all 32 bits in the status word 2010 * were already used, so to make room for the extra 2011 * length bit, RealTek took out the 'frame alignment 2012 * error' bit and shifted the other status bits 2013 * over one slot. The OWN, EOR, FS and LS bits are 2014 * still in the same places. We have already extracted 2015 * the frame length and checked the OWN bit, so rather 2016 * than using an alternate bit mapping, we shift the 2017 * status bits one space to the right so we can evaluate 2018 * them using the 8169 status as though it was in the 2019 * same format as that of the 8139C+. 2020 */ 2021 if (!RE_IS_8139CP(sc)) 2022 rxstat >>= 1; 2023 2024 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 2025 ifp->if_ierrors++; 2026 /* 2027 * If this is part of a multi-fragment packet, 2028 * discard all the pieces. 2029 */ 2030 re_free_rxchain(sc); 2031 re_setup_rxdesc(sc, i); 2032 continue; 2033 } 2034 2035 /* 2036 * If allocating a replacement mbuf fails, 2037 * reload the current one. 2038 */ 2039 2040 if (sc->re_newbuf(sc, i, 0)) { 2041 ifp->if_ierrors++; 2042 continue; 2043 } 2044 2045 if (sc->re_head != NULL) { 2046 m->m_len = total_len % MCLBYTES; 2047 /* 2048 * Special case: if there's 4 bytes or less 2049 * in this buffer, the mbuf can be discarded: 2050 * the last 4 bytes is the CRC, which we don't 2051 * care about anyway. 2052 */ 2053 if (m->m_len <= ETHER_CRC_LEN) { 2054 sc->re_tail->m_len -= 2055 (ETHER_CRC_LEN - m->m_len); 2056 m_freem(m); 2057 } else { 2058 m->m_len -= ETHER_CRC_LEN; 2059 sc->re_tail->m_next = m; 2060 } 2061 m = sc->re_head; 2062 sc->re_head = sc->re_tail = NULL; 2063 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2064 } else { 2065 m->m_pkthdr.len = m->m_len = 2066 (total_len - ETHER_CRC_LEN); 2067 } 2068 2069 ifp->if_ipackets++; 2070 m->m_pkthdr.rcvif = ifp; 2071 2072 /* Do RX checksumming if enabled */ 2073 2074 if (ifp->if_capenable & IFCAP_RXCSUM) { 2075 uint8_t packet_type; 2076 2077 packet_type = re_packet_type(sc, rxstat, rxctrl); 2078 2079 /* Check IP header checksum */ 2080 if (packet_type & RE_IP4_PACKET) { 2081 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2082 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 2083 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2084 } 2085 2086 /* Check TCP/UDP checksum */ 2087 if (((packet_type & RE_TCP_PACKET) && 2088 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 2089 ((packet_type & RE_UDP_PACKET) && 2090 (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) { 2091 m->m_pkthdr.csum_flags |= 2092 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 2093 CSUM_FRAG_NOT_CHECKED; 2094 m->m_pkthdr.csum_data = 0xffff; 2095 } 2096 } 2097 2098 if (rxctrl & RE_RDESC_CTL_HASTAG) { 2099 m->m_flags |= M_VLANTAG; 2100 m->m_pkthdr.ether_vlantag = 2101 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA)); 2102 } 2103 ether_input_chain(ifp, m, chain); 2104 } 2105 2106 ether_input_dispatch(chain); 2107 2108 /* Flush the RX DMA ring */ 2109 2110 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 2111 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); 2112 2113 sc->re_ldata.re_rx_prodidx = i; 2114 2115 return rx; 2116 } 2117 2118 #undef RE_IP4_PACKET 2119 #undef RE_TCP_PACKET 2120 #undef RE_UDP_PACKET 2121 2122 static int 2123 re_tx_collect(struct re_softc *sc) 2124 { 2125 struct ifnet *ifp = &sc->arpcom.ac_if; 2126 uint32_t txstat; 2127 int idx, tx = 0; 2128 2129 /* Invalidate the TX descriptor list */ 2130 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 2131 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD); 2132 2133 for (idx = sc->re_ldata.re_tx_considx; 2134 sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt; 2135 RE_TXDESC_INC(sc, idx)) { 2136 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 2137 if (txstat & RE_TDESC_CMD_OWN) 2138 break; 2139 2140 tx = 1; 2141 2142 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0; 2143 2144 /* 2145 * We only stash mbufs in the last descriptor 2146 * in a fragment chain, which also happens to 2147 * be the only place where the TX status bits 2148 * are valid. 2149 */ 2150 if (txstat & RE_TDESC_CMD_EOF) { 2151 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2152 sc->re_ldata.re_tx_dmamap[idx]); 2153 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 2154 sc->re_ldata.re_tx_mbuf[idx] = NULL; 2155 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 2156 RE_TDESC_STAT_COLCNT)) 2157 ifp->if_collisions++; 2158 if (txstat & RE_TDESC_STAT_TXERRSUM) 2159 ifp->if_oerrors++; 2160 else 2161 ifp->if_opackets++; 2162 } 2163 sc->re_ldata.re_tx_free++; 2164 } 2165 sc->re_ldata.re_tx_considx = idx; 2166 2167 return tx; 2168 } 2169 2170 static int 2171 re_txeof(struct re_softc *sc) 2172 { 2173 struct ifnet *ifp = &sc->arpcom.ac_if; 2174 int tx; 2175 2176 tx = re_tx_collect(sc); 2177 2178 /* There is enough free TX descs */ 2179 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE) 2180 ifp->if_flags &= ~IFF_OACTIVE; 2181 2182 /* 2183 * Some chips will ignore a second TX request issued while an 2184 * existing transmission is in progress. If the transmitter goes 2185 * idle but there are still packets waiting to be sent, we need 2186 * to restart the channel here to flush them out. This only seems 2187 * to be required with the PCIe devices. 2188 */ 2189 if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt) 2190 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2191 else 2192 ifp->if_timer = 0; 2193 2194 return tx; 2195 } 2196 2197 static void 2198 re_tick(void *xsc) 2199 { 2200 struct re_softc *sc = xsc; 2201 2202 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2203 re_tick_serialized(xsc); 2204 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2205 } 2206 2207 static void 2208 re_tick_serialized(void *xsc) 2209 { 2210 struct re_softc *sc = xsc; 2211 struct ifnet *ifp = &sc->arpcom.ac_if; 2212 struct mii_data *mii; 2213 2214 ASSERT_SERIALIZED(ifp->if_serializer); 2215 2216 mii = device_get_softc(sc->re_miibus); 2217 mii_tick(mii); 2218 if (sc->re_flags & RE_F_LINKED) { 2219 if (!(mii->mii_media_status & IFM_ACTIVE)) 2220 sc->re_flags &= ~RE_F_LINKED; 2221 } else { 2222 if (mii->mii_media_status & IFM_ACTIVE && 2223 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2224 sc->re_flags |= RE_F_LINKED; 2225 if (!ifq_is_empty(&ifp->if_snd)) 2226 if_devstart(ifp); 2227 } 2228 } 2229 2230 callout_reset(&sc->re_timer, hz, re_tick, sc); 2231 } 2232 2233 #ifdef DEVICE_POLLING 2234 2235 static void 2236 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2237 { 2238 struct re_softc *sc = ifp->if_softc; 2239 2240 ASSERT_SERIALIZED(ifp->if_serializer); 2241 2242 switch(cmd) { 2243 case POLL_REGISTER: 2244 /* disable interrupts */ 2245 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2246 break; 2247 2248 case POLL_DEREGISTER: 2249 /* enable interrupts */ 2250 re_setup_intr(sc, 1, sc->re_imtype); 2251 break; 2252 2253 default: 2254 sc->rxcycles = count; 2255 re_rxeof(sc); 2256 re_txeof(sc); 2257 2258 if (!ifq_is_empty(&ifp->if_snd)) 2259 if_devstart(ifp); 2260 2261 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2262 uint16_t status; 2263 2264 status = CSR_READ_2(sc, RE_ISR); 2265 if (status == 0xffff) 2266 return; 2267 if (status) 2268 CSR_WRITE_2(sc, RE_ISR, status); 2269 2270 /* 2271 * XXX check behaviour on receiver stalls. 2272 */ 2273 2274 if (status & RE_ISR_SYSTEM_ERR) 2275 re_init(sc); 2276 } 2277 break; 2278 } 2279 } 2280 #endif /* DEVICE_POLLING */ 2281 2282 static void 2283 re_intr(void *arg) 2284 { 2285 struct re_softc *sc = arg; 2286 struct ifnet *ifp = &sc->arpcom.ac_if; 2287 uint16_t status; 2288 int rx, tx; 2289 2290 ASSERT_SERIALIZED(ifp->if_serializer); 2291 2292 if ((sc->re_flags & RE_F_SUSPENDED) || 2293 (ifp->if_flags & IFF_RUNNING) == 0) 2294 return; 2295 2296 rx = tx = 0; 2297 for (;;) { 2298 status = CSR_READ_2(sc, RE_ISR); 2299 /* If the card has gone away the read returns 0xffff. */ 2300 if (status == 0xffff) 2301 break; 2302 if (status) 2303 CSR_WRITE_2(sc, RE_ISR, status); 2304 2305 if ((status & sc->re_intrs) == 0) 2306 break; 2307 2308 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR)) 2309 rx |= re_rxeof(sc); 2310 2311 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR)) 2312 tx |= re_txeof(sc); 2313 2314 if (status & RE_ISR_SYSTEM_ERR) 2315 re_init(sc); 2316 2317 if (status & RE_ISR_LINKCHG) { 2318 callout_stop(&sc->re_timer); 2319 re_tick_serialized(sc); 2320 } 2321 } 2322 2323 if (sc->re_imtype == RE_IMTYPE_SIM) { 2324 if ((sc->re_flags & RE_F_TIMER_INTR)) { 2325 if ((tx | rx) == 0) { 2326 /* 2327 * Nothing needs to be processed, fallback 2328 * to use TX/RX interrupts. 2329 */ 2330 re_setup_intr(sc, 1, RE_IMTYPE_NONE); 2331 2332 /* 2333 * Recollect, mainly to avoid the possible 2334 * race introduced by changing interrupt 2335 * masks. 2336 */ 2337 re_rxeof(sc); 2338 tx = re_txeof(sc); 2339 } else { 2340 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 2341 } 2342 } else if (tx | rx) { 2343 /* 2344 * Assume that using simulated interrupt moderation 2345 * (hardware timer based) could reduce the interript 2346 * rate. 2347 */ 2348 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 2349 } 2350 } 2351 2352 if (tx && !ifq_is_empty(&ifp->if_snd)) 2353 if_devstart(ifp); 2354 } 2355 2356 static int 2357 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0) 2358 { 2359 struct ifnet *ifp = &sc->arpcom.ac_if; 2360 struct mbuf *m; 2361 struct re_dmaload_arg arg; 2362 bus_dma_segment_t segs[RE_MAXSEGS]; 2363 bus_dmamap_t map; 2364 int error, maxsegs, idx, i; 2365 struct re_desc *d, *tx_ring; 2366 uint32_t cmd_csum, ctl_csum, vlantag; 2367 2368 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE, 2369 ("not enough free TX desc\n")); 2370 2371 m = *m_head; 2372 map = sc->re_ldata.re_tx_dmamap[*idx0]; 2373 2374 /* 2375 * Set up checksum offload. Note: checksum offload bits must 2376 * appear in all descriptors of a multi-descriptor transmit 2377 * attempt. (This is according to testing done with an 8169 2378 * chip. I'm not sure if this is a requirement or a bug.) 2379 */ 2380 cmd_csum = ctl_csum = 0; 2381 if (m->m_pkthdr.csum_flags & CSUM_IP) { 2382 cmd_csum |= RE_TDESC_CMD_IPCSUM; 2383 ctl_csum |= RE_TDESC_CTL_IPCSUM; 2384 } 2385 if (m->m_pkthdr.csum_flags & CSUM_TCP) { 2386 cmd_csum |= RE_TDESC_CMD_TCPCSUM; 2387 ctl_csum |= RE_TDESC_CTL_TCPCSUM; 2388 } 2389 if (m->m_pkthdr.csum_flags & CSUM_UDP) { 2390 cmd_csum |= RE_TDESC_CMD_UDPCSUM; 2391 ctl_csum |= RE_TDESC_CTL_UDPCSUM; 2392 } 2393 2394 /* For MAC2 chips, csum flags are set on re_control */ 2395 if (sc->re_caps & RE_C_MAC2) 2396 cmd_csum = 0; 2397 else 2398 ctl_csum = 0; 2399 2400 if ((sc->re_caps & RE_C_AUTOPAD) == 0) { 2401 /* 2402 * With some of the RealTek chips, using the checksum offload 2403 * support in conjunction with the autopadding feature results 2404 * in the transmission of corrupt frames. For example, if we 2405 * need to send a really small IP fragment that's less than 60 2406 * bytes in size, and IP header checksumming is enabled, the 2407 * resulting ethernet frame that appears on the wire will 2408 * have garbled payload. To work around this, if TX checksum 2409 * offload is enabled, we always manually pad short frames out 2410 * to the minimum ethernet frame size. 2411 * 2412 * Note: this appears unnecessary for TCP, and doing it for TCP 2413 * with PCIe adapters seems to result in bad checksums. 2414 */ 2415 if ((m->m_pkthdr.csum_flags & 2416 (CSUM_DELAY_IP | CSUM_DELAY_DATA)) && 2417 (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 && 2418 m->m_pkthdr.len < RE_MIN_FRAMELEN) { 2419 error = m_devpad(m, RE_MIN_FRAMELEN); 2420 if (error) 2421 goto back; 2422 } 2423 } 2424 2425 vlantag = 0; 2426 if (m->m_flags & M_VLANTAG) { 2427 vlantag = htobe16(m->m_pkthdr.ether_vlantag) | 2428 RE_TDESC_CTL_INSTAG; 2429 } 2430 2431 maxsegs = sc->re_ldata.re_tx_free; 2432 if (maxsegs > RE_MAXSEGS) 2433 maxsegs = RE_MAXSEGS; 2434 2435 arg.re_nsegs = maxsegs; 2436 arg.re_segs = segs; 2437 error = bus_dmamap_load_mbuf(sc->re_ldata.re_tx_mtag, map, m, 2438 re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2439 if (error && error != EFBIG) { 2440 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2441 goto back; 2442 } 2443 2444 /* 2445 * Too many segments to map, coalesce into a single mbuf 2446 */ 2447 if (!error && arg.re_nsegs == 0) { 2448 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, map); 2449 error = EFBIG; 2450 } 2451 if (error) { 2452 struct mbuf *m_new; 2453 2454 m_new = m_defrag(m, MB_DONTWAIT); 2455 if (m_new == NULL) { 2456 if_printf(ifp, "can't defrag TX mbuf\n"); 2457 error = ENOBUFS; 2458 goto back; 2459 } else { 2460 *m_head = m = m_new; 2461 } 2462 2463 arg.re_nsegs = maxsegs; 2464 arg.re_segs = segs; 2465 error = bus_dmamap_load_mbuf(sc->re_ldata.re_tx_mtag, map, m, 2466 re_dma_map_desc, &arg, 2467 BUS_DMA_NOWAIT); 2468 if (error || arg.re_nsegs == 0) { 2469 if (!error) { 2470 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, map); 2471 error = EFBIG; 2472 } 2473 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2474 goto back; 2475 } 2476 } 2477 bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE); 2478 2479 /* 2480 * Map the segment array into descriptors. We also keep track 2481 * of the end of the ring and set the end-of-ring bits as needed, 2482 * and we set the ownership bits in all except the very first 2483 * descriptor, whose ownership bits will be turned on later. 2484 */ 2485 tx_ring = sc->re_ldata.re_tx_list; 2486 idx = *idx0; 2487 i = 0; 2488 for (;;) { 2489 uint32_t cmdstat; 2490 2491 d = &tx_ring[idx]; 2492 2493 cmdstat = segs[i].ds_len; 2494 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 2495 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 2496 if (i == 0) 2497 cmdstat |= RE_TDESC_CMD_SOF; 2498 else 2499 cmdstat |= RE_TDESC_CMD_OWN; 2500 if (idx == (sc->re_tx_desc_cnt - 1)) 2501 cmdstat |= RE_TDESC_CMD_EOR; 2502 d->re_cmdstat = htole32(cmdstat | cmd_csum); 2503 d->re_control = htole32(ctl_csum | vlantag); 2504 2505 i++; 2506 if (i == arg.re_nsegs) 2507 break; 2508 RE_TXDESC_INC(sc, idx); 2509 } 2510 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 2511 2512 /* Transfer ownership of packet to the chip. */ 2513 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2514 if (*idx0 != idx) 2515 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2516 2517 /* 2518 * Insure that the map for this transmission 2519 * is placed at the array index of the last descriptor 2520 * in this chain. 2521 */ 2522 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx]; 2523 sc->re_ldata.re_tx_dmamap[idx] = map; 2524 2525 sc->re_ldata.re_tx_mbuf[idx] = m; 2526 sc->re_ldata.re_tx_free -= arg.re_nsegs; 2527 2528 RE_TXDESC_INC(sc, idx); 2529 *idx0 = idx; 2530 back: 2531 if (error) { 2532 m_freem(m); 2533 *m_head = NULL; 2534 } 2535 return error; 2536 } 2537 2538 /* 2539 * Main transmit routine for C+ and gigE NICs. 2540 */ 2541 2542 static void 2543 re_start(struct ifnet *ifp) 2544 { 2545 struct re_softc *sc = ifp->if_softc; 2546 struct mbuf *m_head; 2547 int idx, need_trans, oactive, error; 2548 2549 ASSERT_SERIALIZED(ifp->if_serializer); 2550 2551 if ((sc->re_flags & RE_F_LINKED) == 0) { 2552 ifq_purge(&ifp->if_snd); 2553 return; 2554 } 2555 2556 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 2557 return; 2558 2559 idx = sc->re_ldata.re_tx_prodidx; 2560 2561 need_trans = 0; 2562 oactive = 0; 2563 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 2564 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2565 if (!oactive) { 2566 if (re_tx_collect(sc)) { 2567 oactive = 1; 2568 continue; 2569 } 2570 } 2571 ifp->if_flags |= IFF_OACTIVE; 2572 break; 2573 } 2574 2575 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2576 if (m_head == NULL) 2577 break; 2578 2579 error = re_encap(sc, &m_head, &idx); 2580 if (error) { 2581 /* m_head is freed by re_encap(), if we reach here */ 2582 ifp->if_oerrors++; 2583 2584 if (error == EFBIG && !oactive) { 2585 if (re_tx_collect(sc)) { 2586 oactive = 1; 2587 continue; 2588 } 2589 } 2590 ifp->if_flags |= IFF_OACTIVE; 2591 break; 2592 } 2593 2594 oactive = 0; 2595 need_trans = 1; 2596 2597 /* 2598 * If there's a BPF listener, bounce a copy of this frame 2599 * to him. 2600 */ 2601 ETHER_BPF_MTAP(ifp, m_head); 2602 } 2603 2604 if (!need_trans) 2605 return; 2606 2607 /* Flush the TX descriptors */ 2608 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 2609 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 2610 2611 sc->re_ldata.re_tx_prodidx = idx; 2612 2613 /* 2614 * RealTek put the TX poll request register in a different 2615 * location on the 8169 gigE chip. I don't know why. 2616 */ 2617 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2618 2619 /* 2620 * Set a timeout in case the chip goes out to lunch. 2621 */ 2622 ifp->if_timer = 5; 2623 } 2624 2625 static void 2626 re_init(void *xsc) 2627 { 2628 struct re_softc *sc = xsc; 2629 struct ifnet *ifp = &sc->arpcom.ac_if; 2630 struct mii_data *mii; 2631 int error, framelen; 2632 2633 ASSERT_SERIALIZED(ifp->if_serializer); 2634 2635 mii = device_get_softc(sc->re_miibus); 2636 2637 /* 2638 * Cancel pending I/O and free all RX/TX buffers. 2639 */ 2640 re_stop(sc); 2641 2642 if (sc->re_caps & RE_C_CONTIGRX) { 2643 if (ifp->if_mtu > ETHERMTU) { 2644 KKASSERT(sc->re_ldata.re_jbuf != NULL); 2645 sc->re_flags |= RE_F_USE_JPOOL; 2646 sc->re_rxbuf_size = RE_FRAMELEN_MAX; 2647 sc->re_newbuf = re_newbuf_jumbo; 2648 } else { 2649 sc->re_flags &= ~RE_F_USE_JPOOL; 2650 sc->re_rxbuf_size = MCLBYTES; 2651 sc->re_newbuf = re_newbuf_std; 2652 } 2653 } 2654 2655 /* 2656 * Adjust max read request size according to MTU; mainly to 2657 * improve TX performance for common case (ETHERMTU) on GigE 2658 * NICs. However, this could _not_ be done on 10/100 only 2659 * NICs; their DMA engines will malfunction using non-default 2660 * max read request size. 2661 */ 2662 if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) { 2663 if (ifp->if_mtu > ETHERMTU) { 2664 /* 2665 * 512 seems to be the only value that works 2666 * reliably with jumbo frame 2667 */ 2668 pcie_set_max_readrq(sc->re_dev, 2669 PCIEM_DEVCTL_MAX_READRQ_512); 2670 } else { 2671 pcie_set_max_readrq(sc->re_dev, 2672 PCIEM_DEVCTL_MAX_READRQ_4096); 2673 } 2674 } 2675 2676 /* 2677 * Enable C+ RX and TX mode, as well as VLAN stripping and 2678 * RX checksum offload. We must configure the C+ register 2679 * before all others. 2680 */ 2681 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 2682 RE_CPLUSCMD_PCI_MRW | 2683 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 2684 RE_CPLUSCMD_VLANSTRIP : 0) | 2685 (ifp->if_capenable & IFCAP_RXCSUM ? 2686 RE_CPLUSCMD_RXCSUM_ENB : 0)); 2687 2688 /* 2689 * Init our MAC address. Even though the chipset 2690 * documentation doesn't mention it, we need to enter "Config 2691 * register write enable" mode to modify the ID registers. 2692 */ 2693 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 2694 CSR_WRITE_4(sc, RE_IDR0, 2695 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0]))); 2696 CSR_WRITE_2(sc, RE_IDR4, 2697 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4]))); 2698 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 2699 2700 /* 2701 * For C+ mode, initialize the RX descriptors and mbufs. 2702 */ 2703 error = re_rx_list_init(sc); 2704 if (error) { 2705 re_stop(sc); 2706 return; 2707 } 2708 error = re_tx_list_init(sc); 2709 if (error) { 2710 re_stop(sc); 2711 return; 2712 } 2713 2714 /* 2715 * Load the addresses of the RX and TX lists into the chip. 2716 */ 2717 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2718 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2719 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2720 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2721 2722 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2723 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2724 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2725 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2726 2727 /* 2728 * Enable transmit and receive. 2729 */ 2730 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2731 2732 /* 2733 * Set the initial TX and RX configuration. 2734 */ 2735 if (sc->re_flags & RE_F_TESTMODE) { 2736 if (!RE_IS_8139CP(sc)) 2737 CSR_WRITE_4(sc, RE_TXCFG, 2738 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 2739 else 2740 CSR_WRITE_4(sc, RE_TXCFG, 2741 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 2742 } else 2743 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 2744 2745 framelen = RE_FRAMELEN(ifp->if_mtu); 2746 if (framelen < MCLBYTES) 2747 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128)); 2748 else 2749 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128)); 2750 2751 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 2752 2753 /* 2754 * Program the multicast filter, if necessary. 2755 */ 2756 re_setmulti(sc); 2757 2758 #ifdef DEVICE_POLLING 2759 /* 2760 * Disable interrupts if we are polling. 2761 */ 2762 if (ifp->if_flags & IFF_POLLING) 2763 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2764 else /* otherwise ... */ 2765 #endif /* DEVICE_POLLING */ 2766 /* 2767 * Enable interrupts. 2768 */ 2769 if (sc->re_flags & RE_F_TESTMODE) 2770 CSR_WRITE_2(sc, RE_IMR, 0); 2771 else 2772 re_setup_intr(sc, 1, sc->re_imtype); 2773 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs); 2774 2775 /* Start RX/TX process. */ 2776 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 2777 2778 #ifdef notdef 2779 /* Enable receiver and transmitter. */ 2780 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2781 #endif 2782 2783 /* 2784 * For 8169 gigE NICs, set the max allowed RX packet 2785 * size so we can receive jumbo frames. 2786 */ 2787 if (!RE_IS_8139CP(sc)) { 2788 if (sc->re_caps & RE_C_CONTIGRX) 2789 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size); 2790 else 2791 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2792 } 2793 2794 if (sc->re_flags & RE_F_TESTMODE) 2795 return; 2796 2797 mii_mediachg(mii); 2798 2799 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2800 2801 ifp->if_flags |= IFF_RUNNING; 2802 ifp->if_flags &= ~IFF_OACTIVE; 2803 2804 callout_reset(&sc->re_timer, hz, re_tick, sc); 2805 } 2806 2807 /* 2808 * Set media options. 2809 */ 2810 static int 2811 re_ifmedia_upd(struct ifnet *ifp) 2812 { 2813 struct re_softc *sc = ifp->if_softc; 2814 struct mii_data *mii; 2815 2816 ASSERT_SERIALIZED(ifp->if_serializer); 2817 2818 mii = device_get_softc(sc->re_miibus); 2819 mii_mediachg(mii); 2820 2821 return(0); 2822 } 2823 2824 /* 2825 * Report current media status. 2826 */ 2827 static void 2828 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2829 { 2830 struct re_softc *sc = ifp->if_softc; 2831 struct mii_data *mii; 2832 2833 ASSERT_SERIALIZED(ifp->if_serializer); 2834 2835 mii = device_get_softc(sc->re_miibus); 2836 2837 mii_pollstat(mii); 2838 ifmr->ifm_active = mii->mii_media_active; 2839 ifmr->ifm_status = mii->mii_media_status; 2840 } 2841 2842 static int 2843 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2844 { 2845 struct re_softc *sc = ifp->if_softc; 2846 struct ifreq *ifr = (struct ifreq *) data; 2847 struct mii_data *mii; 2848 int error = 0, mask; 2849 2850 ASSERT_SERIALIZED(ifp->if_serializer); 2851 2852 switch(command) { 2853 case SIOCSIFMTU: 2854 if (ifr->ifr_mtu > sc->re_maxmtu) { 2855 error = EINVAL; 2856 } else if (ifp->if_mtu != ifr->ifr_mtu) { 2857 ifp->if_mtu = ifr->ifr_mtu; 2858 if (ifp->if_flags & IFF_RUNNING) 2859 ifp->if_init(sc); 2860 } 2861 break; 2862 2863 case SIOCSIFFLAGS: 2864 if (ifp->if_flags & IFF_UP) { 2865 if (ifp->if_flags & IFF_RUNNING) { 2866 if ((ifp->if_flags ^ sc->re_if_flags) & 2867 (IFF_PROMISC | IFF_ALLMULTI)) 2868 re_setmulti(sc); 2869 } else { 2870 re_init(sc); 2871 } 2872 } else if (ifp->if_flags & IFF_RUNNING) { 2873 re_stop(sc); 2874 } 2875 sc->re_if_flags = ifp->if_flags; 2876 break; 2877 2878 case SIOCADDMULTI: 2879 case SIOCDELMULTI: 2880 re_setmulti(sc); 2881 break; 2882 2883 case SIOCGIFMEDIA: 2884 case SIOCSIFMEDIA: 2885 mii = device_get_softc(sc->re_miibus); 2886 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2887 break; 2888 2889 case SIOCSIFCAP: 2890 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & 2891 ifp->if_capabilities; 2892 ifp->if_capenable ^= mask; 2893 2894 if (mask & IFCAP_HWCSUM) { 2895 if (ifp->if_capenable & IFCAP_TXCSUM) 2896 ifp->if_hwassist = RE_CSUM_FEATURES; 2897 else 2898 ifp->if_hwassist = 0; 2899 } 2900 if (mask && (ifp->if_flags & IFF_RUNNING)) 2901 re_init(sc); 2902 break; 2903 2904 default: 2905 error = ether_ioctl(ifp, command, data); 2906 break; 2907 } 2908 return(error); 2909 } 2910 2911 static void 2912 re_watchdog(struct ifnet *ifp) 2913 { 2914 struct re_softc *sc = ifp->if_softc; 2915 2916 ASSERT_SERIALIZED(ifp->if_serializer); 2917 2918 if_printf(ifp, "watchdog timeout\n"); 2919 2920 ifp->if_oerrors++; 2921 2922 re_txeof(sc); 2923 re_rxeof(sc); 2924 2925 re_init(sc); 2926 2927 if (!ifq_is_empty(&ifp->if_snd)) 2928 if_devstart(ifp); 2929 } 2930 2931 /* 2932 * Stop the adapter and free any mbufs allocated to the 2933 * RX and TX lists. 2934 */ 2935 static void 2936 re_stop(struct re_softc *sc) 2937 { 2938 struct ifnet *ifp = &sc->arpcom.ac_if; 2939 int i; 2940 2941 ASSERT_SERIALIZED(ifp->if_serializer); 2942 2943 /* Reset the adapter. */ 2944 re_reset(sc, ifp->if_flags & IFF_RUNNING); 2945 2946 ifp->if_timer = 0; 2947 callout_stop(&sc->re_timer); 2948 2949 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2950 sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED); 2951 2952 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2953 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2954 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 2955 2956 re_free_rxchain(sc); 2957 2958 /* Free the TX list buffers. */ 2959 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 2960 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2961 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2962 sc->re_ldata.re_tx_dmamap[i]); 2963 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2964 sc->re_ldata.re_tx_mbuf[i] = NULL; 2965 } 2966 } 2967 2968 /* Free the RX list buffers. */ 2969 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 2970 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2971 if ((sc->re_flags & RE_F_USE_JPOOL) == 0) { 2972 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 2973 sc->re_ldata.re_rx_dmamap[i]); 2974 } 2975 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2976 sc->re_ldata.re_rx_mbuf[i] = NULL; 2977 } 2978 } 2979 } 2980 2981 /* 2982 * Device suspend routine. Stop the interface and save some PCI 2983 * settings in case the BIOS doesn't restore them properly on 2984 * resume. 2985 */ 2986 static int 2987 re_suspend(device_t dev) 2988 { 2989 #ifndef BURN_BRIDGES 2990 int i; 2991 #endif 2992 struct re_softc *sc = device_get_softc(dev); 2993 struct ifnet *ifp = &sc->arpcom.ac_if; 2994 2995 lwkt_serialize_enter(ifp->if_serializer); 2996 2997 re_stop(sc); 2998 2999 #ifndef BURN_BRIDGES 3000 for (i = 0; i < 5; i++) 3001 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3002 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3003 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3004 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3005 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3006 #endif 3007 3008 sc->re_flags |= RE_F_SUSPENDED; 3009 3010 lwkt_serialize_exit(ifp->if_serializer); 3011 3012 return (0); 3013 } 3014 3015 /* 3016 * Device resume routine. Restore some PCI settings in case the BIOS 3017 * doesn't, re-enable busmastering, and restart the interface if 3018 * appropriate. 3019 */ 3020 static int 3021 re_resume(device_t dev) 3022 { 3023 struct re_softc *sc = device_get_softc(dev); 3024 struct ifnet *ifp = &sc->arpcom.ac_if; 3025 #ifndef BURN_BRIDGES 3026 int i; 3027 #endif 3028 3029 lwkt_serialize_enter(ifp->if_serializer); 3030 3031 #ifndef BURN_BRIDGES 3032 /* better way to do this? */ 3033 for (i = 0; i < 5; i++) 3034 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3035 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3036 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3037 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3038 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3039 3040 /* reenable busmastering */ 3041 pci_enable_busmaster(dev); 3042 pci_enable_io(dev, SYS_RES_IOPORT); 3043 #endif 3044 3045 /* reinitialize interface if necessary */ 3046 if (ifp->if_flags & IFF_UP) 3047 re_init(sc); 3048 3049 sc->re_flags &= ~RE_F_SUSPENDED; 3050 3051 lwkt_serialize_exit(ifp->if_serializer); 3052 3053 return (0); 3054 } 3055 3056 /* 3057 * Stop all chip I/O so that the kernel's probe routines don't 3058 * get confused by errant DMAs when rebooting. 3059 */ 3060 static void 3061 re_shutdown(device_t dev) 3062 { 3063 struct re_softc *sc = device_get_softc(dev); 3064 struct ifnet *ifp = &sc->arpcom.ac_if; 3065 3066 lwkt_serialize_enter(ifp->if_serializer); 3067 re_stop(sc); 3068 lwkt_serialize_exit(ifp->if_serializer); 3069 } 3070 3071 static int 3072 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS) 3073 { 3074 struct re_softc *sc = arg1; 3075 3076 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time); 3077 } 3078 3079 static int 3080 re_sysctl_txtime(SYSCTL_HANDLER_ARGS) 3081 { 3082 struct re_softc *sc = arg1; 3083 3084 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time); 3085 } 3086 3087 static int 3088 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime) 3089 { 3090 struct re_softc *sc = arg1; 3091 struct ifnet *ifp = &sc->arpcom.ac_if; 3092 int error, v; 3093 3094 lwkt_serialize_enter(ifp->if_serializer); 3095 3096 v = *hwtime; 3097 error = sysctl_handle_int(oidp, &v, 0, req); 3098 if (error || req->newptr == NULL) 3099 goto back; 3100 3101 if (v <= 0) { 3102 error = EINVAL; 3103 goto back; 3104 } 3105 3106 if (v != *hwtime) { 3107 *hwtime = v; 3108 3109 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) == 3110 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW) 3111 re_setup_hw_im(sc); 3112 } 3113 back: 3114 lwkt_serialize_exit(ifp->if_serializer); 3115 return error; 3116 } 3117 3118 static int 3119 re_sysctl_simtime(SYSCTL_HANDLER_ARGS) 3120 { 3121 struct re_softc *sc = arg1; 3122 struct ifnet *ifp = &sc->arpcom.ac_if; 3123 int error, v; 3124 3125 lwkt_serialize_enter(ifp->if_serializer); 3126 3127 v = sc->re_sim_time; 3128 error = sysctl_handle_int(oidp, &v, 0, req); 3129 if (error || req->newptr == NULL) 3130 goto back; 3131 3132 if (v <= 0) { 3133 error = EINVAL; 3134 goto back; 3135 } 3136 3137 if (v != sc->re_sim_time) { 3138 sc->re_sim_time = v; 3139 3140 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) == 3141 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) { 3142 #ifdef foo 3143 int reg; 3144 3145 /* 3146 * Following code causes various strange 3147 * performance problems. Hmm ... 3148 */ 3149 CSR_WRITE_2(sc, RE_IMR, 0); 3150 if (!RE_IS_8139CP(sc)) 3151 reg = RE_TIMERINT_8169; 3152 else 3153 reg = RE_TIMERINT; 3154 CSR_WRITE_4(sc, reg, 0); 3155 CSR_READ_4(sc, reg); /* flush */ 3156 3157 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3158 re_setup_sim_im(sc); 3159 #else 3160 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 3161 DELAY(10); 3162 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 3163 #endif 3164 } 3165 } 3166 back: 3167 lwkt_serialize_exit(ifp->if_serializer); 3168 return error; 3169 } 3170 3171 static int 3172 re_sysctl_imtype(SYSCTL_HANDLER_ARGS) 3173 { 3174 struct re_softc *sc = arg1; 3175 struct ifnet *ifp = &sc->arpcom.ac_if; 3176 int error, v; 3177 3178 lwkt_serialize_enter(ifp->if_serializer); 3179 3180 v = sc->re_imtype; 3181 error = sysctl_handle_int(oidp, &v, 0, req); 3182 if (error || req->newptr == NULL) 3183 goto back; 3184 3185 if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) { 3186 error = EINVAL; 3187 goto back; 3188 } 3189 if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) { 3190 /* Can't do hardware interrupt moderation */ 3191 error = EOPNOTSUPP; 3192 goto back; 3193 } 3194 3195 if (v != sc->re_imtype) { 3196 sc->re_imtype = v; 3197 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) == 3198 IFF_RUNNING) 3199 re_setup_intr(sc, 1, sc->re_imtype); 3200 } 3201 back: 3202 lwkt_serialize_exit(ifp->if_serializer); 3203 return error; 3204 } 3205 3206 static void 3207 re_setup_hw_im(struct re_softc *sc) 3208 { 3209 KKASSERT(sc->re_caps & RE_C_HWIM); 3210 3211 /* 3212 * Interrupt moderation 3213 * 3214 * 0xABCD 3215 * A - unknown (maybe TX related) 3216 * B - TX timer (unit: 25us) 3217 * C - unknown (maybe RX related) 3218 * D - RX timer (unit: 25us) 3219 * 3220 * 3221 * re(4)'s interrupt moderation is actually controlled by 3222 * two variables, like most other NICs (bge, bce etc.) 3223 * o timer 3224 * o number of packets [P] 3225 * 3226 * The logic relationship between these two variables is 3227 * similar to other NICs too: 3228 * if (timer expire || packets > [P]) 3229 * Interrupt is delivered 3230 * 3231 * Currently we only know how to set 'timer', but not 3232 * 'number of packets', which should be ~30, as far as I 3233 * tested (sink ~900Kpps, interrupt rate is 30KHz) 3234 */ 3235 CSR_WRITE_2(sc, RE_IM, 3236 RE_IM_RXTIME(sc->re_rx_time) | 3237 RE_IM_TXTIME(sc->re_tx_time) | 3238 RE_IM_MAGIC); 3239 } 3240 3241 static void 3242 re_disable_hw_im(struct re_softc *sc) 3243 { 3244 if (sc->re_caps & RE_C_HWIM) 3245 CSR_WRITE_2(sc, RE_IM, 0); 3246 } 3247 3248 static void 3249 re_setup_sim_im(struct re_softc *sc) 3250 { 3251 if (!RE_IS_8139CP(sc)) { 3252 uint32_t ticks; 3253 3254 /* 3255 * Datasheet says tick decreases at bus speed, 3256 * but it seems the clock runs a little bit 3257 * faster, so we do some compensation here. 3258 */ 3259 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5; 3260 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks); 3261 } else { 3262 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */ 3263 } 3264 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 3265 sc->re_flags |= RE_F_TIMER_INTR; 3266 } 3267 3268 static void 3269 re_disable_sim_im(struct re_softc *sc) 3270 { 3271 if (!RE_IS_8139CP(sc)) 3272 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0); 3273 else 3274 CSR_WRITE_4(sc, RE_TIMERINT, 0); 3275 sc->re_flags &= ~RE_F_TIMER_INTR; 3276 } 3277 3278 static void 3279 re_config_imtype(struct re_softc *sc, int imtype) 3280 { 3281 switch (imtype) { 3282 case RE_IMTYPE_HW: 3283 KKASSERT(sc->re_caps & RE_C_HWIM); 3284 /* FALL THROUGH */ 3285 case RE_IMTYPE_NONE: 3286 sc->re_intrs = RE_INTRS; 3287 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW | 3288 RE_ISR_RX_OVERRUN; 3289 sc->re_tx_ack = RE_ISR_TX_OK; 3290 break; 3291 3292 case RE_IMTYPE_SIM: 3293 sc->re_intrs = RE_INTRS_TIMER; 3294 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED; 3295 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; 3296 break; 3297 3298 default: 3299 panic("%s: unknown imtype %d\n", 3300 sc->arpcom.ac_if.if_xname, imtype); 3301 } 3302 } 3303 3304 static void 3305 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype) 3306 { 3307 re_config_imtype(sc, imtype); 3308 3309 if (enable_intrs) 3310 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3311 else 3312 CSR_WRITE_2(sc, RE_IMR, 0); 3313 3314 switch (imtype) { 3315 case RE_IMTYPE_NONE: 3316 re_disable_sim_im(sc); 3317 re_disable_hw_im(sc); 3318 break; 3319 3320 case RE_IMTYPE_HW: 3321 KKASSERT(sc->re_caps & RE_C_HWIM); 3322 re_disable_sim_im(sc); 3323 re_setup_hw_im(sc); 3324 break; 3325 3326 case RE_IMTYPE_SIM: 3327 re_disable_hw_im(sc); 3328 re_setup_sim_im(sc); 3329 break; 3330 3331 default: 3332 panic("%s: unknown imtype %d\n", 3333 sc->arpcom.ac_if.if_xname, imtype); 3334 } 3335 } 3336 3337 static void 3338 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr) 3339 { 3340 int i; 3341 3342 if (sc->re_macver == RE_MACVER_11 || sc->re_macver == RE_MACVER_12) { 3343 uint16_t re_did; 3344 3345 re_get_eewidth(sc); 3346 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 3347 if (re_did == 0x8128) { 3348 uint16_t as[ETHER_ADDR_LEN / 2]; 3349 3350 /* 3351 * Get station address from the EEPROM. 3352 */ 3353 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3); 3354 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 3355 as[i] = le16toh(as[i]); 3356 bcopy(as, eaddr, sizeof(eaddr)); 3357 return; 3358 } 3359 } 3360 3361 /* 3362 * Get station address from IDRx. 3363 */ 3364 for (i = 0; i < ETHER_ADDR_LEN; ++i) 3365 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i); 3366 } 3367 3368 static int 3369 re_jpool_alloc(struct re_softc *sc) 3370 { 3371 struct re_list_data *ldata = &sc->re_ldata; 3372 struct re_jbuf *jbuf; 3373 bus_addr_t paddr; 3374 bus_size_t jpool_size; 3375 caddr_t buf; 3376 int i, error; 3377 3378 lwkt_serialize_init(&ldata->re_jbuf_serializer); 3379 3380 ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc), 3381 M_DEVBUF, M_WAITOK | M_ZERO); 3382 3383 jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE; 3384 3385 error = bus_dma_tag_create(sc->re_parent_tag, 3386 RE_RXBUF_ALIGN, 0, /* alignment, boundary */ 3387 BUS_SPACE_MAXADDR, /* lowaddr */ 3388 BUS_SPACE_MAXADDR, /* highaddr */ 3389 NULL, NULL, /* filter, filterarg */ 3390 jpool_size, 1, /* maxsize, nsegments */ 3391 jpool_size, /* maxsegsize */ 3392 0, /* flags */ 3393 &ldata->re_jpool_tag); 3394 if (error) { 3395 device_printf(sc->re_dev, "could not allocate jumbo dma tag\n"); 3396 return error; 3397 } 3398 3399 error = bus_dmamem_alloc(ldata->re_jpool_tag, (void **)&ldata->re_jpool, 3400 BUS_DMA_WAITOK, &ldata->re_jpool_map); 3401 if (error) { 3402 device_printf(sc->re_dev, 3403 "could not allocate jumbo dma memory\n"); 3404 bus_dma_tag_destroy(ldata->re_jpool_tag); 3405 ldata->re_jpool_tag = NULL; 3406 return error; 3407 } 3408 3409 error = bus_dmamap_load(ldata->re_jpool_tag, ldata->re_jpool_map, 3410 ldata->re_jpool, jpool_size, 3411 re_dma_map_addr, &paddr, BUS_DMA_WAITOK); 3412 if (error) { 3413 device_printf(sc->re_dev, "could not load jumbo dma map\n"); 3414 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool, 3415 ldata->re_jpool_map); 3416 bus_dma_tag_destroy(ldata->re_jpool_tag); 3417 ldata->re_jpool_tag = NULL; 3418 return error; 3419 } 3420 3421 /* ..and split it into 9KB chunks */ 3422 SLIST_INIT(&ldata->re_jbuf_free); 3423 3424 buf = ldata->re_jpool; 3425 for (i = 0; i < RE_JBUF_COUNT(sc); i++) { 3426 jbuf = &ldata->re_jbuf[i]; 3427 3428 jbuf->re_sc = sc; 3429 jbuf->re_inuse = 0; 3430 jbuf->re_slot = i; 3431 jbuf->re_buf = buf; 3432 jbuf->re_paddr = paddr; 3433 3434 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3435 3436 buf += RE_JBUF_SIZE; 3437 paddr += RE_JBUF_SIZE; 3438 } 3439 return 0; 3440 } 3441 3442 static void 3443 re_jpool_free(struct re_softc *sc) 3444 { 3445 struct re_list_data *ldata = &sc->re_ldata; 3446 3447 if (ldata->re_jpool_tag != NULL) { 3448 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map); 3449 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool, 3450 ldata->re_jpool_map); 3451 bus_dma_tag_destroy(ldata->re_jpool_tag); 3452 ldata->re_jpool_tag = NULL; 3453 } 3454 3455 if (ldata->re_jbuf != NULL) { 3456 kfree(ldata->re_jbuf, M_DEVBUF); 3457 ldata->re_jbuf = NULL; 3458 } 3459 } 3460 3461 static struct re_jbuf * 3462 re_jbuf_alloc(struct re_softc *sc) 3463 { 3464 struct re_list_data *ldata = &sc->re_ldata; 3465 struct re_jbuf *jbuf; 3466 3467 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3468 3469 jbuf = SLIST_FIRST(&ldata->re_jbuf_free); 3470 if (jbuf != NULL) { 3471 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link); 3472 jbuf->re_inuse = 1; 3473 } 3474 3475 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3476 3477 return jbuf; 3478 } 3479 3480 static void 3481 re_jbuf_free(void *arg) 3482 { 3483 struct re_jbuf *jbuf = arg; 3484 struct re_softc *sc = jbuf->re_sc; 3485 struct re_list_data *ldata = &sc->re_ldata; 3486 3487 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3488 panic("%s: free wrong jumbo buffer\n", 3489 sc->arpcom.ac_if.if_xname); 3490 } else if (jbuf->re_inuse == 0) { 3491 panic("%s: jumbo buffer already freed\n", 3492 sc->arpcom.ac_if.if_xname); 3493 } 3494 3495 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3496 atomic_subtract_int(&jbuf->re_inuse, 1); 3497 if (jbuf->re_inuse == 0) 3498 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3499 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3500 } 3501 3502 static void 3503 re_jbuf_ref(void *arg) 3504 { 3505 struct re_jbuf *jbuf = arg; 3506 struct re_softc *sc = jbuf->re_sc; 3507 struct re_list_data *ldata = &sc->re_ldata; 3508 3509 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3510 panic("%s: ref wrong jumbo buffer\n", 3511 sc->arpcom.ac_if.if_xname); 3512 } else if (jbuf->re_inuse == 0) { 3513 panic("%s: jumbo buffer already freed\n", 3514 sc->arpcom.ac_if.if_xname); 3515 } 3516 atomic_add_int(&jbuf->re_inuse, 1); 3517 } 3518