xref: /dragonfly/sys/dev/netif/re/if_revar.h (revision 25a2db75)
1 /*
2  * Copyright (c) 2004
3  *	Joerg Sonnenberger <joerg@bec.de>.  All rights reserved.
4  *
5  * Copyright (c) 1997, 1998-2003
6  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product includes software developed by Bill Paul.
19  * 4. Neither the name of the author nor the names of any co-contributors
20  *    may be used to endorse or promote products derived from this software
21  *    without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33  * THE POSSIBILITY OF SUCH DAMAGE.
34  *
35  * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $
36  * $DragonFly: src/sys/dev/netif/re/if_revar.h,v 1.31 2008/10/21 12:31:01 sephe Exp $
37  */
38 
39 #define RE_RX_DESC_CNT_8139CP	64
40 #define RE_TX_DESC_CNT_8139CP	64
41 
42 #define RE_RX_DESC_CNT_DEF	256
43 #define RE_TX_DESC_CNT_DEF	256
44 #define RE_RX_DESC_CNT_MAX	1024
45 #define RE_TX_DESC_CNT_MAX	1024
46 
47 #define RE_RX_LIST_SZ(sc)	((sc)->re_rx_desc_cnt * sizeof(struct re_desc))
48 #define RE_TX_LIST_SZ(sc)	((sc)->re_tx_desc_cnt * sizeof(struct re_desc))
49 #define RE_RING_ALIGN		256
50 #define RE_IFQ_MAXLEN		512
51 #define RE_MAXSEGS		16
52 #define RE_TXDESC_SPARE		5
53 #define RE_JBUF_COUNT(sc)	(((sc)->re_rx_desc_cnt * 3) / 2)
54 
55 #define RE_RXDESC_INC(sc, x)	(x = (x + 1) % (sc)->re_rx_desc_cnt)
56 #define RE_TXDESC_INC(sc, x)	(x = (x + 1) % (sc)->re_tx_desc_cnt)
57 #define RE_OWN(x)		(le32toh((x)->re_cmdstat) & RE_RDESC_STAT_OWN)
58 #define RE_RXBYTES(x)		(le32toh((x)->re_cmdstat) & sc->re_rxlenmask)
59 #define RE_PKTSZ(x)		((x)/* >> 3*/)
60 
61 #define RE_ADDR_LO(y)		((uint64_t) (y) & 0xFFFFFFFF)
62 #define RE_ADDR_HI(y)		((uint64_t) (y) >> 32)
63 
64 #define RE_MTU_6K		(6 * 1024)
65 #define RE_MTU_9K		(9 * 1024)
66 
67 #define RE_ETHER_EXTRA		(ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN)
68 #define RE_FRAMELEN(mtu)	((mtu) + RE_ETHER_EXTRA)
69 
70 #define RE_FRAMELEN_6K		RE_FRAMELEN(RE_MTU_6K)
71 #define RE_FRAMELEN_9K		RE_FRAMELEN(RE_MTU_9K)
72 #define RE_FRAMELEN_MAX		RE_FRAMELEN_9K
73 
74 #define RE_RXBUF_ALIGN		8
75 #define RE_JBUF_SIZE		roundup2(RE_FRAMELEN_MAX, RE_RXBUF_ALIGN)
76 
77 #define	RE_TIMEOUT		1000
78 
79 struct re_hwrev {
80 	uint32_t		re_hwrev;
81 	uint32_t		re_macver;	/* see RE_MACVER_ */
82 	int			re_maxmtu;
83 	uint32_t		re_caps;	/* see RE_C_ */
84 };
85 
86 #define RE_MACVER_UNKN		0
87 #define RE_MACVER_03		0x03
88 #define RE_MACVER_04		0x04
89 #define RE_MACVER_05		0x05
90 #define RE_MACVER_06		0x06
91 #define RE_MACVER_11		0x11
92 #define RE_MACVER_12		0x12
93 #define RE_MACVER_13		0x13
94 #define RE_MACVER_14		0x14
95 #define RE_MACVER_15		0x15
96 #define RE_MACVER_16		0x16
97 #define RE_MACVER_21		0x21
98 #define RE_MACVER_22		0x22
99 #define RE_MACVER_23		0x23
100 #define RE_MACVER_24		0x24
101 #define RE_MACVER_25		0x25
102 #define RE_MACVER_26		0x26
103 #define RE_MACVER_27		0x27
104 #define RE_MACVER_28		0x28
105 #define RE_MACVER_29		0x29
106 #define RE_MACVER_2A		0x2a
107 #define RE_MACVER_2B		0x2b
108 #define RE_MACVER_2C		0x2c
109 #define RE_MACVER_2D		0x2d
110 #define RE_MACVER_2E		0x2e
111 #define RE_MACVER_2F		0x2f
112 #define RE_MACVER_30		0x30
113 #define RE_MACVER_31		0x31
114 
115 struct re_softc;
116 struct re_jbuf {
117 	struct re_softc 	*re_sc;
118 	int			re_inuse;
119 	int			re_slot;
120 	caddr_t			re_buf;
121 	bus_addr_t		re_paddr;
122 	SLIST_ENTRY(re_jbuf)	re_link;
123 };
124 
125 struct re_list_data {
126 	struct mbuf		**re_tx_mbuf;
127 	struct mbuf		**re_rx_mbuf;
128 	bus_addr_t		*re_rx_paddr;
129 	int			re_tx_prodidx;
130 	int			re_rx_prodidx;
131 	int			re_tx_considx;
132 	int			re_tx_free;
133 	bus_dmamap_t		*re_tx_dmamap;
134 	bus_dmamap_t		*re_rx_dmamap;
135 	bus_dmamap_t		re_rx_spare;
136 	bus_dma_tag_t		re_rx_mtag;	/* RX mbuf mapping tag */
137 	bus_dma_tag_t		re_tx_mtag;	/* TX mbuf mapping tag */
138 	bus_dma_tag_t		re_stag;	/* stats mapping tag */
139 	bus_dmamap_t		re_smap;	/* stats map */
140 	struct re_stats		*re_stats;
141 	bus_addr_t		re_stats_addr;
142 	bus_dma_tag_t		re_rx_list_tag;
143 	bus_dmamap_t		re_rx_list_map;
144 	struct re_desc		*re_rx_list;
145 	bus_addr_t		re_rx_list_addr;
146 	bus_dma_tag_t		re_tx_list_tag;
147 	bus_dmamap_t		re_tx_list_map;
148 	struct re_desc		*re_tx_list;
149 	bus_addr_t		re_tx_list_addr;
150 
151 	bus_dma_tag_t		re_jpool_tag;
152 	bus_dmamap_t		re_jpool_map;
153 	caddr_t			re_jpool;
154 	struct re_jbuf		*re_jbuf;
155 	struct lwkt_serialize	re_jbuf_serializer;
156 	SLIST_HEAD(, re_jbuf)	re_jbuf_free;
157 };
158 
159 struct re_softc {
160 	struct arpcom		arpcom;		/* interface info */
161 	device_t		re_dev;
162 	bus_space_handle_t	re_bhandle;	/* bus space handle */
163 	bus_space_tag_t		re_btag;	/* bus space tag */
164 	int			re_res_rid;
165 	int			re_res_type;
166 	struct resource		*re_res;
167 	struct resource		*re_irq;
168 	void			*re_intrhand;
169 	device_t		re_miibus;
170 	bus_dma_tag_t		re_parent_tag;
171 	bus_dma_tag_t		re_tag;
172 	uint32_t		re_hwrev;
173 	struct ifpoll_compat	re_npoll;
174 	struct re_list_data	re_ldata;
175 	struct callout		re_timer;
176 	struct mbuf		*re_head;
177 	struct mbuf		*re_tail;
178 	uint32_t		re_caps;	/* see RE_C_ */
179 	uint32_t		re_macver;	/* see RE_MACVER_ */
180 	uint32_t		re_rxlenmask;
181 	int			re_txstart;
182 	int			re_eewidth;
183 	int			re_maxmtu;
184 	int			re_rx_desc_cnt;
185 	int			re_tx_desc_cnt;
186 	int			re_bus_speed;
187 	int			rxcycles;
188 	int			re_rxbuf_size;
189 	int			(*re_newbuf)(struct re_softc *, int, int);
190 	int			re_irq_type;
191 	int			re_irq_rid;
192 
193 	uint32_t		re_flags;	/* see RE_F_ */
194 	int			re_if_flags;	/* saved ifnet.if_flags */
195 
196 	u_long			re_hwassist;
197 	struct sysctl_ctx_list	re_sysctl_ctx;
198 	struct sysctl_oid	*re_sysctl_tree;
199 	uint16_t		re_intrs;
200 	uint16_t		re_tx_ack;
201 	uint16_t		re_rx_ack;
202 	int			re_tx_time;
203 	int			re_rx_time;
204 	int			re_sim_time;
205 	int			re_imtype;	/* see RE_IMTYPE_ */
206 
207 	uint32_t		saved_maps[5];	/* pci data */
208 	uint32_t		saved_biosaddr;
209 	uint8_t			saved_intline;
210 	uint8_t			saved_cachelnsz;
211 	uint8_t			saved_lattimer;
212 };
213 
214 #define RE_C_PCIE		0x1	/* PCI-E */
215 #define RE_C_PCI64		0x2	/* PCI64 */
216 #define RE_C_HWIM		0x4	/* hardware interrupt moderation */
217 #define RE_C_HWCSUM		0x8	/* hardware csum offload */
218 #define RE_C_8139CP		0x20	/* is 8139C+ */
219 #define RE_C_MAC2		0x40	/* MAC style 2 */
220 #define RE_C_PHYPMGT		0x80	/* PHY supports power mgmt */
221 #define RE_C_8169		0x100	/* is 8110/8169 */
222 #define RE_C_AUTOPAD		0x200	/* hardware auto-pad short frames */
223 #define RE_C_CONTIGRX		0x400	/* need contig buf to RX jumbo frames */
224 #define RE_C_STOP_RXTX		0x800	/* could stop RX/TX engine */
225 #define RE_C_FASTE		0x1000	/* 10/100 only NIC */
226 
227 #define RE_IS_8139CP(sc)	((sc)->re_caps & RE_C_8139CP)
228 #define RE_IS_8169(sc)		((sc)->re_caps & RE_C_8169)
229 
230 /* Interrupt moderation types */
231 #define RE_IMTYPE_NONE		0
232 #define RE_IMTYPE_SIM		1	/* simulated */
233 #define RE_IMTYPE_HW		2	/* hardware based */
234 
235 #define RE_F_TIMER_INTR		0x1
236 #define RE_F_USE_JPOOL		0x2
237 #define RE_F_DROP_RXFRAG	0x4
238 #define RE_F_LINKED		0x8
239 #define RE_F_SUSPENDED		0x10
240 #define RE_F_TESTMODE		0x20
241 
242 /*
243  * register space access macros
244  */
245 #define CSR_WRITE_STREAM_4(sc, reg, val)	\
246 	bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val)
247 #define CSR_WRITE_4(sc, reg, val)	\
248 	bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val)
249 #define CSR_WRITE_2(sc, reg, val)	\
250 	bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val)
251 #define CSR_WRITE_1(sc, reg, val)	\
252 	bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val)
253 
254 #define CSR_READ_4(sc, reg)		\
255 	bus_space_read_4(sc->re_btag, sc->re_bhandle, reg)
256 #define CSR_READ_2(sc, reg)		\
257 	bus_space_read_2(sc->re_btag, sc->re_bhandle, reg)
258 #define CSR_READ_1(sc, reg)		\
259 	bus_space_read_1(sc->re_btag, sc->re_bhandle, reg)
260 
261 #define CSR_SETBIT_1(sc, reg, val)	\
262 	CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val))
263 #define CSR_CLRBIT_1(sc, reg, val)	\
264 	CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val))
265