1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/dev/re/if_rereg.h,v 1.14.2.1 2001/07/19 18:33:07 wpaul Exp $ 33 */ 34 35 #ifndef __DragonFly__ 36 /*#define VERSION(_MainVer,_MinorVer) ((_MainVer)*10+(_MinorVer))*/ 37 /*#define OS_VER VERSION(5,1)*/ 38 #if __FreeBSD_version < 500000 39 #define VERSION(_MainVer,_MinorVer) ((_MainVer)*100000+(_MinorVer)*10000) 40 #else 41 #define VERSION(_MainVer,_MinorVer) ((_MainVer)*100000+(_MinorVer)*1000) 42 #endif 43 #define OS_VER __FreeBSD_version 44 45 #if OS_VER>=VERSION(4,0) 46 #define RE_USE_NEW_CALLOUT_FUN 1 47 #endif 48 #endif /* !__DragonFly__ */ 49 50 51 /* 52 * RealTek RTL8110S/SB/SC register offsets 53 */ 54 55 #define RE_TPPOLL 0x0038 /* transmit priority polling */ 56 57 /* 58 * RealTek RTL8110S/SB/SC register contents 59 */ 60 61 /* Transmit Priority Polling --- 0x40 */ 62 #define RE_HPQ 0x80 /* high priority queue polling */ 63 #define RE_NPQ 0x40 /* normal priority queue polling */ 64 #define RE_FSWInt 0x01 /* Forced Software Interrupt */ 65 66 67 /* 68 * RealTek 8129/8139 register offsets 69 */ 70 71 #define RE_IDR0 0x0000 /* ID register 0 (station addr) */ 72 #define RE_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 73 #define RE_IDR2 0x0002 74 #define RE_IDR3 0x0003 75 #define RE_IDR4 0x0004 76 #define RE_IDR5 0x0005 77 /* 0006-0007 reserved */ 78 #define RE_MAR0 0x0008 /* Multicast hash table */ 79 #define RE_MAR1 0x0009 80 #define RE_MAR2 0x000A 81 #define RE_MAR3 0x000B 82 #define RE_MAR4 0x000C 83 #define RE_MAR5 0x000D 84 #define RE_MAR6 0x000E 85 #define RE_MAR7 0x000F 86 87 #define RE_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 88 #define RE_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 89 #define RE_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 90 #define RE_CUSTOM_LED 0x0018 91 #define RE_TXSTAT3 0x001C /* status of TX descriptor 3 */ 92 93 #define RE_TXADDR0 0x0020 /* address of TX descriptor 0 */ 94 #define RE_TXADDR1 0x0024 /* address of TX descriptor 1 */ 95 #define RE_TXADDR2 0x0028 /* address of TX descriptor 2 */ 96 #define RE_TXADDR3 0x002C /* address of TX descriptor 3 */ 97 98 #define RE_RXADDR 0x0030 /* RX ring start address */ 99 #define RE_COMMAND 0x0037 /* command register */ 100 #define RE_CURRXADDR 0x0038 /* current address of packet read */ 101 #define RE_CURRXBUF 0x003A /* current RX buffer address */ 102 #define RE_IMR 0x003C /* interrupt mask register */ 103 #define RE_ISR 0x003E /* interrupt status register */ 104 #define RE_TXCFG 0x0040 /* transmit config */ 105 #define RE_RXCFG 0x0044 /* receive config */ 106 #define RE_TIMERCNT 0x0048 /* timer count register */ 107 #define RE_MISSEDPKT 0x004C /* missed packet counter */ 108 #define RE_EECMD 0x0050 /* EEPROM command register */ 109 #define RE_CFG0 0x0051 /* config register #0 */ 110 #define RE_CFG1 0x0052 /* config register #1 */ 111 #define RE_CFG2 0x0053 /* config register #2 */ 112 #define RE_CFG3 0x0054 /* config register #3 */ 113 #define RE_CFG4 0x0055 /* config register #4 */ 114 #define RE_CFG5 0x0056 /* config register #5 */ 115 /* 0053-0057 reserved */ 116 #define RE_MEDIASTAT 0x0058 /* media status register (8139) */ 117 /* 0059-005A reserved */ 118 #define RE_MII 0x005A /* 8129 chip only */ 119 #define RE_HALTCLK 0x005B 120 #define RE_MULTIINTR 0x005C /* multiple interrupt */ 121 #define RE_PCIREV 0x005E /* PCI revision value */ 122 /* 005F reserved */ 123 #define RE_PHYAR 0x0060 /* PHY register access */ 124 #define RE_CSIDR 0x0064 125 #define RE_CSIAR 0x0068 126 #define RE_PHY_STATUS 0x006C /* PHY status */ 127 #define RE_MACDBG 0x006D 128 #define RE_PMCH 0x006F /* 8 bits */ 129 #define RE_ERIDR 0x0070 130 #define RE_ERIAR 0x0074 131 #define RE_EPHY_RXER_NUM 0x007C 132 #define RE_EPHYAR 0x0080 133 #define RE_MCUACCESS 0x00B0 134 #define RE_OCPDR 0x00B0 135 #define RE_OCPAR 0x00B4 136 #define RE_SecMAC0 0x00B4 137 #define RE_SecMAC4 0x00B8 138 #define RE_PHYOCPACCESS 0x00B8 139 #define RE_DBG_reg 0x00D1 140 #define RE_TwiCmdReg 0x00D2 141 #define RE_MCU_CMD 0x00D3 142 #define RE_RxMaxSize 0x00DA 143 #define RE_CPlusCmd 0x00E0 144 #define RE_MTPS 0x00EC 145 #define RE_IBCR0 0x00F8 146 #define RE_IBCR2 0x00F9 147 #define RE_IBIMR0 0x00FA 148 #define RE_IBISR0 0x00FB 149 150 /* ERI access */ 151 #define ERIAR_Flag 0x80000000 152 #define ERIAR_Write 0x80000000 153 #define ERIAR_Read 0x00000000 154 #define ERIAR_Addr_Align 4 /* ERI access register address must be 4 byte alignment */ 155 #define ERIAR_ExGMAC 0 156 #define ERIAR_MSIX 1 157 #define ERIAR_ASF 2 158 #define ERIAR_Type_shift 16 159 #define ERIAR_ByteEn 0x0f 160 #define ERIAR_ByteEn_shift 12 161 #define ERIAR_OOB 2 162 163 164 165 166 167 /* Direct PHY access registers only available on 8139 */ 168 #define RE_BMCR 0x0062 /* PHY basic mode control */ 169 #define RE_BMSR 0x0064 /* PHY basic mode status */ 170 #define RE_ANAR 0x0066 /* PHY autoneg advert */ 171 #define RE_LPAR 0x0068 /* PHY link partner ability */ 172 #define RE_ANER 0x006A /* PHY autoneg expansion */ 173 174 #define RE_DISCCNT 0x006C /* disconnect counter */ 175 #define RE_FALSECAR 0x006E /* false carrier counter */ 176 #define RE_NWAYTST 0x0070 /* NWAY test register */ 177 #define RE_RX_ER 0x0072 /* RX_ER counter */ 178 #define RE_CSCFG 0x0074 /* CS configuration register */ 179 #define RE_LDPS 0x0082 /* Link Down Power Saving */ 180 #define RE_CPCR 0x00E0 181 #define RE_IM 0x00E2 182 183 184 /* 185 * TX config register bits 186 */ 187 #define RE_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 188 #define RE_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 189 #define RE_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 190 #define RE_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 191 #define RE_TXCFG_IFG 0x03000000 /* interframe gap */ 192 193 #define RE_TXDMA_16BYTES 0x00000000 194 #define RE_TXDMA_32BYTES 0x00000100 195 #define RE_TXDMA_64BYTES 0x00000200 196 #define RE_TXDMA_128BYTES 0x00000300 197 #define RE_TXDMA_256BYTES 0x00000400 198 #define RE_TXDMA_512BYTES 0x00000500 199 #define RE_TXDMA_1024BYTES 0x00000600 200 #define RE_TXDMA_2048BYTES 0x00000700 201 202 /* 203 * Transmit descriptor status register bits. 204 */ 205 #define RE_TXSTAT_LENMASK 0x00001FFF 206 #define RE_TXSTAT_OWN 0x00002000 207 #define RE_TXSTAT_TX_UNDERRUN 0x00004000 208 #define RE_TXSTAT_TX_OK 0x00008000 209 #define RE_TXSTAT_COLLCNT 0x0F000000 210 #define RE_TXSTAT_CARR_HBEAT 0x10000000 211 #define RE_TXSTAT_OUTOFWIN 0x20000000 212 #define RE_TXSTAT_TXABRT 0x40000000 213 #define RE_TXSTAT_CARRLOSS 0x80000000 214 215 /* 216 * Interrupt status register bits. 217 */ 218 #define RE_ISR_RX_OK 0x0001 219 #define RE_ISR_RX_ERR 0x0002 220 #define RE_ISR_TX_OK 0x0004 221 #define RE_ISR_TX_ERR 0x0008 222 #define RE_ISR_RX_OVERRUN 0x0010 223 #define RE_ISR_PKT_UNDERRUN 0x0020 224 #define RE_ISR_LINKCHG 0x0020 225 #define RE_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 226 #define RE_ISR_TDU 0x0080 227 #define RE_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 228 #define RE_ISR_SYSTEM_ERR 0x8000 229 230 /* 231 #define RE_INTRS \ 232 (RE_ISR_TX_OK|RE_ISR_RX_OK|RE_ISR_RX_ERR|RE_ISR_TX_ERR| \ 233 RE_ISR_RX_OVERRUN|RE_ISR_PKT_UNDERRUN|RE_ISR_FIFO_OFLOW| \ 234 RE_ISR_PCS_TIMEOUT|RE_ISR_SYSTEM_ERR) 235 */ 236 237 #define RE_INTRS \ 238 (RE_ISR_TX_OK|RE_ISR_RX_OK|RE_ISR_RX_ERR|RE_ISR_TX_ERR| \ 239 RE_ISR_RX_OVERRUN|RE_ISR_PKT_UNDERRUN|RE_ISR_TDU| \ 240 RE_ISR_PCS_TIMEOUT|RE_ISR_SYSTEM_ERR) 241 242 /* 243 * Media status register. (8139 only) 244 */ 245 #define RE_MEDIASTAT_RXPAUSE 0x01 246 #define RE_MEDIASTAT_TXPAUSE 0x02 247 #define RE_MEDIASTAT_LINK 0x04 248 #define RE_MEDIASTAT_SPEED10 0x08 249 #define RE_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 250 #define RE_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 251 252 /* 253 * Receive config register. 254 */ 255 #define RE_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 256 #define RE_RXCFG_RX_INDIV 0x00000002 /* match filter */ 257 #define RE_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 258 #define RE_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 259 #define RE_RXCFG_RX_RUNT 0x00000010 260 #define RE_RXCFG_RX_ERRPKT 0x00000020 261 #define RE_RXCFG_RX_9356SEL 0x00000040 262 #define RE_RXCFG_WRAP 0x00000080 263 #define RE_RXCFG_MAXDMA 0x00000700 264 #define RE_RXCFG_BUFSZ 0x00001800 265 266 #define RE_RXDMA_16BYTES 0x00000000 267 #define RE_RXDMA_32BYTES 0x00000100 268 #define RE_RXDMA_64BYTES 0x00000200 269 #define RE_RXDMA_128BYTES 0x00000300 270 #define RE_RXDMA_256BYTES 0x00000400 271 #define RE_RXDMA_512BYTES 0x00000500 272 #define RE_RXDMA_1024BYTES 0x00000600 273 #define RE_RXDMA_UNLIMITED 0x00000700 274 275 #define RE_RXBUF_8 0x00000000 276 #define RE_RXBUF_16 0x00000800 277 #define RE_RXBUF_32 0x00001000 278 #define RE_RXBUF_64 0x00001800 279 280 #define RE_RXRESVERED 0x0000E000 281 282 /* 283 * Bits in RX status header (included with RX'ed packet 284 * in ring buffer). 285 */ 286 #define RE_RXSTAT_RXOK 0x00000001 287 #define RE_RXSTAT_ALIGNERR 0x00000002 288 #define RE_RXSTAT_CRCERR 0x00000004 289 #define RE_RXSTAT_GIANT 0x00000008 290 #define RE_RXSTAT_RUNT 0x00000010 291 #define RE_RXSTAT_BADSYM 0x00000020 292 #define RE_RXSTAT_BROAD 0x00002000 293 #define RE_RXSTAT_INDIV 0x00004000 294 #define RE_RXSTAT_MULTI 0x00008000 295 #define RE_RXSTAT_LENMASK 0xFFFF0000 296 297 #define RE_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 298 /* 299 * Command register. 300 */ 301 #define RE_CMD_EMPTY_RXBUF 0x0001 302 #define RE_CMD_TX_ENB 0x0004 303 #define RE_CMD_RX_ENB 0x0008 304 #define RE_CMD_RESET 0x0010 305 306 /* 307 * EEPROM control register 308 */ 309 #define RE_EE_DATAOUT 0x01 /* Data out */ 310 #define RE_EE_DATAIN 0x02 /* Data in */ 311 #define RE_EE_CLK 0x04 /* clock */ 312 #define RE_EE_SEL 0x08 /* chip select */ 313 #define RE_EE_MODE (0x40|0x80) 314 315 #define RE_EEMODE_OFF 0x00 316 #define RE_EEMODE_AUTOLOAD 0x40 317 #define RE_EEMODE_PROGRAM 0x80 318 #define RE_EEMODE_WRITECFG (0x80|0x40) 319 320 /* 9346 EEPROM commands */ 321 #define RE_EECMD_WRITE 0x140 322 #define RE_EECMD_READ 0x180 323 #define RE_EECMD_ERASE 0x1c0 324 325 #define RE_EE_ID 0x00 326 #define RE_EE_PCI_VID 0x01 327 #define RE_EE_PCI_DID 0x02 328 /* Location of station address inside EEPROM */ 329 #define RE_EE_EADDR 0x07 330 331 /* 332 * MII register (8129 only) 333 */ 334 #define RE_MII_CLK 0x01 335 #define RE_MII_DATAIN 0x02 336 #define RE_MII_DATAOUT 0x04 337 #define RE_MII_DIR 0x80 /* 0 == input, 1 == output */ 338 339 /* 340 * Config 0 register 341 */ 342 #define RE_CFG0_ROM0 0x01 343 #define RE_CFG0_ROM1 0x02 344 #define RE_CFG0_ROM2 0x04 345 #define RE_CFG0_PL0 0x08 346 #define RE_CFG0_PL1 0x10 347 #define RE_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 348 #define RE_CFG0_PCS 0x40 349 #define RE_CFG0_SCR 0x80 350 351 /* 352 * Config 1 register 353 */ 354 #define RE_CFG1_PME 0x01 355 #define RE_CFG1_IOMAP 0x04 356 #define RE_CFG1_MEMMAP 0x08 357 #define RE_CFG1_RSVD 0x10 358 #define RE_CFG1_LED0 0x40 359 #define RE_CFG1_LED1 0x80 360 361 /* 362 * Config 3 register 363 */ 364 #define RL_CFG3_GRANTSEL 0x80 365 #define RL_CFG3_WOL_MAGIC 0x20 366 #define RL_CFG3_WOL_LINK 0x10 367 #define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */ 368 #define RL_CFG3_FAST_B2B 0x01 369 370 /* 371 * Config 4 register 372 */ 373 #define RL_CFG4_LWPTN 0x04 374 #define RL_CFG4_LWPME 0x10 375 #define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */ 376 #define RL_CFG4_CUSTOMIZED_LED 0x40 377 378 /* 379 * Config 5 register 380 */ 381 #define RL_CFG5_WOL_BCAST 0x40 382 #define RL_CFG5_WOL_MCAST 0x20 383 #define RL_CFG5_WOL_UCAST 0x10 384 #define RL_CFG5_WOL_LANWAKE 0x02 385 #define RL_CFG5_PME_STS 0x01 386 387 /* 388 * PHY Status register 389 */ 390 #define RL_PHY_STATUS_1000MF 0x10 391 #define RL_PHY_STATUS_100M 0x08 392 #define RL_PHY_STATUS_10M 0x04 393 #define RL_PHY_STATUS_LINK_STS 0x02 394 #define RL_PHY_STATUS_FULL_DUP 0x01 395 396 /* OCP GPHY access */ 397 #define OCPDR_Write 0x80000000 398 #define OCPDR_Read 0x00000000 399 #define OCPDR_Reg_Mask 0xFF 400 #define OCPDR_Data_Mask 0xFFFF 401 #define OCPDR_GPHY_Reg_shift 16 402 #define OCPAR_Flag 0x80000000 403 #define OCPAR_GPHY_Write 0x8000F060 404 #define OCPAR_GPHY_Read 0x0000F060 405 #define OCPR_Write 0x80000000 406 #define OCPR_Read 0x00000000 407 #define OCPR_Addr_Reg_shift 16 408 #define OCPR_Flag 0x80000000 409 #define OCP_STD_PHY_BASE_PAGE 0x0A40 410 411 /* MCU Command */ 412 #define RE_NOW_IS_OOB (1 << 7) 413 #define RE_TXFIFO_EMPTY (1 << 5) 414 #define RE_RXFIFO_EMPTY (1 << 4) 415 416 /* OOB Command */ 417 #define OOB_CMD_RESET 0x00 418 #define OOB_CMD_DRIVER_START 0x05 419 #define OOB_CMD_DRIVER_STOP 0x06 420 #define OOB_CMD_SET_IPMAC 0x41 421 422 /* Ethernet PHY MDI Mode */ 423 #define RE_ETH_PHY_FORCE_MDI 0 424 #define RE_ETH_PHY_FORCE_MDIX 1 425 #define RE_ETH_PHY_AUTO_MDI_MDIX 2 426 427 /* 428 * The RealTek doesn't use a fragment-based descriptor mechanism. 429 * Instead, there are only four register sets, each or which represents 430 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 431 * packet buffer (32-bit aligned!) and we place the buffer addresses in 432 * the registers so the chip knows where they are. 433 * 434 * We can sort of kludge together the same kind of buffer management 435 * used in previous drivers, but we have to do buffer copies almost all 436 * the time, so it doesn't really buy us much. 437 * 438 * For reception, there's just one large buffer where the chip stores 439 * all received packets. 440 */ 441 #ifndef __NO_STRICT_ALIGNMENT 442 #define RE_FIXUP_RX 1 443 #endif 444 445 446 #define RE_RX_BUF_SZ RE_RXBUF_64 447 #define RE_RXBUFLEN (1 << ((RE_RX_BUF_SZ >> 11) + 13)) 448 #define RE_TX_LIST_CNT 4 /* C mode Tx buffer number */ 449 #define RE_TX_BUF_NUM 256 /* Tx buffer number */ 450 #define RE_RX_BUF_NUM 256 /* Rx buffer number */ 451 #define RE_BUF_SIZE 9216 /* Buffer size of descriptor buffer */ 452 #define RE_MIN_FRAMELEN 60 453 #define RE_TXREV(x) ((x) << 11) 454 #define RE_RX_RESVERED RE_RXRESVERED 455 #define RE_RX_MAXDMA RE_RXDMA_UNLIMITED 456 #define RE_TX_MAXDMA RE_TXDMA_2048BYTES 457 #define RE_NTXSEGS 32 458 459 #define RE_TXCFG_CONFIG 0x03000780 //(RE_TXCFG_IFG|RE_TX_MAXDMA) 460 461 #define RE_DESC_ALIGN 256 /* descriptor alignment */ 462 #define RE_RX_BUFFER_ALIGN 8 /* descriptor alignment */ 463 464 #ifdef RE_FIXUP_RX 465 #define RE_ETHER_ALIGN RE_RX_BUFFER_ALIGN 466 #else 467 #define RE_ETHER_ALIGN 0 468 #endif 469 470 #ifdef __DragonFly__ 471 #ifndef ETHER_VLAN_ENCAP_LEN 472 #define ETHER_VLAN_ENCAP_LEN EVL_ENCAPLEN 473 #endif 474 #endif 475 #define Jumbo_Frame_2k ((2 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 476 #define Jumbo_Frame_3k ((3 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 477 #define Jumbo_Frame_4k ((4 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 478 #define Jumbo_Frame_5k ((5 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 479 #define Jumbo_Frame_6k ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 480 #define Jumbo_Frame_7k ((7 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 481 #define Jumbo_Frame_8k ((8 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 482 #define Jumbo_Frame_9k ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 483 484 #ifndef __DragonFly__ 485 struct re_chain_data { 486 u_int16_t cur_rx; 487 caddr_t re_rx_buf; 488 caddr_t re_rx_buf_ptr; 489 490 struct mbuf *re_tx_chain[RE_TX_LIST_CNT]; 491 u_int8_t last_tx; /* Previous Tx OK */ 492 u_int8_t cur_tx; /* Next to TX */ 493 }; 494 495 //+++ From FreeBSD 9.0 +++ 496 497 #define RL_MSI_MESSAGES 1 498 499 #define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 500 #define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 501 /* 502 * RX/TX descriptor definition. When large send mode is enabled, the 503 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 504 * the checksum offload bits are disabled. The structure layout is 505 * the same for RX and TX descriptors 506 */ 507 508 #define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 509 #define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 510 #define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 511 #define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 512 #define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 513 #define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 514 #define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 515 #define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 516 #define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 517 #define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 518 #define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 519 520 #define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 521 #define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 522 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 523 #define RL_TDESC_CMD_UDPCSUMV2 0x80000000 524 #define RL_TDESC_CMD_TCPCSUMV2 0x40000000 525 #define RL_TDESC_CMD_IPCSUMV2 0x20000000 526 #define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 527 #define RL_TDESC_CMD_MSSVALV2_SHIFT 18 528 529 #define RL_TDESC_CMD_BUFLEN 0x0000FFFF 530 531 /* 532 * Error bits are valid only on the last descriptor of a frame 533 * (i.e. RL_TDESC_CMD_EOF == 1) 534 */ 535 536 #define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 537 #define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 538 #define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 539 #define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 540 #define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 541 #define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 542 #define RL_TDESC_STAT_OWN 0x80000000 543 544 /* 545 * RX descriptor cmd/vlan definitions 546 */ 547 548 #define RL_RDESC_CMD_EOR 0x40000000 549 #define RL_RDESC_CMD_OWN 0x80000000 550 #define RL_RDESC_CMD_BUFLEN 0x00003FFF 551 552 #define RL_RDESC_STAT_OWN 0x80000000 553 #define RL_RDESC_STAT_EOR 0x40000000 554 #define RL_RDESC_STAT_SOF 0x20000000 555 #define RL_RDESC_STAT_EOF 0x10000000 556 #define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 557 #define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 558 #define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 559 #define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 560 #define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 561 #define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 562 #define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 563 #define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 564 #define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 565 #define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 566 #define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 567 #define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 568 #define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 569 #define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 570 #define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 571 #define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 572 #define RL_RDESC_STAT_GFRAGLEN RL_RDESC_CMD_BUFLEN /* RX'ed frame/frag len */ 573 #define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 574 RL_RDESC_STAT_CRCERR) 575 576 #define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 577 (rl_vlandata valid)*/ 578 #define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 579 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 580 #define RL_RDESC_IPV6 0x80000000 581 #define RL_RDESC_IPV4 0x40000000 582 583 #define RL_PROTOID_NONIP 0x00000000 584 #define RL_PROTOID_TCPIP 0x00010000 585 #define RL_PROTOID_UDPIP 0x00020000 586 #define RL_PROTOID_IP 0x00030000 587 #define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 588 RL_PROTOID_TCPIP) 589 #define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 590 RL_PROTOID_UDPIP) 591 592 //--- From FreeBSD 9.0--- 593 594 595 union RxDesc { 596 u_int32_t ul[4]; 597 struct { 598 #if defined(_LITTLE_ENDIAN) 599 u_int32_t Frame_Length:14; 600 u_int32_t TCPF:1; 601 u_int32_t UDPF:1; 602 u_int32_t IPF:1; 603 u_int32_t TCPT:1; 604 u_int32_t UDPT:1; 605 u_int32_t CRC:1; 606 u_int32_t RUNT:1; 607 u_int32_t RES:1; 608 u_int32_t RWT:1; 609 u_int32_t RESV:2; 610 u_int32_t BAR:1; 611 u_int32_t PAM:1; 612 u_int32_t MAR:1; 613 u_int32_t LS:1; 614 u_int32_t FS:1; 615 u_int32_t EOR:1; 616 u_int32_t OWN:1; 617 618 u_int32_t VLAN_TAG:16; 619 u_int32_t TAVA:1; 620 u_int32_t RESV1:15; 621 #elif defined(_BIG_ENDIAN) 622 u_int32_t OWN:1; 623 u_int32_t EOR:1; 624 u_int32_t FS:1; 625 u_int32_t LS:1; 626 u_int32_t MAR:1; 627 u_int32_t PAM:1; 628 u_int32_t BAR:1; 629 u_int32_t RESV:2; 630 u_int32_t RWT:1; 631 u_int32_t RES:1; 632 u_int32_t RUNT:1; 633 u_int32_t CRC:1; 634 u_int32_t UDPT:1; 635 u_int32_t TCPT:1; 636 u_int32_t IPF:1; 637 u_int32_t UDPF:1; 638 u_int32_t TCPF:1; 639 u_int32_t Frame_Length:14; 640 641 u_int32_t RESV1:15; 642 u_int32_t TAVA:1; 643 u_int32_t VLAN_TAG:16; 644 #else 645 #error "what endian is this machine?" 646 #endif 647 u_int32_t RxBuffL; 648 u_int32_t RxBuffH; 649 } so0; /* symbol owner=0 */ 650 }; 651 652 union TxDesc { 653 u_int32_t ul[4]; 654 struct { 655 #if defined(_LITTLE_ENDIAN) 656 u_int32_t Frame_Length:16; 657 u_int32_t TCPCS:1; 658 u_int32_t UDPCS:1; 659 u_int32_t IPCS:1; 660 u_int32_t SCRC:1; 661 u_int32_t RESV:6; 662 u_int32_t TDMA:1; 663 u_int32_t LGSEN:1; 664 u_int32_t LS:1; 665 u_int32_t FS:1; 666 u_int32_t EOR:1; 667 u_int32_t OWN:1; 668 669 u_int32_t VLAN_TAG:16; 670 u_int32_t TAGC0:1; 671 u_int32_t TAGC1:1; 672 u_int32_t RESV1:14; 673 #elif defined(_BIG_ENDIAN) 674 u_int32_t OWN:1; 675 u_int32_t EOR:1; 676 u_int32_t FS:1; 677 u_int32_t LS:1; 678 u_int32_t LGSEN:1; 679 u_int32_t TDMA:1; 680 u_int32_t RESV:6; 681 u_int32_t SCRC:1; 682 u_int32_t IPCS:1; 683 u_int32_t UDPCS:1; 684 u_int32_t TCPCS:1; 685 u_int32_t Frame_Length:16; 686 687 u_int32_t RESV1:14; 688 u_int32_t TAGC1:1; 689 u_int32_t TAGC0:1; 690 u_int32_t VLAN_TAG:16; 691 #else 692 #error "what endian is this machine?" 693 #endif 694 u_int32_t TxBuffL; 695 u_int32_t TxBuffH; 696 } so1; /* symbol owner=1 */ 697 }; 698 699 struct re_descriptor { 700 u_int8_t rx_cur_index; 701 u_int8_t rx_last_index; 702 union RxDesc *rx_desc; /* 8 bits alignment */ 703 struct mbuf *rx_buf[RE_RX_BUF_NUM]; 704 705 u_int8_t tx_cur_index; 706 u_int8_t tx_last_index; 707 union TxDesc *tx_desc; /* 8 bits alignment */ 708 struct mbuf *tx_buf[RE_TX_BUF_NUM]; 709 bus_dma_tag_t rx_desc_tag; 710 bus_dmamap_t rx_desc_dmamap; 711 bus_dma_tag_t re_rx_mtag; /* mbuf RX mapping tag */ 712 bus_dmamap_t re_rx_dmamap[RE_RX_BUF_NUM]; 713 714 bus_dma_tag_t tx_desc_tag; 715 bus_dmamap_t tx_desc_dmamap; 716 bus_dma_tag_t re_tx_mtag; /* mbuf TX mapping tag */ 717 bus_dmamap_t re_tx_dmamap[RE_TX_BUF_NUM]; 718 }; 719 720 #define RE_INC(x) (x = (x + 1) % RE_TX_LIST_CNT) 721 #define RE_CUR_TXADDR(x) ((x->re_cdata.cur_tx * 4) + RE_TXADDR0) 722 #define RE_CUR_TXSTAT(x) ((x->re_cdata.cur_tx * 4) + RE_TXSTAT0) 723 #define RE_CUR_TXMBUF(x) (x->re_cdata.re_tx_chain[x->re_cdata.cur_tx]) 724 #define RE_LAST_TXADDR(x) ((x->re_cdata.last_tx * 4) + RE_TXADDR0) 725 #define RE_LAST_TXSTAT(x) ((x->re_cdata.last_tx * 4) + RE_TXSTAT0) 726 #define RE_LAST_TXMBUF(x) (x->re_cdata.re_tx_chain[x->re_cdata.last_tx]) 727 728 struct re_type { 729 u_int16_t re_vid; 730 u_int16_t re_did; 731 char *re_name; 732 }; 733 734 struct re_mii_frame { 735 u_int8_t mii_stdelim; 736 u_int8_t mii_opcode; 737 u_int8_t mii_phyaddr; 738 u_int8_t mii_regaddr; 739 u_int8_t mii_turnaround; 740 u_int16_t mii_data; 741 }; 742 #endif /* !__DragonFly__ */ 743 744 /* 745 * MII constants 746 */ 747 #define RE_MII_STARTDELIM 0x01 748 #define RE_MII_READOP 0x02 749 #define RE_MII_WRITEOP 0x01 750 #define RE_MII_TURNAROUND 0x02 751 #define RL_TDESC_VLANCTL_TAG 0x00020000 752 #define RL_RDESC_VLANCTL_TAG 0x00010000 753 #define RL_RDESC_VLANCTL_DATA 0x0000FFFF 754 #define RL_CPLUSCMD_VLANSTRIP 0x0040 755 #define RL_FLAG_MSI 0x00000001 756 #define RL_FLAG_PHYWAKE_PM 0x00000004 757 #define RL_FLAG_DESCV2 0x00000040 758 #define RL_FLAG_MSIX 0x00000800 759 #define RL_FLAG_MAGIC_PACKET_V2 0x20000000 760 #define RL_FLAG_PCIE 0x40000000 761 762 #define RL_ProtoIP ((1<<17)|(1<<18)) 763 //#define RL_ProtoIP ((1<<16)|(1<<17)) 764 #define RL_TCPT (1<<17) 765 #define RL_UDPT (1<<18) 766 #define RL_IPF (1<<16) 767 #define RL_UDPF (1<<15) 768 #define RL_TCPF (1<<14) 769 #define RL_V4F (1<<30) 770 771 #define RL_IPV4CS (1<<29) 772 #define RL_TCPCS (1<<30) 773 #define RL_UDPCS (1<<31) 774 #define RL_IPV4CS1 (1<<18) 775 #define RL_TCPCS1 (1<<16) 776 #define RL_UDPCS1 (1<<17) 777 778 #define RL_RxChkSum (1<<5) 779 780 enum { 781 MACFG_3 = 3, 782 MACFG_4, 783 MACFG_5, 784 MACFG_6, 785 786 MACFG_11 = 11, 787 MACFG_12, 788 MACFG_13, 789 MACFG_14, 790 MACFG_15, 791 MACFG_16, 792 MACFG_17, 793 MACFG_18, 794 MACFG_19, 795 796 MACFG_21 = 21, 797 MACFG_22, 798 MACFG_23, 799 MACFG_24, 800 MACFG_25, 801 MACFG_26, 802 MACFG_27, 803 MACFG_28, 804 805 MACFG_31 = 31, 806 MACFG_32, 807 MACFG_33, 808 809 MACFG_36 = 36, 810 MACFG_37, 811 MACFG_38, 812 MACFG_39, 813 814 MACFG_41 = 41, 815 MACFG_42, 816 MACFG_43, 817 818 MACFG_50 = 50, 819 MACFG_51, 820 MACFG_52, 821 MACFG_53, 822 MACFG_54, 823 MACFG_55, 824 MACFG_56, 825 MACFG_57, 826 MACFG_58, 827 MACFG_59, 828 MACFG_60, 829 MACFG_61, 830 MACFG_62, 831 MACFG_63, 832 MACFG_64, 833 MACFG_65, 834 MACFG_66, 835 MACFG_67, 836 MACFG_68, 837 MACFG_69, 838 839 MACFG_FF = 0xFF 840 }; 841 842 //#define MAC_STYLE_1 1 /* RTL8110S/SB/SC, RTL8111B and RTL8101E */ 843 //#define MAC_STYLE_2 2 /* RTL8111C/CP/D and RTL8102E */ 844 845 #ifndef __DragonFly__ 846 struct re_softc { 847 #if OS_VER<VERSION(6,0) 848 struct arpcom arpcom; /* interface info */ 849 #else 850 struct ifnet *re_ifp; 851 #endif 852 853 bus_space_handle_t re_bhandle; /* bus space handle */ 854 bus_space_tag_t re_btag; /* bus space tag */ 855 struct resource *re_res; 856 int re_res_id; 857 int re_res_type; 858 struct resource *re_res_pba; 859 struct resource *re_irq; 860 void *re_intrhand; 861 struct ifmedia media; /* used to instead of MII */ 862 863 /* Variable for 8169 family */ 864 u_int8_t re_8169_MacVersion; 865 u_int8_t re_8169_PhyVersion; 866 867 u_int8_t rx_fifo_overflow; 868 u_int8_t driver_detach; 869 870 u_int8_t re_unit; /* interface number */ 871 u_int8_t re_type; 872 u_int8_t re_stats_no_timeout; 873 u_int8_t re_revid; 874 u_int16_t re_device_id; 875 876 struct re_chain_data re_cdata; /* Tx buffer chain, Used only in ~C+ mode */ 877 struct re_descriptor re_desc; /* Descriptor, Used only in C+ mode */ 878 #ifdef RE_USE_NEW_CALLOUT_FUN 879 struct callout re_stat_ch; 880 #else 881 struct callout_handle re_stat_ch; 882 #endif 883 u_int8_t re_link_chg_det; 884 struct mtx mtx; 885 bus_dma_tag_t re_parent_tag; 886 device_t dev; 887 int re_expcap; 888 int max_jumbo_frame_size; 889 int re_rx_mbuf_sz; 890 int re_rx_desc_buf_sz; 891 int re_if_flags; 892 int re_tx_cstag; 893 int re_rx_cstag; 894 int suspended; /* 0 = normal 1 = suspended */ 895 896 u_int8_t RequireAdcBiasPatch; 897 u_int16_t AdcBiasPatchIoffset; 898 899 u_int8_t RequireAdjustUpsTxLinkPulseTiming; 900 u_int16_t SwrCnt1msIni; 901 #if OS_VER>=VERSION(7,0) 902 struct task re_inttask; 903 #endif 904 u_int16_t cur_page; 905 906 u_int8_t re_hw_enable_msi_msix; 907 908 u_int8_t re_coalesce_tx_pkt; 909 910 u_int8_t link_state; 911 912 u_int8_t prohibit_access_reg; 913 914 u_int8_t re_hw_supp_now_is_oob_ver; 915 }; 916 #endif /* !__DragonFly__ */ 917 918 enum bits { 919 BIT_0 = (1 << 0), 920 BIT_1 = (1 << 1), 921 BIT_2 = (1 << 2), 922 BIT_3 = (1 << 3), 923 BIT_4 = (1 << 4), 924 BIT_5 = (1 << 5), 925 BIT_6 = (1 << 6), 926 BIT_7 = (1 << 7), 927 BIT_8 = (1 << 8), 928 BIT_9 = (1 << 9), 929 BIT_10 = (1 << 10), 930 BIT_11 = (1 << 11), 931 BIT_12 = (1 << 12), 932 BIT_13 = (1 << 13), 933 BIT_14 = (1 << 14), 934 BIT_15 = (1 << 15), 935 BIT_16 = (1 << 16), 936 BIT_17 = (1 << 17), 937 BIT_18 = (1 << 18), 938 BIT_19 = (1 << 19), 939 BIT_20 = (1 << 20), 940 BIT_21 = (1 << 21), 941 BIT_22 = (1 << 22), 942 BIT_23 = (1 << 23), 943 BIT_24 = (1 << 24), 944 BIT_25 = (1 << 25), 945 BIT_26 = (1 << 26), 946 BIT_27 = (1 << 27), 947 BIT_28 = (1 << 28), 948 BIT_29 = (1 << 29), 949 BIT_30 = (1 << 30), 950 BIT_31 = (1 << 31) 951 }; 952 953 #ifndef __DragonFly__ 954 #define RE_LOCK(_sc) mtx_lock(&(_sc)->mtx) 955 #define RE_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 956 #define RE_LOCK_INIT(_sc,_name) mtx_init(&(_sc)->mtx,_name,MTX_NETWORK_LOCK,MTX_DEF) 957 #define RE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) 958 #define RE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx,MA_OWNED) 959 960 /* 961 * register space access macros 962 */ 963 #if OS_VER>VERSION(5,9) 964 #define CSR_WRITE_STREAM_4(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val)) 965 #define CSR_WRITE_STREAM_2(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_stream_2(sc->re_btag, sc->re_bhandle, reg, val)) 966 #endif 967 #define CSR_WRITE_4(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val)) 968 #define CSR_WRITE_2(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val)) 969 #define CSR_WRITE_1(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val)) 970 971 #define CSR_READ_4(sc, reg) ((sc->prohibit_access_reg)?0xFFFFFFFF:bus_space_read_4(sc->re_btag, sc->re_bhandle, reg)) 972 #define CSR_READ_2(sc, reg) ((sc->prohibit_access_reg)?0xFFFF:bus_space_read_2(sc->re_btag, sc->re_bhandle, reg)) 973 #define CSR_READ_1(sc, reg) ((sc->prohibit_access_reg)?0xFF:bus_space_read_1(sc->re_btag, sc->re_bhandle, reg)) 974 #endif /* !__DragonFly__ */ 975 976 #define RE_TIMEOUT 1000 977 978 /* 979 * General constants that are fun to know. 980 * 981 * RealTek PCI vendor ID 982 */ 983 #define RT_VENDORID 0x10EC 984 985 /* 986 * RealTek chip device IDs. 987 */ 988 #define RT_DEVICEID_8129 0x8129 989 #define RT_DEVICEID_8139 0x8139 990 #define RT_DEVICEID_8169 0x8169 /* For RTL8169 */ 991 #define RT_DEVICEID_8169SC 0x8167 /* For RTL8169SC */ 992 #define RT_DEVICEID_8168 0x8168 /* For RTL8168B */ 993 #define RT_DEVICEID_8161 0x8161 /* For RTL8168 Series add-on card */ 994 #define RT_DEVICEID_8136 0x8136 /* For RTL8101E */ 995 996 /* 997 * Accton PCI vendor ID 998 */ 999 #define ACCTON_VENDORID 0x1113 1000 1001 /* 1002 * Accton MPX 5030/5038 device ID. 1003 */ 1004 #define ACCTON_DEVICEID_5030 0x1211 1005 1006 /* 1007 * Delta Electronics Vendor ID. 1008 */ 1009 #define DELTA_VENDORID 0x1500 1010 1011 /* 1012 * Delta device IDs. 1013 */ 1014 #define DELTA_DEVICEID_8139 0x1360 1015 1016 /* 1017 * Addtron vendor ID. 1018 */ 1019 #define ADDTRON_VENDORID 0x4033 1020 1021 /* 1022 * Addtron device IDs. 1023 */ 1024 #define ADDTRON_DEVICEID_8139 0x1360 1025 1026 /* 1027 * D-Link vendor ID. 1028 */ 1029 #define DLINK_VENDORID 0x1186 1030 1031 /* 1032 * D-Link DFE-530TX+ device ID 1033 */ 1034 #define DLINK_DEVICEID_530TXPLUS 0x1300 1035 1036 /* 1037 * PCI low memory base and low I/O base register, and 1038 * other PCI registers. 1039 */ 1040 1041 #define RE_PCI_VENDOR_ID 0x00 1042 #define RE_PCI_DEVICE_ID 0x02 1043 #define RE_PCI_COMMAND 0x04 1044 #define RE_PCI_STATUS 0x06 1045 #define RE_PCI_REVISION_ID 0x08 /* 8 bits */ 1046 #define RE_PCI_CLASSCODE 0x09 1047 #define RE_PCI_LATENCY_TIMER 0x0D 1048 #define RE_PCI_HEADER_TYPE 0x0E 1049 #define RE_PCI_BIOSROM 0x30 1050 #define RE_PCI_INTLINE 0x3C 1051 #define RE_PCI_INTPIN 0x3D 1052 #define RE_PCI_MINGNT 0x3E 1053 #define RE_PCI_MINLAT 0x0F 1054 #define RE_PCI_RESETOPT 0x48 1055 #define RE_PCI_EEPROM_DATA 0x4C 1056 1057 #define RE_PCI_CAPID 0x50 /* 8 bits */ 1058 #define RE_PCI_NEXTPTR 0x51 /* 8 bits */ 1059 #define RE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 1060 #define RE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 1061 1062 #define RE_PSTATE_MASK 0x0003 1063 #define RE_PSTATE_D0 0x0000 1064 #define RE_PSTATE_D1 0x0002 1065 #define RE_PSTATE_D2 0x0002 1066 #define RE_PSTATE_D3 0x0003 1067 #define RE_PME_EN 0x0010 1068 #define RE_PME_STATUS 0x8000 1069 1070 #define RE_WOL_LINK_SPEED_10M_FIRST ( 0 ) 1071 #define RE_WOL_LINK_SPEED_100M_FIRST ( 1 ) 1072 1073 #ifdef __alpha__ 1074 #undef vtophys 1075 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1076 #endif 1077 1078 #ifndef TRUE 1079 #define TRUE 1 1080 #endif 1081 #ifndef FALSE 1082 #define FALSE 0 1083 #endif 1084 1085 #define PHYAR_Flag 0x80000000 1086 #define RE_CPlusMode 0x20 /* In Revision ID */ 1087 1088 /* interrupt service routine loop time*/ 1089 /* the minimum value is 1 */ 1090 #define INTR_MAX_LOOP 1 1091 1092 /*#define RE_DBG*/ 1093 1094 #ifdef RE_DBG 1095 #define DBGPRINT(_unit, _msg) printf ("re%d: %s\n", _unit,_msg) 1096 #define DBGPRINT1(_unit, _msg, _para1) \ 1097 { \ 1098 char buf[100]; \ 1099 sprintf(buf,_msg,_para1); \ 1100 printf ("re%d: %s\n", _unit,buf); \ 1101 } 1102 #else 1103 #define DBGPRINT(_unit, _msg) 1104 #define DBGPRINT1(_unit, _msg, _para1) 1105 #endif 1106 1107 #ifndef __DragonFly__ 1108 #if OS_VER<VERSION(4,9) 1109 #define IFM_1000_T IFM_1000_TX 1110 #elif OS_VER<VERSION(6,0) 1111 #define RE_GET_IFNET(SC) &SC->arpcom.ac_if 1112 #define if_drv_flags if_flags 1113 #define IFF_DRV_RUNNING IFF_RUNNING 1114 #define IFF_DRV_OACTIVE IFF_OACTIVE 1115 #else 1116 #define RE_GET_IFNET(SC) SC->re_ifp 1117 #endif 1118 1119 #if OS_VER>=VERSION(10,0) 1120 #define IF_ADDR_LOCK IF_ADDR_WLOCK 1121 #define IF_ADDR_UNLOCK IF_ADDR_WUNLOCK 1122 #endif 1123 1124 #if OS_VER>=VERSION(7,4) 1125 #if OS_VER>=VERSION(9,2) 1126 #define RE_PCIEM_LINK_CAP_ASPM PCIEM_LINK_CAP_ASPM 1127 #define RE_PCIER_LINK_CTL PCIER_LINK_CTL 1128 #define RE_PCIER_LINK_CAP PCIER_LINK_CAP 1129 #else //OS_VER>=VERSION(9,2) 1130 #define RE_PCIEM_LINK_CAP_ASPM PCIM_LINK_CAP_ASPM 1131 #define RE_PCIER_LINK_CTL PCIR_EXPRESS_LINK_CTL 1132 #define RE_PCIER_LINK_CAP PCIR_EXPRESS_LINK_CAP 1133 #endif 1134 #endif //OS_VER>=VERSION(7,4) 1135 #endif /* !__DragonFly__ */ 1136