1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.14 2004/07/23 07:16:28 joerg Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $ 36 */ 37 38 /* 39 * RealTek 8129/8139 PCI NIC driver 40 * 41 * Supports several extremely cheap PCI 10/100 adapters based on 42 * the RealTek chipset. Datasheets can be obtained from 43 * www.realtek.com.tw. 44 * 45 * Written by Bill Paul <wpaul@ctr.columbia.edu> 46 * Electrical Engineering Department 47 * Columbia University, New York City 48 */ 49 50 /* 51 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 52 * probably the worst PCI ethernet controller ever made, with the possible 53 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 54 * DMA, but it has a terrible interface that nullifies any performance 55 * gains that bus-master DMA usually offers. 56 * 57 * For transmission, the chip offers a series of four TX descriptor 58 * registers. Each transmit frame must be in a contiguous buffer, aligned 59 * on a longword (32-bit) boundary. This means we almost always have to 60 * do mbuf copies in order to transmit a frame, except in the unlikely 61 * case where a) the packet fits into a single mbuf, and b) the packet 62 * is 32-bit aligned within the mbuf's data area. The presence of only 63 * four descriptor registers means that we can never have more than four 64 * packets queued for transmission at any one time. 65 * 66 * Reception is not much better. The driver has to allocate a single large 67 * buffer area (up to 64K in size) into which the chip will DMA received 68 * frames. Because we don't know where within this region received packets 69 * will begin or end, we have no choice but to copy data from the buffer 70 * area into mbufs in order to pass the packets up to the higher protocol 71 * levels. 72 * 73 * It's impossible given this rotten design to really achieve decent 74 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 75 * some equally overmuscled CPU to drive it. 76 * 77 * On the bright side, the 8139 does have a built-in PHY, although 78 * rather than using an MDIO serial interface like most other NICs, the 79 * PHY registers are directly accessible through the 8139's register 80 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 81 * filter. 82 * 83 * The 8129 chip is an older version of the 8139 that uses an external PHY 84 * chip. The 8129 has a serial MDIO interface for accessing the MII where 85 * the 8139 lets you directly access the on-board PHY registers. We need 86 * to select which interface to use depending on the chip type. 87 */ 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 97 #include <net/if.h> 98 #include <net/if_arp.h> 99 #include <net/ethernet.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 103 #include <net/bpf.h> 104 105 #include <vm/vm.h> /* for vtophys */ 106 #include <vm/pmap.h> /* for vtophys */ 107 #include <machine/clock.h> /* for DELAY */ 108 #include <machine/bus_pio.h> 109 #include <machine/bus_memio.h> 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #include "../mii_layer/mii.h" 116 #include "../mii_layer/miivar.h" 117 118 #include <bus/pci/pcireg.h> 119 #include <bus/pci/pcivar.h> 120 121 /* "controller miibus0" required. See GENERIC if you get errors here. */ 122 #include "miibus_if.h" 123 124 /* 125 * Default to using PIO access for this driver. On SMP systems, 126 * there appear to be problems with memory mapped mode: it looks like 127 * doing too many memory mapped access back to back in rapid succession 128 * can hang the bus. I'm inclined to blame this on crummy design/construction 129 * on the part of RealTek. Memory mapped mode does appear to work on 130 * uniprocessor systems though. 131 */ 132 #define RL_USEIOSPACE 133 134 #include "if_rlreg.h" 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 static struct rl_type rl_devs[] = { 140 { RT_VENDORID, RT_DEVICEID_8129, 141 "RealTek 8129 10/100BaseTX" }, 142 { RT_VENDORID, RT_DEVICEID_8139, 143 "RealTek 8139 10/100BaseTX" }, 144 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 145 "Accton MPX 5030/5038 10/100BaseTX" }, 146 { DELTA_VENDORID, DELTA_DEVICEID_8139, 147 "Delta Electronics 8139 10/100BaseTX" }, 148 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 149 "Addtron Technolgy 8139 10/100BaseTX" }, 150 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 151 "D-Link DFE-530TX+ 10/100BaseTX" }, 152 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 153 "Nortel Networks 10/100BaseTX" }, 154 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, 155 "Peppercon AG ROL/F" }, 156 { 0, 0, NULL } 157 }; 158 159 static int rl_probe (device_t); 160 static int rl_attach (device_t); 161 static int rl_detach (device_t); 162 163 static int rl_encap (struct rl_softc *, struct mbuf * ); 164 165 static void rl_rxeof (struct rl_softc *); 166 static void rl_txeof (struct rl_softc *); 167 static void rl_intr (void *); 168 static void rl_tick (void *); 169 static void rl_start (struct ifnet *); 170 static int rl_ioctl (struct ifnet *, u_long, caddr_t, 171 struct ucred *); 172 static void rl_init (void *); 173 static void rl_stop (struct rl_softc *); 174 static void rl_watchdog (struct ifnet *); 175 static int rl_suspend (device_t); 176 static int rl_resume (device_t); 177 static void rl_shutdown (device_t); 178 static int rl_ifmedia_upd (struct ifnet *); 179 static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 180 181 static void rl_eeprom_putbyte (struct rl_softc *, int); 182 static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 183 static void rl_read_eeprom (struct rl_softc *, caddr_t, 184 int, int, int); 185 static void rl_mii_sync (struct rl_softc *); 186 static void rl_mii_send (struct rl_softc *, u_int32_t, int); 187 static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 188 static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 189 190 static int rl_miibus_readreg (device_t, int, int); 191 static int rl_miibus_writereg (device_t, int, int, int); 192 static void rl_miibus_statchg (device_t); 193 194 static u_int8_t rl_calchash (caddr_t); 195 static void rl_setmulti (struct rl_softc *); 196 static void rl_reset (struct rl_softc *); 197 static int rl_list_tx_init (struct rl_softc *); 198 199 #ifdef RL_USEIOSPACE 200 #define RL_RES SYS_RES_IOPORT 201 #define RL_RID RL_PCI_LOIO 202 #else 203 #define RL_RES SYS_RES_MEMORY 204 #define RL_RID RL_PCI_LOMEM 205 #endif 206 207 static device_method_t rl_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_probe, rl_probe), 210 DEVMETHOD(device_attach, rl_attach), 211 DEVMETHOD(device_detach, rl_detach), 212 DEVMETHOD(device_suspend, rl_suspend), 213 DEVMETHOD(device_resume, rl_resume), 214 DEVMETHOD(device_shutdown, rl_shutdown), 215 216 /* bus interface */ 217 DEVMETHOD(bus_print_child, bus_generic_print_child), 218 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 219 220 /* MII interface */ 221 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 222 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 223 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 224 225 { 0, 0 } 226 }; 227 228 static driver_t rl_driver = { 229 "rl", 230 rl_methods, 231 sizeof(struct rl_softc) 232 }; 233 234 static devclass_t rl_devclass; 235 236 DECLARE_DUMMY_MODULE(if_rl); 237 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 238 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 239 240 #define EE_SET(x) \ 241 CSR_WRITE_1(sc, RL_EECMD, \ 242 CSR_READ_1(sc, RL_EECMD) | x) 243 244 #define EE_CLR(x) \ 245 CSR_WRITE_1(sc, RL_EECMD, \ 246 CSR_READ_1(sc, RL_EECMD) & ~x) 247 248 /* 249 * Send a read command and address to the EEPROM, check for ACK. 250 */ 251 static void rl_eeprom_putbyte(sc, addr) 252 struct rl_softc *sc; 253 int addr; 254 { 255 int d, i; 256 257 d = addr | RL_EECMD_READ; 258 259 /* 260 * Feed in each bit and strobe the clock. 261 */ 262 for (i = 0x400; i; i >>= 1) { 263 if (d & i) { 264 EE_SET(RL_EE_DATAIN); 265 } else { 266 EE_CLR(RL_EE_DATAIN); 267 } 268 DELAY(100); 269 EE_SET(RL_EE_CLK); 270 DELAY(150); 271 EE_CLR(RL_EE_CLK); 272 DELAY(100); 273 } 274 275 return; 276 } 277 278 /* 279 * Read a word of data stored in the EEPROM at address 'addr.' 280 */ 281 static void rl_eeprom_getword(sc, addr, dest) 282 struct rl_softc *sc; 283 int addr; 284 u_int16_t *dest; 285 { 286 int i; 287 u_int16_t word = 0; 288 289 /* Enter EEPROM access mode. */ 290 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 291 292 /* 293 * Send address of word we want to read. 294 */ 295 rl_eeprom_putbyte(sc, addr); 296 297 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 298 299 /* 300 * Start reading bits from EEPROM. 301 */ 302 for (i = 0x8000; i; i >>= 1) { 303 EE_SET(RL_EE_CLK); 304 DELAY(100); 305 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 306 word |= i; 307 EE_CLR(RL_EE_CLK); 308 DELAY(100); 309 } 310 311 /* Turn off EEPROM access mode. */ 312 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 313 314 *dest = word; 315 316 return; 317 } 318 319 /* 320 * Read a sequence of words from the EEPROM. 321 */ 322 static void rl_read_eeprom(sc, dest, off, cnt, swap) 323 struct rl_softc *sc; 324 caddr_t dest; 325 int off; 326 int cnt; 327 int swap; 328 { 329 int i; 330 u_int16_t word = 0, *ptr; 331 332 for (i = 0; i < cnt; i++) { 333 rl_eeprom_getword(sc, off + i, &word); 334 ptr = (u_int16_t *)(dest + (i * 2)); 335 if (swap) 336 *ptr = ntohs(word); 337 else 338 *ptr = word; 339 } 340 341 return; 342 } 343 344 345 /* 346 * MII access routines are provided for the 8129, which 347 * doesn't have a built-in PHY. For the 8139, we fake things 348 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 349 * direct access PHY registers. 350 */ 351 #define MII_SET(x) \ 352 CSR_WRITE_1(sc, RL_MII, \ 353 CSR_READ_1(sc, RL_MII) | x) 354 355 #define MII_CLR(x) \ 356 CSR_WRITE_1(sc, RL_MII, \ 357 CSR_READ_1(sc, RL_MII) & ~x) 358 359 /* 360 * Sync the PHYs by setting data bit and strobing the clock 32 times. 361 */ 362 static void rl_mii_sync(sc) 363 struct rl_softc *sc; 364 { 365 int i; 366 367 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 368 369 for (i = 0; i < 32; i++) { 370 MII_SET(RL_MII_CLK); 371 DELAY(1); 372 MII_CLR(RL_MII_CLK); 373 DELAY(1); 374 } 375 376 return; 377 } 378 379 /* 380 * Clock a series of bits through the MII. 381 */ 382 static void rl_mii_send(sc, bits, cnt) 383 struct rl_softc *sc; 384 u_int32_t bits; 385 int cnt; 386 { 387 int i; 388 389 MII_CLR(RL_MII_CLK); 390 391 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 392 if (bits & i) { 393 MII_SET(RL_MII_DATAOUT); 394 } else { 395 MII_CLR(RL_MII_DATAOUT); 396 } 397 DELAY(1); 398 MII_CLR(RL_MII_CLK); 399 DELAY(1); 400 MII_SET(RL_MII_CLK); 401 } 402 } 403 404 /* 405 * Read an PHY register through the MII. 406 */ 407 static int rl_mii_readreg(sc, frame) 408 struct rl_softc *sc; 409 struct rl_mii_frame *frame; 410 411 { 412 int i, ack, s; 413 414 s = splimp(); 415 416 /* 417 * Set up frame for RX. 418 */ 419 frame->mii_stdelim = RL_MII_STARTDELIM; 420 frame->mii_opcode = RL_MII_READOP; 421 frame->mii_turnaround = 0; 422 frame->mii_data = 0; 423 424 CSR_WRITE_2(sc, RL_MII, 0); 425 426 /* 427 * Turn on data xmit. 428 */ 429 MII_SET(RL_MII_DIR); 430 431 rl_mii_sync(sc); 432 433 /* 434 * Send command/address info. 435 */ 436 rl_mii_send(sc, frame->mii_stdelim, 2); 437 rl_mii_send(sc, frame->mii_opcode, 2); 438 rl_mii_send(sc, frame->mii_phyaddr, 5); 439 rl_mii_send(sc, frame->mii_regaddr, 5); 440 441 /* Idle bit */ 442 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 443 DELAY(1); 444 MII_SET(RL_MII_CLK); 445 DELAY(1); 446 447 /* Turn off xmit. */ 448 MII_CLR(RL_MII_DIR); 449 450 /* Check for ack */ 451 MII_CLR(RL_MII_CLK); 452 DELAY(1); 453 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 454 MII_SET(RL_MII_CLK); 455 DELAY(1); 456 457 /* 458 * Now try reading data bits. If the ack failed, we still 459 * need to clock through 16 cycles to keep the PHY(s) in sync. 460 */ 461 if (ack) { 462 for(i = 0; i < 16; i++) { 463 MII_CLR(RL_MII_CLK); 464 DELAY(1); 465 MII_SET(RL_MII_CLK); 466 DELAY(1); 467 } 468 goto fail; 469 } 470 471 for (i = 0x8000; i; i >>= 1) { 472 MII_CLR(RL_MII_CLK); 473 DELAY(1); 474 if (!ack) { 475 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 476 frame->mii_data |= i; 477 DELAY(1); 478 } 479 MII_SET(RL_MII_CLK); 480 DELAY(1); 481 } 482 483 fail: 484 485 MII_CLR(RL_MII_CLK); 486 DELAY(1); 487 MII_SET(RL_MII_CLK); 488 DELAY(1); 489 490 splx(s); 491 492 if (ack) 493 return(1); 494 return(0); 495 } 496 497 /* 498 * Write to a PHY register through the MII. 499 */ 500 static int rl_mii_writereg(sc, frame) 501 struct rl_softc *sc; 502 struct rl_mii_frame *frame; 503 504 { 505 int s; 506 507 s = splimp(); 508 /* 509 * Set up frame for TX. 510 */ 511 512 frame->mii_stdelim = RL_MII_STARTDELIM; 513 frame->mii_opcode = RL_MII_WRITEOP; 514 frame->mii_turnaround = RL_MII_TURNAROUND; 515 516 /* 517 * Turn on data output. 518 */ 519 MII_SET(RL_MII_DIR); 520 521 rl_mii_sync(sc); 522 523 rl_mii_send(sc, frame->mii_stdelim, 2); 524 rl_mii_send(sc, frame->mii_opcode, 2); 525 rl_mii_send(sc, frame->mii_phyaddr, 5); 526 rl_mii_send(sc, frame->mii_regaddr, 5); 527 rl_mii_send(sc, frame->mii_turnaround, 2); 528 rl_mii_send(sc, frame->mii_data, 16); 529 530 /* Idle bit. */ 531 MII_SET(RL_MII_CLK); 532 DELAY(1); 533 MII_CLR(RL_MII_CLK); 534 DELAY(1); 535 536 /* 537 * Turn off xmit. 538 */ 539 MII_CLR(RL_MII_DIR); 540 541 splx(s); 542 543 return(0); 544 } 545 546 static int rl_miibus_readreg(dev, phy, reg) 547 device_t dev; 548 int phy, reg; 549 { 550 struct rl_softc *sc; 551 struct rl_mii_frame frame; 552 u_int16_t rval = 0; 553 u_int16_t rl8139_reg = 0; 554 555 sc = device_get_softc(dev); 556 557 if (sc->rl_type == RL_8139) { 558 /* Pretend the internal PHY is only at address 0 */ 559 if (phy) 560 return(0); 561 switch(reg) { 562 case MII_BMCR: 563 rl8139_reg = RL_BMCR; 564 break; 565 case MII_BMSR: 566 rl8139_reg = RL_BMSR; 567 break; 568 case MII_ANAR: 569 rl8139_reg = RL_ANAR; 570 break; 571 case MII_ANER: 572 rl8139_reg = RL_ANER; 573 break; 574 case MII_ANLPAR: 575 rl8139_reg = RL_LPAR; 576 break; 577 case MII_PHYIDR1: 578 case MII_PHYIDR2: 579 return(0); 580 break; 581 /* 582 * Allow the rlphy driver to read the media status 583 * register. If we have a link partner which does not 584 * support NWAY, this is the register which will tell 585 * us the results of parallel detection. 586 */ 587 case RL_MEDIASTAT: 588 rval = CSR_READ_1(sc, RL_MEDIASTAT); 589 return(rval); 590 break; 591 default: 592 printf("rl%d: bad phy register\n", sc->rl_unit); 593 return(0); 594 } 595 rval = CSR_READ_2(sc, rl8139_reg); 596 return(rval); 597 } 598 599 bzero((char *)&frame, sizeof(frame)); 600 601 frame.mii_phyaddr = phy; 602 frame.mii_regaddr = reg; 603 rl_mii_readreg(sc, &frame); 604 605 return(frame.mii_data); 606 } 607 608 static int rl_miibus_writereg(dev, phy, reg, data) 609 device_t dev; 610 int phy, reg, data; 611 { 612 struct rl_softc *sc; 613 struct rl_mii_frame frame; 614 u_int16_t rl8139_reg = 0; 615 616 sc = device_get_softc(dev); 617 618 if (sc->rl_type == RL_8139) { 619 /* Pretend the internal PHY is only at address 0 */ 620 if (phy) 621 return(0); 622 switch(reg) { 623 case MII_BMCR: 624 rl8139_reg = RL_BMCR; 625 break; 626 case MII_BMSR: 627 rl8139_reg = RL_BMSR; 628 break; 629 case MII_ANAR: 630 rl8139_reg = RL_ANAR; 631 break; 632 case MII_ANER: 633 rl8139_reg = RL_ANER; 634 break; 635 case MII_ANLPAR: 636 rl8139_reg = RL_LPAR; 637 break; 638 case MII_PHYIDR1: 639 case MII_PHYIDR2: 640 return(0); 641 break; 642 default: 643 printf("rl%d: bad phy register\n", sc->rl_unit); 644 return(0); 645 } 646 CSR_WRITE_2(sc, rl8139_reg, data); 647 return(0); 648 } 649 650 bzero((char *)&frame, sizeof(frame)); 651 652 frame.mii_phyaddr = phy; 653 frame.mii_regaddr = reg; 654 frame.mii_data = data; 655 656 rl_mii_writereg(sc, &frame); 657 658 return(0); 659 } 660 661 static void rl_miibus_statchg(dev) 662 device_t dev; 663 { 664 return; 665 } 666 667 /* 668 * Calculate CRC of a multicast group address, return the upper 6 bits. 669 */ 670 static u_int8_t rl_calchash(addr) 671 caddr_t addr; 672 { 673 u_int32_t crc, carry; 674 int i, j; 675 u_int8_t c; 676 677 /* Compute CRC for the address value. */ 678 crc = 0xFFFFFFFF; /* initial value */ 679 680 for (i = 0; i < 6; i++) { 681 c = *(addr + i); 682 for (j = 0; j < 8; j++) { 683 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 684 crc <<= 1; 685 c >>= 1; 686 if (carry) 687 crc = (crc ^ 0x04c11db6) | carry; 688 } 689 } 690 691 /* return the filter bit position */ 692 return(crc >> 26); 693 } 694 695 /* 696 * Program the 64-bit multicast hash filter. 697 */ 698 static void rl_setmulti(sc) 699 struct rl_softc *sc; 700 { 701 struct ifnet *ifp; 702 int h = 0; 703 u_int32_t hashes[2] = { 0, 0 }; 704 struct ifmultiaddr *ifma; 705 u_int32_t rxfilt; 706 int mcnt = 0; 707 708 ifp = &sc->arpcom.ac_if; 709 710 rxfilt = CSR_READ_4(sc, RL_RXCFG); 711 712 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 713 rxfilt |= RL_RXCFG_RX_MULTI; 714 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 715 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 716 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 717 return; 718 } 719 720 /* first, zot all the existing hash bits */ 721 CSR_WRITE_4(sc, RL_MAR0, 0); 722 CSR_WRITE_4(sc, RL_MAR4, 0); 723 724 /* now program new ones */ 725 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 726 ifma = ifma->ifma_link.le_next) { 727 if (ifma->ifma_addr->sa_family != AF_LINK) 728 continue; 729 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 730 if (h < 32) 731 hashes[0] |= (1 << h); 732 else 733 hashes[1] |= (1 << (h - 32)); 734 mcnt++; 735 } 736 737 if (mcnt) 738 rxfilt |= RL_RXCFG_RX_MULTI; 739 else 740 rxfilt &= ~RL_RXCFG_RX_MULTI; 741 742 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 743 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 744 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 745 746 return; 747 } 748 749 static void rl_reset(sc) 750 struct rl_softc *sc; 751 { 752 int i; 753 754 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 755 756 for (i = 0; i < RL_TIMEOUT; i++) { 757 DELAY(10); 758 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 759 break; 760 } 761 if (i == RL_TIMEOUT) 762 printf("rl%d: reset never completed!\n", sc->rl_unit); 763 764 return; 765 } 766 767 /* 768 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 769 * IDs against our list and return a device name if we find a match. 770 * 771 * Return with a value < 0 to give re(4) a change to attach. 772 */ 773 static int rl_probe(dev) 774 device_t dev; 775 { 776 struct rl_type *t; 777 778 for (t = rl_devs; t->rl_name != NULL; t++) { 779 if ((pci_get_vendor(dev) == t->rl_vid) && 780 (pci_get_device(dev) == t->rl_did)) 781 return(-100); 782 } 783 784 return(ENXIO); 785 } 786 787 /* 788 * Attach the interface. Allocate softc structures, do ifmedia 789 * setup and ethernet/BPF attach. 790 */ 791 static int rl_attach(dev) 792 device_t dev; 793 { 794 int s; 795 u_char eaddr[ETHER_ADDR_LEN]; 796 u_int32_t command; 797 struct rl_softc *sc; 798 struct ifnet *ifp; 799 u_int16_t rl_did = 0; 800 int unit, error = 0, rid; 801 struct rl_type *t; 802 803 for (t = rl_devs; t->rl_name != NULL; t++) { 804 if ((pci_get_vendor(dev) == t->rl_vid) && 805 (pci_get_device(dev) == t->rl_did)) { 806 device_set_desc(dev, t->rl_name); 807 break; 808 } 809 } 810 811 s = splimp(); 812 813 sc = device_get_softc(dev); 814 unit = device_get_unit(dev); 815 bzero(sc, sizeof(struct rl_softc)); 816 817 /* 818 * Handle power management nonsense. 819 */ 820 821 command = pci_read_config(dev, RL_PCI_CAPID, 4) & 0x000000FF; 822 if (command == 0x01) { 823 824 command = pci_read_config(dev, RL_PCI_PWRMGMTCTRL, 4); 825 if (command & RL_PSTATE_MASK) { 826 u_int32_t iobase, membase, irq; 827 828 /* Save important PCI config data. */ 829 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 830 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 831 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 832 833 /* Reset the power state. */ 834 printf("rl%d: chip is is in D%d power mode " 835 "-- setting to D0\n", unit, command & RL_PSTATE_MASK); 836 command &= 0xFFFFFFFC; 837 pci_write_config(dev, RL_PCI_PWRMGMTCTRL, command, 4); 838 839 /* Restore PCI config data. */ 840 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 841 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 842 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 843 } 844 } 845 846 /* 847 * Map control/status registers. 848 */ 849 command = pci_read_config(dev, PCIR_COMMAND, 4); 850 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 851 pci_write_config(dev, PCIR_COMMAND, command, 4); 852 command = pci_read_config(dev, PCIR_COMMAND, 4); 853 854 #ifdef RL_USEIOSPACE 855 if (!(command & PCIM_CMD_PORTEN)) { 856 printf("rl%d: failed to enable I/O ports!\n", unit); 857 error = ENXIO; 858 goto fail; 859 } 860 #else 861 if (!(command & PCIM_CMD_MEMEN)) { 862 printf("rl%d: failed to enable memory mapping!\n", unit); 863 error = ENXIO; 864 goto fail; 865 } 866 #endif 867 868 rid = RL_RID; 869 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 870 0, ~0, 1, RF_ACTIVE); 871 872 if (sc->rl_res == NULL) { 873 printf ("rl%d: couldn't map ports/memory\n", unit); 874 error = ENXIO; 875 goto fail; 876 } 877 878 sc->rl_btag = rman_get_bustag(sc->rl_res); 879 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 880 881 rid = 0; 882 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 883 RF_SHAREABLE | RF_ACTIVE); 884 885 if (sc->rl_irq == NULL) { 886 printf("rl%d: couldn't map interrupt\n", unit); 887 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 888 error = ENXIO; 889 goto fail; 890 } 891 892 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 893 rl_intr, sc, &sc->rl_intrhand); 894 895 if (error) { 896 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 897 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 898 printf("rl%d: couldn't set up irq\n", unit); 899 goto fail; 900 } 901 902 callout_handle_init(&sc->rl_stat_ch); 903 904 /* Reset the adapter. */ 905 rl_reset(sc); 906 907 /* 908 * Get station address from the EEPROM. 909 */ 910 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 911 912 sc->rl_unit = unit; 913 914 /* 915 * Now read the exact device type from the EEPROM to find 916 * out if it's an 8129 or 8139. 917 */ 918 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 919 920 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 921 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 922 rl_did == DLINK_DEVICEID_530TXPLUS) 923 sc->rl_type = RL_8139; 924 else if (rl_did == RT_DEVICEID_8129) 925 sc->rl_type = RL_8129; 926 else { 927 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 928 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 929 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 930 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 931 error = ENXIO; 932 goto fail; 933 } 934 935 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 1518, M_DEVBUF, 936 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 937 938 if (sc->rl_cdata.rl_rx_buf == NULL) { 939 printf("rl%d: no memory for list buffers!\n", unit); 940 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 941 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 942 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 943 error = ENXIO; 944 goto fail; 945 } 946 947 /* Leave a few bytes before the start of the RX ring buffer. */ 948 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 949 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 950 951 /* Do MII setup */ 952 if (mii_phy_probe(dev, &sc->rl_miibus, 953 rl_ifmedia_upd, rl_ifmedia_sts)) { 954 printf("rl%d: MII without any phy!\n", sc->rl_unit); 955 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 1518, 956 M_DEVBUF); 957 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 958 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 959 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 960 free(sc->rl_cdata.rl_rx_buf, M_DEVBUF); 961 error = ENXIO; 962 goto fail; 963 } 964 965 ifp = &sc->arpcom.ac_if; 966 ifp->if_softc = sc; 967 if_initname(ifp, "rl", unit); 968 ifp->if_mtu = ETHERMTU; 969 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 970 ifp->if_ioctl = rl_ioctl; 971 ifp->if_start = rl_start; 972 ifp->if_watchdog = rl_watchdog; 973 ifp->if_init = rl_init; 974 ifp->if_baudrate = 10000000; 975 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 976 977 /* 978 * Call MI attach routine. 979 */ 980 ether_ifattach(ifp, eaddr); 981 982 fail: 983 splx(s); 984 return(error); 985 } 986 987 static int rl_detach(dev) 988 device_t dev; 989 { 990 struct rl_softc *sc; 991 struct ifnet *ifp; 992 int s; 993 994 s = splimp(); 995 996 sc = device_get_softc(dev); 997 ifp = &sc->arpcom.ac_if; 998 999 ether_ifdetach(ifp); 1000 rl_stop(sc); 1001 1002 bus_generic_detach(dev); 1003 device_delete_child(dev, sc->rl_miibus); 1004 1005 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1006 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1007 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1008 1009 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 1518, M_DEVBUF); 1010 1011 splx(s); 1012 1013 return(0); 1014 } 1015 1016 /* 1017 * Initialize the transmit descriptors. 1018 */ 1019 static int rl_list_tx_init(sc) 1020 struct rl_softc *sc; 1021 { 1022 struct rl_chain_data *cd; 1023 int i; 1024 1025 cd = &sc->rl_cdata; 1026 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1027 cd->rl_tx_chain[i] = NULL; 1028 CSR_WRITE_4(sc, 1029 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1030 } 1031 1032 sc->rl_cdata.cur_tx = 0; 1033 sc->rl_cdata.last_tx = 0; 1034 1035 return(0); 1036 } 1037 1038 /* 1039 * A frame has been uploaded: pass the resulting mbuf chain up to 1040 * the higher level protocols. 1041 * 1042 * You know there's something wrong with a PCI bus-master chip design 1043 * when you have to use m_devget(). 1044 * 1045 * The receive operation is badly documented in the datasheet, so I'll 1046 * attempt to document it here. The driver provides a buffer area and 1047 * places its base address in the RX buffer start address register. 1048 * The chip then begins copying frames into the RX buffer. Each frame 1049 * is preceeded by a 32-bit RX status word which specifies the length 1050 * of the frame and certain other status bits. Each frame (starting with 1051 * the status word) is also 32-bit aligned. The frame length is in the 1052 * first 16 bits of the status word; the lower 15 bits correspond with 1053 * the 'rx status register' mentioned in the datasheet. 1054 * 1055 * Note: to make the Alpha happy, the frame payload needs to be aligned 1056 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 1057 * the ring buffer starting at an address two bytes before the actual 1058 * data location. We can then shave off the first two bytes using m_adj(). 1059 * The reason we do this is because m_devget() doesn't let us specify an 1060 * offset into the mbuf storage space, so we have to artificially create 1061 * one. The ring is allocated in such a way that there are a few unused 1062 * bytes of space preceecing it so that it will be safe for us to do the 1063 * 2-byte backstep even if reading from the ring at offset 0. 1064 */ 1065 static void rl_rxeof(sc) 1066 struct rl_softc *sc; 1067 { 1068 struct mbuf *m; 1069 struct ifnet *ifp; 1070 int total_len = 0; 1071 u_int32_t rxstat; 1072 caddr_t rxbufpos; 1073 int wrap = 0; 1074 u_int16_t cur_rx; 1075 u_int16_t limit; 1076 u_int16_t rx_bytes = 0, max_bytes; 1077 1078 ifp = &sc->arpcom.ac_if; 1079 1080 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1081 1082 /* Do not try to read past this point. */ 1083 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1084 1085 if (limit < cur_rx) 1086 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1087 else 1088 max_bytes = limit - cur_rx; 1089 1090 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1091 #ifdef DEVICE_POLLING 1092 if (ifp->if_flags & IFF_POLLING) { 1093 if (sc->rxcycles <= 0) 1094 break; 1095 sc->rxcycles--; 1096 } 1097 #endif /* DEVICE_POLLING */ 1098 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1099 rxstat = *(u_int32_t *)rxbufpos; 1100 1101 /* 1102 * Here's a totally undocumented fact for you. When the 1103 * RealTek chip is in the process of copying a packet into 1104 * RAM for you, the length will be 0xfff0. If you spot a 1105 * packet header with this value, you need to stop. The 1106 * datasheet makes absolutely no mention of this and 1107 * RealTek should be shot for this. 1108 */ 1109 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1110 break; 1111 1112 if (!(rxstat & RL_RXSTAT_RXOK)) { 1113 ifp->if_ierrors++; 1114 rl_init(sc); 1115 return; 1116 } 1117 1118 /* No errors; receive the packet. */ 1119 total_len = rxstat >> 16; 1120 rx_bytes += total_len + 4; 1121 1122 /* 1123 * XXX The RealTek chip includes the CRC with every 1124 * received frame, and there's no way to turn this 1125 * behavior off (at least, I can't find anything in 1126 * the manual that explains how to do it) so we have 1127 * to trim off the CRC manually. 1128 */ 1129 total_len -= ETHER_CRC_LEN; 1130 1131 /* 1132 * Avoid trying to read more bytes than we know 1133 * the chip has prepared for us. 1134 */ 1135 if (rx_bytes > max_bytes) 1136 break; 1137 1138 rxbufpos = sc->rl_cdata.rl_rx_buf + 1139 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1140 1141 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1142 rxbufpos = sc->rl_cdata.rl_rx_buf; 1143 1144 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1145 1146 if (total_len > wrap) { 1147 /* 1148 * Fool m_devget() into thinking we want to copy 1149 * the whole buffer so we don't end up fragmenting 1150 * the data. 1151 */ 1152 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1153 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1154 if (m == NULL) { 1155 ifp->if_ierrors++; 1156 } else { 1157 m_adj(m, RL_ETHER_ALIGN); 1158 m_copyback(m, wrap, total_len - wrap, 1159 sc->rl_cdata.rl_rx_buf); 1160 } 1161 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1162 } else { 1163 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1164 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1165 if (m == NULL) { 1166 ifp->if_ierrors++; 1167 } else 1168 m_adj(m, RL_ETHER_ALIGN); 1169 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1170 } 1171 1172 /* 1173 * Round up to 32-bit boundary. 1174 */ 1175 cur_rx = (cur_rx + 3) & ~3; 1176 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1177 1178 if (m == NULL) 1179 continue; 1180 1181 ifp->if_ipackets++; 1182 1183 (*ifp->if_input)(ifp, m); 1184 } 1185 1186 return; 1187 } 1188 1189 /* 1190 * A frame was downloaded to the chip. It's safe for us to clean up 1191 * the list buffers. 1192 */ 1193 static void rl_txeof(sc) 1194 struct rl_softc *sc; 1195 { 1196 struct ifnet *ifp; 1197 u_int32_t txstat; 1198 1199 ifp = &sc->arpcom.ac_if; 1200 1201 /* 1202 * Go through our tx list and free mbufs for those 1203 * frames that have been uploaded. 1204 */ 1205 do { 1206 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1207 if (!(txstat & (RL_TXSTAT_TX_OK| 1208 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1209 break; 1210 1211 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1212 1213 if (RL_LAST_TXMBUF(sc) != NULL) { 1214 m_freem(RL_LAST_TXMBUF(sc)); 1215 RL_LAST_TXMBUF(sc) = NULL; 1216 } 1217 if (txstat & RL_TXSTAT_TX_OK) 1218 ifp->if_opackets++; 1219 else { 1220 int oldthresh; 1221 ifp->if_oerrors++; 1222 if ((txstat & RL_TXSTAT_TXABRT) || 1223 (txstat & RL_TXSTAT_OUTOFWIN)) 1224 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1225 oldthresh = sc->rl_txthresh; 1226 /* error recovery */ 1227 rl_reset(sc); 1228 rl_init(sc); 1229 /* 1230 * If there was a transmit underrun, 1231 * bump the TX threshold. 1232 */ 1233 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1234 sc->rl_txthresh = oldthresh + 32; 1235 return; 1236 } 1237 RL_INC(sc->rl_cdata.last_tx); 1238 ifp->if_flags &= ~IFF_OACTIVE; 1239 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1240 1241 ifp->if_timer = 1242 (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 1243 1244 return; 1245 } 1246 1247 static void rl_tick(xsc) 1248 void *xsc; 1249 { 1250 struct rl_softc *sc; 1251 struct mii_data *mii; 1252 int s; 1253 1254 s = splimp(); 1255 1256 sc = xsc; 1257 mii = device_get_softc(sc->rl_miibus); 1258 1259 mii_tick(mii); 1260 1261 splx(s); 1262 1263 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1264 1265 return; 1266 } 1267 1268 #ifdef DEVICE_POLLING 1269 static poll_handler_t rl_poll; 1270 1271 static void 1272 rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1273 { 1274 struct rl_softc *sc = ifp->if_softc; 1275 1276 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1277 CSR_WRITE_4(sc, RL_IMR, RL_INTRS); 1278 return; 1279 } 1280 1281 sc->rxcycles = count; 1282 rl_rxeof(sc); 1283 rl_txeof(sc); 1284 if (ifp->if_snd.ifq_head != NULL) 1285 rl_start(ifp); 1286 1287 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1288 u_int16_t status; 1289 1290 status = CSR_READ_2(sc, RL_ISR); 1291 if (status) 1292 CSR_WRITE_2(sc, RL_ISR, status); 1293 1294 /* 1295 * XXX check behaviour on receiver stalls. 1296 */ 1297 1298 if (status & RL_ISR_SYSTEM_ERR) { 1299 rl_reset(sc); 1300 rl_init(sc); 1301 } 1302 } 1303 } 1304 #endif /* DEVICE_POLLING */ 1305 1306 static void rl_intr(arg) 1307 void *arg; 1308 { 1309 struct rl_softc *sc; 1310 struct ifnet *ifp; 1311 u_int16_t status; 1312 1313 sc = arg; 1314 1315 if (sc->suspended) { 1316 return; 1317 } 1318 1319 ifp = &sc->arpcom.ac_if; 1320 #ifdef DEVICE_POLLING 1321 if (ifp->if_flags & IFF_POLLING) 1322 return; 1323 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 1324 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1325 rl_poll(ifp, 0, 1); 1326 return; 1327 } 1328 #endif /* DEVICE_POLLING */ 1329 1330 for (;;) { 1331 1332 status = CSR_READ_2(sc, RL_ISR); 1333 if (status) 1334 CSR_WRITE_2(sc, RL_ISR, status); 1335 1336 if ((status & RL_INTRS) == 0) 1337 break; 1338 1339 if (status & RL_ISR_RX_OK) 1340 rl_rxeof(sc); 1341 1342 if (status & RL_ISR_RX_ERR) 1343 rl_rxeof(sc); 1344 1345 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1346 rl_txeof(sc); 1347 1348 if (status & RL_ISR_SYSTEM_ERR) { 1349 rl_reset(sc); 1350 rl_init(sc); 1351 } 1352 1353 } 1354 if (ifp->if_snd.ifq_head != NULL) 1355 rl_start(ifp); 1356 1357 return; 1358 } 1359 1360 /* 1361 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1362 * pointers to the fragment pointers. 1363 */ 1364 static int rl_encap(sc, m_head) 1365 struct rl_softc *sc; 1366 struct mbuf *m_head; 1367 { 1368 struct mbuf *m_new = NULL; 1369 1370 /* 1371 * The RealTek is brain damaged and wants longword-aligned 1372 * TX buffers, plus we can only have one fragment buffer 1373 * per packet. We have to copy pretty much all the time. 1374 */ 1375 1376 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1377 if (m_new == NULL) 1378 return(1); 1379 if (m_head->m_pkthdr.len > MHLEN) { 1380 MCLGET(m_new, MB_DONTWAIT); 1381 if (!(m_new->m_flags & M_EXT)) { 1382 m_freem(m_new); 1383 return(1); 1384 } 1385 } 1386 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1387 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1388 m_freem(m_head); 1389 m_head = m_new; 1390 1391 /* Pad frames to at least 60 bytes. */ 1392 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1393 /* 1394 * Make security concious people happy: zero out the 1395 * bytes in the pad area, since we don't know what 1396 * this mbuf cluster buffer's previous user might 1397 * have left in it. 1398 */ 1399 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1400 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1401 m_head->m_pkthdr.len += 1402 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1403 m_head->m_len = m_head->m_pkthdr.len; 1404 } 1405 1406 RL_CUR_TXMBUF(sc) = m_head; 1407 1408 return(0); 1409 } 1410 1411 /* 1412 * Main transmit routine. 1413 */ 1414 1415 static void rl_start(ifp) 1416 struct ifnet *ifp; 1417 { 1418 struct rl_softc *sc; 1419 struct mbuf *m_head = NULL; 1420 1421 sc = ifp->if_softc; 1422 1423 while(RL_CUR_TXMBUF(sc) == NULL) { 1424 IF_DEQUEUE(&ifp->if_snd, m_head); 1425 if (m_head == NULL) 1426 break; 1427 1428 if (rl_encap(sc, m_head)) { 1429 IF_PREPEND(&ifp->if_snd, m_head); 1430 ifp->if_flags |= IFF_OACTIVE; 1431 break; 1432 } 1433 1434 /* 1435 * If there's a BPF listener, bounce a copy of this frame 1436 * to him. 1437 */ 1438 if (ifp->if_bpf) 1439 bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 1440 1441 /* 1442 * Transmit the frame. 1443 */ 1444 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 1445 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t))); 1446 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1447 RL_TXTHRESH(sc->rl_txthresh) | 1448 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1449 1450 RL_INC(sc->rl_cdata.cur_tx); 1451 } 1452 1453 /* 1454 * We broke out of the loop because all our TX slots are 1455 * full. Mark the NIC as busy until it drains some of the 1456 * packets from the queue. 1457 */ 1458 if (RL_CUR_TXMBUF(sc) != NULL) 1459 ifp->if_flags |= IFF_OACTIVE; 1460 1461 /* 1462 * Set a timeout in case the chip goes out to lunch. 1463 */ 1464 ifp->if_timer = 5; 1465 1466 return; 1467 } 1468 1469 static void rl_init(xsc) 1470 void *xsc; 1471 { 1472 struct rl_softc *sc = xsc; 1473 struct ifnet *ifp = &sc->arpcom.ac_if; 1474 struct mii_data *mii; 1475 int s, i; 1476 u_int32_t rxcfg = 0; 1477 1478 s = splimp(); 1479 1480 mii = device_get_softc(sc->rl_miibus); 1481 1482 /* 1483 * Cancel pending I/O and free all RX/TX buffers. 1484 */ 1485 rl_stop(sc); 1486 1487 /* Init our MAC address */ 1488 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1489 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1490 } 1491 1492 /* Init the RX buffer pointer register. */ 1493 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); 1494 1495 /* Init TX descriptors. */ 1496 rl_list_tx_init(sc); 1497 1498 /* 1499 * Enable transmit and receive. 1500 */ 1501 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1502 1503 /* 1504 * Set the initial TX and RX configuration. 1505 */ 1506 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1507 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1508 1509 /* Set the individual bit to receive frames for this host only. */ 1510 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1511 rxcfg |= RL_RXCFG_RX_INDIV; 1512 1513 /* If we want promiscuous mode, set the allframes bit. */ 1514 if (ifp->if_flags & IFF_PROMISC) { 1515 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1516 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1517 } else { 1518 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1519 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1520 } 1521 1522 /* 1523 * Set capture broadcast bit to capture broadcast frames. 1524 */ 1525 if (ifp->if_flags & IFF_BROADCAST) { 1526 rxcfg |= RL_RXCFG_RX_BROAD; 1527 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1528 } else { 1529 rxcfg &= ~RL_RXCFG_RX_BROAD; 1530 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1531 } 1532 1533 /* 1534 * Program the multicast filter, if necessary. 1535 */ 1536 rl_setmulti(sc); 1537 1538 #ifdef DEVICE_POLLING 1539 /* 1540 * Only enable interrupts if we are polling, keep them off otherwise. 1541 */ 1542 if (ifp->if_flags & IFF_POLLING) 1543 CSR_WRITE_2(sc, RL_IMR, 0); 1544 else 1545 #endif /* DEVICE_POLLING */ 1546 /* 1547 * Enable interrupts. 1548 */ 1549 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1550 1551 /* Set initial TX threshold */ 1552 sc->rl_txthresh = RL_TX_THRESH_INIT; 1553 1554 /* Start RX/TX process. */ 1555 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1556 1557 /* Enable receiver and transmitter. */ 1558 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1559 1560 mii_mediachg(mii); 1561 1562 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1563 1564 ifp->if_flags |= IFF_RUNNING; 1565 ifp->if_flags &= ~IFF_OACTIVE; 1566 1567 (void)splx(s); 1568 1569 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1570 1571 return; 1572 } 1573 1574 /* 1575 * Set media options. 1576 */ 1577 static int rl_ifmedia_upd(ifp) 1578 struct ifnet *ifp; 1579 { 1580 struct rl_softc *sc; 1581 struct mii_data *mii; 1582 1583 sc = ifp->if_softc; 1584 mii = device_get_softc(sc->rl_miibus); 1585 mii_mediachg(mii); 1586 1587 return(0); 1588 } 1589 1590 /* 1591 * Report current media status. 1592 */ 1593 static void rl_ifmedia_sts(ifp, ifmr) 1594 struct ifnet *ifp; 1595 struct ifmediareq *ifmr; 1596 { 1597 struct rl_softc *sc; 1598 struct mii_data *mii; 1599 1600 sc = ifp->if_softc; 1601 mii = device_get_softc(sc->rl_miibus); 1602 1603 mii_pollstat(mii); 1604 ifmr->ifm_active = mii->mii_media_active; 1605 ifmr->ifm_status = mii->mii_media_status; 1606 1607 return; 1608 } 1609 1610 static int rl_ioctl(ifp, command, data, cr) 1611 struct ifnet *ifp; 1612 u_long command; 1613 caddr_t data; 1614 struct ucred *cr; 1615 { 1616 struct rl_softc *sc = ifp->if_softc; 1617 struct ifreq *ifr = (struct ifreq *) data; 1618 struct mii_data *mii; 1619 int s, error = 0; 1620 1621 s = splimp(); 1622 1623 switch(command) { 1624 case SIOCSIFADDR: 1625 case SIOCGIFADDR: 1626 case SIOCSIFMTU: 1627 error = ether_ioctl(ifp, command, data); 1628 break; 1629 case SIOCSIFFLAGS: 1630 if (ifp->if_flags & IFF_UP) { 1631 rl_init(sc); 1632 } else { 1633 if (ifp->if_flags & IFF_RUNNING) 1634 rl_stop(sc); 1635 } 1636 error = 0; 1637 break; 1638 case SIOCADDMULTI: 1639 case SIOCDELMULTI: 1640 rl_setmulti(sc); 1641 error = 0; 1642 break; 1643 case SIOCGIFMEDIA: 1644 case SIOCSIFMEDIA: 1645 mii = device_get_softc(sc->rl_miibus); 1646 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1647 break; 1648 default: 1649 error = EINVAL; 1650 break; 1651 } 1652 1653 (void)splx(s); 1654 1655 return(error); 1656 } 1657 1658 static void rl_watchdog(ifp) 1659 struct ifnet *ifp; 1660 { 1661 struct rl_softc *sc; 1662 1663 sc = ifp->if_softc; 1664 1665 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1666 ifp->if_oerrors++; 1667 1668 rl_txeof(sc); 1669 rl_rxeof(sc); 1670 rl_init(sc); 1671 1672 return; 1673 } 1674 1675 /* 1676 * Stop the adapter and free any mbufs allocated to the 1677 * RX and TX lists. 1678 */ 1679 static void rl_stop(sc) 1680 struct rl_softc *sc; 1681 { 1682 int i; 1683 struct ifnet *ifp; 1684 1685 ifp = &sc->arpcom.ac_if; 1686 ifp->if_timer = 0; 1687 1688 untimeout(rl_tick, sc, sc->rl_stat_ch); 1689 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1690 #ifdef DEVICE_POLLING 1691 ether_poll_deregister(ifp); 1692 #endif /* DEVICE_POLLING */ 1693 1694 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1695 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1696 1697 /* 1698 * Free the TX list buffers. 1699 */ 1700 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1701 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1702 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1703 sc->rl_cdata.rl_tx_chain[i] = NULL; 1704 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1705 } 1706 } 1707 1708 1709 return; 1710 } 1711 1712 /* 1713 * Stop all chip I/O so that the kernel's probe routines don't 1714 * get confused by errant DMAs when rebooting. 1715 */ 1716 static void rl_shutdown(dev) 1717 device_t dev; 1718 { 1719 struct rl_softc *sc; 1720 1721 sc = device_get_softc(dev); 1722 1723 rl_stop(sc); 1724 1725 return; 1726 } 1727 1728 /* 1729 * Device suspend routine. Stop the interface and save some PCI 1730 * settings in case the BIOS doesn't restore them properly on 1731 * resume. 1732 */ 1733 static int rl_suspend(dev) 1734 device_t dev; 1735 { 1736 int i; 1737 struct rl_softc *sc; 1738 1739 sc = device_get_softc(dev); 1740 1741 rl_stop(sc); 1742 1743 for (i = 0; i < 5; i++) 1744 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1745 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1746 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1747 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1748 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1749 1750 sc->suspended = 1; 1751 1752 return (0); 1753 } 1754 1755 /* 1756 * Device resume routine. Restore some PCI settings in case the BIOS 1757 * doesn't, re-enable busmastering, and restart the interface if 1758 * appropriate. 1759 */ 1760 static int rl_resume(dev) 1761 device_t dev; 1762 { 1763 int i; 1764 struct rl_softc *sc; 1765 struct ifnet *ifp; 1766 1767 sc = device_get_softc(dev); 1768 ifp = &sc->arpcom.ac_if; 1769 1770 /* better way to do this? */ 1771 for (i = 0; i < 5; i++) 1772 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1773 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1774 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1775 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1776 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1777 1778 /* reenable busmastering */ 1779 pci_enable_busmaster(dev); 1780 pci_enable_io(dev, RL_RES); 1781 1782 /* reinitialize interface if necessary */ 1783 if (ifp->if_flags & IFF_UP) 1784 rl_init(sc); 1785 1786 sc->suspended = 0; 1787 1788 return (0); 1789 } 1790