1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $ 33 * $DragonFly: src/sys/dev/netif/sf/if_sf.c,v 1.11 2004/07/23 07:16:28 joerg Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $ 36 */ 37 38 /* 39 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 40 * Programming manual is available from: 41 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Department of Electical Engineering 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 50 * controller designed with flexibility and reducing CPU load in mind. 51 * The Starfire offers high and low priority buffer queues, a 52 * producer/consumer index mechanism and several different buffer 53 * queue and completion queue descriptor types. Any one of a number 54 * of different driver designs can be used, depending on system and 55 * OS requirements. This driver makes use of type0 transmit frame 56 * descriptors (since BSD fragments packets across an mbuf chain) 57 * and two RX buffer queues prioritized on size (one queue for small 58 * frames that will fit into a single mbuf, another with full size 59 * mbuf clusters for everything else). The producer/consumer indexes 60 * and completion queues are also used. 61 * 62 * One downside to the Starfire has to do with alignment: buffer 63 * queues must be aligned on 256-byte boundaries, and receive buffers 64 * must be aligned on longword boundaries. The receive buffer alignment 65 * causes problems on the Alpha platform, where the packet payload 66 * should be longword aligned. There is no simple way around this. 67 * 68 * For receive filtering, the Starfire offers 16 perfect filter slots 69 * and a 512-bit hash table. 70 * 71 * The Starfire has no internal transceiver, relying instead on an 72 * external MII-based transceiver. Accessing registers on external 73 * PHYs is done through a special register map rather than with the 74 * usual bitbang MDIO method. 75 * 76 * Acesssing the registers on the Starfire is a little tricky. The 77 * Starfire has a 512K internal register space. When programmed for 78 * PCI memory mapped mode, the entire register space can be accessed 79 * directly. However in I/O space mode, only 256 bytes are directly 80 * mapped into PCI I/O space. The other registers can be accessed 81 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 82 * registers inside the 256-byte I/O window. 83 */ 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/socket.h> 92 93 #include <net/if.h> 94 #include <net/if_arp.h> 95 #include <net/ethernet.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 99 #include <net/bpf.h> 100 101 #include <vm/vm.h> /* for vtophys */ 102 #include <vm/pmap.h> /* for vtophys */ 103 #include <machine/clock.h> /* for DELAY */ 104 #include <machine/bus_pio.h> 105 #include <machine/bus_memio.h> 106 #include <machine/bus.h> 107 #include <machine/resource.h> 108 #include <sys/bus.h> 109 #include <sys/rman.h> 110 111 #include "../mii_layer/mii.h" 112 #include "../mii_layer/miivar.h" 113 114 /* "controller miibus0" required. See GENERIC if you get errors here. */ 115 #include "miibus_if.h" 116 117 #include <bus/pci/pcireg.h> 118 #include <bus/pci/pcivar.h> 119 120 #define SF_USEIOSPACE 121 122 #include "if_sfreg.h" 123 124 static struct sf_type sf_devs[] = { 125 { AD_VENDORID, AD_DEVICEID_STARFIRE, 126 "Adaptec AIC-6915 10/100BaseTX" }, 127 { 0, 0, NULL } 128 }; 129 130 static int sf_probe (device_t); 131 static int sf_attach (device_t); 132 static int sf_detach (device_t); 133 static void sf_intr (void *); 134 static void sf_stats_update (void *); 135 static void sf_rxeof (struct sf_softc *); 136 static void sf_txeof (struct sf_softc *); 137 static int sf_encap (struct sf_softc *, 138 struct sf_tx_bufdesc_type0 *, 139 struct mbuf *); 140 static void sf_start (struct ifnet *); 141 static int sf_ioctl (struct ifnet *, u_long, caddr_t, 142 struct ucred *); 143 static void sf_init (void *); 144 static void sf_stop (struct sf_softc *); 145 static void sf_watchdog (struct ifnet *); 146 static void sf_shutdown (device_t); 147 static int sf_ifmedia_upd (struct ifnet *); 148 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149 static void sf_reset (struct sf_softc *); 150 static int sf_init_rx_ring (struct sf_softc *); 151 static void sf_init_tx_ring (struct sf_softc *); 152 static int sf_newbuf (struct sf_softc *, 153 struct sf_rx_bufdesc_type0 *, 154 struct mbuf *); 155 static void sf_setmulti (struct sf_softc *); 156 static int sf_setperf (struct sf_softc *, int, caddr_t); 157 static int sf_sethash (struct sf_softc *, caddr_t, int); 158 #ifdef notdef 159 static int sf_setvlan (struct sf_softc *, int, u_int32_t); 160 #endif 161 162 static u_int8_t sf_read_eeprom (struct sf_softc *, int); 163 static u_int32_t sf_calchash (caddr_t); 164 165 static int sf_miibus_readreg (device_t, int, int); 166 static int sf_miibus_writereg (device_t, int, int, int); 167 static void sf_miibus_statchg (device_t); 168 169 static u_int32_t csr_read_4 (struct sf_softc *, int); 170 static void csr_write_4 (struct sf_softc *, int, u_int32_t); 171 static void sf_txthresh_adjust (struct sf_softc *); 172 173 #ifdef SF_USEIOSPACE 174 #define SF_RES SYS_RES_IOPORT 175 #define SF_RID SF_PCI_LOIO 176 #else 177 #define SF_RES SYS_RES_MEMORY 178 #define SF_RID SF_PCI_LOMEM 179 #endif 180 181 static device_method_t sf_methods[] = { 182 /* Device interface */ 183 DEVMETHOD(device_probe, sf_probe), 184 DEVMETHOD(device_attach, sf_attach), 185 DEVMETHOD(device_detach, sf_detach), 186 DEVMETHOD(device_shutdown, sf_shutdown), 187 188 /* bus interface */ 189 DEVMETHOD(bus_print_child, bus_generic_print_child), 190 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 191 192 /* MII interface */ 193 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 194 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 195 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 196 197 { 0, 0 } 198 }; 199 200 static driver_t sf_driver = { 201 "sf", 202 sf_methods, 203 sizeof(struct sf_softc), 204 }; 205 206 static devclass_t sf_devclass; 207 208 DECLARE_DUMMY_MODULE(if_sf); 209 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 210 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 211 212 #define SF_SETBIT(sc, reg, x) \ 213 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 214 215 #define SF_CLRBIT(sc, reg, x) \ 216 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 217 218 static u_int32_t csr_read_4(sc, reg) 219 struct sf_softc *sc; 220 int reg; 221 { 222 u_int32_t val; 223 224 #ifdef SF_USEIOSPACE 225 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 226 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 227 #else 228 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 229 #endif 230 231 return(val); 232 } 233 234 static u_int8_t sf_read_eeprom(sc, reg) 235 struct sf_softc *sc; 236 int reg; 237 { 238 u_int8_t val; 239 240 val = (csr_read_4(sc, SF_EEADDR_BASE + 241 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 242 243 return(val); 244 } 245 246 static void csr_write_4(sc, reg, val) 247 struct sf_softc *sc; 248 int reg; 249 u_int32_t val; 250 { 251 #ifdef SF_USEIOSPACE 252 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 253 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 254 #else 255 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 256 #endif 257 return; 258 } 259 260 static u_int32_t sf_calchash(addr) 261 caddr_t addr; 262 { 263 u_int32_t crc, carry; 264 int i, j; 265 u_int8_t c; 266 267 /* Compute CRC for the address value. */ 268 crc = 0xFFFFFFFF; /* initial value */ 269 270 for (i = 0; i < 6; i++) { 271 c = *(addr + i); 272 for (j = 0; j < 8; j++) { 273 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 274 crc <<= 1; 275 c >>= 1; 276 if (carry) 277 crc = (crc ^ 0x04c11db6) | carry; 278 } 279 } 280 281 /* return the filter bit position */ 282 return(crc >> 23 & 0x1FF); 283 } 284 285 /* 286 * Copy the address 'mac' into the perfect RX filter entry at 287 * offset 'idx.' The perfect filter only has 16 entries so do 288 * some sanity tests. 289 */ 290 static int sf_setperf(sc, idx, mac) 291 struct sf_softc *sc; 292 int idx; 293 caddr_t mac; 294 { 295 u_int16_t *p; 296 297 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 298 return(EINVAL); 299 300 if (mac == NULL) 301 return(EINVAL); 302 303 p = (u_int16_t *)mac; 304 305 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 306 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 307 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 308 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 309 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 310 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 311 312 return(0); 313 } 314 315 /* 316 * Set the bit in the 512-bit hash table that corresponds to the 317 * specified mac address 'mac.' If 'prio' is nonzero, update the 318 * priority hash table instead of the filter hash table. 319 */ 320 static int sf_sethash(sc, mac, prio) 321 struct sf_softc *sc; 322 caddr_t mac; 323 int prio; 324 { 325 u_int32_t h = 0; 326 327 if (mac == NULL) 328 return(EINVAL); 329 330 h = sf_calchash(mac); 331 332 if (prio) { 333 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 334 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 335 } else { 336 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 337 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 338 } 339 340 return(0); 341 } 342 343 #ifdef notdef 344 /* 345 * Set a VLAN tag in the receive filter. 346 */ 347 static int sf_setvlan(sc, idx, vlan) 348 struct sf_softc *sc; 349 int idx; 350 u_int32_t vlan; 351 { 352 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 353 return(EINVAL); 354 355 csr_write_4(sc, SF_RXFILT_HASH_BASE + 356 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 357 358 return(0); 359 } 360 #endif 361 362 static int sf_miibus_readreg(dev, phy, reg) 363 device_t dev; 364 int phy, reg; 365 { 366 struct sf_softc *sc; 367 int i; 368 u_int32_t val = 0; 369 370 sc = device_get_softc(dev); 371 372 for (i = 0; i < SF_TIMEOUT; i++) { 373 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 374 if (val & SF_MII_DATAVALID) 375 break; 376 } 377 378 if (i == SF_TIMEOUT) 379 return(0); 380 381 if ((val & 0x0000FFFF) == 0xFFFF) 382 return(0); 383 384 return(val & 0x0000FFFF); 385 } 386 387 static int sf_miibus_writereg(dev, phy, reg, val) 388 device_t dev; 389 int phy, reg, val; 390 { 391 struct sf_softc *sc; 392 int i; 393 int busy; 394 395 sc = device_get_softc(dev); 396 397 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 398 399 for (i = 0; i < SF_TIMEOUT; i++) { 400 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 401 if (!(busy & SF_MII_BUSY)) 402 break; 403 } 404 405 return(0); 406 } 407 408 static void sf_miibus_statchg(dev) 409 device_t dev; 410 { 411 struct sf_softc *sc; 412 struct mii_data *mii; 413 414 sc = device_get_softc(dev); 415 mii = device_get_softc(sc->sf_miibus); 416 417 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 418 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 419 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 420 } else { 421 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 422 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 423 } 424 425 return; 426 } 427 428 static void sf_setmulti(sc) 429 struct sf_softc *sc; 430 { 431 struct ifnet *ifp; 432 int i; 433 struct ifmultiaddr *ifma; 434 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 435 436 ifp = &sc->arpcom.ac_if; 437 438 /* First zot all the existing filters. */ 439 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 440 sf_setperf(sc, i, (char *)&dummy); 441 for (i = SF_RXFILT_HASH_BASE; 442 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 443 csr_write_4(sc, i, 0); 444 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 445 446 /* Now program new ones. */ 447 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 448 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 449 } else { 450 i = 1; 451 /* First find the tail of the list. */ 452 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 453 ifma = ifma->ifma_link.le_next) { 454 if (ifma->ifma_link.le_next == NULL) 455 break; 456 } 457 /* Now traverse the list backwards. */ 458 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 459 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 460 if (ifma->ifma_addr->sa_family != AF_LINK) 461 continue; 462 /* 463 * Program the first 15 multicast groups 464 * into the perfect filter. For all others, 465 * use the hash table. 466 */ 467 if (i < SF_RXFILT_PERFECT_CNT) { 468 sf_setperf(sc, i, 469 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 470 i++; 471 continue; 472 } 473 474 sf_sethash(sc, 475 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 476 } 477 } 478 479 return; 480 } 481 482 /* 483 * Set media options. 484 */ 485 static int sf_ifmedia_upd(ifp) 486 struct ifnet *ifp; 487 { 488 struct sf_softc *sc; 489 struct mii_data *mii; 490 491 sc = ifp->if_softc; 492 mii = device_get_softc(sc->sf_miibus); 493 sc->sf_link = 0; 494 if (mii->mii_instance) { 495 struct mii_softc *miisc; 496 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 497 miisc = LIST_NEXT(miisc, mii_list)) 498 mii_phy_reset(miisc); 499 } 500 mii_mediachg(mii); 501 502 return(0); 503 } 504 505 /* 506 * Report current media status. 507 */ 508 static void sf_ifmedia_sts(ifp, ifmr) 509 struct ifnet *ifp; 510 struct ifmediareq *ifmr; 511 { 512 struct sf_softc *sc; 513 struct mii_data *mii; 514 515 sc = ifp->if_softc; 516 mii = device_get_softc(sc->sf_miibus); 517 518 mii_pollstat(mii); 519 ifmr->ifm_active = mii->mii_media_active; 520 ifmr->ifm_status = mii->mii_media_status; 521 522 return; 523 } 524 525 static int sf_ioctl(ifp, command, data, cr) 526 struct ifnet *ifp; 527 u_long command; 528 caddr_t data; 529 struct ucred *cr; 530 { 531 struct sf_softc *sc = ifp->if_softc; 532 struct ifreq *ifr = (struct ifreq *) data; 533 struct mii_data *mii; 534 int s, error = 0; 535 536 s = splimp(); 537 538 switch(command) { 539 case SIOCSIFADDR: 540 case SIOCGIFADDR: 541 case SIOCSIFMTU: 542 error = ether_ioctl(ifp, command, data); 543 break; 544 case SIOCSIFFLAGS: 545 if (ifp->if_flags & IFF_UP) { 546 if (ifp->if_flags & IFF_RUNNING && 547 ifp->if_flags & IFF_PROMISC && 548 !(sc->sf_if_flags & IFF_PROMISC)) { 549 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 550 } else if (ifp->if_flags & IFF_RUNNING && 551 !(ifp->if_flags & IFF_PROMISC) && 552 sc->sf_if_flags & IFF_PROMISC) { 553 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 554 } else if (!(ifp->if_flags & IFF_RUNNING)) 555 sf_init(sc); 556 } else { 557 if (ifp->if_flags & IFF_RUNNING) 558 sf_stop(sc); 559 } 560 sc->sf_if_flags = ifp->if_flags; 561 error = 0; 562 break; 563 case SIOCADDMULTI: 564 case SIOCDELMULTI: 565 sf_setmulti(sc); 566 error = 0; 567 break; 568 case SIOCGIFMEDIA: 569 case SIOCSIFMEDIA: 570 mii = device_get_softc(sc->sf_miibus); 571 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 572 break; 573 default: 574 error = EINVAL; 575 break; 576 } 577 578 (void)splx(s); 579 580 return(error); 581 } 582 583 static void sf_reset(sc) 584 struct sf_softc *sc; 585 { 586 register int i; 587 588 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 589 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 590 DELAY(1000); 591 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 592 593 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 594 595 for (i = 0; i < SF_TIMEOUT; i++) { 596 DELAY(10); 597 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 598 break; 599 } 600 601 if (i == SF_TIMEOUT) 602 printf("sf%d: reset never completed!\n", sc->sf_unit); 603 604 /* Wait a little while for the chip to get its brains in order. */ 605 DELAY(1000); 606 return; 607 } 608 609 /* 610 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 611 * IDs against our list and return a device name if we find a match. 612 * We also check the subsystem ID so that we can identify exactly which 613 * NIC has been found, if possible. 614 */ 615 static int sf_probe(dev) 616 device_t dev; 617 { 618 struct sf_type *t; 619 620 t = sf_devs; 621 622 while(t->sf_name != NULL) { 623 if ((pci_get_vendor(dev) == t->sf_vid) && 624 (pci_get_device(dev) == t->sf_did)) { 625 switch((pci_read_config(dev, 626 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 627 case AD_SUBSYSID_62011_REV0: 628 case AD_SUBSYSID_62011_REV1: 629 device_set_desc(dev, 630 "Adaptec ANA-62011 10/100BaseTX"); 631 return(0); 632 break; 633 case AD_SUBSYSID_62022: 634 device_set_desc(dev, 635 "Adaptec ANA-62022 10/100BaseTX"); 636 return(0); 637 break; 638 case AD_SUBSYSID_62044_REV0: 639 case AD_SUBSYSID_62044_REV1: 640 device_set_desc(dev, 641 "Adaptec ANA-62044 10/100BaseTX"); 642 return(0); 643 break; 644 case AD_SUBSYSID_62020: 645 device_set_desc(dev, 646 "Adaptec ANA-62020 10/100BaseFX"); 647 return(0); 648 break; 649 case AD_SUBSYSID_69011: 650 device_set_desc(dev, 651 "Adaptec ANA-69011 10/100BaseTX"); 652 return(0); 653 break; 654 default: 655 device_set_desc(dev, t->sf_name); 656 return(0); 657 break; 658 } 659 } 660 t++; 661 } 662 663 return(ENXIO); 664 } 665 666 /* 667 * Attach the interface. Allocate softc structures, do ifmedia 668 * setup and ethernet/BPF attach. 669 */ 670 static int sf_attach(dev) 671 device_t dev; 672 { 673 int s, i; 674 u_int32_t command; 675 struct sf_softc *sc; 676 struct ifnet *ifp; 677 int unit, rid, error = 0; 678 679 s = splimp(); 680 681 sc = device_get_softc(dev); 682 unit = device_get_unit(dev); 683 bzero(sc, sizeof(struct sf_softc)); 684 685 /* 686 * Handle power management nonsense. 687 */ 688 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 689 if (command == 0x01) { 690 691 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 692 if (command & SF_PSTATE_MASK) { 693 u_int32_t iobase, membase, irq; 694 695 /* Save important PCI config data. */ 696 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 697 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 698 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 699 700 /* Reset the power state. */ 701 printf("sf%d: chip is in D%d power mode " 702 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 703 command &= 0xFFFFFFFC; 704 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 705 706 /* Restore PCI config data. */ 707 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 708 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 709 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 710 } 711 } 712 713 /* 714 * Map control/status registers. 715 */ 716 command = pci_read_config(dev, PCIR_COMMAND, 4); 717 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 718 pci_write_config(dev, PCIR_COMMAND, command, 4); 719 command = pci_read_config(dev, PCIR_COMMAND, 4); 720 721 #ifdef SF_USEIOSPACE 722 if (!(command & PCIM_CMD_PORTEN)) { 723 printf("sf%d: failed to enable I/O ports!\n", unit); 724 error = ENXIO; 725 goto fail; 726 } 727 #else 728 if (!(command & PCIM_CMD_MEMEN)) { 729 printf("sf%d: failed to enable memory mapping!\n", unit); 730 error = ENXIO; 731 goto fail; 732 } 733 #endif 734 735 rid = SF_RID; 736 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 737 0, ~0, 1, RF_ACTIVE); 738 739 if (sc->sf_res == NULL) { 740 printf ("sf%d: couldn't map ports\n", unit); 741 error = ENXIO; 742 goto fail; 743 } 744 745 sc->sf_btag = rman_get_bustag(sc->sf_res); 746 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 747 748 /* Allocate interrupt */ 749 rid = 0; 750 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 751 RF_SHAREABLE | RF_ACTIVE); 752 753 if (sc->sf_irq == NULL) { 754 printf("sf%d: couldn't map interrupt\n", unit); 755 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 756 error = ENXIO; 757 goto fail; 758 } 759 760 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 761 sf_intr, sc, &sc->sf_intrhand); 762 763 if (error) { 764 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 765 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 766 printf("sf%d: couldn't set up irq\n", unit); 767 goto fail; 768 } 769 770 callout_handle_init(&sc->sf_stat_ch); 771 772 /* Reset the adapter. */ 773 sf_reset(sc); 774 775 /* 776 * Get station address from the EEPROM. 777 */ 778 for (i = 0; i < ETHER_ADDR_LEN; i++) 779 sc->arpcom.ac_enaddr[i] = 780 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 781 782 sc->sf_unit = unit; 783 784 /* Allocate the descriptor queues. */ 785 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 786 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 787 788 if (sc->sf_ldata == NULL) { 789 printf("sf%d: no memory for list buffers!\n", unit); 790 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 791 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 792 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 793 error = ENXIO; 794 goto fail; 795 } 796 797 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 798 799 /* Do MII setup. */ 800 if (mii_phy_probe(dev, &sc->sf_miibus, 801 sf_ifmedia_upd, sf_ifmedia_sts)) { 802 printf("sf%d: MII without any phy!\n", sc->sf_unit); 803 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF); 804 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 805 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 806 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 807 error = ENXIO; 808 goto fail; 809 } 810 811 ifp = &sc->arpcom.ac_if; 812 ifp->if_softc = sc; 813 if_initname(ifp, "sf", unit); 814 ifp->if_mtu = ETHERMTU; 815 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 816 ifp->if_ioctl = sf_ioctl; 817 ifp->if_start = sf_start; 818 ifp->if_watchdog = sf_watchdog; 819 ifp->if_init = sf_init; 820 ifp->if_baudrate = 10000000; 821 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 822 823 /* 824 * Call MI attach routine. 825 */ 826 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 827 828 fail: 829 splx(s); 830 return(error); 831 } 832 833 static int sf_detach(dev) 834 device_t dev; 835 { 836 struct sf_softc *sc; 837 struct ifnet *ifp; 838 int s; 839 840 s = splimp(); 841 842 sc = device_get_softc(dev); 843 ifp = &sc->arpcom.ac_if; 844 845 ether_ifdetach(ifp); 846 sf_stop(sc); 847 848 bus_generic_detach(dev); 849 device_delete_child(dev, sc->sf_miibus); 850 851 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 852 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 853 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 854 855 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 856 857 splx(s); 858 859 return(0); 860 } 861 862 static int sf_init_rx_ring(sc) 863 struct sf_softc *sc; 864 { 865 struct sf_list_data *ld; 866 int i; 867 868 ld = sc->sf_ldata; 869 870 bzero((char *)ld->sf_rx_dlist_big, 871 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 872 bzero((char *)ld->sf_rx_clist, 873 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 874 875 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 876 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 877 return(ENOBUFS); 878 } 879 880 return(0); 881 } 882 883 static void sf_init_tx_ring(sc) 884 struct sf_softc *sc; 885 { 886 struct sf_list_data *ld; 887 int i; 888 889 ld = sc->sf_ldata; 890 891 bzero((char *)ld->sf_tx_dlist, 892 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 893 bzero((char *)ld->sf_tx_clist, 894 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 895 896 for (i = 0; i < SF_TX_DLIST_CNT; i++) 897 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 898 for (i = 0; i < SF_TX_CLIST_CNT; i++) 899 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 900 901 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 902 sc->sf_tx_cnt = 0; 903 904 return; 905 } 906 907 static int sf_newbuf(sc, c, m) 908 struct sf_softc *sc; 909 struct sf_rx_bufdesc_type0 *c; 910 struct mbuf *m; 911 { 912 struct mbuf *m_new = NULL; 913 914 if (m == NULL) { 915 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 916 if (m_new == NULL) 917 return(ENOBUFS); 918 919 MCLGET(m_new, MB_DONTWAIT); 920 if (!(m_new->m_flags & M_EXT)) { 921 m_freem(m_new); 922 return(ENOBUFS); 923 } 924 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 925 } else { 926 m_new = m; 927 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 928 m_new->m_data = m_new->m_ext.ext_buf; 929 } 930 931 m_adj(m_new, sizeof(u_int64_t)); 932 933 c->sf_mbuf = m_new; 934 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 935 c->sf_valid = 1; 936 937 return(0); 938 } 939 940 /* 941 * The starfire is programmed to use 'normal' mode for packet reception, 942 * which means we use the consumer/producer model for both the buffer 943 * descriptor queue and the completion descriptor queue. The only problem 944 * with this is that it involves a lot of register accesses: we have to 945 * read the RX completion consumer and producer indexes and the RX buffer 946 * producer index, plus the RX completion consumer and RX buffer producer 947 * indexes have to be updated. It would have been easier if Adaptec had 948 * put each index in a separate register, especially given that the damn 949 * NIC has a 512K register space. 950 * 951 * In spite of all the lovely features that Adaptec crammed into the 6915, 952 * it is marred by one truly stupid design flaw, which is that receive 953 * buffer addresses must be aligned on a longword boundary. This forces 954 * the packet payload to be unaligned, which is suboptimal on the x86 and 955 * completely unuseable on the Alpha. Our only recourse is to copy received 956 * packets into properly aligned buffers before handing them off. 957 */ 958 959 static void sf_rxeof(sc) 960 struct sf_softc *sc; 961 { 962 struct mbuf *m; 963 struct ifnet *ifp; 964 struct sf_rx_bufdesc_type0 *desc; 965 struct sf_rx_cmpdesc_type3 *cur_rx; 966 u_int32_t rxcons, rxprod; 967 int cmpprodidx, cmpconsidx, bufprodidx; 968 969 ifp = &sc->arpcom.ac_if; 970 971 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 972 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 973 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 974 cmpconsidx = SF_IDX_LO(rxcons); 975 bufprodidx = SF_IDX_LO(rxprod); 976 977 while (cmpconsidx != cmpprodidx) { 978 struct mbuf *m0; 979 980 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 981 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 982 m = desc->sf_mbuf; 983 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 984 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 985 986 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 987 ifp->if_ierrors++; 988 sf_newbuf(sc, desc, m); 989 continue; 990 } 991 992 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 993 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 994 sf_newbuf(sc, desc, m); 995 if (m0 == NULL) { 996 ifp->if_ierrors++; 997 continue; 998 } 999 m_adj(m0, ETHER_ALIGN); 1000 m = m0; 1001 1002 ifp->if_ipackets++; 1003 1004 (*ifp->if_input)(ifp, m); 1005 } 1006 1007 csr_write_4(sc, SF_CQ_CONSIDX, 1008 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1009 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1010 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1011 1012 return; 1013 } 1014 1015 /* 1016 * Read the transmit status from the completion queue and release 1017 * mbufs. Note that the buffer descriptor index in the completion 1018 * descriptor is an offset from the start of the transmit buffer 1019 * descriptor list in bytes. This is important because the manual 1020 * gives the impression that it should match the producer/consumer 1021 * index, which is the offset in 8 byte blocks. 1022 */ 1023 static void sf_txeof(sc) 1024 struct sf_softc *sc; 1025 { 1026 int txcons, cmpprodidx, cmpconsidx; 1027 struct sf_tx_cmpdesc_type1 *cur_cmp; 1028 struct sf_tx_bufdesc_type0 *cur_tx; 1029 struct ifnet *ifp; 1030 1031 ifp = &sc->arpcom.ac_if; 1032 1033 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1034 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1035 cmpconsidx = SF_IDX_HI(txcons); 1036 1037 while (cmpconsidx != cmpprodidx) { 1038 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1039 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1040 1041 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1042 ifp->if_opackets++; 1043 else { 1044 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1045 sf_txthresh_adjust(sc); 1046 ifp->if_oerrors++; 1047 } 1048 1049 sc->sf_tx_cnt--; 1050 if (cur_tx->sf_mbuf != NULL) { 1051 m_freem(cur_tx->sf_mbuf); 1052 cur_tx->sf_mbuf = NULL; 1053 } else 1054 break; 1055 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1056 } 1057 1058 ifp->if_timer = 0; 1059 ifp->if_flags &= ~IFF_OACTIVE; 1060 1061 csr_write_4(sc, SF_CQ_CONSIDX, 1062 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1063 ((cmpconsidx << 16) & 0xFFFF0000)); 1064 1065 return; 1066 } 1067 1068 static void sf_txthresh_adjust(sc) 1069 struct sf_softc *sc; 1070 { 1071 u_int32_t txfctl; 1072 u_int8_t txthresh; 1073 1074 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1075 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1076 if (txthresh < 0xFF) { 1077 txthresh++; 1078 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1079 txfctl |= txthresh; 1080 #ifdef DIAGNOSTIC 1081 printf("sf%d: tx underrun, increasing " 1082 "tx threshold to %d bytes\n", 1083 sc->sf_unit, txthresh * 4); 1084 #endif 1085 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1086 } 1087 1088 return; 1089 } 1090 1091 static void sf_intr(arg) 1092 void *arg; 1093 { 1094 struct sf_softc *sc; 1095 struct ifnet *ifp; 1096 u_int32_t status; 1097 1098 sc = arg; 1099 ifp = &sc->arpcom.ac_if; 1100 1101 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1102 return; 1103 1104 /* Disable interrupts. */ 1105 csr_write_4(sc, SF_IMR, 0x00000000); 1106 1107 for (;;) { 1108 status = csr_read_4(sc, SF_ISR); 1109 if (status) 1110 csr_write_4(sc, SF_ISR, status); 1111 1112 if (!(status & SF_INTRS)) 1113 break; 1114 1115 if (status & SF_ISR_RXDQ1_DMADONE) 1116 sf_rxeof(sc); 1117 1118 if (status & SF_ISR_TX_TXDONE || 1119 status & SF_ISR_TX_DMADONE || 1120 status & SF_ISR_TX_QUEUEDONE) 1121 sf_txeof(sc); 1122 1123 if (status & SF_ISR_TX_LOFIFO) 1124 sf_txthresh_adjust(sc); 1125 1126 if (status & SF_ISR_ABNORMALINTR) { 1127 if (status & SF_ISR_STATSOFLOW) { 1128 untimeout(sf_stats_update, sc, 1129 sc->sf_stat_ch); 1130 sf_stats_update(sc); 1131 } else 1132 sf_init(sc); 1133 } 1134 } 1135 1136 /* Re-enable interrupts. */ 1137 csr_write_4(sc, SF_IMR, SF_INTRS); 1138 1139 if (ifp->if_snd.ifq_head != NULL) 1140 sf_start(ifp); 1141 1142 return; 1143 } 1144 1145 static void sf_init(xsc) 1146 void *xsc; 1147 { 1148 struct sf_softc *sc; 1149 struct ifnet *ifp; 1150 struct mii_data *mii; 1151 int i, s; 1152 1153 s = splimp(); 1154 1155 sc = xsc; 1156 ifp = &sc->arpcom.ac_if; 1157 mii = device_get_softc(sc->sf_miibus); 1158 1159 sf_stop(sc); 1160 sf_reset(sc); 1161 1162 /* Init all the receive filter registers */ 1163 for (i = SF_RXFILT_PERFECT_BASE; 1164 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1165 csr_write_4(sc, i, 0); 1166 1167 /* Empty stats counter registers. */ 1168 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1169 csr_write_4(sc, SF_STATS_BASE + 1170 (i + sizeof(u_int32_t)), 0); 1171 1172 /* Init our MAC address */ 1173 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1174 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1175 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1176 1177 if (sf_init_rx_ring(sc) == ENOBUFS) { 1178 printf("sf%d: initialization failed: no " 1179 "memory for rx buffers\n", sc->sf_unit); 1180 (void)splx(s); 1181 return; 1182 } 1183 1184 sf_init_tx_ring(sc); 1185 1186 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1187 1188 /* If we want promiscuous mode, set the allframes bit. */ 1189 if (ifp->if_flags & IFF_PROMISC) { 1190 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1191 } else { 1192 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1193 } 1194 1195 if (ifp->if_flags & IFF_BROADCAST) { 1196 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1197 } else { 1198 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1199 } 1200 1201 /* 1202 * Load the multicast filter. 1203 */ 1204 sf_setmulti(sc); 1205 1206 /* Init the completion queue indexes */ 1207 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1208 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1209 1210 /* Init the RX completion queue */ 1211 csr_write_4(sc, SF_RXCQ_CTL_1, 1212 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1213 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1214 1215 /* Init RX DMA control. */ 1216 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1217 1218 /* Init the RX buffer descriptor queue. */ 1219 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1220 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1221 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1222 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1223 1224 /* Init the TX completion queue */ 1225 csr_write_4(sc, SF_TXCQ_CTL, 1226 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1227 1228 /* Init the TX buffer descriptor queue. */ 1229 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1230 vtophys(sc->sf_ldata->sf_tx_dlist)); 1231 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1232 csr_write_4(sc, SF_TXDQ_CTL, 1233 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1234 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1235 1236 /* Enable autopadding of short TX frames. */ 1237 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1238 1239 /* Enable interrupts. */ 1240 csr_write_4(sc, SF_IMR, SF_INTRS); 1241 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1242 1243 /* Enable the RX and TX engines. */ 1244 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1245 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1246 1247 /*mii_mediachg(mii);*/ 1248 sf_ifmedia_upd(ifp); 1249 1250 ifp->if_flags |= IFF_RUNNING; 1251 ifp->if_flags &= ~IFF_OACTIVE; 1252 1253 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1254 1255 splx(s); 1256 1257 return; 1258 } 1259 1260 static int sf_encap(sc, c, m_head) 1261 struct sf_softc *sc; 1262 struct sf_tx_bufdesc_type0 *c; 1263 struct mbuf *m_head; 1264 { 1265 int frag = 0; 1266 struct sf_frag *f = NULL; 1267 struct mbuf *m; 1268 1269 m = m_head; 1270 1271 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1272 if (m->m_len != 0) { 1273 if (frag == SF_MAXFRAGS) 1274 break; 1275 f = &c->sf_frags[frag]; 1276 if (frag == 0) 1277 f->sf_pktlen = m_head->m_pkthdr.len; 1278 f->sf_fraglen = m->m_len; 1279 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1280 frag++; 1281 } 1282 } 1283 1284 if (m != NULL) { 1285 struct mbuf *m_new = NULL; 1286 1287 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1288 if (m_new == NULL) { 1289 printf("sf%d: no memory for tx list", sc->sf_unit); 1290 return(1); 1291 } 1292 1293 if (m_head->m_pkthdr.len > MHLEN) { 1294 MCLGET(m_new, MB_DONTWAIT); 1295 if (!(m_new->m_flags & M_EXT)) { 1296 m_freem(m_new); 1297 printf("sf%d: no memory for tx list", 1298 sc->sf_unit); 1299 return(1); 1300 } 1301 } 1302 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1303 mtod(m_new, caddr_t)); 1304 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1305 m_freem(m_head); 1306 m_head = m_new; 1307 f = &c->sf_frags[0]; 1308 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1309 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1310 frag = 1; 1311 } 1312 1313 c->sf_mbuf = m_head; 1314 c->sf_id = SF_TX_BUFDESC_ID; 1315 c->sf_fragcnt = frag; 1316 c->sf_intr = 1; 1317 c->sf_caltcp = 0; 1318 c->sf_crcen = 1; 1319 1320 return(0); 1321 } 1322 1323 static void sf_start(ifp) 1324 struct ifnet *ifp; 1325 { 1326 struct sf_softc *sc; 1327 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1328 struct mbuf *m_head = NULL; 1329 int i, txprod; 1330 1331 sc = ifp->if_softc; 1332 1333 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) 1334 return; 1335 1336 if (ifp->if_flags & IFF_OACTIVE) 1337 return; 1338 1339 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1340 i = SF_IDX_HI(txprod) >> 4; 1341 1342 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1343 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1344 sf_init(sc); 1345 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1346 i = SF_IDX_HI(txprod) >> 4; 1347 } 1348 1349 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1350 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1351 ifp->if_flags |= IFF_OACTIVE; 1352 cur_tx = NULL; 1353 break; 1354 } 1355 IF_DEQUEUE(&ifp->if_snd, m_head); 1356 if (m_head == NULL) 1357 break; 1358 1359 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1360 if (sf_encap(sc, cur_tx, m_head)) { 1361 IF_PREPEND(&ifp->if_snd, m_head); 1362 ifp->if_flags |= IFF_OACTIVE; 1363 cur_tx = NULL; 1364 break; 1365 } 1366 1367 1368 /* 1369 * If there's a BPF listener, bounce a copy of this frame 1370 * to him. 1371 */ 1372 if (ifp->if_bpf) 1373 bpf_mtap(ifp, m_head); 1374 1375 SF_INC(i, SF_TX_DLIST_CNT); 1376 sc->sf_tx_cnt++; 1377 /* 1378 * Don't get the TX DMA queue get too full. 1379 */ 1380 if (sc->sf_tx_cnt > 64) 1381 break; 1382 } 1383 1384 if (cur_tx == NULL) 1385 return; 1386 1387 /* Transmit */ 1388 csr_write_4(sc, SF_TXDQ_PRODIDX, 1389 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1390 ((i << 20) & 0xFFFF0000)); 1391 1392 ifp->if_timer = 5; 1393 1394 return; 1395 } 1396 1397 static void sf_stop(sc) 1398 struct sf_softc *sc; 1399 { 1400 int i; 1401 struct ifnet *ifp; 1402 1403 ifp = &sc->arpcom.ac_if; 1404 1405 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1406 1407 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1408 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1409 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1410 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1411 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1412 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1413 csr_write_4(sc, SF_TXCQ_CTL, 0); 1414 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1415 csr_write_4(sc, SF_TXDQ_CTL, 0); 1416 sf_reset(sc); 1417 1418 sc->sf_link = 0; 1419 1420 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1421 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1422 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1423 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1424 } 1425 } 1426 1427 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1428 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1429 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1430 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1431 } 1432 } 1433 1434 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1435 1436 return; 1437 } 1438 1439 /* 1440 * Note: it is important that this function not be interrupted. We 1441 * use a two-stage register access scheme: if we are interrupted in 1442 * between setting the indirect address register and reading from the 1443 * indirect data register, the contents of the address register could 1444 * be changed out from under us. 1445 */ 1446 static void sf_stats_update(xsc) 1447 void *xsc; 1448 { 1449 struct sf_softc *sc; 1450 struct ifnet *ifp; 1451 struct mii_data *mii; 1452 struct sf_stats stats; 1453 u_int32_t *ptr; 1454 int i, s; 1455 1456 s = splimp(); 1457 1458 sc = xsc; 1459 ifp = &sc->arpcom.ac_if; 1460 mii = device_get_softc(sc->sf_miibus); 1461 1462 ptr = (u_int32_t *)&stats; 1463 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1464 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1465 (i + sizeof(u_int32_t))); 1466 1467 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1468 csr_write_4(sc, SF_STATS_BASE + 1469 (i + sizeof(u_int32_t)), 0); 1470 1471 ifp->if_collisions += stats.sf_tx_single_colls + 1472 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1473 1474 mii_tick(mii); 1475 if (!sc->sf_link) { 1476 mii_pollstat(mii); 1477 if (mii->mii_media_status & IFM_ACTIVE && 1478 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1479 sc->sf_link++; 1480 if (ifp->if_snd.ifq_head != NULL) 1481 sf_start(ifp); 1482 } 1483 1484 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1485 1486 splx(s); 1487 1488 return; 1489 } 1490 1491 static void sf_watchdog(ifp) 1492 struct ifnet *ifp; 1493 { 1494 struct sf_softc *sc; 1495 1496 sc = ifp->if_softc; 1497 1498 ifp->if_oerrors++; 1499 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1500 1501 sf_stop(sc); 1502 sf_reset(sc); 1503 sf_init(sc); 1504 1505 if (ifp->if_snd.ifq_head != NULL) 1506 sf_start(ifp); 1507 1508 return; 1509 } 1510 1511 static void sf_shutdown(dev) 1512 device_t dev; 1513 { 1514 struct sf_softc *sc; 1515 1516 sc = device_get_softc(dev); 1517 1518 sf_stop(sc); 1519 1520 return; 1521 } 1522