1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.18 2004/07/23 07:16:28 joerg Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $ 36 */ 37 38 /* 39 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 40 * available from http://www.sis.com.tw. 41 * 42 * This driver also supports the NatSemi DP83815. Datasheets are 43 * available from http://www.national.com. 44 * 45 * Written by Bill Paul <wpaul@ee.columbia.edu> 46 * Electrical Engineering Department 47 * Columbia University, New York City 48 */ 49 50 /* 51 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 52 * simple TX and RX descriptors of 3 longwords in size. The receiver 53 * has a single perfect filter entry for the station address and a 54 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 55 * transceiver while the 7016 requires an external transceiver chip. 56 * Both chips offer the standard bit-bang MII interface as well as 57 * an enchanced PHY interface which simplifies accessing MII registers. 58 * 59 * The only downside to this chipset is that RX descriptors must be 60 * longword aligned. 61 */ 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/sockio.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/sysctl.h> 71 72 #include <net/if.h> 73 #include <net/if_arp.h> 74 #include <net/ethernet.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/vlan/if_vlan_var.h> 79 80 #include <net/bpf.h> 81 82 #include <machine/bus_pio.h> 83 #include <machine/bus_memio.h> 84 #include <machine/bus.h> 85 #include <machine/resource.h> 86 #include <sys/bus.h> 87 #include <sys/rman.h> 88 89 #include <dev/netif/mii_layer/mii.h> 90 #include <dev/netif/mii_layer/miivar.h> 91 92 #include <bus/pci/pcireg.h> 93 #include <bus/pci/pcivar.h> 94 95 #define SIS_USEIOSPACE 96 97 #include "if_sisreg.h" 98 99 /* "controller miibus0" required. See GENERIC if you get errors here. */ 100 #include "miibus_if.h" 101 102 /* 103 * Various supported device vendors/types and their names. 104 */ 105 static struct sis_type sis_devs[] = { 106 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 107 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 108 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 109 { 0, 0, NULL } 110 }; 111 112 static int sis_probe(device_t); 113 static int sis_attach(device_t); 114 static int sis_detach(device_t); 115 116 static int sis_newbuf(struct sis_softc *, struct sis_desc *, 117 struct mbuf *); 118 static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *); 119 static void sis_rxeof(struct sis_softc *); 120 static void sis_rxeoc(struct sis_softc *); 121 static void sis_txeof(struct sis_softc *); 122 static void sis_intr(void *); 123 static void sis_tick(void *); 124 static void sis_start(struct ifnet *); 125 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 126 static void sis_init(void *); 127 static void sis_stop(struct sis_softc *); 128 static void sis_watchdog(struct ifnet *); 129 static void sis_shutdown(device_t); 130 static int sis_ifmedia_upd(struct ifnet *); 131 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 132 133 static uint16_t sis_reverse(uint16_t); 134 static void sis_delay(struct sis_softc *); 135 static void sis_eeprom_idle(struct sis_softc *); 136 static void sis_eeprom_putbyte(struct sis_softc *, int); 137 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *); 138 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int); 139 #ifdef __i386__ 140 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int); 141 static void sis_read_mac(struct sis_softc *, device_t, caddr_t); 142 static device_t sis_find_bridge(device_t); 143 #endif 144 145 static void sis_mii_sync(struct sis_softc *); 146 static void sis_mii_send(struct sis_softc *, uint32_t, int); 147 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *); 148 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *); 149 static int sis_miibus_readreg(device_t, int, int); 150 static int sis_miibus_writereg(device_t, int, int, int); 151 static void sis_miibus_statchg(device_t); 152 153 static void sis_setmulti_sis(struct sis_softc *); 154 static void sis_setmulti_ns(struct sis_softc *); 155 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *); 156 static void sis_reset(struct sis_softc *); 157 static int sis_list_rx_init(struct sis_softc *); 158 static int sis_list_tx_init(struct sis_softc *); 159 160 static void sis_dma_map_desc_ptr(void *, bus_dma_segment_t *, int, int); 161 static void sis_dma_map_desc_next(void *, bus_dma_segment_t *, int, int); 162 static void sis_dma_map_ring(void *, bus_dma_segment_t *, int, int); 163 #ifdef SIS_USEIOSPACE 164 #define SIS_RES SYS_RES_IOPORT 165 #define SIS_RID SIS_PCI_LOIO 166 #else 167 #define SIS_RES SYS_RES_MEMORY 168 #define SIS_RID SIS_PCI_LOMEM 169 #endif 170 171 static device_method_t sis_methods[] = { 172 /* Device interface */ 173 DEVMETHOD(device_probe, sis_probe), 174 DEVMETHOD(device_attach, sis_attach), 175 DEVMETHOD(device_detach, sis_detach), 176 DEVMETHOD(device_shutdown, sis_shutdown), 177 178 /* bus interface */ 179 DEVMETHOD(bus_print_child, bus_generic_print_child), 180 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 181 182 /* MII interface */ 183 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 184 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 185 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 186 187 { 0, 0 } 188 }; 189 190 static driver_t sis_driver = { 191 "sis", 192 sis_methods, 193 sizeof(struct sis_softc) 194 }; 195 196 static devclass_t sis_devclass; 197 198 DECLARE_DUMMY_MODULE(if_sis); 199 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 200 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 201 202 #define SIS_SETBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 204 205 #define SIS_CLRBIT(sc, reg, x) \ 206 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 207 208 #define SIO_SET(x) \ 209 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 210 211 #define SIO_CLR(x) \ 212 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 213 214 static void 215 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error) 216 { 217 struct sis_desc *r; 218 219 r = arg; 220 r->sis_next = segs->ds_addr; 221 } 222 223 static void 224 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 225 { 226 struct sis_desc *r; 227 228 r = arg; 229 r->sis_ptr = segs->ds_addr; 230 } 231 232 static void 233 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error) 234 { 235 uint32_t *p; 236 237 p = arg; 238 *p = segs->ds_addr; 239 } 240 241 /* 242 * Routine to reverse the bits in a word. Stolen almost 243 * verbatim from /usr/games/fortune. 244 */ 245 static uint16_t 246 sis_reverse(uint16_t n) 247 { 248 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 249 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 250 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 251 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 252 253 return(n); 254 } 255 256 static void 257 sis_delay(struct sis_softc *sc) 258 { 259 int idx; 260 261 for (idx = (300 / 33) + 1; idx > 0; idx--) 262 CSR_READ_4(sc, SIS_CSR); 263 } 264 265 static void 266 sis_eeprom_idle(struct sis_softc *sc) 267 { 268 int i; 269 270 SIO_SET(SIS_EECTL_CSEL); 271 sis_delay(sc); 272 SIO_SET(SIS_EECTL_CLK); 273 sis_delay(sc); 274 275 for (i = 0; i < 25; i++) { 276 SIO_CLR(SIS_EECTL_CLK); 277 sis_delay(sc); 278 SIO_SET(SIS_EECTL_CLK); 279 sis_delay(sc); 280 } 281 282 SIO_CLR(SIS_EECTL_CLK); 283 sis_delay(sc); 284 SIO_CLR(SIS_EECTL_CSEL); 285 sis_delay(sc); 286 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 287 } 288 289 /* 290 * Send a read command and address to the EEPROM, check for ACK. 291 */ 292 static void 293 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 294 { 295 int d, i; 296 297 d = addr | SIS_EECMD_READ; 298 299 /* 300 * Feed in each bit and stobe the clock. 301 */ 302 for (i = 0x400; i; i >>= 1) { 303 if (d & i) 304 SIO_SET(SIS_EECTL_DIN); 305 else 306 SIO_CLR(SIS_EECTL_DIN); 307 sis_delay(sc); 308 SIO_SET(SIS_EECTL_CLK); 309 sis_delay(sc); 310 SIO_CLR(SIS_EECTL_CLK); 311 sis_delay(sc); 312 } 313 } 314 315 /* 316 * Read a word of data stored in the EEPROM at address 'addr.' 317 */ 318 static void 319 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 320 { 321 int i; 322 uint16_t word = 0; 323 324 /* Force EEPROM to idle state. */ 325 sis_eeprom_idle(sc); 326 327 /* Enter EEPROM access mode. */ 328 sis_delay(sc); 329 SIO_CLR(SIS_EECTL_CLK); 330 sis_delay(sc); 331 SIO_SET(SIS_EECTL_CSEL); 332 sis_delay(sc); 333 334 /* 335 * Send address of word we want to read. 336 */ 337 sis_eeprom_putbyte(sc, addr); 338 339 /* 340 * Start reading bits from EEPROM. 341 */ 342 for (i = 0x8000; i; i >>= 1) { 343 SIO_SET(SIS_EECTL_CLK); 344 sis_delay(sc); 345 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 346 word |= i; 347 sis_delay(sc); 348 SIO_CLR(SIS_EECTL_CLK); 349 sis_delay(sc); 350 } 351 352 /* Turn off EEPROM access mode. */ 353 sis_eeprom_idle(sc); 354 355 *dest = word; 356 } 357 358 /* 359 * Read a sequence of words from the EEPROM. 360 */ 361 static void 362 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 363 { 364 int i; 365 uint16_t word = 0, *ptr; 366 367 for (i = 0; i < cnt; i++) { 368 sis_eeprom_getword(sc, off + i, &word); 369 ptr = (uint16_t *)(dest + (i * 2)); 370 if (swap) 371 *ptr = ntohs(word); 372 else 373 *ptr = word; 374 } 375 } 376 377 #ifdef __i386__ 378 static device_t 379 sis_find_bridge(device_t dev) 380 { 381 devclass_t pci_devclass; 382 device_t *pci_devices; 383 int pci_count = 0; 384 device_t *pci_children; 385 int pci_childcount = 0; 386 device_t *busp, *childp; 387 device_t child = NULL; 388 int i, j; 389 390 if ((pci_devclass = devclass_find("pci")) == NULL) 391 return(NULL); 392 393 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 394 395 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 396 pci_childcount = 0; 397 device_get_children(*busp, &pci_children, &pci_childcount); 398 for (j = 0, childp = pci_children; j < pci_childcount; 399 j++, childp++) { 400 if (pci_get_vendor(*childp) == SIS_VENDORID && 401 pci_get_device(*childp) == 0x0008) { 402 child = *childp; 403 goto done; 404 } 405 } 406 } 407 408 done: 409 free(pci_devices, M_TEMP); 410 free(pci_children, M_TEMP); 411 return(child); 412 } 413 414 static void 415 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, 416 int cnt) 417 { 418 device_t bridge; 419 uint8_t reg; 420 int i; 421 bus_space_tag_t btag; 422 423 bridge = sis_find_bridge(dev); 424 if (bridge == NULL) 425 return; 426 reg = pci_read_config(bridge, 0x48, 1); 427 pci_write_config(bridge, 0x48, reg|0x40, 1); 428 429 /* XXX */ 430 btag = I386_BUS_SPACE_IO; 431 432 for (i = 0; i < cnt; i++) { 433 bus_space_write_1(btag, 0x0, 0x70, i + off); 434 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 435 } 436 437 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 438 } 439 440 static void 441 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 442 { 443 uint32_t filtsave, csrsave; 444 445 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 446 csrsave = CSR_READ_4(sc, SIS_CSR); 447 448 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 449 CSR_WRITE_4(sc, SIS_CSR, 0); 450 451 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 452 453 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 454 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 455 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 456 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 457 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 458 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 459 460 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 461 CSR_WRITE_4(sc, SIS_CSR, csrsave); 462 } 463 #endif 464 465 /* 466 * Sync the PHYs by setting data bit and strobing the clock 32 times. 467 */ 468 static void 469 sis_mii_sync(struct sis_softc *sc) 470 { 471 int i; 472 473 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 474 475 for (i = 0; i < 32; i++) { 476 SIO_SET(SIS_MII_CLK); 477 DELAY(1); 478 SIO_CLR(SIS_MII_CLK); 479 DELAY(1); 480 } 481 } 482 483 /* 484 * Clock a series of bits through the MII. 485 */ 486 static void 487 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 488 { 489 int i; 490 491 SIO_CLR(SIS_MII_CLK); 492 493 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 494 if (bits & i) 495 SIO_SET(SIS_MII_DATA); 496 else 497 SIO_CLR(SIS_MII_DATA); 498 DELAY(1); 499 SIO_CLR(SIS_MII_CLK); 500 DELAY(1); 501 SIO_SET(SIS_MII_CLK); 502 } 503 } 504 505 /* 506 * Read an PHY register through the MII. 507 */ 508 static int 509 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 510 { 511 int i, ack, s; 512 513 s = splimp(); 514 515 /* 516 * Set up frame for RX. 517 */ 518 frame->mii_stdelim = SIS_MII_STARTDELIM; 519 frame->mii_opcode = SIS_MII_READOP; 520 frame->mii_turnaround = 0; 521 frame->mii_data = 0; 522 523 /* 524 * Turn on data xmit. 525 */ 526 SIO_SET(SIS_MII_DIR); 527 528 sis_mii_sync(sc); 529 530 /* 531 * Send command/address info. 532 */ 533 sis_mii_send(sc, frame->mii_stdelim, 2); 534 sis_mii_send(sc, frame->mii_opcode, 2); 535 sis_mii_send(sc, frame->mii_phyaddr, 5); 536 sis_mii_send(sc, frame->mii_regaddr, 5); 537 538 /* Idle bit */ 539 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 540 DELAY(1); 541 SIO_SET(SIS_MII_CLK); 542 DELAY(1); 543 544 /* Turn off xmit. */ 545 SIO_CLR(SIS_MII_DIR); 546 547 /* Check for ack */ 548 SIO_CLR(SIS_MII_CLK); 549 DELAY(1); 550 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 551 SIO_SET(SIS_MII_CLK); 552 DELAY(1); 553 554 /* 555 * Now try reading data bits. If the ack failed, we still 556 * need to clock through 16 cycles to keep the PHY(s) in sync. 557 */ 558 if (ack) { 559 for(i = 0; i < 16; i++) { 560 SIO_CLR(SIS_MII_CLK); 561 DELAY(1); 562 SIO_SET(SIS_MII_CLK); 563 DELAY(1); 564 } 565 goto fail; 566 } 567 568 for (i = 0x8000; i; i >>= 1) { 569 SIO_CLR(SIS_MII_CLK); 570 DELAY(1); 571 if (!ack) { 572 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 573 frame->mii_data |= i; 574 DELAY(1); 575 } 576 SIO_SET(SIS_MII_CLK); 577 DELAY(1); 578 } 579 580 fail: 581 582 SIO_CLR(SIS_MII_CLK); 583 DELAY(1); 584 SIO_SET(SIS_MII_CLK); 585 DELAY(1); 586 587 splx(s); 588 589 if (ack) 590 return(1); 591 return(0); 592 } 593 594 /* 595 * Write to a PHY register through the MII. 596 */ 597 static int 598 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 599 { 600 int s; 601 602 s = splimp(); 603 /* 604 * Set up frame for TX. 605 */ 606 607 frame->mii_stdelim = SIS_MII_STARTDELIM; 608 frame->mii_opcode = SIS_MII_WRITEOP; 609 frame->mii_turnaround = SIS_MII_TURNAROUND; 610 611 /* 612 * Turn on data output. 613 */ 614 SIO_SET(SIS_MII_DIR); 615 616 sis_mii_sync(sc); 617 618 sis_mii_send(sc, frame->mii_stdelim, 2); 619 sis_mii_send(sc, frame->mii_opcode, 2); 620 sis_mii_send(sc, frame->mii_phyaddr, 5); 621 sis_mii_send(sc, frame->mii_regaddr, 5); 622 sis_mii_send(sc, frame->mii_turnaround, 2); 623 sis_mii_send(sc, frame->mii_data, 16); 624 625 /* Idle bit. */ 626 SIO_SET(SIS_MII_CLK); 627 DELAY(1); 628 SIO_CLR(SIS_MII_CLK); 629 DELAY(1); 630 631 /* 632 * Turn off xmit. 633 */ 634 SIO_CLR(SIS_MII_DIR); 635 636 splx(s); 637 638 return(0); 639 } 640 641 static int 642 sis_miibus_readreg(device_t dev, int phy, int reg) 643 { 644 struct sis_softc *sc; 645 struct sis_mii_frame frame; 646 647 sc = device_get_softc(dev); 648 649 if (sc->sis_type == SIS_TYPE_83815) { 650 if (phy != 0) 651 return(0); 652 /* 653 * The NatSemi chip can take a while after 654 * a reset to come ready, during which the BMSR 655 * returns a value of 0. This is *never* supposed 656 * to happen: some of the BMSR bits are meant to 657 * be hardwired in the on position, and this can 658 * confuse the miibus code a bit during the probe 659 * and attach phase. So we make an effort to check 660 * for this condition and wait for it to clear. 661 */ 662 if (!CSR_READ_4(sc, NS_BMSR)) 663 DELAY(1000); 664 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 665 } 666 /* 667 * Chipsets < SIS_635 seem not to be able to read/write 668 * through mdio. Use the enhanced PHY access register 669 * again for them. 670 */ 671 if (sc->sis_type == SIS_TYPE_900 && 672 sc->sis_rev < SIS_REV_635) { 673 int i, val = 0; 674 675 if (phy != 0) 676 return(0); 677 678 CSR_WRITE_4(sc, SIS_PHYCTL, 679 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 680 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 681 682 for (i = 0; i < SIS_TIMEOUT; i++) { 683 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 684 break; 685 } 686 687 if (i == SIS_TIMEOUT) { 688 device_printf(dev, "PHY failed to come ready\n"); 689 return(0); 690 } 691 692 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 693 694 if (val == 0xFFFF) 695 return(0); 696 697 return(val); 698 } else { 699 bzero((char *)&frame, sizeof(frame)); 700 701 frame.mii_phyaddr = phy; 702 frame.mii_regaddr = reg; 703 sis_mii_readreg(sc, &frame); 704 705 return(frame.mii_data); 706 } 707 } 708 709 static int 710 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 711 { 712 struct sis_softc *sc; 713 struct sis_mii_frame frame; 714 715 sc = device_get_softc(dev); 716 717 if (sc->sis_type == SIS_TYPE_83815) { 718 if (phy != 0) 719 return(0); 720 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 721 return(0); 722 } 723 724 if (sc->sis_type == SIS_TYPE_900 && 725 sc->sis_rev < SIS_REV_635) { 726 int i; 727 728 if (phy != 0) 729 return(0); 730 731 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 732 (reg << 6) | SIS_PHYOP_WRITE); 733 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 734 735 for (i = 0; i < SIS_TIMEOUT; i++) { 736 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 737 break; 738 } 739 740 if (i == SIS_TIMEOUT) 741 device_printf(dev, "PHY failed to come ready\n"); 742 } else { 743 bzero((char *)&frame, sizeof(frame)); 744 745 frame.mii_phyaddr = phy; 746 frame.mii_regaddr = reg; 747 frame.mii_data = data; 748 sis_mii_writereg(sc, &frame); 749 } 750 return(0); 751 } 752 753 static void sis_miibus_statchg(device_t dev) 754 { 755 struct sis_softc *sc; 756 757 sc = device_get_softc(dev); 758 sis_init(sc); 759 } 760 761 static uint32_t 762 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 763 { 764 uint32_t crc, carry; 765 int i, j; 766 uint8_t c; 767 768 /* Compute CRC for the address value. */ 769 crc = 0xFFFFFFFF; /* initial value */ 770 771 for (i = 0; i < 6; i++) { 772 c = *(addr + i); 773 for (j = 0; j < 8; j++) { 774 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 775 crc <<= 1; 776 c >>= 1; 777 if (carry) 778 crc = (crc ^ 0x04c11db6) | carry; 779 } 780 } 781 782 /* 783 * return the filter bit position 784 * 785 * The NatSemi chip has a 512-bit filter, which is 786 * different than the SiS, so we special-case it. 787 */ 788 if (sc->sis_type == SIS_TYPE_83815) 789 return (crc >> 23); 790 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 791 return (crc >> 24); 792 else 793 return (crc >> 25); 794 } 795 796 static void 797 sis_setmulti_ns(struct sis_softc *sc) 798 { 799 struct ifnet *ifp; 800 struct ifmultiaddr *ifma; 801 uint32_t h = 0, i, filtsave; 802 int bit, index; 803 804 ifp = &sc->arpcom.ac_if; 805 806 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 807 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 808 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 809 return; 810 } 811 812 /* 813 * We have to explicitly enable the multicast hash table 814 * on the NatSemi chip if we want to use it, which we do. 815 */ 816 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 817 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 818 819 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 820 821 /* first, zot all the existing hash bits */ 822 for (i = 0; i < 32; i++) { 823 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 824 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 825 } 826 827 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 828 if (ifma->ifma_addr->sa_family != AF_LINK) 829 continue; 830 h = sis_mchash(sc, 831 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 832 index = h >> 3; 833 bit = h & 0x1F; 834 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 835 if (bit > 0xF) 836 bit -= 0x10; 837 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 838 } 839 840 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 841 } 842 843 static void 844 sis_setmulti_sis(struct sis_softc *sc) 845 { 846 struct ifnet *ifp; 847 struct ifmultiaddr *ifma; 848 uint32_t h, i, n, ctl; 849 uint16_t hashes[16]; 850 851 ifp = &sc->arpcom.ac_if; 852 853 /* hash table size */ 854 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 855 n = 16; 856 else 857 n = 8; 858 859 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 860 861 if (ifp->if_flags & IFF_BROADCAST) 862 ctl |= SIS_RXFILTCTL_BROAD; 863 864 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 865 ctl |= SIS_RXFILTCTL_ALLMULTI; 866 if (ifp->if_flags & IFF_PROMISC) 867 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 868 for (i = 0; i < n; i++) 869 hashes[i] = ~0; 870 } else { 871 for (i = 0; i < n; i++) 872 hashes[i] = 0; 873 i = 0; 874 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 875 if (ifma->ifma_addr->sa_family != AF_LINK) 876 continue; 877 h = sis_mchash(sc, 878 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 879 hashes[h >> 4] |= 1 << (h & 0xf); 880 i++; 881 } 882 if (i > n) { 883 ctl |= SIS_RXFILTCTL_ALLMULTI; 884 for (i = 0; i < n; i++) 885 hashes[i] = ~0; 886 } 887 } 888 889 for (i = 0; i < n; i++) { 890 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 891 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 892 } 893 894 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 895 } 896 897 static void 898 sis_reset(struct sis_softc *sc) 899 { 900 struct ifnet *ifp = &sc->arpcom.ac_if; 901 int i; 902 903 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 904 905 for (i = 0; i < SIS_TIMEOUT; i++) { 906 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 907 break; 908 } 909 910 if (i == SIS_TIMEOUT) 911 if_printf(ifp, "reset never completed\n"); 912 913 /* Wait a little while for the chip to get its brains in order. */ 914 DELAY(1000); 915 916 /* 917 * If this is a NetSemi chip, make sure to clear 918 * PME mode. 919 */ 920 if (sc->sis_type == SIS_TYPE_83815) { 921 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 922 CSR_WRITE_4(sc, NS_CLKRUN, 0); 923 } 924 } 925 926 /* 927 * Probe for an SiS chip. Check the PCI vendor and device 928 * IDs against our list and return a device name if we find a match. 929 */ 930 static int 931 sis_probe(device_t dev) 932 { 933 struct sis_type *t; 934 935 t = sis_devs; 936 937 while(t->sis_name != NULL) { 938 if ((pci_get_vendor(dev) == t->sis_vid) && 939 (pci_get_device(dev) == t->sis_did)) { 940 device_set_desc(dev, t->sis_name); 941 return(0); 942 } 943 t++; 944 } 945 946 return(ENXIO); 947 } 948 949 /* 950 * Attach the interface. Allocate softc structures, do ifmedia 951 * setup and ethernet/BPF attach. 952 */ 953 static int 954 sis_attach(device_t dev) 955 { 956 uint8_t eaddr[ETHER_ADDR_LEN]; 957 uint32_t command; 958 struct sis_softc *sc; 959 struct ifnet *ifp; 960 int error, rid, waittime; 961 962 error = waittime = 0; 963 sc = device_get_softc(dev); 964 bzero(sc, sizeof(struct sis_softc)); 965 966 if (pci_get_device(dev) == SIS_DEVICEID_900) 967 sc->sis_type = SIS_TYPE_900; 968 if (pci_get_device(dev) == SIS_DEVICEID_7016) 969 sc->sis_type = SIS_TYPE_7016; 970 if (pci_get_vendor(dev) == NS_VENDORID) 971 sc->sis_type = SIS_TYPE_83815; 972 973 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 974 975 /* 976 * Handle power management nonsense. 977 */ 978 979 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 980 if (command == 0x01) { 981 982 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 983 if (command & SIS_PSTATE_MASK) { 984 uint32_t iobase, membase, irq; 985 986 /* Save important PCI config data. */ 987 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 988 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 989 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 990 991 /* Reset the power state. */ 992 device_printf(dev, "chip is in D%d power mode " 993 "-- setting to D0\n", command & SIS_PSTATE_MASK); 994 command &= 0xFFFFFFFC; 995 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 996 997 /* Restore PCI config data. */ 998 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 999 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 1000 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 1001 } 1002 } 1003 1004 /* 1005 * Map control/status registers. 1006 */ 1007 command = pci_read_config(dev, PCIR_COMMAND, 4); 1008 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1009 pci_write_config(dev, PCIR_COMMAND, command, 4); 1010 command = pci_read_config(dev, PCIR_COMMAND, 4); 1011 1012 #ifdef SIS_USEIOSPACE 1013 if (!(command & PCIM_CMD_PORTEN)) { 1014 device_printf(dev, "failed to enable I/O ports!\n"); 1015 error = ENXIO;; 1016 goto fail; 1017 } 1018 #else 1019 if (!(command & PCIM_CMD_MEMEN)) { 1020 device_printf(dev, "failed to enable memory mapping!\n"); 1021 error = ENXIO;; 1022 goto fail; 1023 } 1024 #endif 1025 1026 rid = SIS_RID; 1027 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 1028 0, ~0, 1, RF_ACTIVE); 1029 1030 if (sc->sis_res == NULL) { 1031 device_printf(dev, "couldn't map ports/memory\n"); 1032 error = ENXIO; 1033 goto fail; 1034 } 1035 1036 sc->sis_btag = rman_get_bustag(sc->sis_res); 1037 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1038 1039 /* Allocate interrupt */ 1040 rid = 0; 1041 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1042 RF_SHAREABLE | RF_ACTIVE); 1043 1044 if (sc->sis_irq == NULL) { 1045 device_printf(dev, "couldn't map interrupt\n"); 1046 error = ENXIO; 1047 goto fail; 1048 } 1049 1050 /* Reset the adapter. */ 1051 sis_reset(sc); 1052 1053 if (sc->sis_type == SIS_TYPE_900 && 1054 (sc->sis_rev == SIS_REV_635 || 1055 sc->sis_rev == SIS_REV_900B)) { 1056 SIO_SET(SIS_CFG_RND_CNT); 1057 SIO_SET(SIS_CFG_PERR_DETECT); 1058 } 1059 1060 /* 1061 * Get station address from the EEPROM. 1062 */ 1063 switch (pci_get_vendor(dev)) { 1064 case NS_VENDORID: 1065 /* 1066 * Reading the MAC address out of the EEPROM on 1067 * the NatSemi chip takes a bit more work than 1068 * you'd expect. The address spans 4 16-bit words, 1069 * with the first word containing only a single bit. 1070 * You have to shift everything over one bit to 1071 * get it aligned properly. Also, the bits are 1072 * stored backwards (the LSB is really the MSB, 1073 * and so on) so you have to reverse them in order 1074 * to get the MAC address into the form we want. 1075 * Why? Who the hell knows. 1076 */ 1077 { 1078 uint16_t tmp[4]; 1079 1080 sis_read_eeprom(sc, (caddr_t)&tmp, 1081 NS_EE_NODEADDR, 4, 0); 1082 1083 /* Shift everything over one bit. */ 1084 tmp[3] = tmp[3] >> 1; 1085 tmp[3] |= tmp[2] << 15; 1086 tmp[2] = tmp[2] >> 1; 1087 tmp[2] |= tmp[1] << 15; 1088 tmp[1] = tmp[1] >> 1; 1089 tmp[1] |= tmp[0] << 15; 1090 1091 /* Now reverse all the bits. */ 1092 tmp[3] = sis_reverse(tmp[3]); 1093 tmp[2] = sis_reverse(tmp[2]); 1094 tmp[1] = sis_reverse(tmp[1]); 1095 1096 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1097 } 1098 break; 1099 case SIS_VENDORID: 1100 default: 1101 #ifdef __i386__ 1102 /* 1103 * If this is a SiS 630E chipset with an embedded 1104 * SiS 900 controller, we have to read the MAC address 1105 * from the APC CMOS RAM. Our method for doing this 1106 * is very ugly since we have to reach out and grab 1107 * ahold of hardware for which we cannot properly 1108 * allocate resources. This code is only compiled on 1109 * the i386 architecture since the SiS 630E chipset 1110 * is for x86 motherboards only. Note that there are 1111 * a lot of magic numbers in this hack. These are 1112 * taken from SiS's Linux driver. I'd like to replace 1113 * them with proper symbolic definitions, but that 1114 * requires some datasheets that I don't have access 1115 * to at the moment. 1116 */ 1117 if (sc->sis_rev == SIS_REV_630S || 1118 sc->sis_rev == SIS_REV_630E || 1119 sc->sis_rev == SIS_REV_630EA1) 1120 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1121 1122 else if (sc->sis_rev == SIS_REV_635 || 1123 sc->sis_rev == SIS_REV_630ET) 1124 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1125 else if (sc->sis_rev == SIS_REV_96x) { 1126 /* 1127 * Allow to read EEPROM from LAN. It is shared 1128 * between a 1394 controller and the NIC and each 1129 * time we access it, we need to set SIS_EECMD_REQ. 1130 */ 1131 SIO_SET(SIS_EECMD_REQ); 1132 for (waittime = 0; waittime < SIS_TIMEOUT; 1133 waittime++) { 1134 /* Force EEPROM to idle state. */ 1135 sis_eeprom_idle(sc); 1136 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1137 sis_read_eeprom(sc, (caddr_t)&eaddr, 1138 SIS_EE_NODEADDR, 3, 0); 1139 break; 1140 } 1141 DELAY(1); 1142 } 1143 /* 1144 * Set SIS_EECTL_CLK to high, so a other master 1145 * can operate on the i2c bus. 1146 */ 1147 SIO_SET(SIS_EECTL_CLK); 1148 /* Refuse EEPROM access by LAN */ 1149 SIO_SET(SIS_EECMD_DONE); 1150 } else 1151 #endif 1152 sis_read_eeprom(sc, (caddr_t)&eaddr, 1153 SIS_EE_NODEADDR, 3, 0); 1154 break; 1155 } 1156 1157 callout_init(&sc->sis_timer); 1158 1159 /* 1160 * Allocate the parent bus DMA tag appropriate for PCI. 1161 */ 1162 #define SIS_NSEG_NEW 32 1163 error = bus_dma_tag_create(NULL, /* parent */ 1164 1, 0, /* alignment, boundary */ 1165 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1166 BUS_SPACE_MAXADDR, /* highaddr */ 1167 NULL, NULL, /* filter, filterarg */ 1168 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1169 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1170 BUS_DMA_ALLOCNOW, /* flags */ 1171 &sc->sis_parent_tag); 1172 if (error) 1173 goto fail; 1174 1175 /* 1176 * Now allocate a tag for the DMA descriptor lists and a chunk 1177 * of DMA-able memory based on the tag. Also obtain the physical 1178 * addresses of the RX and TX ring, which we'll need later. 1179 * All of our lists are allocated as a contiguous block of memory. 1180 */ 1181 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1182 1, 0, /* alignment, boundary */ 1183 BUS_SPACE_MAXADDR, /* lowaddr */ 1184 BUS_SPACE_MAXADDR, /* highaddr */ 1185 NULL, NULL, /* filter, filterarg */ 1186 SIS_RX_LIST_SZ, 1, /* maxsize, nsegments */ 1187 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1188 0, /* flags */ 1189 &sc->sis_ldata.sis_rx_tag); 1190 if (error) 1191 goto fail; 1192 1193 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1194 (void **)&sc->sis_ldata.sis_rx_list, 1195 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1196 &sc->sis_ldata.sis_rx_dmamap); 1197 1198 if (error) { 1199 device_printf(dev, "no memory for rx list buffers!\n"); 1200 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1201 sc->sis_ldata.sis_rx_tag = NULL; 1202 goto fail; 1203 } 1204 1205 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1206 sc->sis_ldata.sis_rx_dmamap, 1207 sc->sis_ldata.sis_rx_list, 1208 sizeof(struct sis_desc), sis_dma_map_ring, 1209 &sc->sis_cdata.sis_rx_paddr, 0); 1210 1211 if (error) { 1212 device_printf(dev, "cannot get address of the rx ring!\n"); 1213 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1214 sc->sis_ldata.sis_rx_list, 1215 sc->sis_ldata.sis_rx_dmamap); 1216 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1217 sc->sis_ldata.sis_rx_tag = NULL; 1218 goto fail; 1219 } 1220 1221 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1222 1, 0, /* alignment, boundary */ 1223 BUS_SPACE_MAXADDR, /* lowaddr */ 1224 BUS_SPACE_MAXADDR, /* highaddr */ 1225 NULL, NULL, /* filter, filterarg */ 1226 SIS_TX_LIST_SZ, 1, /* maxsize, nsegments */ 1227 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1228 0, /* flags */ 1229 &sc->sis_ldata.sis_tx_tag); 1230 if (error) 1231 goto fail; 1232 1233 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1234 (void **)&sc->sis_ldata.sis_tx_list, 1235 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1236 &sc->sis_ldata.sis_tx_dmamap); 1237 1238 if (error) { 1239 device_printf(dev, "no memory for tx list buffers!\n"); 1240 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1241 sc->sis_ldata.sis_tx_tag = NULL; 1242 goto fail; 1243 } 1244 1245 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1246 sc->sis_ldata.sis_tx_dmamap, 1247 sc->sis_ldata.sis_tx_list, 1248 sizeof(struct sis_desc), sis_dma_map_ring, 1249 &sc->sis_cdata.sis_tx_paddr, 0); 1250 1251 if (error) { 1252 device_printf(dev, "cannot get address of the tx ring!\n"); 1253 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1254 sc->sis_ldata.sis_tx_list, 1255 sc->sis_ldata.sis_tx_dmamap); 1256 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1257 sc->sis_ldata.sis_tx_tag = NULL; 1258 goto fail; 1259 } 1260 1261 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1262 1, 0, /* alignment, boundary */ 1263 BUS_SPACE_MAXADDR, /* lowaddr */ 1264 BUS_SPACE_MAXADDR, /* highaddr */ 1265 NULL, NULL, /* filter, filterarg */ 1266 MCLBYTES, 1, /* maxsize, nsegments */ 1267 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1268 0, /* flags */ 1269 &sc->sis_tag); 1270 if (error) 1271 goto fail; 1272 1273 ifp = &sc->arpcom.ac_if; 1274 ifp->if_softc = sc; 1275 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1276 ifp->if_mtu = ETHERMTU; 1277 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1278 ifp->if_ioctl = sis_ioctl; 1279 ifp->if_start = sis_start; 1280 ifp->if_watchdog = sis_watchdog; 1281 ifp->if_init = sis_init; 1282 ifp->if_baudrate = 10000000; 1283 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1284 #ifdef DEVICE_POLLING 1285 ifp->if_capabilities |= IFCAP_POLLING; 1286 #endif 1287 ifp->if_capenable = ifp->if_capabilities; 1288 1289 /* 1290 * Do MII setup. 1291 */ 1292 if (mii_phy_probe(dev, &sc->sis_miibus, 1293 sis_ifmedia_upd, sis_ifmedia_sts)) { 1294 device_printf(dev, "MII without any PHY!\n"); 1295 error = ENXIO; 1296 goto fail; 1297 } 1298 1299 /* 1300 * Call MI attach routine. 1301 */ 1302 ether_ifattach(ifp, eaddr); 1303 1304 /* 1305 * Tell the upper layer(s) we support long frames. 1306 */ 1307 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1308 1309 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 1310 sis_intr, sc, &sc->sis_intrhand); 1311 1312 if (error) { 1313 device_printf(dev, "couldn't set up irq\n"); 1314 ether_ifdetach(ifp); 1315 goto fail; 1316 } 1317 1318 fail: 1319 if (error) 1320 sis_detach(dev); 1321 1322 return(error); 1323 } 1324 1325 /* 1326 * Shutdown hardware and free up resources. It is called in both the error case 1327 * and the normal detach case so it needs to be careful about only freeing 1328 * resources that have actually been allocated. 1329 */ 1330 static int 1331 sis_detach(device_t dev) 1332 { 1333 struct sis_softc *sc; 1334 struct ifnet *ifp; 1335 int s; 1336 1337 s = splimp(); 1338 1339 sc = device_get_softc(dev); 1340 ifp = &sc->arpcom.ac_if; 1341 1342 if (device_is_attached(dev)) { 1343 sis_reset(sc); 1344 sis_stop(sc); 1345 ether_ifdetach(ifp); 1346 } 1347 if (sc->sis_miibus) 1348 device_delete_child(dev, sc->sis_miibus); 1349 bus_generic_detach(dev); 1350 1351 if (sc->sis_intrhand) 1352 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1353 if (sc->sis_irq) 1354 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1355 if (sc->sis_res) 1356 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1357 1358 if (sc->sis_ldata.sis_rx_tag) { 1359 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1360 sc->sis_ldata.sis_rx_dmamap); 1361 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1362 sc->sis_ldata.sis_rx_list, 1363 sc->sis_ldata.sis_rx_dmamap); 1364 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1365 } 1366 1367 if (sc->sis_ldata.sis_tx_tag) { 1368 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1369 sc->sis_ldata.sis_tx_dmamap); 1370 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1371 sc->sis_ldata.sis_tx_list, 1372 sc->sis_ldata.sis_tx_dmamap); 1373 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1374 } 1375 if (sc->sis_tag) 1376 bus_dma_tag_destroy(sc->sis_tag); 1377 if (sc->sis_parent_tag) 1378 bus_dma_tag_destroy(sc->sis_parent_tag); 1379 1380 splx(s); 1381 1382 return(0); 1383 } 1384 1385 /* 1386 * Initialize the transmit descriptors. 1387 */ 1388 static int 1389 sis_list_tx_init(struct sis_softc *sc) 1390 { 1391 struct sis_list_data *ld; 1392 struct sis_ring_data *cd; 1393 int i, nexti; 1394 1395 cd = &sc->sis_cdata; 1396 ld = &sc->sis_ldata; 1397 1398 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1399 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1400 ld->sis_tx_list[i].sis_nextdesc = 1401 &ld->sis_tx_list[nexti]; 1402 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1403 sc->sis_ldata.sis_tx_dmamap, 1404 &ld->sis_tx_list[nexti], 1405 sizeof(struct sis_desc), sis_dma_map_desc_next, 1406 &ld->sis_tx_list[i], 0); 1407 ld->sis_tx_list[i].sis_mbuf = NULL; 1408 ld->sis_tx_list[i].sis_ptr = 0; 1409 ld->sis_tx_list[i].sis_ctl = 0; 1410 } 1411 1412 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1413 1414 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap, 1415 BUS_DMASYNC_PREWRITE); 1416 1417 return(0); 1418 } 1419 1420 /* 1421 * Initialize the RX descriptors and allocate mbufs for them. Note that 1422 * we arrange the descriptors in a closed ring, so that the last descriptor 1423 * points back to the first. 1424 */ 1425 static int 1426 sis_list_rx_init(struct sis_softc *sc) 1427 { 1428 struct sis_list_data *ld; 1429 struct sis_ring_data *cd; 1430 int i, nexti; 1431 1432 ld = &sc->sis_ldata; 1433 cd = &sc->sis_cdata; 1434 1435 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1436 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1437 return(ENOBUFS); 1438 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1439 ld->sis_rx_list[i].sis_nextdesc = 1440 &ld->sis_rx_list[nexti]; 1441 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1442 sc->sis_ldata.sis_rx_dmamap, 1443 &ld->sis_rx_list[nexti], 1444 sizeof(struct sis_desc), sis_dma_map_desc_next, 1445 &ld->sis_rx_list[i], 0); 1446 } 1447 1448 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap, 1449 BUS_DMASYNC_PREWRITE); 1450 1451 cd->sis_rx_prod = 0; 1452 1453 return(0); 1454 } 1455 1456 /* 1457 * Initialize an RX descriptor and attach an MBUF cluster. 1458 */ 1459 static int 1460 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m) 1461 { 1462 if (m == NULL) { 1463 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1464 if (m == NULL) 1465 return(ENOBUFS); 1466 } else { 1467 m->m_data = m->m_ext.ext_buf; 1468 } 1469 1470 c->sis_mbuf = m; 1471 c->sis_ctl = SIS_RXLEN; 1472 1473 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1474 bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES, 1475 sis_dma_map_desc_ptr, c, 0); 1476 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1477 1478 return(0); 1479 } 1480 1481 /* 1482 * A frame has been uploaded: pass the resulting mbuf chain up to 1483 * the higher level protocols. 1484 */ 1485 static void 1486 sis_rxeof(struct sis_softc *sc) 1487 { 1488 struct mbuf *m; 1489 struct ifnet *ifp; 1490 struct sis_desc *cur_rx; 1491 int i, total_len = 0; 1492 uint32_t rxstat; 1493 1494 ifp = &sc->arpcom.ac_if; 1495 i = sc->sis_cdata.sis_rx_prod; 1496 1497 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1498 1499 #ifdef DEVICE_POLLING 1500 if (ifp->if_flags & IFF_POLLING) { 1501 if (sc->rxcycles <= 0) 1502 break; 1503 sc->rxcycles--; 1504 } 1505 #endif /* DEVICE_POLLING */ 1506 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1507 rxstat = cur_rx->sis_rxstat; 1508 bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map, 1509 BUS_DMASYNC_POSTWRITE); 1510 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1511 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1512 m = cur_rx->sis_mbuf; 1513 cur_rx->sis_mbuf = NULL; 1514 total_len = SIS_RXBYTES(cur_rx); 1515 SIS_INC(i, SIS_RX_LIST_CNT); 1516 1517 /* 1518 * If an error occurs, update stats, clear the 1519 * status word and leave the mbuf cluster in place: 1520 * it should simply get re-used next time this descriptor 1521 * comes up in the ring. 1522 */ 1523 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1524 ifp->if_ierrors++; 1525 if (rxstat & SIS_RXSTAT_COLL) 1526 ifp->if_collisions++; 1527 sis_newbuf(sc, cur_rx, m); 1528 continue; 1529 } 1530 1531 /* No errors; receive the packet. */ 1532 #ifdef __i386__ 1533 /* 1534 * On the x86 we do not have alignment problems, so try to 1535 * allocate a new buffer for the receive ring, and pass up 1536 * the one where the packet is already, saving the expensive 1537 * copy done in m_devget(). 1538 * If we are on an architecture with alignment problems, or 1539 * if the allocation fails, then use m_devget and leave the 1540 * existing buffer in the receive ring. 1541 */ 1542 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1543 m->m_pkthdr.len = m->m_len = total_len; 1544 else 1545 #endif 1546 { 1547 struct mbuf *m0; 1548 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1549 total_len + ETHER_ALIGN, 0, ifp, NULL); 1550 sis_newbuf(sc, cur_rx, m); 1551 if (m0 == NULL) { 1552 ifp->if_ierrors++; 1553 continue; 1554 } 1555 m_adj(m0, ETHER_ALIGN); 1556 m = m0; 1557 } 1558 1559 ifp->if_ipackets++; 1560 (*ifp->if_input)(ifp, m); 1561 } 1562 1563 sc->sis_cdata.sis_rx_prod = i; 1564 } 1565 1566 static void 1567 sis_rxeoc(struct sis_softc *sc) 1568 { 1569 sis_rxeof(sc); 1570 sis_init(sc); 1571 } 1572 1573 /* 1574 * A frame was downloaded to the chip. It's safe for us to clean up 1575 * the list buffers. 1576 */ 1577 1578 static void 1579 sis_txeof(struct sis_softc *sc) 1580 { 1581 struct sis_desc *cur_tx; 1582 struct ifnet *ifp; 1583 uint32_t idx; 1584 1585 ifp = &sc->arpcom.ac_if; 1586 1587 /* 1588 * Go through our tx list and free mbufs for those 1589 * frames that have been transmitted. 1590 */ 1591 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1592 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1593 cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1594 1595 if (SIS_OWNDESC(cur_tx)) 1596 break; 1597 1598 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1599 continue; 1600 1601 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1602 ifp->if_oerrors++; 1603 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1604 ifp->if_collisions++; 1605 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1606 ifp->if_collisions++; 1607 } 1608 1609 ifp->if_collisions += 1610 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1611 1612 ifp->if_opackets++; 1613 if (cur_tx->sis_mbuf != NULL) { 1614 m_freem(cur_tx->sis_mbuf); 1615 cur_tx->sis_mbuf = NULL; 1616 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1617 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1618 } 1619 } 1620 1621 if (idx != sc->sis_cdata.sis_tx_cons) { 1622 /* we freed up some buffers */ 1623 sc->sis_cdata.sis_tx_cons = idx; 1624 ifp->if_flags &= ~IFF_OACTIVE; 1625 } 1626 1627 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1628 } 1629 1630 static void 1631 sis_tick(void *xsc) 1632 { 1633 struct sis_softc *sc; 1634 struct mii_data *mii; 1635 struct ifnet *ifp; 1636 int s; 1637 1638 s = splimp(); 1639 1640 sc = xsc; 1641 ifp = &sc->arpcom.ac_if; 1642 1643 mii = device_get_softc(sc->sis_miibus); 1644 mii_tick(mii); 1645 1646 if (!sc->sis_link) { 1647 mii_pollstat(mii); 1648 if (mii->mii_media_status & IFM_ACTIVE && 1649 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1650 sc->sis_link++; 1651 if (ifp->if_snd.ifq_head != NULL) 1652 sis_start(ifp); 1653 } 1654 1655 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 1656 1657 splx(s); 1658 } 1659 1660 #ifdef DEVICE_POLLING 1661 static poll_handler_t sis_poll; 1662 1663 static void 1664 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1665 { 1666 struct sis_softc *sc = ifp->if_softc; 1667 1668 if ((ifp->if_capenable & IFCAP_POLLING) == 0) { 1669 ether_poll_deregister(ifp); 1670 cmd = POLL_DEREGISTER; 1671 } 1672 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1673 CSR_WRITE_4(sc, SIS_IER, 1); 1674 return; 1675 } 1676 1677 /* 1678 * On the sis, reading the status register also clears it. 1679 * So before returning to intr mode we must make sure that all 1680 * possible pending sources of interrupts have been served. 1681 * In practice this means run to completion the *eof routines, 1682 * and then call the interrupt routine 1683 */ 1684 sc->rxcycles = count; 1685 sis_rxeof(sc); 1686 sis_txeof(sc); 1687 if (ifp->if_snd.ifq_head != NULL) 1688 sis_start(ifp); 1689 1690 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1691 uint32_t status; 1692 1693 /* Reading the ISR register clears all interrupts. */ 1694 status = CSR_READ_4(sc, SIS_ISR); 1695 1696 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1697 sis_rxeoc(sc); 1698 1699 if (status & (SIS_ISR_RX_IDLE)) 1700 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1701 1702 if (status & SIS_ISR_SYSERR) { 1703 sis_reset(sc); 1704 sis_init(sc); 1705 } 1706 } 1707 } 1708 #endif /* DEVICE_POLLING */ 1709 1710 static void 1711 sis_intr(void *arg) 1712 { 1713 struct sis_softc *sc; 1714 struct ifnet *ifp; 1715 uint32_t status; 1716 1717 sc = arg; 1718 ifp = &sc->arpcom.ac_if; 1719 1720 #ifdef DEVICE_POLLING 1721 if (ifp->if_flags & IFF_POLLING) 1722 return; 1723 if ((ifp->if_capenable & IFCAP_POLLING) && 1724 ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1725 CSR_WRITE_4(sc, SIS_IER, 0); 1726 sis_poll(ifp, 0, 1); 1727 return; 1728 } 1729 #endif /* DEVICE_POLLING */ 1730 1731 /* Supress unwanted interrupts */ 1732 if (!(ifp->if_flags & IFF_UP)) { 1733 sis_stop(sc); 1734 return; 1735 } 1736 1737 /* Disable interrupts. */ 1738 CSR_WRITE_4(sc, SIS_IER, 0); 1739 1740 for (;;) { 1741 /* Reading the ISR register clears all interrupts. */ 1742 status = CSR_READ_4(sc, SIS_ISR); 1743 1744 if ((status & SIS_INTRS) == 0) 1745 break; 1746 1747 if (status & 1748 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK | 1749 SIS_ISR_TX_IDLE) ) 1750 sis_txeof(sc); 1751 1752 if (status & 1753 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE)) 1754 sis_rxeof(sc); 1755 1756 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1757 sis_rxeoc(sc); 1758 1759 if (status & (SIS_ISR_RX_IDLE)) 1760 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1761 1762 if (status & SIS_ISR_SYSERR) { 1763 sis_reset(sc); 1764 sis_init(sc); 1765 } 1766 } 1767 1768 /* Re-enable interrupts. */ 1769 CSR_WRITE_4(sc, SIS_IER, 1); 1770 1771 if (ifp->if_snd.ifq_head != NULL) 1772 sis_start(ifp); 1773 } 1774 1775 /* 1776 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1777 * pointers to the fragment pointers. 1778 */ 1779 static int 1780 sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1781 { 1782 struct sis_desc *f = NULL; 1783 struct mbuf *m; 1784 int frag, cur, cnt = 0; 1785 1786 /* 1787 * If there's no way we can send any packets, return now. 1788 */ 1789 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1790 return (ENOBUFS); 1791 1792 /* 1793 * Start packing the mbufs in this chain into 1794 * the fragment pointers. Stop when we run out 1795 * of fragments or hit the end of the mbuf chain. 1796 */ 1797 m = m_head; 1798 cur = frag = *txidx; 1799 1800 for (m = m_head; m != NULL; m = m->m_next) { 1801 if (m->m_len != 0) { 1802 if ((SIS_TX_LIST_CNT - 1803 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1804 return(ENOBUFS); 1805 f = &sc->sis_ldata.sis_tx_list[frag]; 1806 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1807 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1808 bus_dmamap_load(sc->sis_tag, f->sis_map, 1809 mtod(m, void *), m->m_len, 1810 sis_dma_map_desc_ptr, f, 0); 1811 bus_dmamap_sync(sc->sis_tag, f->sis_map, 1812 BUS_DMASYNC_PREREAD); 1813 if (cnt != 0) 1814 f->sis_ctl |= SIS_CMDSTS_OWN; 1815 cur = frag; 1816 SIS_INC(frag, SIS_TX_LIST_CNT); 1817 cnt++; 1818 } 1819 } 1820 1821 if (m != NULL) 1822 return(ENOBUFS); 1823 1824 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1825 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1826 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1827 sc->sis_cdata.sis_tx_cnt += cnt; 1828 *txidx = frag; 1829 1830 return(0); 1831 } 1832 1833 /* 1834 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1835 * to the mbuf data regions directly in the transmit lists. We also save a 1836 * copy of the pointers since the transmit list fragment pointers are 1837 * physical addresses. 1838 */ 1839 1840 static void 1841 sis_start(struct ifnet *ifp) 1842 { 1843 struct sis_softc *sc; 1844 struct mbuf *m_head = NULL; 1845 uint32_t idx; 1846 1847 sc = ifp->if_softc; 1848 1849 if (!sc->sis_link) 1850 return; 1851 1852 idx = sc->sis_cdata.sis_tx_prod; 1853 1854 if (ifp->if_flags & IFF_OACTIVE) 1855 return; 1856 1857 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1858 IF_DEQUEUE(&ifp->if_snd, m_head); 1859 if (m_head == NULL) 1860 break; 1861 1862 if (sis_encap(sc, m_head, &idx)) { 1863 IF_PREPEND(&ifp->if_snd, m_head); 1864 ifp->if_flags |= IFF_OACTIVE; 1865 break; 1866 } 1867 1868 /* 1869 * If there's a BPF listener, bounce a copy of this frame 1870 * to him. 1871 */ 1872 BPF_MTAP(ifp, m_head); 1873 } 1874 1875 /* Transmit */ 1876 sc->sis_cdata.sis_tx_prod = idx; 1877 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1878 1879 /* 1880 * Set a timeout in case the chip goes out to lunch. 1881 */ 1882 ifp->if_timer = 5; 1883 } 1884 1885 static void 1886 sis_init(void *xsc) 1887 { 1888 struct sis_softc *sc = xsc; 1889 struct ifnet *ifp = &sc->arpcom.ac_if; 1890 struct mii_data *mii; 1891 int s; 1892 1893 s = splimp(); 1894 1895 /* 1896 * Cancel pending I/O and free all RX/TX buffers. 1897 */ 1898 sis_stop(sc); 1899 1900 mii = device_get_softc(sc->sis_miibus); 1901 1902 /* Set MAC address */ 1903 if (sc->sis_type == SIS_TYPE_83815) { 1904 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1905 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1906 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1907 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1908 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1909 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1910 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1911 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1912 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1913 } else { 1914 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1915 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1916 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1917 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1918 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1919 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1920 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1921 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1922 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1923 } 1924 1925 /* Init circular RX list. */ 1926 if (sis_list_rx_init(sc) == ENOBUFS) { 1927 if_printf(ifp, "initialization failed: " 1928 "no memory for rx buffers\n"); 1929 sis_stop(sc); 1930 splx(s); 1931 return; 1932 } 1933 1934 /* 1935 * Init tx descriptors. 1936 */ 1937 sis_list_tx_init(sc); 1938 1939 /* 1940 * For the NatSemi chip, we have to explicitly enable the 1941 * reception of ARP frames, as well as turn on the 'perfect 1942 * match' filter where we store the station address, otherwise 1943 * we won't receive unicasts meant for this host. 1944 */ 1945 if (sc->sis_type == SIS_TYPE_83815) { 1946 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1947 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1948 } 1949 1950 /* If we want promiscuous mode, set the allframes bit. */ 1951 if (ifp->if_flags & IFF_PROMISC) 1952 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1953 else 1954 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1955 1956 /* 1957 * Set the capture broadcast bit to capture broadcast frames. 1958 */ 1959 if (ifp->if_flags & IFF_BROADCAST) 1960 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1961 else 1962 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1963 1964 /* 1965 * Load the multicast filter. 1966 */ 1967 if (sc->sis_type == SIS_TYPE_83815) 1968 sis_setmulti_ns(sc); 1969 else 1970 sis_setmulti_sis(sc); 1971 1972 /* Turn the receive filter on */ 1973 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1974 1975 /* 1976 * Load the address of the RX and TX lists. 1977 */ 1978 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 1979 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 1980 1981 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1982 * the PCI bus. When this bit is set, the Max DMA Burst Size 1983 * for TX/RX DMA should be no larger than 16 double words. 1984 */ 1985 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) 1986 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1987 else 1988 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1989 1990 /* Accept Long Packets for VLAN support */ 1991 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1992 1993 /* Set TX configuration */ 1994 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 1995 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1996 else 1997 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1998 1999 /* Set full/half duplex mode. */ 2000 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 2001 SIS_SETBIT(sc, SIS_TX_CFG, 2002 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2003 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2004 } else { 2005 SIS_CLRBIT(sc, SIS_TX_CFG, 2006 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2007 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2008 } 2009 2010 /* 2011 * Enable interrupts. 2012 */ 2013 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2014 #ifdef DEVICE_POLLING 2015 /* 2016 * ... only enable interrupts if we are not polling, make sure 2017 * they are off otherwise. 2018 */ 2019 if (ifp->if_flags & IFF_POLLING) 2020 CSR_WRITE_4(sc, SIS_IER, 0); 2021 else 2022 #endif /* DEVICE_POLLING */ 2023 CSR_WRITE_4(sc, SIS_IER, 1); 2024 2025 /* Enable receiver and transmitter. */ 2026 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2027 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2028 2029 #ifdef notdef 2030 mii_mediachg(mii); 2031 #endif 2032 2033 /* 2034 * Page 75 of the DP83815 manual recommends the 2035 * following register settings "for optimum 2036 * performance." Note however that at least three 2037 * of the registers are listed as "reserved" in 2038 * the register map, so who knows what they do. 2039 */ 2040 if (sc->sis_type == SIS_TYPE_83815) { 2041 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2042 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2043 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2044 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2045 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2046 } 2047 2048 ifp->if_flags |= IFF_RUNNING; 2049 ifp->if_flags &= ~IFF_OACTIVE; 2050 2051 splx(s); 2052 2053 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 2054 } 2055 2056 /* 2057 * Set media options. 2058 */ 2059 static int 2060 sis_ifmedia_upd(struct ifnet *ifp) 2061 { 2062 struct sis_softc *sc; 2063 struct mii_data *mii; 2064 2065 sc = ifp->if_softc; 2066 2067 mii = device_get_softc(sc->sis_miibus); 2068 sc->sis_link = 0; 2069 if (mii->mii_instance) { 2070 struct mii_softc *miisc; 2071 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2072 mii_phy_reset(miisc); 2073 } 2074 mii_mediachg(mii); 2075 2076 return(0); 2077 } 2078 2079 /* 2080 * Report current media status. 2081 */ 2082 static void 2083 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2084 { 2085 struct sis_softc *sc; 2086 struct mii_data *mii; 2087 2088 sc = ifp->if_softc; 2089 2090 mii = device_get_softc(sc->sis_miibus); 2091 mii_pollstat(mii); 2092 ifmr->ifm_active = mii->mii_media_active; 2093 ifmr->ifm_status = mii->mii_media_status; 2094 } 2095 2096 static int 2097 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2098 { 2099 struct sis_softc *sc = ifp->if_softc; 2100 struct ifreq *ifr = (struct ifreq *) data; 2101 struct mii_data *mii; 2102 int s, error = 0; 2103 2104 switch(command) { 2105 case SIOCSIFFLAGS: 2106 if (ifp->if_flags & IFF_UP) { 2107 sis_init(sc); 2108 } else { 2109 if (ifp->if_flags & IFF_RUNNING) 2110 sis_stop(sc); 2111 } 2112 error = 0; 2113 break; 2114 case SIOCADDMULTI: 2115 case SIOCDELMULTI: 2116 s = splimp(); 2117 if (sc->sis_type == SIS_TYPE_83815) 2118 sis_setmulti_ns(sc); 2119 else 2120 sis_setmulti_sis(sc); 2121 splx(s); 2122 error = 0; 2123 break; 2124 case SIOCGIFMEDIA: 2125 case SIOCSIFMEDIA: 2126 mii = device_get_softc(sc->sis_miibus); 2127 s = splimp(); 2128 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2129 splx(s); 2130 break; 2131 default: 2132 error = ether_ioctl(ifp, command, data); 2133 break; 2134 } 2135 2136 return(error); 2137 } 2138 2139 static void 2140 sis_watchdog(struct ifnet *ifp) 2141 { 2142 struct sis_softc *sc; 2143 2144 sc = ifp->if_softc; 2145 2146 ifp->if_oerrors++; 2147 if_printf(ifp, "watchdog timeout\n"); 2148 2149 sis_stop(sc); 2150 sis_reset(sc); 2151 sis_init(sc); 2152 2153 if (ifp->if_snd.ifq_head != NULL) 2154 sis_start(ifp); 2155 } 2156 2157 /* 2158 * Stop the adapter and free any mbufs allocated to the 2159 * RX and TX lists. 2160 */ 2161 static void 2162 sis_stop(struct sis_softc *sc) 2163 { 2164 int i; 2165 struct ifnet *ifp; 2166 2167 ifp = &sc->arpcom.ac_if; 2168 ifp->if_timer = 0; 2169 2170 callout_stop(&sc->sis_timer); 2171 2172 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2173 #ifdef DEVICE_POLLING 2174 ether_poll_deregister(ifp); 2175 #endif 2176 CSR_WRITE_4(sc, SIS_IER, 0); 2177 CSR_WRITE_4(sc, SIS_IMR, 0); 2178 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2179 DELAY(1000); 2180 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2181 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2182 2183 sc->sis_link = 0; 2184 2185 /* 2186 * Free data in the RX lists. 2187 */ 2188 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2189 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2190 bus_dmamap_unload(sc->sis_tag, 2191 sc->sis_ldata.sis_rx_list[i].sis_map); 2192 bus_dmamap_destroy(sc->sis_tag, 2193 sc->sis_ldata.sis_rx_list[i].sis_map); 2194 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2195 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2196 } 2197 } 2198 bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list)); 2199 2200 /* 2201 * Free the TX list buffers. 2202 */ 2203 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2204 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2205 bus_dmamap_unload(sc->sis_tag, 2206 sc->sis_ldata.sis_tx_list[i].sis_map); 2207 bus_dmamap_destroy(sc->sis_tag, 2208 sc->sis_ldata.sis_tx_list[i].sis_map); 2209 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2210 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2211 } 2212 } 2213 2214 bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list)); 2215 } 2216 2217 /* 2218 * Stop all chip I/O so that the kernel's probe routines don't 2219 * get confused by errant DMAs when rebooting. 2220 */ 2221 static void 2222 sis_shutdown(device_t dev) 2223 { 2224 struct sis_softc *sc; 2225 2226 sc = device_get_softc(dev); 2227 2228 sis_reset(sc); 2229 sis_stop(sc); 2230 } 2231