1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $ 33 */ 34 35 /* 36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37 * available from http://www.sis.com.tw. 38 * 39 * This driver also supports the NatSemi DP83815. Datasheets are 40 * available from http://www.national.com. 41 * 42 * Written by Bill Paul <wpaul@ee.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/sockio.h> 63 #include <sys/mbuf.h> 64 #include <sys/malloc.h> 65 #include <sys/kernel.h> 66 #include <sys/socket.h> 67 #include <sys/sysctl.h> 68 69 #include <net/if.h> 70 #include <net/if_arp.h> 71 #include <net/ethernet.h> 72 #include <net/if_dl.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 #include <net/if_vlan_var.h> 76 77 #include <net/bpf.h> 78 79 #include <vm/vm.h> /* for vtophys */ 80 #include <vm/pmap.h> /* for vtophys */ 81 #include <machine/clock.h> /* for DELAY */ 82 #include <machine/bus_pio.h> 83 #include <machine/bus_memio.h> 84 #include <machine/bus.h> 85 #include <machine/resource.h> 86 #include <sys/bus.h> 87 #include <sys/rman.h> 88 89 #include <dev/mii/mii.h> 90 #include <dev/mii/miivar.h> 91 92 #include <pci/pcireg.h> 93 #include <pci/pcivar.h> 94 95 #define SIS_USEIOSPACE 96 97 #include <pci/if_sisreg.h> 98 99 /* "controller miibus0" required. See GENERIC if you get errors here. */ 100 #include "miibus_if.h" 101 102 #ifndef lint 103 static const char rcsid[] = 104 "$FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $"; 105 #endif 106 107 /* 108 * Various supported device vendors/types and their names. 109 */ 110 static struct sis_type sis_devs[] = { 111 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 112 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 113 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 114 { 0, 0, NULL } 115 }; 116 117 static int sis_probe __P((device_t)); 118 static int sis_attach __P((device_t)); 119 static int sis_detach __P((device_t)); 120 121 static int sis_newbuf __P((struct sis_softc *, 122 struct sis_desc *, 123 struct mbuf *)); 124 static int sis_encap __P((struct sis_softc *, 125 struct mbuf *, u_int32_t *)); 126 static void sis_rxeof __P((struct sis_softc *)); 127 static void sis_rxeoc __P((struct sis_softc *)); 128 static void sis_txeof __P((struct sis_softc *)); 129 static void sis_intr __P((void *)); 130 static void sis_tick __P((void *)); 131 static void sis_start __P((struct ifnet *)); 132 static int sis_ioctl __P((struct ifnet *, u_long, caddr_t)); 133 static void sis_init __P((void *)); 134 static void sis_stop __P((struct sis_softc *)); 135 static void sis_watchdog __P((struct ifnet *)); 136 static void sis_shutdown __P((device_t)); 137 static int sis_ifmedia_upd __P((struct ifnet *)); 138 static void sis_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 139 140 static u_int16_t sis_reverse __P((u_int16_t)); 141 static void sis_delay __P((struct sis_softc *)); 142 static void sis_eeprom_idle __P((struct sis_softc *)); 143 static void sis_eeprom_putbyte __P((struct sis_softc *, int)); 144 static void sis_eeprom_getword __P((struct sis_softc *, int, u_int16_t *)); 145 static void sis_read_eeprom __P((struct sis_softc *, caddr_t, int, 146 int, int)); 147 #ifdef __i386__ 148 static void sis_read_cmos __P((struct sis_softc *, device_t, caddr_t, 149 int, int)); 150 static void sis_read_mac __P((struct sis_softc *, device_t, caddr_t)); 151 static device_t sis_find_bridge __P((device_t)); 152 #endif 153 154 static void sis_mii_sync __P((struct sis_softc *)); 155 static void sis_mii_send __P((struct sis_softc *, u_int32_t, int)); 156 static int sis_mii_readreg __P((struct sis_softc *, struct sis_mii_frame *)); 157 static int sis_mii_writereg __P((struct sis_softc *, struct sis_mii_frame *)); 158 static int sis_miibus_readreg __P((device_t, int, int)); 159 static int sis_miibus_writereg __P((device_t, int, int, int)); 160 static void sis_miibus_statchg __P((device_t)); 161 162 static void sis_setmulti_sis __P((struct sis_softc *)); 163 static void sis_setmulti_ns __P((struct sis_softc *)); 164 static u_int32_t sis_crc __P((struct sis_softc *, caddr_t)); 165 static void sis_reset __P((struct sis_softc *)); 166 static int sis_list_rx_init __P((struct sis_softc *)); 167 static int sis_list_tx_init __P((struct sis_softc *)); 168 169 #ifdef SIS_USEIOSPACE 170 #define SIS_RES SYS_RES_IOPORT 171 #define SIS_RID SIS_PCI_LOIO 172 #else 173 #define SIS_RES SYS_RES_MEMORY 174 #define SIS_RID SIS_PCI_LOMEM 175 #endif 176 177 static device_method_t sis_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, sis_probe), 180 DEVMETHOD(device_attach, sis_attach), 181 DEVMETHOD(device_detach, sis_detach), 182 DEVMETHOD(device_shutdown, sis_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 190 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 191 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 192 193 { 0, 0 } 194 }; 195 196 static driver_t sis_driver = { 197 "sis", 198 sis_methods, 199 sizeof(struct sis_softc) 200 }; 201 202 static devclass_t sis_devclass; 203 204 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 205 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 206 207 #define SIS_SETBIT(sc, reg, x) \ 208 CSR_WRITE_4(sc, reg, \ 209 CSR_READ_4(sc, reg) | (x)) 210 211 #define SIS_CLRBIT(sc, reg, x) \ 212 CSR_WRITE_4(sc, reg, \ 213 CSR_READ_4(sc, reg) & ~(x)) 214 215 #define SIO_SET(x) \ 216 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 217 218 #define SIO_CLR(x) \ 219 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 220 221 /* 222 * Routine to reverse the bits in a word. Stolen almost 223 * verbatim from /usr/games/fortune. 224 */ 225 static u_int16_t sis_reverse(n) 226 u_int16_t n; 227 { 228 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 229 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 230 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 231 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 232 233 return(n); 234 } 235 236 static void sis_delay(sc) 237 struct sis_softc *sc; 238 { 239 int idx; 240 241 for (idx = (300 / 33) + 1; idx > 0; idx--) 242 CSR_READ_4(sc, SIS_CSR); 243 244 return; 245 } 246 247 static void sis_eeprom_idle(sc) 248 struct sis_softc *sc; 249 { 250 register int i; 251 252 SIO_SET(SIS_EECTL_CSEL); 253 sis_delay(sc); 254 SIO_SET(SIS_EECTL_CLK); 255 sis_delay(sc); 256 257 for (i = 0; i < 25; i++) { 258 SIO_CLR(SIS_EECTL_CLK); 259 sis_delay(sc); 260 SIO_SET(SIS_EECTL_CLK); 261 sis_delay(sc); 262 } 263 264 SIO_CLR(SIS_EECTL_CLK); 265 sis_delay(sc); 266 SIO_CLR(SIS_EECTL_CSEL); 267 sis_delay(sc); 268 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 269 270 return; 271 } 272 273 /* 274 * Send a read command and address to the EEPROM, check for ACK. 275 */ 276 static void sis_eeprom_putbyte(sc, addr) 277 struct sis_softc *sc; 278 int addr; 279 { 280 register int d, i; 281 282 d = addr | SIS_EECMD_READ; 283 284 /* 285 * Feed in each bit and stobe the clock. 286 */ 287 for (i = 0x400; i; i >>= 1) { 288 if (d & i) { 289 SIO_SET(SIS_EECTL_DIN); 290 } else { 291 SIO_CLR(SIS_EECTL_DIN); 292 } 293 sis_delay(sc); 294 SIO_SET(SIS_EECTL_CLK); 295 sis_delay(sc); 296 SIO_CLR(SIS_EECTL_CLK); 297 sis_delay(sc); 298 } 299 300 return; 301 } 302 303 /* 304 * Read a word of data stored in the EEPROM at address 'addr.' 305 */ 306 static void sis_eeprom_getword(sc, addr, dest) 307 struct sis_softc *sc; 308 int addr; 309 u_int16_t *dest; 310 { 311 register int i; 312 u_int16_t word = 0; 313 314 /* Force EEPROM to idle state. */ 315 sis_eeprom_idle(sc); 316 317 /* Enter EEPROM access mode. */ 318 sis_delay(sc); 319 SIO_CLR(SIS_EECTL_CLK); 320 sis_delay(sc); 321 SIO_SET(SIS_EECTL_CSEL); 322 sis_delay(sc); 323 324 /* 325 * Send address of word we want to read. 326 */ 327 sis_eeprom_putbyte(sc, addr); 328 329 /* 330 * Start reading bits from EEPROM. 331 */ 332 for (i = 0x8000; i; i >>= 1) { 333 SIO_SET(SIS_EECTL_CLK); 334 sis_delay(sc); 335 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 336 word |= i; 337 sis_delay(sc); 338 SIO_CLR(SIS_EECTL_CLK); 339 sis_delay(sc); 340 } 341 342 /* Turn off EEPROM access mode. */ 343 sis_eeprom_idle(sc); 344 345 *dest = word; 346 347 return; 348 } 349 350 /* 351 * Read a sequence of words from the EEPROM. 352 */ 353 static void sis_read_eeprom(sc, dest, off, cnt, swap) 354 struct sis_softc *sc; 355 caddr_t dest; 356 int off; 357 int cnt; 358 int swap; 359 { 360 int i; 361 u_int16_t word = 0, *ptr; 362 363 for (i = 0; i < cnt; i++) { 364 sis_eeprom_getword(sc, off + i, &word); 365 ptr = (u_int16_t *)(dest + (i * 2)); 366 if (swap) 367 *ptr = ntohs(word); 368 else 369 *ptr = word; 370 } 371 372 return; 373 } 374 375 #ifdef __i386__ 376 static device_t sis_find_bridge(dev) 377 device_t dev; 378 { 379 devclass_t pci_devclass; 380 device_t *pci_devices; 381 int pci_count = 0; 382 device_t *pci_children; 383 int pci_childcount = 0; 384 device_t *busp, *childp; 385 device_t child = NULL; 386 int i, j; 387 388 if ((pci_devclass = devclass_find("pci")) == NULL) 389 return(NULL); 390 391 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 392 393 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 394 pci_childcount = 0; 395 device_get_children(*busp, &pci_children, &pci_childcount); 396 for (j = 0, childp = pci_children; 397 j < pci_childcount; j++, childp++) { 398 if (pci_get_vendor(*childp) == SIS_VENDORID && 399 pci_get_device(*childp) == 0x0008) { 400 child = *childp; 401 goto done; 402 } 403 } 404 } 405 406 done: 407 free(pci_devices, M_TEMP); 408 free(pci_children, M_TEMP); 409 return(child); 410 } 411 412 static void sis_read_cmos(sc, dev, dest, off, cnt) 413 struct sis_softc *sc; 414 device_t dev; 415 caddr_t dest; 416 int off; 417 int cnt; 418 { 419 device_t bridge; 420 u_int8_t reg; 421 int i; 422 bus_space_tag_t btag; 423 424 bridge = sis_find_bridge(dev); 425 if (bridge == NULL) 426 return; 427 reg = pci_read_config(bridge, 0x48, 1); 428 pci_write_config(bridge, 0x48, reg|0x40, 1); 429 430 /* XXX */ 431 btag = I386_BUS_SPACE_IO; 432 433 for (i = 0; i < cnt; i++) { 434 bus_space_write_1(btag, 0x0, 0x70, i + off); 435 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 436 } 437 438 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 439 return; 440 } 441 442 static void sis_read_mac(sc, dev, dest) 443 struct sis_softc *sc; 444 device_t dev; 445 caddr_t dest; 446 { 447 u_int32_t filtsave, csrsave; 448 449 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 450 csrsave = CSR_READ_4(sc, SIS_CSR); 451 452 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 453 CSR_WRITE_4(sc, SIS_CSR, 0); 454 455 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 456 457 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 458 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 459 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 460 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 461 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 462 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 463 464 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 465 CSR_WRITE_4(sc, SIS_CSR, csrsave); 466 return; 467 } 468 #endif 469 470 /* 471 * Sync the PHYs by setting data bit and strobing the clock 32 times. 472 */ 473 static void sis_mii_sync(sc) 474 struct sis_softc *sc; 475 { 476 register int i; 477 478 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 479 480 for (i = 0; i < 32; i++) { 481 SIO_SET(SIS_MII_CLK); 482 DELAY(1); 483 SIO_CLR(SIS_MII_CLK); 484 DELAY(1); 485 } 486 487 return; 488 } 489 490 /* 491 * Clock a series of bits through the MII. 492 */ 493 static void sis_mii_send(sc, bits, cnt) 494 struct sis_softc *sc; 495 u_int32_t bits; 496 int cnt; 497 { 498 int i; 499 500 SIO_CLR(SIS_MII_CLK); 501 502 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 503 if (bits & i) { 504 SIO_SET(SIS_MII_DATA); 505 } else { 506 SIO_CLR(SIS_MII_DATA); 507 } 508 DELAY(1); 509 SIO_CLR(SIS_MII_CLK); 510 DELAY(1); 511 SIO_SET(SIS_MII_CLK); 512 } 513 } 514 515 /* 516 * Read an PHY register through the MII. 517 */ 518 static int sis_mii_readreg(sc, frame) 519 struct sis_softc *sc; 520 struct sis_mii_frame *frame; 521 522 { 523 int i, ack, s; 524 525 s = splimp(); 526 527 /* 528 * Set up frame for RX. 529 */ 530 frame->mii_stdelim = SIS_MII_STARTDELIM; 531 frame->mii_opcode = SIS_MII_READOP; 532 frame->mii_turnaround = 0; 533 frame->mii_data = 0; 534 535 /* 536 * Turn on data xmit. 537 */ 538 SIO_SET(SIS_MII_DIR); 539 540 sis_mii_sync(sc); 541 542 /* 543 * Send command/address info. 544 */ 545 sis_mii_send(sc, frame->mii_stdelim, 2); 546 sis_mii_send(sc, frame->mii_opcode, 2); 547 sis_mii_send(sc, frame->mii_phyaddr, 5); 548 sis_mii_send(sc, frame->mii_regaddr, 5); 549 550 /* Idle bit */ 551 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 552 DELAY(1); 553 SIO_SET(SIS_MII_CLK); 554 DELAY(1); 555 556 /* Turn off xmit. */ 557 SIO_CLR(SIS_MII_DIR); 558 559 /* Check for ack */ 560 SIO_CLR(SIS_MII_CLK); 561 DELAY(1); 562 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 563 SIO_SET(SIS_MII_CLK); 564 DELAY(1); 565 566 /* 567 * Now try reading data bits. If the ack failed, we still 568 * need to clock through 16 cycles to keep the PHY(s) in sync. 569 */ 570 if (ack) { 571 for(i = 0; i < 16; i++) { 572 SIO_CLR(SIS_MII_CLK); 573 DELAY(1); 574 SIO_SET(SIS_MII_CLK); 575 DELAY(1); 576 } 577 goto fail; 578 } 579 580 for (i = 0x8000; i; i >>= 1) { 581 SIO_CLR(SIS_MII_CLK); 582 DELAY(1); 583 if (!ack) { 584 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 585 frame->mii_data |= i; 586 DELAY(1); 587 } 588 SIO_SET(SIS_MII_CLK); 589 DELAY(1); 590 } 591 592 fail: 593 594 SIO_CLR(SIS_MII_CLK); 595 DELAY(1); 596 SIO_SET(SIS_MII_CLK); 597 DELAY(1); 598 599 splx(s); 600 601 if (ack) 602 return(1); 603 return(0); 604 } 605 606 /* 607 * Write to a PHY register through the MII. 608 */ 609 static int sis_mii_writereg(sc, frame) 610 struct sis_softc *sc; 611 struct sis_mii_frame *frame; 612 613 { 614 int s; 615 616 s = splimp(); 617 /* 618 * Set up frame for TX. 619 */ 620 621 frame->mii_stdelim = SIS_MII_STARTDELIM; 622 frame->mii_opcode = SIS_MII_WRITEOP; 623 frame->mii_turnaround = SIS_MII_TURNAROUND; 624 625 /* 626 * Turn on data output. 627 */ 628 SIO_SET(SIS_MII_DIR); 629 630 sis_mii_sync(sc); 631 632 sis_mii_send(sc, frame->mii_stdelim, 2); 633 sis_mii_send(sc, frame->mii_opcode, 2); 634 sis_mii_send(sc, frame->mii_phyaddr, 5); 635 sis_mii_send(sc, frame->mii_regaddr, 5); 636 sis_mii_send(sc, frame->mii_turnaround, 2); 637 sis_mii_send(sc, frame->mii_data, 16); 638 639 /* Idle bit. */ 640 SIO_SET(SIS_MII_CLK); 641 DELAY(1); 642 SIO_CLR(SIS_MII_CLK); 643 DELAY(1); 644 645 /* 646 * Turn off xmit. 647 */ 648 SIO_CLR(SIS_MII_DIR); 649 650 splx(s); 651 652 return(0); 653 } 654 655 static int sis_miibus_readreg(dev, phy, reg) 656 device_t dev; 657 int phy, reg; 658 { 659 struct sis_softc *sc; 660 int i, val = 0; 661 struct sis_mii_frame frame; 662 663 sc = device_get_softc(dev); 664 665 if (sc->sis_type == SIS_TYPE_83815) { 666 if (phy != 0) 667 return(0); 668 /* 669 * The NatSemi chip can take a while after 670 * a reset to come ready, during which the BMSR 671 * returns a value of 0. This is *never* supposed 672 * to happen: some of the BMSR bits are meant to 673 * be hardwired in the on position, and this can 674 * confuse the miibus code a bit during the probe 675 * and attach phase. So we make an effort to check 676 * for this condition and wait for it to clear. 677 */ 678 if (!CSR_READ_4(sc, NS_BMSR)) 679 DELAY(1000); 680 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 681 } 682 /* 683 * Chipsets < SIS_635 seem not to be able to read/write 684 * through mdio. Use the enhanced PHY access register 685 * again for them. 686 */ 687 if (sc->sis_type == SIS_TYPE_900 && 688 sc->sis_rev < SIS_REV_635) { 689 690 if (phy != 0) 691 return(0); 692 693 CSR_WRITE_4(sc, SIS_PHYCTL, 694 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 695 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 696 697 for (i = 0; i < SIS_TIMEOUT; i++) { 698 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 699 break; 700 } 701 702 if (i == SIS_TIMEOUT) { 703 printf("sis%d: PHY failed to come ready\n", 704 sc->sis_unit); 705 return(0); 706 } 707 708 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 709 710 if (val == 0xFFFF) 711 return(0); 712 713 return(val); 714 } else { 715 bzero((char *)&frame, sizeof(frame)); 716 frame.mii_phyaddr = phy; 717 frame.mii_regaddr = reg; 718 sis_mii_readreg(sc, &frame); 719 return(frame.mii_data); 720 } 721 } 722 723 static int sis_miibus_writereg(dev, phy, reg, data) 724 device_t dev; 725 int phy, reg, data; 726 { 727 struct sis_softc *sc; 728 int i; 729 struct sis_mii_frame frame; 730 731 sc = device_get_softc(dev); 732 733 if (sc->sis_type == SIS_TYPE_83815) { 734 if (phy != 0) 735 return(0); 736 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 737 return(0); 738 } 739 740 if (sc->sis_type == SIS_TYPE_900 && 741 sc->sis_rev < SIS_REV_635) { 742 743 if (phy != 0) 744 return(0); 745 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 746 (reg << 6) | SIS_PHYOP_WRITE); 747 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 748 749 for (i = 0; i < SIS_TIMEOUT; i++) { 750 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 751 break; 752 } 753 754 if (i == SIS_TIMEOUT) 755 printf("sis%d: PHY failed to come ready\n", 756 sc->sis_unit); 757 } else { 758 bzero((char *)&frame, sizeof(frame)); 759 760 frame.mii_phyaddr = phy; 761 frame.mii_regaddr = reg; 762 frame.mii_data = data; 763 sis_mii_writereg(sc, &frame); 764 } 765 return(0); 766 } 767 768 static void sis_miibus_statchg(dev) 769 device_t dev; 770 { 771 struct sis_softc *sc; 772 773 sc = device_get_softc(dev); 774 sis_init(sc); 775 776 return; 777 } 778 779 static u_int32_t sis_crc(sc, addr) 780 struct sis_softc *sc; 781 caddr_t addr; 782 { 783 u_int32_t crc, carry; 784 int i, j; 785 u_int8_t c; 786 787 /* Compute CRC for the address value. */ 788 crc = 0xFFFFFFFF; /* initial value */ 789 790 for (i = 0; i < 6; i++) { 791 c = *(addr + i); 792 for (j = 0; j < 8; j++) { 793 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 794 crc <<= 1; 795 c >>= 1; 796 if (carry) 797 crc = (crc ^ 0x04c11db6) | carry; 798 } 799 } 800 801 /* 802 * return the filter bit position 803 * 804 * The NatSemi chip has a 512-bit filter, which is 805 * different than the SiS, so we special-case it. 806 */ 807 if (sc->sis_type == SIS_TYPE_83815) 808 return (crc >> 23); 809 else if (sc->sis_rev >= SIS_REV_635 || 810 sc->sis_rev == SIS_REV_900B) 811 return (crc >> 24); 812 else 813 return (crc >> 25); 814 } 815 816 static void sis_setmulti_ns(sc) 817 struct sis_softc *sc; 818 { 819 struct ifnet *ifp; 820 struct ifmultiaddr *ifma; 821 u_int32_t h = 0, i, filtsave; 822 int bit, index; 823 824 ifp = &sc->arpcom.ac_if; 825 826 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 827 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 828 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 829 return; 830 } 831 832 /* 833 * We have to explicitly enable the multicast hash table 834 * on the NatSemi chip if we want to use it, which we do. 835 */ 836 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 837 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 838 839 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 840 841 /* first, zot all the existing hash bits */ 842 for (i = 0; i < 32; i++) { 843 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 844 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 845 } 846 847 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 848 ifma = ifma->ifma_link.le_next) { 849 if (ifma->ifma_addr->sa_family != AF_LINK) 850 continue; 851 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 852 index = h >> 3; 853 bit = h & 0x1F; 854 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 855 if (bit > 0xF) 856 bit -= 0x10; 857 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 858 } 859 860 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 861 862 return; 863 } 864 865 static void sis_setmulti_sis(sc) 866 struct sis_softc *sc; 867 { 868 struct ifnet *ifp; 869 struct ifmultiaddr *ifma; 870 u_int32_t h, i, n, ctl; 871 u_int16_t hashes[16]; 872 873 ifp = &sc->arpcom.ac_if; 874 875 /* hash table size */ 876 if (sc->sis_rev >= SIS_REV_635 || 877 sc->sis_rev == SIS_REV_900B) 878 n = 16; 879 else 880 n = 8; 881 882 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 883 884 if (ifp->if_flags & IFF_BROADCAST) 885 ctl |= SIS_RXFILTCTL_BROAD; 886 887 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 888 ctl |= SIS_RXFILTCTL_ALLMULTI; 889 if (ifp->if_flags & IFF_PROMISC) 890 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 891 for (i = 0; i < n; i++) 892 hashes[i] = ~0; 893 } else { 894 for (i = 0; i < n; i++) 895 hashes[i] = 0; 896 i = 0; 897 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 898 if (ifma->ifma_addr->sa_family != AF_LINK) 899 continue; 900 h = sis_crc(sc, 901 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 902 hashes[h >> 4] |= 1 << (h & 0xf); 903 i++; 904 } 905 if (i > n) { 906 ctl |= SIS_RXFILTCTL_ALLMULTI; 907 for (i = 0; i < n; i++) 908 hashes[i] = ~0; 909 } 910 } 911 912 for (i = 0; i < n; i++) { 913 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 914 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 915 } 916 917 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 918 } 919 920 static void sis_reset(sc) 921 struct sis_softc *sc; 922 { 923 register int i; 924 925 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 926 927 for (i = 0; i < SIS_TIMEOUT; i++) { 928 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 929 break; 930 } 931 932 if (i == SIS_TIMEOUT) 933 printf("sis%d: reset never completed\n", sc->sis_unit); 934 935 /* Wait a little while for the chip to get its brains in order. */ 936 DELAY(1000); 937 938 /* 939 * If this is a NetSemi chip, make sure to clear 940 * PME mode. 941 */ 942 if (sc->sis_type == SIS_TYPE_83815) { 943 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 944 CSR_WRITE_4(sc, NS_CLKRUN, 0); 945 } 946 947 return; 948 } 949 950 /* 951 * Probe for an SiS chip. Check the PCI vendor and device 952 * IDs against our list and return a device name if we find a match. 953 */ 954 static int sis_probe(dev) 955 device_t dev; 956 { 957 struct sis_type *t; 958 959 t = sis_devs; 960 961 while(t->sis_name != NULL) { 962 if ((pci_get_vendor(dev) == t->sis_vid) && 963 (pci_get_device(dev) == t->sis_did)) { 964 device_set_desc(dev, t->sis_name); 965 return(0); 966 } 967 t++; 968 } 969 970 return(ENXIO); 971 } 972 973 /* 974 * Attach the interface. Allocate softc structures, do ifmedia 975 * setup and ethernet/BPF attach. 976 */ 977 static int sis_attach(dev) 978 device_t dev; 979 { 980 int s; 981 u_char eaddr[ETHER_ADDR_LEN]; 982 u_int32_t command; 983 struct sis_softc *sc; 984 struct ifnet *ifp; 985 int unit, error, rid, waittime; 986 987 s = splimp(); 988 989 error = waittime = 0; 990 sc = device_get_softc(dev); 991 unit = device_get_unit(dev); 992 bzero(sc, sizeof(struct sis_softc)); 993 994 if (pci_get_device(dev) == SIS_DEVICEID_900) 995 sc->sis_type = SIS_TYPE_900; 996 if (pci_get_device(dev) == SIS_DEVICEID_7016) 997 sc->sis_type = SIS_TYPE_7016; 998 if (pci_get_vendor(dev) == NS_VENDORID) 999 sc->sis_type = SIS_TYPE_83815; 1000 1001 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1002 1003 /* 1004 * Handle power management nonsense. 1005 */ 1006 1007 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 1008 if (command == 0x01) { 1009 1010 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 1011 if (command & SIS_PSTATE_MASK) { 1012 u_int32_t iobase, membase, irq; 1013 1014 /* Save important PCI config data. */ 1015 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 1016 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 1017 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 1018 1019 /* Reset the power state. */ 1020 printf("sis%d: chip is in D%d power mode " 1021 "-- setting to D0\n", unit, command & SIS_PSTATE_MASK); 1022 command &= 0xFFFFFFFC; 1023 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 1024 1025 /* Restore PCI config data. */ 1026 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 1027 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 1028 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 1029 } 1030 } 1031 1032 /* 1033 * Map control/status registers. 1034 */ 1035 command = pci_read_config(dev, PCIR_COMMAND, 4); 1036 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1037 pci_write_config(dev, PCIR_COMMAND, command, 4); 1038 command = pci_read_config(dev, PCIR_COMMAND, 4); 1039 1040 #ifdef SIS_USEIOSPACE 1041 if (!(command & PCIM_CMD_PORTEN)) { 1042 printf("sis%d: failed to enable I/O ports!\n", unit); 1043 error = ENXIO;; 1044 goto fail; 1045 } 1046 #else 1047 if (!(command & PCIM_CMD_MEMEN)) { 1048 printf("sis%d: failed to enable memory mapping!\n", unit); 1049 error = ENXIO;; 1050 goto fail; 1051 } 1052 #endif 1053 1054 rid = SIS_RID; 1055 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 1056 0, ~0, 1, RF_ACTIVE); 1057 1058 if (sc->sis_res == NULL) { 1059 printf("sis%d: couldn't map ports/memory\n", unit); 1060 error = ENXIO; 1061 goto fail; 1062 } 1063 1064 sc->sis_btag = rman_get_bustag(sc->sis_res); 1065 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1066 1067 /* Allocate interrupt */ 1068 rid = 0; 1069 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1070 RF_SHAREABLE | RF_ACTIVE); 1071 1072 if (sc->sis_irq == NULL) { 1073 printf("sis%d: couldn't map interrupt\n", unit); 1074 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1075 error = ENXIO; 1076 goto fail; 1077 } 1078 1079 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 1080 sis_intr, sc, &sc->sis_intrhand); 1081 1082 if (error) { 1083 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1084 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1085 printf("sis%d: couldn't set up irq\n", unit); 1086 goto fail; 1087 } 1088 1089 /* Reset the adapter. */ 1090 sis_reset(sc); 1091 1092 if (sc->sis_type == SIS_TYPE_900 && 1093 (sc->sis_rev == SIS_REV_635 || 1094 sc->sis_rev == SIS_REV_900B)) { 1095 SIO_SET(SIS_CFG_RND_CNT); 1096 SIO_SET(SIS_CFG_PERR_DETECT); 1097 } 1098 1099 /* 1100 * Get station address from the EEPROM. 1101 */ 1102 switch (pci_get_vendor(dev)) { 1103 case NS_VENDORID: 1104 /* 1105 * Reading the MAC address out of the EEPROM on 1106 * the NatSemi chip takes a bit more work than 1107 * you'd expect. The address spans 4 16-bit words, 1108 * with the first word containing only a single bit. 1109 * You have to shift everything over one bit to 1110 * get it aligned properly. Also, the bits are 1111 * stored backwards (the LSB is really the MSB, 1112 * and so on) so you have to reverse them in order 1113 * to get the MAC address into the form we want. 1114 * Why? Who the hell knows. 1115 */ 1116 { 1117 u_int16_t tmp[4]; 1118 1119 sis_read_eeprom(sc, (caddr_t)&tmp, 1120 NS_EE_NODEADDR, 4, 0); 1121 1122 /* Shift everything over one bit. */ 1123 tmp[3] = tmp[3] >> 1; 1124 tmp[3] |= tmp[2] << 15; 1125 tmp[2] = tmp[2] >> 1; 1126 tmp[2] |= tmp[1] << 15; 1127 tmp[1] = tmp[1] >> 1; 1128 tmp[1] |= tmp[0] << 15; 1129 1130 /* Now reverse all the bits. */ 1131 tmp[3] = sis_reverse(tmp[3]); 1132 tmp[2] = sis_reverse(tmp[2]); 1133 tmp[1] = sis_reverse(tmp[1]); 1134 1135 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1136 } 1137 break; 1138 case SIS_VENDORID: 1139 default: 1140 #ifdef __i386__ 1141 /* 1142 * If this is a SiS 630E chipset with an embedded 1143 * SiS 900 controller, we have to read the MAC address 1144 * from the APC CMOS RAM. Our method for doing this 1145 * is very ugly since we have to reach out and grab 1146 * ahold of hardware for which we cannot properly 1147 * allocate resources. This code is only compiled on 1148 * the i386 architecture since the SiS 630E chipset 1149 * is for x86 motherboards only. Note that there are 1150 * a lot of magic numbers in this hack. These are 1151 * taken from SiS's Linux driver. I'd like to replace 1152 * them with proper symbolic definitions, but that 1153 * requires some datasheets that I don't have access 1154 * to at the moment. 1155 */ 1156 if (sc->sis_rev == SIS_REV_630S || 1157 sc->sis_rev == SIS_REV_630E || 1158 sc->sis_rev == SIS_REV_630EA1) 1159 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1160 1161 else if (sc->sis_rev == SIS_REV_635 || 1162 sc->sis_rev == SIS_REV_630ET) 1163 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1164 else if (sc->sis_rev == SIS_REV_96x) { 1165 /* 1166 * Allow to read EEPROM from LAN. It is shared 1167 * between a 1394 controller and the NIC and each 1168 * time we access it, we need to set SIS_EECMD_REQ. 1169 */ 1170 SIO_SET(SIS_EECMD_REQ); 1171 for (waittime = 0; waittime < SIS_TIMEOUT; 1172 waittime++) { 1173 /* Force EEPROM to idle state. */ 1174 sis_eeprom_idle(sc); 1175 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1176 sis_read_eeprom(sc, (caddr_t)&eaddr, 1177 SIS_EE_NODEADDR, 3, 0); 1178 break; 1179 } 1180 DELAY(1); 1181 } 1182 /* 1183 * Set SIS_EECTL_CLK to high, so a other master 1184 * can operate on the i2c bus. 1185 */ 1186 SIO_SET(SIS_EECTL_CLK); 1187 /* Refuse EEPROM access by LAN */ 1188 SIO_SET(SIS_EECMD_DONE); 1189 } else 1190 #endif 1191 sis_read_eeprom(sc, (caddr_t)&eaddr, 1192 SIS_EE_NODEADDR, 3, 0); 1193 break; 1194 } 1195 1196 /* 1197 * A SiS chip was detected. Inform the world. 1198 */ 1199 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1200 1201 sc->sis_unit = unit; 1202 callout_handle_init(&sc->sis_stat_ch); 1203 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1204 1205 sc->sis_ldata = contigmalloc(sizeof(struct sis_list_data), M_DEVBUF, 1206 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1207 1208 if (sc->sis_ldata == NULL) { 1209 printf("sis%d: no memory for list buffers!\n", unit); 1210 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1211 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1212 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1213 error = ENXIO; 1214 goto fail; 1215 } 1216 bzero(sc->sis_ldata, sizeof(struct sis_list_data)); 1217 1218 ifp = &sc->arpcom.ac_if; 1219 ifp->if_softc = sc; 1220 ifp->if_unit = unit; 1221 ifp->if_name = "sis"; 1222 ifp->if_mtu = ETHERMTU; 1223 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1224 ifp->if_ioctl = sis_ioctl; 1225 ifp->if_output = ether_output; 1226 ifp->if_start = sis_start; 1227 ifp->if_watchdog = sis_watchdog; 1228 ifp->if_init = sis_init; 1229 ifp->if_baudrate = 10000000; 1230 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1231 1232 /* 1233 * Do MII setup. 1234 */ 1235 if (mii_phy_probe(dev, &sc->sis_miibus, 1236 sis_ifmedia_upd, sis_ifmedia_sts)) { 1237 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1238 contigfree(sc->sis_ldata, sizeof(struct sis_list_data), 1239 M_DEVBUF); 1240 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1241 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1242 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1243 error = ENXIO; 1244 goto fail; 1245 } 1246 1247 /* 1248 * Call MI attach routine. 1249 */ 1250 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1251 1252 /* 1253 * Tell the upper layer(s) we support long frames. 1254 */ 1255 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1256 1257 callout_handle_init(&sc->sis_stat_ch); 1258 1259 fail: 1260 splx(s); 1261 return(error); 1262 } 1263 1264 static int sis_detach(dev) 1265 device_t dev; 1266 { 1267 struct sis_softc *sc; 1268 struct ifnet *ifp; 1269 int s; 1270 1271 s = splimp(); 1272 1273 sc = device_get_softc(dev); 1274 ifp = &sc->arpcom.ac_if; 1275 1276 sis_reset(sc); 1277 sis_stop(sc); 1278 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1279 1280 bus_generic_detach(dev); 1281 device_delete_child(dev, sc->sis_miibus); 1282 1283 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1284 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1285 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1286 1287 contigfree(sc->sis_ldata, sizeof(struct sis_list_data), M_DEVBUF); 1288 1289 splx(s); 1290 1291 return(0); 1292 } 1293 1294 /* 1295 * Initialize the transmit descriptors. 1296 */ 1297 static int sis_list_tx_init(sc) 1298 struct sis_softc *sc; 1299 { 1300 struct sis_list_data *ld; 1301 struct sis_ring_data *cd; 1302 int i, nexti; 1303 1304 cd = &sc->sis_cdata; 1305 ld = sc->sis_ldata; 1306 1307 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1308 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1309 ld->sis_tx_list[i].sis_nextdesc = 1310 &ld->sis_tx_list[nexti]; 1311 ld->sis_tx_list[i].sis_next = 1312 vtophys(&ld->sis_tx_list[nexti]); 1313 ld->sis_tx_list[i].sis_mbuf = NULL; 1314 ld->sis_tx_list[i].sis_ptr = 0; 1315 ld->sis_tx_list[i].sis_ctl = 0; 1316 } 1317 1318 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1319 1320 return(0); 1321 } 1322 1323 1324 /* 1325 * Initialize the RX descriptors and allocate mbufs for them. Note that 1326 * we arrange the descriptors in a closed ring, so that the last descriptor 1327 * points back to the first. 1328 */ 1329 static int sis_list_rx_init(sc) 1330 struct sis_softc *sc; 1331 { 1332 struct sis_list_data *ld; 1333 struct sis_ring_data *cd; 1334 int i, nexti; 1335 1336 ld = sc->sis_ldata; 1337 cd = &sc->sis_cdata; 1338 1339 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1340 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1341 return(ENOBUFS); 1342 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1343 ld->sis_rx_list[i].sis_nextdesc = 1344 &ld->sis_rx_list[nexti]; 1345 ld->sis_rx_list[i].sis_next = 1346 vtophys(&ld->sis_rx_list[nexti]); 1347 } 1348 1349 cd->sis_rx_prod = 0; 1350 1351 return(0); 1352 } 1353 1354 /* 1355 * Initialize an RX descriptor and attach an MBUF cluster. 1356 */ 1357 static int sis_newbuf(sc, c, m) 1358 struct sis_softc *sc; 1359 struct sis_desc *c; 1360 struct mbuf *m; 1361 { 1362 1363 if (m == NULL) { 1364 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1365 if (m == NULL) 1366 return(ENOBUFS); 1367 } else { 1368 m->m_data = m->m_ext.ext_buf; 1369 } 1370 1371 c->sis_mbuf = m; 1372 c->sis_ptr = vtophys(mtod(m, caddr_t)); 1373 c->sis_ctl = SIS_RXLEN; 1374 1375 return(0); 1376 } 1377 1378 /* 1379 * A frame has been uploaded: pass the resulting mbuf chain up to 1380 * the higher level protocols. 1381 */ 1382 static void sis_rxeof(sc) 1383 struct sis_softc *sc; 1384 { 1385 struct mbuf *m; 1386 struct ifnet *ifp; 1387 struct sis_desc *cur_rx; 1388 int i, total_len = 0; 1389 u_int32_t rxstat; 1390 1391 ifp = &sc->arpcom.ac_if; 1392 i = sc->sis_cdata.sis_rx_prod; 1393 1394 while(SIS_OWNDESC(&sc->sis_ldata->sis_rx_list[i])) { 1395 1396 #ifdef DEVICE_POLLING 1397 if (ifp->if_ipending & IFF_POLLING) { 1398 if (sc->rxcycles <= 0) 1399 break; 1400 sc->rxcycles--; 1401 } 1402 #endif /* DEVICE_POLLING */ 1403 cur_rx = &sc->sis_ldata->sis_rx_list[i]; 1404 rxstat = cur_rx->sis_rxstat; 1405 m = cur_rx->sis_mbuf; 1406 cur_rx->sis_mbuf = NULL; 1407 total_len = SIS_RXBYTES(cur_rx); 1408 SIS_INC(i, SIS_RX_LIST_CNT); 1409 1410 /* 1411 * If an error occurs, update stats, clear the 1412 * status word and leave the mbuf cluster in place: 1413 * it should simply get re-used next time this descriptor 1414 * comes up in the ring. 1415 */ 1416 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1417 ifp->if_ierrors++; 1418 if (rxstat & SIS_RXSTAT_COLL) 1419 ifp->if_collisions++; 1420 sis_newbuf(sc, cur_rx, m); 1421 continue; 1422 } 1423 1424 /* No errors; receive the packet. */ 1425 #ifdef __i386__ 1426 /* 1427 * On the x86 we do not have alignment problems, so try to 1428 * allocate a new buffer for the receive ring, and pass up 1429 * the one where the packet is already, saving the expensive 1430 * copy done in m_devget(). 1431 * If we are on an architecture with alignment problems, or 1432 * if the allocation fails, then use m_devget and leave the 1433 * existing buffer in the receive ring. 1434 */ 1435 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1436 m->m_pkthdr.len = m->m_len = total_len; 1437 else 1438 #endif 1439 { 1440 struct mbuf *m0; 1441 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1442 total_len + ETHER_ALIGN, 0, ifp, NULL); 1443 sis_newbuf(sc, cur_rx, m); 1444 if (m0 == NULL) { 1445 ifp->if_ierrors++; 1446 continue; 1447 } 1448 m_adj(m0, ETHER_ALIGN); 1449 m = m0; 1450 } 1451 1452 ifp->if_ipackets++; 1453 ether_input(ifp, NULL, m); 1454 } 1455 1456 sc->sis_cdata.sis_rx_prod = i; 1457 1458 return; 1459 } 1460 1461 void sis_rxeoc(sc) 1462 struct sis_softc *sc; 1463 { 1464 sis_rxeof(sc); 1465 /* sis_init(sc); */ 1466 return; 1467 } 1468 1469 /* 1470 * A frame was downloaded to the chip. It's safe for us to clean up 1471 * the list buffers. 1472 */ 1473 1474 static void sis_txeof(sc) 1475 struct sis_softc *sc; 1476 { 1477 struct sis_desc *cur_tx = NULL; 1478 struct ifnet *ifp; 1479 u_int32_t idx; 1480 1481 ifp = &sc->arpcom.ac_if; 1482 1483 /* 1484 * Go through our tx list and free mbufs for those 1485 * frames that have been transmitted. 1486 */ 1487 idx = sc->sis_cdata.sis_tx_cons; 1488 while (idx != sc->sis_cdata.sis_tx_prod) { 1489 cur_tx = &sc->sis_ldata->sis_tx_list[idx]; 1490 1491 if (SIS_OWNDESC(cur_tx)) 1492 break; 1493 1494 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) { 1495 sc->sis_cdata.sis_tx_cnt--; 1496 SIS_INC(idx, SIS_TX_LIST_CNT); 1497 continue; 1498 } 1499 1500 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1501 ifp->if_oerrors++; 1502 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1503 ifp->if_collisions++; 1504 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1505 ifp->if_collisions++; 1506 } 1507 1508 ifp->if_collisions += 1509 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1510 1511 ifp->if_opackets++; 1512 if (cur_tx->sis_mbuf != NULL) { 1513 m_freem(cur_tx->sis_mbuf); 1514 cur_tx->sis_mbuf = NULL; 1515 } 1516 1517 sc->sis_cdata.sis_tx_cnt--; 1518 SIS_INC(idx, SIS_TX_LIST_CNT); 1519 ifp->if_timer = 0; 1520 } 1521 1522 if (idx != sc->sis_cdata.sis_tx_cons) { 1523 sc->sis_cdata.sis_tx_cons = idx; 1524 ifp->if_flags &= ~IFF_OACTIVE; 1525 } 1526 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1527 return; 1528 } 1529 1530 static void sis_tick(xsc) 1531 void *xsc; 1532 { 1533 struct sis_softc *sc; 1534 struct mii_data *mii; 1535 struct ifnet *ifp; 1536 int s; 1537 1538 s = splimp(); 1539 1540 sc = xsc; 1541 ifp = &sc->arpcom.ac_if; 1542 1543 mii = device_get_softc(sc->sis_miibus); 1544 mii_tick(mii); 1545 1546 if (!sc->sis_link) { 1547 mii_pollstat(mii); 1548 if (mii->mii_media_status & IFM_ACTIVE && 1549 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1550 sc->sis_link++; 1551 if (ifp->if_snd.ifq_head != NULL) 1552 sis_start(ifp); 1553 } 1554 1555 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1556 1557 splx(s); 1558 1559 return; 1560 } 1561 1562 #ifdef DEVICE_POLLING 1563 static poll_handler_t sis_poll; 1564 1565 static void 1566 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1567 { 1568 struct sis_softc *sc = ifp->if_softc; 1569 1570 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1571 CSR_WRITE_4(sc, SIS_IER, 1); 1572 return; 1573 } 1574 1575 /* 1576 * On the sis, reading the status register also clears it. 1577 * So before returning to intr mode we must make sure that all 1578 * possible pending sources of interrupts have been served. 1579 * In practice this means run to completion the *eof routines, 1580 * and then call the interrupt routine 1581 */ 1582 sc->rxcycles = count; 1583 sis_rxeof(sc); 1584 sis_txeof(sc); 1585 if (ifp->if_snd.ifq_head != NULL) 1586 sis_start(ifp); 1587 1588 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1589 u_int32_t status; 1590 1591 /* Reading the ISR register clears all interrupts. */ 1592 status = CSR_READ_4(sc, SIS_ISR); 1593 1594 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1595 sis_rxeoc(sc); 1596 1597 if (status & (SIS_ISR_RX_IDLE)) 1598 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1599 1600 if (status & SIS_ISR_SYSERR) { 1601 sis_reset(sc); 1602 sis_init(sc); 1603 } 1604 } 1605 } 1606 #endif /* DEVICE_POLLING */ 1607 1608 static void sis_intr(arg) 1609 void *arg; 1610 { 1611 struct sis_softc *sc; 1612 struct ifnet *ifp; 1613 u_int32_t status; 1614 1615 sc = arg; 1616 ifp = &sc->arpcom.ac_if; 1617 1618 #ifdef DEVICE_POLLING 1619 if (ifp->if_ipending & IFF_POLLING) 1620 return; 1621 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1622 CSR_WRITE_4(sc, SIS_IER, 0); 1623 sis_poll(ifp, 0, 1); 1624 return; 1625 } 1626 #endif /* DEVICE_POLLING */ 1627 1628 /* Supress unwanted interrupts */ 1629 if (!(ifp->if_flags & IFF_UP)) { 1630 sis_stop(sc); 1631 return; 1632 } 1633 1634 /* Disable interrupts. */ 1635 CSR_WRITE_4(sc, SIS_IER, 0); 1636 1637 for (;;) { 1638 /* Reading the ISR register clears all interrupts. */ 1639 status = CSR_READ_4(sc, SIS_ISR); 1640 1641 if ((status & SIS_INTRS) == 0) 1642 break; 1643 1644 if (status & 1645 (SIS_ISR_TX_DESC_OK|SIS_ISR_TX_ERR| 1646 SIS_ISR_TX_OK|SIS_ISR_TX_IDLE) ) 1647 sis_txeof(sc); 1648 1649 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1650 sis_rxeof(sc); 1651 1652 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1653 sis_rxeoc(sc); 1654 1655 if (status & (SIS_ISR_RX_IDLE)) 1656 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1657 1658 if (status & SIS_ISR_SYSERR) { 1659 sis_reset(sc); 1660 sis_init(sc); 1661 } 1662 } 1663 1664 /* Re-enable interrupts. */ 1665 CSR_WRITE_4(sc, SIS_IER, 1); 1666 1667 if (ifp->if_snd.ifq_head != NULL) 1668 sis_start(ifp); 1669 1670 return; 1671 } 1672 1673 /* 1674 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1675 * pointers to the fragment pointers. 1676 */ 1677 static int sis_encap(sc, m_head, txidx) 1678 struct sis_softc *sc; 1679 struct mbuf *m_head; 1680 u_int32_t *txidx; 1681 { 1682 struct sis_desc *f = NULL; 1683 struct mbuf *m; 1684 int frag, cur, cnt = 0; 1685 1686 /* 1687 * Start packing the mbufs in this chain into 1688 * the fragment pointers. Stop when we run out 1689 * of fragments or hit the end of the mbuf chain. 1690 */ 1691 m = m_head; 1692 cur = frag = *txidx; 1693 1694 for (m = m_head; m != NULL; m = m->m_next) { 1695 if (m->m_len != 0) { 1696 if ((SIS_TX_LIST_CNT - 1697 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1698 return(ENOBUFS); 1699 f = &sc->sis_ldata->sis_tx_list[frag]; 1700 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1701 f->sis_ptr = vtophys(mtod(m, vm_offset_t)); 1702 if (cnt != 0) 1703 f->sis_ctl |= SIS_CMDSTS_OWN; 1704 cur = frag; 1705 SIS_INC(frag, SIS_TX_LIST_CNT); 1706 cnt++; 1707 } 1708 } 1709 1710 if (m != NULL) 1711 return(ENOBUFS); 1712 1713 sc->sis_ldata->sis_tx_list[cur].sis_mbuf = m_head; 1714 sc->sis_ldata->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1715 sc->sis_ldata->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1716 sc->sis_cdata.sis_tx_cnt += cnt; 1717 *txidx = frag; 1718 1719 return(0); 1720 } 1721 1722 /* 1723 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1724 * to the mbuf data regions directly in the transmit lists. We also save a 1725 * copy of the pointers since the transmit list fragment pointers are 1726 * physical addresses. 1727 */ 1728 1729 static void sis_start(ifp) 1730 struct ifnet *ifp; 1731 { 1732 struct sis_softc *sc; 1733 struct mbuf *m_head = NULL; 1734 u_int32_t idx; 1735 1736 sc = ifp->if_softc; 1737 1738 if (!sc->sis_link) 1739 return; 1740 1741 idx = sc->sis_cdata.sis_tx_prod; 1742 1743 if (ifp->if_flags & IFF_OACTIVE) 1744 return; 1745 1746 while(sc->sis_ldata->sis_tx_list[idx].sis_mbuf == NULL) { 1747 IF_DEQUEUE(&ifp->if_snd, m_head); 1748 if (m_head == NULL) 1749 break; 1750 1751 if (sis_encap(sc, m_head, &idx)) { 1752 IF_PREPEND(&ifp->if_snd, m_head); 1753 ifp->if_flags |= IFF_OACTIVE; 1754 break; 1755 } 1756 1757 /* 1758 * If there's a BPF listener, bounce a copy of this frame 1759 * to him. 1760 */ 1761 if (ifp->if_bpf) 1762 bpf_mtap(ifp, m_head); 1763 1764 } 1765 1766 /* Transmit */ 1767 sc->sis_cdata.sis_tx_prod = idx; 1768 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1769 1770 /* 1771 * Set a timeout in case the chip goes out to lunch. 1772 */ 1773 ifp->if_timer = 5; 1774 1775 return; 1776 } 1777 1778 static void sis_init(xsc) 1779 void *xsc; 1780 { 1781 struct sis_softc *sc = xsc; 1782 struct ifnet *ifp = &sc->arpcom.ac_if; 1783 struct mii_data *mii; 1784 int s; 1785 1786 s = splimp(); 1787 1788 /* 1789 * Cancel pending I/O and free all RX/TX buffers. 1790 */ 1791 sis_stop(sc); 1792 1793 mii = device_get_softc(sc->sis_miibus); 1794 1795 /* Set MAC address */ 1796 if (sc->sis_type == SIS_TYPE_83815) { 1797 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1798 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1799 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1800 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1801 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1802 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1803 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1804 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1805 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1806 } else { 1807 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1808 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1809 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1810 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1811 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1812 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1813 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1814 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1815 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1816 } 1817 1818 /* Init circular RX list. */ 1819 if (sis_list_rx_init(sc) == ENOBUFS) { 1820 printf("sis%d: initialization failed: no " 1821 "memory for rx buffers\n", sc->sis_unit); 1822 sis_stop(sc); 1823 (void)splx(s); 1824 return; 1825 } 1826 1827 /* 1828 * Init tx descriptors. 1829 */ 1830 sis_list_tx_init(sc); 1831 1832 /* 1833 * For the NatSemi chip, we have to explicitly enable the 1834 * reception of ARP frames, as well as turn on the 'perfect 1835 * match' filter where we store the station address, otherwise 1836 * we won't receive unicasts meant for this host. 1837 */ 1838 if (sc->sis_type == SIS_TYPE_83815) { 1839 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1840 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1841 } 1842 1843 /* If we want promiscuous mode, set the allframes bit. */ 1844 if (ifp->if_flags & IFF_PROMISC) { 1845 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1846 } else { 1847 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1848 } 1849 1850 /* 1851 * Set the capture broadcast bit to capture broadcast frames. 1852 */ 1853 if (ifp->if_flags & IFF_BROADCAST) { 1854 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1855 } else { 1856 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1857 } 1858 1859 /* 1860 * Load the multicast filter. 1861 */ 1862 if (sc->sis_type == SIS_TYPE_83815) 1863 sis_setmulti_ns(sc); 1864 else 1865 sis_setmulti_sis(sc); 1866 1867 /* Turn the receive filter on */ 1868 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1869 1870 /* 1871 * Load the address of the RX and TX lists. 1872 */ 1873 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 1874 vtophys(&sc->sis_ldata->sis_rx_list[0])); 1875 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 1876 vtophys(&sc->sis_ldata->sis_tx_list[0])); 1877 1878 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1879 * the PCI bus. When this bit is set, the Max DMA Burst Size 1880 * for TX/RX DMA should be no larger than 16 double words. 1881 */ 1882 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 1883 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1884 } else { 1885 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1886 } 1887 1888 /* Accept Long Packets for VLAN support */ 1889 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1890 1891 /* Set TX configuration */ 1892 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 1893 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1894 } else { 1895 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1896 } 1897 1898 /* Set full/half duplex mode. */ 1899 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1900 SIS_SETBIT(sc, SIS_TX_CFG, 1901 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1902 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1903 } else { 1904 SIS_CLRBIT(sc, SIS_TX_CFG, 1905 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1906 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1907 } 1908 1909 /* 1910 * Enable interrupts. 1911 */ 1912 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1913 #ifdef DEVICE_POLLING 1914 /* 1915 * ... only enable interrupts if we are not polling, make sure 1916 * they are off otherwise. 1917 */ 1918 if (ifp->if_ipending & IFF_POLLING) 1919 CSR_WRITE_4(sc, SIS_IER, 0); 1920 else 1921 #endif /* DEVICE_POLLING */ 1922 CSR_WRITE_4(sc, SIS_IER, 1); 1923 1924 /* Enable receiver and transmitter. */ 1925 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1926 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1927 1928 #ifdef notdef 1929 mii_mediachg(mii); 1930 #endif 1931 1932 /* 1933 * Page 75 of the DP83815 manual recommends the 1934 * following register settings "for optimum 1935 * performance." Note however that at least three 1936 * of the registers are listed as "reserved" in 1937 * the register map, so who knows what they do. 1938 */ 1939 if (sc->sis_type == SIS_TYPE_83815) { 1940 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1941 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1942 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1943 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1944 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1945 } 1946 1947 ifp->if_flags |= IFF_RUNNING; 1948 ifp->if_flags &= ~IFF_OACTIVE; 1949 1950 (void)splx(s); 1951 1952 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1953 1954 return; 1955 } 1956 1957 /* 1958 * Set media options. 1959 */ 1960 static int sis_ifmedia_upd(ifp) 1961 struct ifnet *ifp; 1962 { 1963 struct sis_softc *sc; 1964 struct mii_data *mii; 1965 1966 sc = ifp->if_softc; 1967 1968 mii = device_get_softc(sc->sis_miibus); 1969 sc->sis_link = 0; 1970 if (mii->mii_instance) { 1971 struct mii_softc *miisc; 1972 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1973 miisc = LIST_NEXT(miisc, mii_list)) 1974 mii_phy_reset(miisc); 1975 } 1976 mii_mediachg(mii); 1977 1978 return(0); 1979 } 1980 1981 /* 1982 * Report current media status. 1983 */ 1984 static void sis_ifmedia_sts(ifp, ifmr) 1985 struct ifnet *ifp; 1986 struct ifmediareq *ifmr; 1987 { 1988 struct sis_softc *sc; 1989 struct mii_data *mii; 1990 1991 sc = ifp->if_softc; 1992 1993 mii = device_get_softc(sc->sis_miibus); 1994 mii_pollstat(mii); 1995 ifmr->ifm_active = mii->mii_media_active; 1996 ifmr->ifm_status = mii->mii_media_status; 1997 1998 return; 1999 } 2000 2001 static int sis_ioctl(ifp, command, data) 2002 struct ifnet *ifp; 2003 u_long command; 2004 caddr_t data; 2005 { 2006 struct sis_softc *sc = ifp->if_softc; 2007 struct ifreq *ifr = (struct ifreq *) data; 2008 struct mii_data *mii; 2009 int s, error = 0; 2010 2011 s = splimp(); 2012 2013 switch(command) { 2014 case SIOCSIFADDR: 2015 case SIOCGIFADDR: 2016 case SIOCSIFMTU: 2017 error = ether_ioctl(ifp, command, data); 2018 break; 2019 case SIOCSIFFLAGS: 2020 if (ifp->if_flags & IFF_UP) { 2021 sis_init(sc); 2022 } else { 2023 if (ifp->if_flags & IFF_RUNNING) 2024 sis_stop(sc); 2025 } 2026 error = 0; 2027 break; 2028 case SIOCADDMULTI: 2029 case SIOCDELMULTI: 2030 if (sc->sis_type == SIS_TYPE_83815) 2031 sis_setmulti_ns(sc); 2032 else 2033 sis_setmulti_sis(sc); 2034 error = 0; 2035 break; 2036 case SIOCGIFMEDIA: 2037 case SIOCSIFMEDIA: 2038 mii = device_get_softc(sc->sis_miibus); 2039 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2040 break; 2041 default: 2042 error = EINVAL; 2043 break; 2044 } 2045 2046 (void)splx(s); 2047 2048 return(error); 2049 } 2050 2051 static void sis_watchdog(ifp) 2052 struct ifnet *ifp; 2053 { 2054 struct sis_softc *sc; 2055 2056 sc = ifp->if_softc; 2057 2058 ifp->if_oerrors++; 2059 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2060 2061 sis_stop(sc); 2062 sis_reset(sc); 2063 sis_init(sc); 2064 2065 if (ifp->if_snd.ifq_head != NULL) 2066 sis_start(ifp); 2067 2068 return; 2069 } 2070 2071 /* 2072 * Stop the adapter and free any mbufs allocated to the 2073 * RX and TX lists. 2074 */ 2075 static void sis_stop(sc) 2076 struct sis_softc *sc; 2077 { 2078 register int i; 2079 struct ifnet *ifp; 2080 2081 ifp = &sc->arpcom.ac_if; 2082 ifp->if_timer = 0; 2083 2084 untimeout(sis_tick, sc, sc->sis_stat_ch); 2085 2086 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2087 #ifdef DEVICE_POLLING 2088 ether_poll_deregister(ifp); 2089 #endif 2090 CSR_WRITE_4(sc, SIS_IER, 0); 2091 CSR_WRITE_4(sc, SIS_IMR, 0); 2092 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2093 DELAY(1000); 2094 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2095 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2096 2097 sc->sis_link = 0; 2098 2099 /* 2100 * Free data in the RX lists. 2101 */ 2102 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2103 if (sc->sis_ldata->sis_rx_list[i].sis_mbuf != NULL) { 2104 m_freem(sc->sis_ldata->sis_rx_list[i].sis_mbuf); 2105 sc->sis_ldata->sis_rx_list[i].sis_mbuf = NULL; 2106 } 2107 } 2108 bzero((char *)&sc->sis_ldata->sis_rx_list, 2109 sizeof(sc->sis_ldata->sis_rx_list)); 2110 2111 /* 2112 * Free the TX list buffers. 2113 */ 2114 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2115 if (sc->sis_ldata->sis_tx_list[i].sis_mbuf != NULL) { 2116 m_freem(sc->sis_ldata->sis_tx_list[i].sis_mbuf); 2117 sc->sis_ldata->sis_tx_list[i].sis_mbuf = NULL; 2118 } 2119 } 2120 2121 bzero((char *)&sc->sis_ldata->sis_tx_list, 2122 sizeof(sc->sis_ldata->sis_tx_list)); 2123 2124 return; 2125 } 2126 2127 /* 2128 * Stop all chip I/O so that the kernel's probe routines don't 2129 * get confused by errant DMAs when rebooting. 2130 */ 2131 static void sis_shutdown(dev) 2132 device_t dev; 2133 { 2134 struct sis_softc *sc; 2135 2136 sc = device_get_softc(dev); 2137 2138 sis_reset(sc); 2139 sis_stop(sc); 2140 2141 return; 2142 } 2143