1 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $ 35 * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.36 2005/06/14 11:27:28 joerg Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 /* 55 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 56 * the SK-984x series adapters, both single port and dual port. 57 * References: 58 * The XaQti XMAC II datasheet, 59 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 60 * The SysKonnect GEnesis manual, http://www.syskonnect.com 61 * 62 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 63 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 64 * convenience to others until Vitesse corrects this problem: 65 * 66 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 67 * 68 * Written by Bill Paul <wpaul@ee.columbia.edu> 69 * Department of Electrical Engineering 70 * Columbia University, New York City 71 */ 72 73 /* 74 * The SysKonnect gigabit ethernet adapters consist of two main 75 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 76 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 77 * components and a PHY while the GEnesis controller provides a PCI 78 * interface with DMA support. Each card may have between 512K and 79 * 2MB of SRAM on board depending on the configuration. 80 * 81 * The SysKonnect GEnesis controller can have either one or two XMAC 82 * chips connected to it, allowing single or dual port NIC configurations. 83 * SysKonnect has the distinction of being the only vendor on the market 84 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 85 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 86 * XMAC registers. This driver takes advantage of these features to allow 87 * both XMACs to operate as independent interfaces. 88 */ 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/thread2.h> 98 #include <sys/queue.h> 99 100 #include <net/if.h> 101 #include <net/ifq_var.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 107 #include <net/bpf.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 #include <machine/bus.h> 112 #include <machine/resource.h> 113 #include <sys/bus.h> 114 #include <sys/rman.h> 115 116 #include <dev/netif/mii_layer/mii.h> 117 #include <dev/netif/mii_layer/miivar.h> 118 #include <dev/netif/mii_layer/brgphyreg.h> 119 120 #include <bus/pci/pcireg.h> 121 #include <bus/pci/pcivar.h> 122 123 #if 0 124 #define SK_USEIOSPACE 125 #endif 126 127 #include "if_skreg.h" 128 #include "xmaciireg.h" 129 #include "yukonreg.h" 130 131 /* "controller miibus0" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 static struct sk_type sk_devs[] = { 135 { VENDORID_SK, DEVICEID_SK_V1, 136 "SysKonnect Gigabit Ethernet (V1.0)" }, 137 { VENDORID_SK, DEVICEID_SK_V2, 138 "SysKonnect Gigabit Ethernet (V2.0)" }, 139 { VENDORID_MARVELL, DEVICEID_SK_V2, 140 "Marvell Gigabit Ethernet" }, 141 { VENDORID_3COM, DEVICEID_3COM_3C940, 142 "3Com 3C940 Gigabit Ethernet" }, 143 { VENDORID_LINKSYS, DEVICEID_LINKSYS_EG1032, 144 "Linksys EG1032 Gigabit Ethernet" }, 145 { VENDORID_DLINK, DEVICEID_DLINK_DGE530T, 146 "D-Link DGE-530T Gigabit Ethernet" }, 147 { 0, 0, NULL } 148 }; 149 150 static int skc_probe(device_t); 151 static int skc_attach(device_t); 152 static int skc_detach(device_t); 153 static void skc_shutdown(device_t); 154 static int sk_probe(device_t); 155 static int sk_attach(device_t); 156 static int sk_detach(device_t); 157 static void sk_tick(void *); 158 static void sk_intr(void *); 159 static void sk_intr_bcom(struct sk_if_softc *); 160 static void sk_intr_xmac(struct sk_if_softc *); 161 static void sk_intr_yukon(struct sk_if_softc *); 162 static void sk_rxeof(struct sk_if_softc *); 163 static void sk_txeof(struct sk_if_softc *); 164 static int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 165 static void sk_start(struct ifnet *); 166 static int sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 167 static void sk_init(void *); 168 static void sk_init_xmac(struct sk_if_softc *); 169 static void sk_init_yukon(struct sk_if_softc *); 170 static void sk_stop(struct sk_if_softc *); 171 static void sk_watchdog(struct ifnet *); 172 static int sk_ifmedia_upd(struct ifnet *); 173 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 174 static void sk_reset(struct sk_softc *); 175 static int sk_newbuf(struct sk_if_softc *, struct sk_chain *, 176 struct mbuf *); 177 static int sk_alloc_jumbo_mem(struct sk_if_softc *); 178 static struct sk_jslot 179 *sk_jalloc(struct sk_if_softc *); 180 static void sk_jfree(void *); 181 static void sk_jref(void *); 182 static int sk_init_rx_ring(struct sk_if_softc *); 183 static void sk_init_tx_ring(struct sk_if_softc *); 184 static uint32_t sk_win_read_4(struct sk_softc *, int); 185 static uint16_t sk_win_read_2(struct sk_softc *, int); 186 static uint8_t sk_win_read_1(struct sk_softc *, int); 187 static void sk_win_write_4(struct sk_softc *, int, uint32_t); 188 static void sk_win_write_2(struct sk_softc *, int, uint32_t); 189 static void sk_win_write_1(struct sk_softc *, int, uint32_t); 190 static uint8_t sk_vpd_readbyte(struct sk_softc *, int); 191 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int); 192 static void sk_vpd_read(struct sk_softc *); 193 194 static int sk_miibus_readreg(device_t, int, int); 195 static int sk_miibus_writereg(device_t, int, int, int); 196 static void sk_miibus_statchg(device_t); 197 198 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 199 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int); 200 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 201 202 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 203 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int); 204 static void sk_marv_miibus_statchg(struct sk_if_softc *); 205 206 static void sk_setfilt(struct sk_if_softc *, caddr_t, int); 207 static void sk_setmulti(struct sk_if_softc *); 208 static void sk_setpromisc(struct sk_if_softc *); 209 210 #ifdef SK_USEIOSPACE 211 #define SK_RES SYS_RES_IOPORT 212 #define SK_RID SK_PCI_LOIO 213 #else 214 #define SK_RES SYS_RES_MEMORY 215 #define SK_RID SK_PCI_LOMEM 216 #endif 217 218 /* 219 * Note that we have newbus methods for both the GEnesis controller 220 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 221 * the miibus code is a child of the XMACs. We need to do it this way 222 * so that the miibus drivers can access the PHY registers on the 223 * right PHY. It's not quite what I had in mind, but it's the only 224 * design that achieves the desired effect. 225 */ 226 static device_method_t skc_methods[] = { 227 /* Device interface */ 228 DEVMETHOD(device_probe, skc_probe), 229 DEVMETHOD(device_attach, skc_attach), 230 DEVMETHOD(device_detach, skc_detach), 231 DEVMETHOD(device_shutdown, skc_shutdown), 232 233 /* bus interface */ 234 DEVMETHOD(bus_print_child, bus_generic_print_child), 235 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 236 237 { 0, 0 } 238 }; 239 240 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc)); 241 static devclass_t skc_devclass; 242 243 static device_method_t sk_methods[] = { 244 /* Device interface */ 245 DEVMETHOD(device_probe, sk_probe), 246 DEVMETHOD(device_attach, sk_attach), 247 DEVMETHOD(device_detach, sk_detach), 248 DEVMETHOD(device_shutdown, bus_generic_shutdown), 249 250 /* bus interface */ 251 DEVMETHOD(bus_print_child, bus_generic_print_child), 252 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 253 254 /* MII interface */ 255 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 256 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 257 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 258 259 { 0, 0 } 260 }; 261 262 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc)); 263 static devclass_t sk_devclass; 264 265 DECLARE_DUMMY_MODULE(if_sk); 266 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0); 267 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0); 268 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 269 270 #define SK_SETBIT(sc, reg, x) \ 271 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 272 273 #define SK_CLRBIT(sc, reg, x) \ 274 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 275 276 #define SK_WIN_SETBIT_4(sc, reg, x) \ 277 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 278 279 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 280 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 281 282 #define SK_WIN_SETBIT_2(sc, reg, x) \ 283 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 284 285 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 286 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 287 288 static uint32_t 289 sk_win_read_4(struct sk_softc *sc, int reg) 290 { 291 #ifdef SK_USEIOSPACE 292 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 293 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 294 #else 295 return(CSR_READ_4(sc, reg)); 296 #endif 297 } 298 299 static uint16_t 300 sk_win_read_2(struct sk_softc *sc, int reg) 301 { 302 #ifdef SK_USEIOSPACE 303 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 304 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 305 #else 306 return(CSR_READ_2(sc, reg)); 307 #endif 308 } 309 310 static uint8_t 311 sk_win_read_1(struct sk_softc *sc, int reg) 312 { 313 #ifdef SK_USEIOSPACE 314 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 315 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 316 #else 317 return(CSR_READ_1(sc, reg)); 318 #endif 319 } 320 321 static void 322 sk_win_write_4(struct sk_softc *sc, int reg, uint32_t val) 323 { 324 #ifdef SK_USEIOSPACE 325 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 326 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 327 #else 328 CSR_WRITE_4(sc, reg, val); 329 #endif 330 } 331 332 static void 333 sk_win_write_2(struct sk_softc *sc, int reg, uint32_t val) 334 { 335 #ifdef SK_USEIOSPACE 336 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 337 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 338 #else 339 CSR_WRITE_2(sc, reg, val); 340 #endif 341 } 342 343 static void 344 sk_win_write_1(struct sk_softc *sc, int reg, uint32_t val) 345 { 346 #ifdef SK_USEIOSPACE 347 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 348 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 349 #else 350 CSR_WRITE_1(sc, reg, val); 351 #endif 352 } 353 354 /* 355 * The VPD EEPROM contains Vital Product Data, as suggested in 356 * the PCI 2.1 specification. The VPD data is separared into areas 357 * denoted by resource IDs. The SysKonnect VPD contains an ID string 358 * resource (the name of the adapter), a read-only area resource 359 * containing various key/data fields and a read/write area which 360 * can be used to store asset management information or log messages. 361 * We read the ID string and read-only into buffers attached to 362 * the controller softc structure for later use. At the moment, 363 * we only use the ID string during sk_attach(). 364 */ 365 static uint8_t 366 sk_vpd_readbyte(struct sk_softc *sc, int addr) 367 { 368 int i; 369 370 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 371 for (i = 0; i < SK_TIMEOUT; i++) { 372 DELAY(1); 373 if (sk_win_read_2(sc, 374 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 375 break; 376 } 377 378 if (i == SK_TIMEOUT) 379 return(0); 380 381 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 382 } 383 384 static void 385 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 386 { 387 int i; 388 uint8_t *ptr; 389 390 ptr = (uint8_t *)res; 391 for (i = 0; i < sizeof(struct vpd_res); i++) 392 ptr[i] = sk_vpd_readbyte(sc, i + addr); 393 } 394 395 static void 396 sk_vpd_read(struct sk_softc *sc) 397 { 398 struct vpd_res res; 399 int i, pos = 0; 400 401 if (sc->sk_vpd_prodname != NULL) 402 free(sc->sk_vpd_prodname, M_DEVBUF); 403 if (sc->sk_vpd_readonly != NULL) 404 free(sc->sk_vpd_readonly, M_DEVBUF); 405 sc->sk_vpd_prodname = NULL; 406 sc->sk_vpd_readonly = NULL; 407 408 sk_vpd_read_res(sc, &res, pos); 409 410 if (res.vr_id != VPD_RES_ID) { 411 printf("skc%d: bad VPD resource id: expected %x got %x\n", 412 sc->sk_unit, VPD_RES_ID, res.vr_id); 413 return; 414 } 415 416 pos += sizeof(res); 417 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT); 418 for (i = 0; i < res.vr_len; i++) 419 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 420 sc->sk_vpd_prodname[i] = '\0'; 421 pos += i; 422 423 sk_vpd_read_res(sc, &res, pos); 424 425 if (res.vr_id != VPD_RES_READ) { 426 printf("skc%d: bad VPD resource id: expected %x got %x\n", 427 sc->sk_unit, VPD_RES_READ, res.vr_id); 428 return; 429 } 430 431 pos += sizeof(res); 432 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT); 433 for (i = 0; i < res.vr_len + 1; i++) 434 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 435 } 436 437 static int 438 sk_miibus_readreg(device_t dev, int phy, int reg) 439 { 440 struct sk_if_softc *sc_if = device_get_softc(dev); 441 442 switch(sc_if->sk_softc->sk_type) { 443 case SK_GENESIS: 444 return(sk_xmac_miibus_readreg(sc_if, phy, reg)); 445 case SK_YUKON: 446 return(sk_marv_miibus_readreg(sc_if, phy, reg)); 447 } 448 449 return(0); 450 } 451 452 static int 453 sk_miibus_writereg(device_t dev, int phy, int reg, int val) 454 { 455 struct sk_if_softc *sc_if = device_get_softc(dev); 456 457 switch(sc_if->sk_softc->sk_type) { 458 case SK_GENESIS: 459 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val)); 460 case SK_YUKON: 461 return(sk_marv_miibus_writereg(sc_if, phy, reg, val)); 462 } 463 464 return(0); 465 } 466 467 static void 468 sk_miibus_statchg(device_t dev) 469 { 470 struct sk_if_softc *sc_if = device_get_softc(dev); 471 472 switch(sc_if->sk_softc->sk_type) { 473 case SK_GENESIS: 474 sk_xmac_miibus_statchg(sc_if); 475 break; 476 case SK_YUKON: 477 sk_marv_miibus_statchg(sc_if); 478 break; 479 } 480 } 481 482 static int 483 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 484 { 485 int i; 486 487 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 488 return(0); 489 490 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 491 SK_XM_READ_2(sc_if, XM_PHY_DATA); 492 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 493 for (i = 0; i < SK_TIMEOUT; i++) { 494 DELAY(1); 495 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 496 XM_MMUCMD_PHYDATARDY) 497 break; 498 } 499 500 if (i == SK_TIMEOUT) { 501 printf("sk%d: phy failed to come ready\n", 502 sc_if->sk_unit); 503 return(0); 504 } 505 } 506 DELAY(1); 507 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 508 } 509 510 static int 511 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 512 { 513 int i; 514 515 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 516 for (i = 0; i < SK_TIMEOUT; i++) { 517 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0) 518 break; 519 } 520 521 if (i == SK_TIMEOUT) { 522 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 523 return(ETIMEDOUT); 524 } 525 526 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 527 for (i = 0; i < SK_TIMEOUT; i++) { 528 DELAY(1); 529 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0) 530 break; 531 } 532 533 if (i == SK_TIMEOUT) 534 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 535 536 return(0); 537 } 538 539 static void 540 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if) 541 { 542 struct mii_data *mii; 543 544 mii = device_get_softc(sc_if->sk_miibus); 545 546 /* 547 * If this is a GMII PHY, manually set the XMAC's 548 * duplex mode accordingly. 549 */ 550 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 551 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 552 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 553 else 554 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 555 } 556 } 557 558 static int 559 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 560 { 561 uint16_t val; 562 int i; 563 564 if (phy != 0 || 565 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 566 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 567 return(0); 568 } 569 570 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 571 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 572 573 for (i = 0; i < SK_TIMEOUT; i++) { 574 DELAY(1); 575 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 576 if (val & YU_SMICR_READ_VALID) 577 break; 578 } 579 580 if (i == SK_TIMEOUT) { 581 printf("sk%d: phy failed to come ready\n", 582 sc_if->sk_unit); 583 return(0); 584 } 585 586 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 587 588 return(val); 589 } 590 591 static int 592 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 593 { 594 int i; 595 596 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 597 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 598 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 599 600 for (i = 0; i < SK_TIMEOUT; i++) { 601 DELAY(1); 602 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 603 break; 604 } 605 606 return(0); 607 } 608 609 static void 610 sk_marv_miibus_statchg(struct sk_if_softc *sc_if) 611 { 612 } 613 614 #define HASH_BITS 6 615 616 static void sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 617 { 618 int base; 619 620 base = XM_RXFILT_ENTRY(slot); 621 622 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 623 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 624 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 625 } 626 627 static void 628 sk_setmulti(struct sk_if_softc *sc_if) 629 { 630 struct sk_softc *sc = sc_if->sk_softc; 631 struct ifnet *ifp = &sc_if->arpcom.ac_if; 632 uint32_t hashes[2] = { 0, 0 }; 633 int h, i; 634 struct ifmultiaddr *ifma; 635 uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 636 637 /* First, zot all the existing filters. */ 638 switch(sc->sk_type) { 639 case SK_GENESIS: 640 for (i = 1; i < XM_RXFILT_MAX; i++) 641 sk_setfilt(sc_if, (caddr_t)&dummy, i); 642 643 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 644 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 645 break; 646 case SK_YUKON: 647 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 648 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 649 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 650 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 651 break; 652 } 653 654 /* Now program new ones. */ 655 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 656 hashes[0] = 0xFFFFFFFF; 657 hashes[1] = 0xFFFFFFFF; 658 } else { 659 i = 1; 660 /* First find the tail of the list. */ 661 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 662 if (ifma->ifma_link.le_next == NULL) 663 break; 664 } 665 /* Now traverse the list backwards. */ 666 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 667 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 668 if (ifma->ifma_addr->sa_family != AF_LINK) 669 continue; 670 /* 671 * Program the first XM_RXFILT_MAX multicast groups 672 * into the perfect filter. For all others, 673 * use the hash table. 674 */ 675 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 676 sk_setfilt(sc_if, 677 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 678 i++; 679 continue; 680 } 681 682 switch(sc->sk_type) { 683 case SK_GENESIS: 684 h = ~ether_crc32_le(LLADDR((struct sockaddr_dl *) 685 ifma->ifma_addr), ETHER_ADDR_LEN) & 686 ((1 << HASH_BITS) -1 ); 687 if (h < 32) 688 hashes[0] |= (1 << h); 689 else 690 hashes[1] |= (1 << (h - 32)); 691 break; 692 693 case SK_YUKON: 694 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 695 ifma->ifma_addr), ETHER_ADDR_LEN) & 696 ((1 << HASH_BITS) -1 ); 697 if (h < 32) 698 hashes[0] |= (1 << h); 699 else 700 hashes[1] |= (1 << (h - 32)); 701 break; 702 } 703 } 704 } 705 706 switch(sc->sk_type) { 707 case SK_GENESIS: 708 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 709 XM_MODE_RX_USE_PERFECT); 710 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 711 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 712 break; 713 case SK_YUKON: 714 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 715 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 716 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 717 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 718 break; 719 } 720 } 721 722 static void 723 sk_setpromisc(struct sk_if_softc *sc_if) 724 { 725 struct sk_softc *sc = sc_if->sk_softc; 726 struct ifnet *ifp = &sc_if->arpcom.ac_if; 727 728 switch(sc->sk_type) { 729 case SK_GENESIS: 730 if (ifp->if_flags & IFF_PROMISC) { 731 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 732 } else { 733 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 734 } 735 break; 736 case SK_YUKON: 737 if (ifp->if_flags & IFF_PROMISC) { 738 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 739 YU_RCR_UFLEN | YU_RCR_MUFLEN); 740 } else { 741 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 742 YU_RCR_UFLEN | YU_RCR_MUFLEN); 743 } 744 break; 745 } 746 } 747 748 static int 749 sk_init_rx_ring(struct sk_if_softc *sc_if) 750 { 751 struct sk_chain_data *cd = &sc_if->sk_cdata; 752 struct sk_ring_data *rd = sc_if->sk_rdata; 753 int i; 754 755 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 756 757 for (i = 0; i < SK_RX_RING_CNT; i++) { 758 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 759 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 760 return(ENOBUFS); 761 if (i == (SK_RX_RING_CNT - 1)) { 762 cd->sk_rx_chain[i].sk_next = 763 &cd->sk_rx_chain[0]; 764 rd->sk_rx_ring[i].sk_next = 765 vtophys(&rd->sk_rx_ring[0]); 766 } else { 767 cd->sk_rx_chain[i].sk_next = 768 &cd->sk_rx_chain[i + 1]; 769 rd->sk_rx_ring[i].sk_next = 770 vtophys(&rd->sk_rx_ring[i + 1]); 771 } 772 } 773 774 sc_if->sk_cdata.sk_rx_prod = 0; 775 sc_if->sk_cdata.sk_rx_cons = 0; 776 777 return(0); 778 } 779 780 static void 781 sk_init_tx_ring(struct sk_if_softc *sc_if) 782 { 783 struct sk_chain_data *cd = &sc_if->sk_cdata; 784 struct sk_ring_data *rd = sc_if->sk_rdata; 785 int i, nexti; 786 787 bzero(sc_if->sk_rdata->sk_tx_ring, 788 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 789 790 for (i = 0; i < SK_TX_RING_CNT; i++) { 791 nexti = (i == (SK_TX_RING_CNT - 1)) ? 0 : i + 1; 792 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 793 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 794 rd->sk_tx_ring[i].sk_next = vtophys(&rd->sk_tx_ring[nexti]); 795 } 796 797 sc_if->sk_cdata.sk_tx_prod = 0; 798 sc_if->sk_cdata.sk_tx_cons = 0; 799 sc_if->sk_cdata.sk_tx_cnt = 0; 800 } 801 802 static int 803 sk_newbuf(struct sk_if_softc *sc_if, struct sk_chain *c, struct mbuf *m) 804 { 805 struct mbuf *m_new = NULL; 806 struct sk_rx_desc *r; 807 struct sk_jslot *buf; 808 809 if (m == NULL) { 810 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 811 if (m_new == NULL) 812 return(ENOBUFS); 813 814 /* Allocate the jumbo buffer */ 815 buf = sk_jalloc(sc_if); 816 if (buf == NULL) { 817 m_freem(m_new); 818 #ifdef SK_VERBOSE 819 printf("sk%d: jumbo allocation failed " 820 "-- packet dropped!\n", sc_if->sk_unit); 821 #endif 822 return(ENOBUFS); 823 } 824 825 /* Attach the buffer to the mbuf */ 826 m_new->m_ext.ext_arg = buf; 827 m_new->m_ext.ext_buf = buf->sk_buf; 828 m_new->m_ext.ext_free = sk_jfree; 829 m_new->m_ext.ext_ref = sk_jref; 830 m_new->m_ext.ext_size = SK_JUMBO_FRAMELEN; 831 832 m_new->m_data = m_new->m_ext.ext_buf; 833 m_new->m_flags |= M_EXT; 834 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 835 } else { 836 /* 837 * We're re-using a previously allocated mbuf; 838 * be sure to re-init pointers and lengths to 839 * default values. 840 */ 841 m_new = m; 842 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 843 m_new->m_data = m_new->m_ext.ext_buf; 844 } 845 846 /* 847 * Adjust alignment so packet payload begins on a 848 * longword boundary. Mandatory for Alpha, useful on 849 * x86 too. 850 */ 851 m_adj(m_new, ETHER_ALIGN); 852 853 r = c->sk_desc; 854 c->sk_mbuf = m_new; 855 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 856 r->sk_ctl = m_new->m_len | SK_RXSTAT; 857 858 return(0); 859 } 860 861 /* 862 * Allocate jumbo buffer storage. The SysKonnect adapters support 863 * "jumbograms" (9K frames), although SysKonnect doesn't currently 864 * use them in their drivers. In order for us to use them, we need 865 * large 9K receive buffers, however standard mbuf clusters are only 866 * 2048 bytes in size. Consequently, we need to allocate and manage 867 * our own jumbo buffer pool. Fortunately, this does not require an 868 * excessive amount of additional code. 869 */ 870 static int 871 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 872 { 873 caddr_t ptr; 874 int i; 875 struct sk_jslot *entry; 876 877 /* Grab a big chunk o' storage. */ 878 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 879 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 880 881 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 882 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 883 return(ENOBUFS); 884 } 885 886 SLIST_INIT(&sc_if->sk_jfree_listhead); 887 888 /* 889 * Now divide it up into 9K pieces and save the addresses 890 * in an array. Note that we play an evil trick here by using 891 * the first few bytes in the buffer to hold the the address 892 * of the softc structure for this interface. This is because 893 * sk_jfree() needs it, but it is called by the mbuf management 894 * code which will not pass it to us explicitly. 895 */ 896 ptr = sc_if->sk_cdata.sk_jumbo_buf; 897 for (i = 0; i < SK_JSLOTS; i++) { 898 entry = &sc_if->sk_cdata.sk_jslots[i]; 899 entry->sk_sc = sc_if; 900 entry->sk_buf = ptr; 901 entry->sk_inuse = 0; 902 entry->sk_slot = i; 903 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jslot_link); 904 ptr += SK_JLEN; 905 } 906 907 return(0); 908 } 909 910 /* 911 * Allocate a jumbo buffer. 912 */ 913 static struct sk_jslot * 914 sk_jalloc(struct sk_if_softc *sc_if) 915 { 916 struct sk_jslot *entry; 917 918 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 919 920 if (entry == NULL) { 921 #ifdef SK_VERBOSE 922 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 923 #endif 924 return(NULL); 925 } 926 927 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jslot_link); 928 entry->sk_inuse = 1; 929 930 return(entry); 931 } 932 933 /* 934 * Adjust usage count on a jumbo buffer. In general this doesn't 935 * get used much because our jumbo buffers don't get passed around 936 * a lot, but it's implemented for correctness. 937 */ 938 static void 939 sk_jref(void *arg) 940 { 941 struct sk_jslot *entry = (struct sk_jslot *)arg; 942 struct sk_if_softc *sc = entry->sk_sc; 943 944 if (sc == NULL) 945 panic("sk_jref: can't find softc pointer!"); 946 947 if (&sc->sk_cdata.sk_jslots[entry->sk_slot] != entry) 948 panic("sk_jref: asked to reference buffer " 949 "that we don't manage!"); 950 if (entry->sk_inuse == 0) 951 panic("sk_jref: buffer already free!"); 952 entry->sk_inuse++; 953 } 954 955 /* 956 * Release a jumbo buffer. 957 */ 958 static void 959 sk_jfree(void *arg) 960 { 961 struct sk_jslot *entry = (struct sk_jslot *)arg; 962 struct sk_if_softc *sc = entry->sk_sc; 963 964 if (sc == NULL) 965 panic("sk_jref: can't find softc pointer!"); 966 967 if (&sc->sk_cdata.sk_jslots[entry->sk_slot] != entry) 968 panic("sk_jref: asked to reference buffer " 969 "that we don't manage!"); 970 if (entry->sk_inuse == 0) 971 panic("sk_jref: buffer already free!"); 972 if (--entry->sk_inuse == 0) 973 SLIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jslot_link); 974 } 975 976 /* 977 * Set media options. 978 */ 979 static int 980 sk_ifmedia_upd(struct ifnet *ifp) 981 { 982 struct sk_if_softc *sc_if = ifp->if_softc; 983 struct mii_data *mii; 984 985 mii = device_get_softc(sc_if->sk_miibus); 986 sk_init(sc_if); 987 mii_mediachg(mii); 988 989 return(0); 990 } 991 992 /* 993 * Report current media status. 994 */ 995 static void 996 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 997 { 998 struct sk_if_softc *sc_if; 999 struct mii_data *mii; 1000 1001 sc_if = ifp->if_softc; 1002 mii = device_get_softc(sc_if->sk_miibus); 1003 1004 mii_pollstat(mii); 1005 ifmr->ifm_active = mii->mii_media_active; 1006 ifmr->ifm_status = mii->mii_media_status; 1007 } 1008 1009 static int 1010 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1011 { 1012 struct sk_if_softc *sc_if = ifp->if_softc; 1013 struct ifreq *ifr = (struct ifreq *)data; 1014 struct mii_data *mii; 1015 int error = 0; 1016 1017 crit_enter(); 1018 1019 switch(command) { 1020 case SIOCSIFMTU: 1021 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1022 error = EINVAL; 1023 else { 1024 ifp->if_mtu = ifr->ifr_mtu; 1025 sk_init(sc_if); 1026 } 1027 break; 1028 case SIOCSIFFLAGS: 1029 if (ifp->if_flags & IFF_UP) { 1030 if (ifp->if_flags & IFF_RUNNING) { 1031 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1032 & IFF_PROMISC) { 1033 sk_setpromisc(sc_if); 1034 sk_setmulti(sc_if); 1035 } 1036 } else 1037 sk_init(sc_if); 1038 } else { 1039 if (ifp->if_flags & IFF_RUNNING) 1040 sk_stop(sc_if); 1041 } 1042 sc_if->sk_if_flags = ifp->if_flags; 1043 error = 0; 1044 break; 1045 case SIOCADDMULTI: 1046 case SIOCDELMULTI: 1047 sk_setmulti(sc_if); 1048 error = 0; 1049 break; 1050 case SIOCGIFMEDIA: 1051 case SIOCSIFMEDIA: 1052 mii = device_get_softc(sc_if->sk_miibus); 1053 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1054 break; 1055 default: 1056 error = ether_ioctl(ifp, command, data); 1057 break; 1058 } 1059 1060 crit_exit(); 1061 1062 return(error); 1063 } 1064 1065 /* 1066 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1067 * IDs against our list and return a device name if we find a match. 1068 */ 1069 static int 1070 skc_probe(device_t dev) 1071 { 1072 struct sk_type *t; 1073 uint16_t vendor, product; 1074 1075 vendor = pci_get_vendor(dev); 1076 product = pci_get_device(dev); 1077 1078 for (t = sk_devs; t->sk_name != NULL; t++) { 1079 if (vendor == t->sk_vid && product == t->sk_did) { 1080 device_set_desc(dev, t->sk_name); 1081 return(0); 1082 } 1083 } 1084 1085 return(ENXIO); 1086 } 1087 1088 /* 1089 * Force the GEnesis into reset, then bring it out of reset. 1090 */ 1091 static void 1092 sk_reset(struct sk_softc *sc) 1093 { 1094 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1095 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1096 if (sc->sk_type == SK_YUKON) 1097 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1098 1099 DELAY(1000); 1100 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1101 DELAY(2); 1102 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1103 if (sc->sk_type == SK_YUKON) 1104 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1105 1106 if (sc->sk_type == SK_GENESIS) { 1107 /* Configure packet arbiter */ 1108 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1109 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1110 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1111 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1112 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1113 } 1114 1115 /* Enable RAM interface */ 1116 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1117 1118 /* 1119 * Configure interrupt moderation. The moderation timer 1120 * defers interrupts specified in the interrupt moderation 1121 * timer mask based on the timeout specified in the interrupt 1122 * moderation timer init register. Each bit in the timer 1123 * register represents 18.825ns, so to specify a timeout in 1124 * microseconds, we have to multiply by 54. 1125 */ 1126 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1127 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1128 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1129 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1130 } 1131 1132 static int 1133 sk_probe(device_t dev) 1134 { 1135 struct sk_softc *sc = device_get_softc(device_get_parent(dev)); 1136 1137 /* 1138 * Not much to do here. We always know there will be 1139 * at least one XMAC present, and if there are two, 1140 * skc_attach() will create a second device instance 1141 * for us. 1142 */ 1143 switch (sc->sk_type) { 1144 case SK_GENESIS: 1145 device_set_desc(dev, "XaQti Corp. XMAC II"); 1146 break; 1147 case SK_YUKON: 1148 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1149 break; 1150 } 1151 1152 return(0); 1153 } 1154 1155 /* 1156 * Each XMAC chip is attached as a separate logical IP interface. 1157 * Single port cards will have only one logical interface of course. 1158 */ 1159 static int 1160 sk_attach(device_t dev) 1161 { 1162 struct sk_softc *sc = device_get_softc(device_get_parent(dev)); 1163 struct sk_if_softc *sc_if = device_get_softc(dev); 1164 struct ifnet *ifp; 1165 int i, port; 1166 1167 port = *(int *)device_get_ivars(dev); 1168 free(device_get_ivars(dev), M_DEVBUF); 1169 device_set_ivars(dev, NULL); 1170 sc_if->sk_dev = dev; 1171 callout_init(&sc_if->sk_tick_timer); 1172 1173 sc_if->sk_dev = dev; 1174 sc_if->sk_unit = device_get_unit(dev); 1175 sc_if->sk_port = port; 1176 sc_if->sk_softc = sc; 1177 sc->sk_if[port] = sc_if; 1178 if (port == SK_PORT_A) 1179 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1180 if (port == SK_PORT_B) 1181 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1182 1183 /* 1184 * Get station address for this interface. Note that 1185 * dual port cards actually come with three station 1186 * addresses: one for each port, plus an extra. The 1187 * extra one is used by the SysKonnect driver software 1188 * as a 'virtual' station address for when both ports 1189 * are operating in failover mode. Currently we don't 1190 * use this extra address. 1191 */ 1192 for (i = 0; i < ETHER_ADDR_LEN; i++) 1193 sc_if->arpcom.ac_enaddr[i] = 1194 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1195 1196 /* 1197 * Set up RAM buffer addresses. The NIC will have a certain 1198 * amount of SRAM on it, somewhere between 512K and 2MB. We 1199 * need to divide this up a) between the transmitter and 1200 * receiver and b) between the two XMACs, if this is a 1201 * dual port NIC. Our algotithm is to divide up the memory 1202 * evenly so that everyone gets a fair share. 1203 */ 1204 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1205 uint32_t chunk, val; 1206 1207 chunk = sc->sk_ramsize / 2; 1208 val = sc->sk_rboff / sizeof(uint64_t); 1209 sc_if->sk_rx_ramstart = val; 1210 val += (chunk / sizeof(uint64_t)); 1211 sc_if->sk_rx_ramend = val - 1; 1212 sc_if->sk_tx_ramstart = val; 1213 val += (chunk / sizeof(uint64_t)); 1214 sc_if->sk_tx_ramend = val - 1; 1215 } else { 1216 uint32_t chunk, val; 1217 1218 chunk = sc->sk_ramsize / 4; 1219 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1220 sizeof(uint64_t); 1221 sc_if->sk_rx_ramstart = val; 1222 val += (chunk / sizeof(uint64_t)); 1223 sc_if->sk_rx_ramend = val - 1; 1224 sc_if->sk_tx_ramstart = val; 1225 val += (chunk / sizeof(uint64_t)); 1226 sc_if->sk_tx_ramend = val - 1; 1227 } 1228 1229 /* Read and save PHY type and set PHY address */ 1230 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1231 switch(sc_if->sk_phytype) { 1232 case SK_PHYTYPE_XMAC: 1233 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1234 break; 1235 case SK_PHYTYPE_BCOM: 1236 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1237 break; 1238 case SK_PHYTYPE_MARV_COPPER: 1239 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1240 break; 1241 default: 1242 printf("skc%d: unsupported PHY type: %d\n", 1243 sc->sk_unit, sc_if->sk_phytype); 1244 return(ENODEV); 1245 } 1246 1247 /* Allocate the descriptor queues. */ 1248 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1249 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1250 1251 if (sc_if->sk_rdata == NULL) { 1252 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1253 sc->sk_if[port] = NULL; 1254 return(ENOMEM); 1255 } 1256 1257 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1258 1259 /* Try to allocate memory for jumbo buffers. */ 1260 if (sk_alloc_jumbo_mem(sc_if)) { 1261 printf("sk%d: jumbo buffer allocation failed\n", 1262 sc_if->sk_unit); 1263 contigfree(sc_if->sk_rdata, 1264 sizeof(struct sk_ring_data), M_DEVBUF); 1265 sc->sk_if[port] = NULL; 1266 return(ENOMEM); 1267 } 1268 1269 ifp = &sc_if->arpcom.ac_if; 1270 ifp->if_softc = sc_if; 1271 if_initname(ifp, "sk", sc_if->sk_unit); 1272 ifp->if_mtu = ETHERMTU; 1273 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1274 ifp->if_ioctl = sk_ioctl; 1275 ifp->if_start = sk_start; 1276 ifp->if_watchdog = sk_watchdog; 1277 ifp->if_init = sk_init; 1278 ifp->if_baudrate = 1000000000; 1279 ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1); 1280 ifq_set_ready(&ifp->if_snd); 1281 1282 /* 1283 * Do miibus setup. 1284 */ 1285 switch (sc->sk_type) { 1286 case SK_GENESIS: 1287 sk_init_xmac(sc_if); 1288 break; 1289 case SK_YUKON: 1290 sk_init_yukon(sc_if); 1291 break; 1292 } 1293 1294 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1295 sk_ifmedia_upd, sk_ifmedia_sts)) { 1296 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1297 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, 1298 M_DEVBUF); 1299 contigfree(sc_if->sk_rdata, 1300 sizeof(struct sk_ring_data), M_DEVBUF); 1301 return(ENXIO); 1302 } 1303 1304 /* 1305 * Call MI attach routine. 1306 */ 1307 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr); 1308 callout_init(&sc_if->sk_tick_timer); 1309 1310 return(0); 1311 } 1312 1313 /* 1314 * Attach the interface. Allocate softc structures, do ifmedia 1315 * setup and ethernet/BPF attach. 1316 */ 1317 static int 1318 skc_attach(device_t dev) 1319 { 1320 struct sk_softc *sc; 1321 int error = 0, *port, rid, unit; 1322 uint32_t command; 1323 uint8_t skrs; 1324 1325 crit_enter(); 1326 1327 sc = device_get_softc(dev); 1328 unit = device_get_unit(dev); 1329 switch (pci_get_device(dev)) { 1330 case DEVICEID_SK_V1: 1331 sc->sk_type = SK_GENESIS; 1332 break; 1333 case DEVICEID_SK_V2: 1334 case DEVICEID_3COM_3C940: 1335 case DEVICEID_LINKSYS_EG1032: 1336 case DEVICEID_DLINK_DGE530T: 1337 sc->sk_type = SK_YUKON; 1338 break; 1339 } 1340 1341 /* 1342 * Handle power management nonsense. 1343 */ 1344 command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF; 1345 if (command == 0x01) { 1346 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4); 1347 if (command & SK_PSTATE_MASK) { 1348 uint32_t iobase, membase, irq; 1349 1350 /* Save important PCI config data. */ 1351 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1352 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1353 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1354 1355 /* Reset the power state. */ 1356 printf("skc%d: chip is in D%d power mode " 1357 "-- setting to D0\n", unit, command & SK_PSTATE_MASK); 1358 command &= 0xFFFFFFFC; 1359 pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4); 1360 1361 /* Restore PCI config data. */ 1362 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1363 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1364 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1365 } 1366 } 1367 1368 /* 1369 * Map control/status registers. 1370 */ 1371 command = pci_read_config(dev, PCIR_COMMAND, 4); 1372 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1373 pci_write_config(dev, PCIR_COMMAND, command, 4); 1374 command = pci_read_config(dev, PCIR_COMMAND, 4); 1375 1376 #ifdef SK_USEIOSPACE 1377 if ((command & PCIM_CMD_PORTEN) == 0) { 1378 printf("skc%d: failed to enable I/O ports!\n", unit); 1379 error = ENXIO; 1380 goto fail; 1381 } 1382 #else 1383 if ((command & PCIM_CMD_MEMEN) == 0) { 1384 printf("skc%d: failed to enable memory mapping!\n", unit); 1385 error = ENXIO; 1386 goto fail; 1387 } 1388 #endif 1389 1390 rid = SK_RID; 1391 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE); 1392 1393 if (sc->sk_res == NULL) { 1394 printf("sk%d: couldn't map ports/memory\n", unit); 1395 error = ENXIO; 1396 goto fail; 1397 } 1398 1399 sc->sk_btag = rman_get_bustag(sc->sk_res); 1400 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1401 1402 /* Allocate interrupt */ 1403 rid = 0; 1404 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1405 RF_SHAREABLE | RF_ACTIVE); 1406 1407 if (sc->sk_irq == NULL) { 1408 printf("skc%d: couldn't map interrupt\n", unit); 1409 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1410 error = ENXIO; 1411 goto fail; 1412 } 1413 1414 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET, 1415 sk_intr, sc, 1416 &sc->sk_intrhand, NULL); 1417 1418 if (error) { 1419 printf("skc%d: couldn't set up irq\n", unit); 1420 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1421 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1422 goto fail; 1423 } 1424 1425 /* Reset the adapter. */ 1426 sk_reset(sc); 1427 1428 sc->sk_unit = unit; 1429 1430 /* Read and save vital product data from EEPROM. */ 1431 sk_vpd_read(sc); 1432 1433 skrs = sk_win_read_1(sc, SK_EPROM0); 1434 if (sc->sk_type == SK_GENESIS) { 1435 /* Read and save RAM size and RAMbuffer offset */ 1436 switch(skrs) { 1437 case SK_RAMSIZE_512K_64: 1438 sc->sk_ramsize = 0x80000; 1439 sc->sk_rboff = SK_RBOFF_0; 1440 break; 1441 case SK_RAMSIZE_1024K_64: 1442 sc->sk_ramsize = 0x100000; 1443 sc->sk_rboff = SK_RBOFF_80000; 1444 break; 1445 case SK_RAMSIZE_1024K_128: 1446 sc->sk_ramsize = 0x100000; 1447 sc->sk_rboff = SK_RBOFF_0; 1448 break; 1449 case SK_RAMSIZE_2048K_128: 1450 sc->sk_ramsize = 0x200000; 1451 sc->sk_rboff = SK_RBOFF_0; 1452 break; 1453 default: 1454 printf("skc%d: unknown ram size: %d\n", 1455 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1456 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1457 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1458 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1459 error = ENXIO; 1460 goto fail; 1461 break; 1462 } 1463 } else { /* SK_YUKON */ 1464 if (skrs == 0x00) { 1465 sc->sk_ramsize = 0x20000; 1466 } else { 1467 sc->sk_ramsize = skrs * (1<<12); 1468 } 1469 sc->sk_rboff = SK_RBOFF_0; 1470 } 1471 1472 /* Read and save physical media type */ 1473 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1474 case SK_PMD_1000BASESX: 1475 sc->sk_pmd = IFM_1000_SX; 1476 break; 1477 case SK_PMD_1000BASELX: 1478 sc->sk_pmd = IFM_1000_LX; 1479 break; 1480 case SK_PMD_1000BASECX: 1481 sc->sk_pmd = IFM_1000_CX; 1482 break; 1483 case SK_PMD_1000BASETX: 1484 sc->sk_pmd = IFM_1000_T; 1485 break; 1486 default: 1487 printf("skc%d: unknown media type: 0x%x\n", 1488 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1489 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1490 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1491 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1492 error = ENXIO; 1493 goto fail; 1494 } 1495 1496 /* Announce the product name. */ 1497 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1498 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1499 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1500 *port = SK_PORT_A; 1501 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1502 1503 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1504 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1505 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1506 *port = SK_PORT_B; 1507 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1508 } 1509 1510 /* Turn on the 'driver is loaded' LED. */ 1511 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1512 1513 bus_generic_attach(dev); 1514 1515 fail: 1516 crit_exit(); 1517 return(error); 1518 } 1519 1520 static int 1521 sk_detach(device_t dev) 1522 { 1523 struct sk_if_softc *sc_if = device_get_softc(dev); 1524 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1525 1526 crit_enter(); 1527 1528 sk_stop(sc_if); 1529 ether_ifdetach(ifp); 1530 bus_generic_detach(dev); 1531 if (sc_if->sk_miibus != NULL) 1532 device_delete_child(dev, sc_if->sk_miibus); 1533 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1534 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF); 1535 1536 crit_exit(); 1537 1538 return(0); 1539 } 1540 1541 static int 1542 skc_detach(device_t dev) 1543 { 1544 struct sk_softc *sc; 1545 1546 crit_enter(); 1547 1548 sc = device_get_softc(dev); 1549 1550 bus_generic_detach(dev); 1551 if (sc->sk_devs[SK_PORT_A] != NULL) 1552 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1553 if (sc->sk_devs[SK_PORT_B] != NULL) 1554 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1555 1556 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1557 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1558 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1559 1560 crit_exit(); 1561 1562 return(0); 1563 } 1564 1565 static int 1566 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1567 { 1568 struct sk_tx_desc *f = NULL; 1569 struct mbuf *m; 1570 uint32_t cnt = 0, cur, frag; 1571 1572 m = m_head; 1573 cur = frag = *txidx; 1574 1575 /* 1576 * Start packing the mbufs in this chain into 1577 * the fragment pointers. Stop when we run out 1578 * of fragments or hit the end of the mbuf chain. 1579 */ 1580 for (m = m_head; m != NULL; m = m->m_next) { 1581 if (m->m_len != 0) { 1582 if ((SK_TX_RING_CNT - 1583 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1584 return(ENOBUFS); 1585 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1586 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1587 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1588 if (cnt == 0) 1589 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1590 else 1591 f->sk_ctl |= SK_TXCTL_OWN; 1592 cur = frag; 1593 SK_INC(frag, SK_TX_RING_CNT); 1594 cnt++; 1595 } 1596 } 1597 1598 if (m != NULL) 1599 return(ENOBUFS); 1600 1601 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1602 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1603 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1604 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1605 sc_if->sk_cdata.sk_tx_cnt += cnt; 1606 1607 *txidx = frag; 1608 1609 return(0); 1610 } 1611 1612 static void 1613 sk_start(struct ifnet *ifp) 1614 { 1615 struct sk_if_softc *sc_if = ifp->if_softc; 1616 struct sk_softc *sc = sc_if->sk_softc; 1617 struct mbuf *m_head = NULL; 1618 uint32_t idx; 1619 1620 idx = sc_if->sk_cdata.sk_tx_prod; 1621 1622 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1623 m_head = ifq_poll(&ifp->if_snd); 1624 if (m_head == NULL) 1625 break; 1626 1627 /* 1628 * Pack the data into the transmit ring. If we 1629 * don't have room, set the OACTIVE flag and wait 1630 * for the NIC to drain the ring. 1631 */ 1632 if (sk_encap(sc_if, m_head, &idx)) { 1633 ifp->if_flags |= IFF_OACTIVE; 1634 break; 1635 } 1636 m_head = ifq_dequeue(&ifp->if_snd); 1637 1638 BPF_MTAP(ifp, m_head); 1639 } 1640 1641 /* Transmit */ 1642 sc_if->sk_cdata.sk_tx_prod = idx; 1643 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1644 1645 /* Set a timeout in case the chip goes out to lunch. */ 1646 ifp->if_timer = 5; 1647 } 1648 1649 1650 static void 1651 sk_watchdog(struct ifnet *ifp) 1652 { 1653 struct sk_if_softc *sc_if; 1654 1655 sc_if = ifp->if_softc; 1656 1657 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1658 sk_init(sc_if); 1659 } 1660 1661 static void 1662 skc_shutdown(device_t dev) 1663 { 1664 struct sk_softc *sc = device_get_softc(dev); 1665 1666 /* Turn off the 'driver is loaded' LED. */ 1667 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1668 1669 /* 1670 * Reset the GEnesis controller. Doing this should also 1671 * assert the resets on the attached XMAC(s). 1672 */ 1673 sk_reset(sc); 1674 } 1675 1676 static void 1677 sk_rxeof(struct sk_if_softc *sc_if) 1678 { 1679 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1680 struct mbuf *m; 1681 struct sk_chain *cur_rx; 1682 int i, total_len = 0; 1683 uint32_t rxstat; 1684 1685 i = sc_if->sk_cdata.sk_rx_prod; 1686 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1687 1688 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1689 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1690 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1691 m = cur_rx->sk_mbuf; 1692 cur_rx->sk_mbuf = NULL; 1693 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1694 SK_INC(i, SK_RX_RING_CNT); 1695 1696 if (rxstat & XM_RXSTAT_ERRFRAME) { 1697 ifp->if_ierrors++; 1698 sk_newbuf(sc_if, cur_rx, m); 1699 continue; 1700 } 1701 1702 /* 1703 * Try to allocate a new jumbo buffer. If that 1704 * fails, copy the packet to mbufs and put the 1705 * jumbo buffer back in the ring so it can be 1706 * re-used. If allocating mbufs fails, then we 1707 * have to drop the packet. 1708 */ 1709 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1710 struct mbuf *m0; 1711 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1712 total_len + ETHER_ALIGN, 0, ifp, NULL); 1713 sk_newbuf(sc_if, cur_rx, m); 1714 if (m0 == NULL) { 1715 printf("sk%d: no receive buffers " 1716 "available -- packet dropped!\n", 1717 sc_if->sk_unit); 1718 ifp->if_ierrors++; 1719 continue; 1720 } 1721 m_adj(m0, ETHER_ALIGN); 1722 m = m0; 1723 } else { 1724 m->m_pkthdr.rcvif = ifp; 1725 m->m_pkthdr.len = m->m_len = total_len; 1726 } 1727 1728 ifp->if_ipackets++; 1729 (*ifp->if_input)(ifp, m); 1730 } 1731 1732 sc_if->sk_cdata.sk_rx_prod = i; 1733 } 1734 1735 static void 1736 sk_txeof(struct sk_if_softc *sc_if) 1737 { 1738 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1739 struct sk_tx_desc *cur_tx = NULL; 1740 uint32_t idx; 1741 1742 /* 1743 * Go through our tx ring and free mbufs for those 1744 * frames that have been sent. 1745 */ 1746 idx = sc_if->sk_cdata.sk_tx_cons; 1747 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1748 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1749 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1750 break; 1751 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1752 ifp->if_opackets++; 1753 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1754 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1755 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1756 } 1757 sc_if->sk_cdata.sk_tx_cnt--; 1758 SK_INC(idx, SK_TX_RING_CNT); 1759 ifp->if_timer = 0; 1760 } 1761 1762 sc_if->sk_cdata.sk_tx_cons = idx; 1763 1764 if (cur_tx != NULL) 1765 ifp->if_flags &= ~IFF_OACTIVE; 1766 } 1767 1768 static void 1769 sk_tick(void *xsc_if) 1770 { 1771 struct sk_if_softc *sc_if = xsc_if; 1772 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1773 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 1774 int i; 1775 1776 if ((ifp->if_flags & IFF_UP) == 0) 1777 return; 1778 1779 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1780 sk_intr_bcom(sc_if); 1781 return; 1782 } 1783 1784 /* 1785 * According to SysKonnect, the correct way to verify that 1786 * the link has come back up is to poll bit 0 of the GPIO 1787 * register three times. This pin has the signal from the 1788 * link_sync pin connected to it; if we read the same link 1789 * state 3 times in a row, we know the link is up. 1790 */ 1791 for (i = 0; i < 3; i++) { 1792 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1793 break; 1794 } 1795 1796 if (i != 3) { 1797 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if); 1798 return; 1799 } 1800 1801 /* Turn the GP0 interrupt back on. */ 1802 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1803 SK_XM_READ_2(sc_if, XM_ISR); 1804 mii_tick(mii); 1805 mii_pollstat(mii); 1806 callout_stop(&sc_if->sk_tick_timer); 1807 } 1808 1809 static void 1810 sk_intr_bcom(struct sk_if_softc *sc_if) 1811 { 1812 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1813 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 1814 int status; 1815 1816 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1817 1818 /* 1819 * Read the PHY interrupt register to make sure 1820 * we clear any pending interrupts. 1821 */ 1822 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1823 1824 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1825 sk_init_xmac(sc_if); 1826 return; 1827 } 1828 1829 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1830 int lstat; 1831 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 1832 BRGPHY_MII_AUXSTS); 1833 1834 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1835 mii_mediachg(mii); 1836 /* Turn off the link LED. */ 1837 SK_IF_WRITE_1(sc_if, 0, 1838 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1839 sc_if->sk_link = 0; 1840 } else if (status & BRGPHY_ISR_LNK_CHG) { 1841 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 1842 BRGPHY_MII_IMR, 0xFF00); 1843 mii_tick(mii); 1844 sc_if->sk_link = 1; 1845 /* Turn on the link LED. */ 1846 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1847 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1848 SK_LINKLED_BLINK_OFF); 1849 mii_pollstat(mii); 1850 } else { 1851 mii_tick(mii); 1852 callout_reset(&sc_if->sk_tick_timer, hz, 1853 sk_tick, sc_if); 1854 } 1855 } 1856 1857 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1858 } 1859 1860 static void 1861 sk_intr_xmac(struct sk_if_softc *sc_if) 1862 { 1863 uint16_t status; 1864 1865 status = SK_XM_READ_2(sc_if, XM_ISR); 1866 1867 /* 1868 * Link has gone down. Start MII tick timeout to 1869 * watch for link resync. 1870 */ 1871 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1872 if (status & XM_ISR_GP0_SET) { 1873 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1874 callout_reset(&sc_if->sk_tick_timer, hz, 1875 sk_tick, sc_if); 1876 } 1877 1878 if (status & XM_ISR_AUTONEG_DONE) { 1879 callout_reset(&sc_if->sk_tick_timer, hz, 1880 sk_tick, sc_if); 1881 } 1882 } 1883 1884 if (status & XM_IMR_TX_UNDERRUN) 1885 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1886 1887 if (status & XM_IMR_RX_OVERRUN) 1888 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1889 1890 status = SK_XM_READ_2(sc_if, XM_ISR); 1891 } 1892 1893 static void 1894 sk_intr_yukon(struct sk_if_softc *sc_if) 1895 { 1896 int status; 1897 1898 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1899 } 1900 1901 static void 1902 sk_intr(void *xsc) 1903 { 1904 struct sk_softc *sc = xsc; 1905 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1906 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_A]; 1907 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1908 uint32_t status; 1909 1910 if (sc_if0 != NULL) 1911 ifp0 = &sc_if0->arpcom.ac_if; 1912 if (sc_if1 != NULL) 1913 ifp1 = &sc_if1->arpcom.ac_if; 1914 1915 for (;;) { 1916 status = CSR_READ_4(sc, SK_ISSR); 1917 if ((status & sc->sk_intrmask) == 0) 1918 break; 1919 1920 /* Handle receive interrupts first. */ 1921 if (status & SK_ISR_RX1_EOF) { 1922 sk_rxeof(sc_if0); 1923 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1924 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1925 } 1926 if (status & SK_ISR_RX2_EOF) { 1927 sk_rxeof(sc_if1); 1928 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1929 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1930 } 1931 1932 /* Then transmit interrupts. */ 1933 if (status & SK_ISR_TX1_S_EOF) { 1934 sk_txeof(sc_if0); 1935 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1936 SK_TXBMU_CLR_IRQ_EOF); 1937 } 1938 if (status & SK_ISR_TX2_S_EOF) { 1939 sk_txeof(sc_if1); 1940 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1941 SK_TXBMU_CLR_IRQ_EOF); 1942 } 1943 1944 /* Then MAC interrupts. */ 1945 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) { 1946 if (sc->sk_type == SK_GENESIS) 1947 sk_intr_xmac(sc_if0); 1948 else 1949 sk_intr_yukon(sc_if0); 1950 } 1951 1952 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) { 1953 if (sc->sk_type == SK_GENESIS) 1954 sk_intr_xmac(sc_if1); 1955 else 1956 sk_intr_yukon(sc_if0); 1957 } 1958 1959 if (status & SK_ISR_EXTERNAL_REG) { 1960 if (ifp0 != NULL && 1961 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 1962 sk_intr_bcom(sc_if0); 1963 if (ifp1 != NULL && 1964 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 1965 sk_intr_bcom(sc_if1); 1966 } 1967 } 1968 1969 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1970 1971 if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd)) 1972 sk_start(ifp0); 1973 if (ifp1 != NULL && !ifq_is_empty(&ifp0->if_snd)) 1974 sk_start(ifp1); 1975 } 1976 1977 static void 1978 sk_init_xmac(struct sk_if_softc *sc_if) 1979 { 1980 struct sk_softc *sc = sc_if->sk_softc; 1981 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1982 struct sk_bcom_hack bhack[] = { 1983 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 1984 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 1985 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 1986 { 0, 0 } }; 1987 1988 /* Unreset the XMAC. */ 1989 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 1990 DELAY(1000); 1991 1992 /* Reset the XMAC's internal state. */ 1993 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 1994 1995 /* Save the XMAC II revision */ 1996 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 1997 1998 /* 1999 * Perform additional initialization for external PHYs, 2000 * namely for the 1000baseTX cards that use the XMAC's 2001 * GMII mode. 2002 */ 2003 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2004 int i = 0; 2005 uint32_t val; 2006 2007 /* Take PHY out of reset. */ 2008 val = sk_win_read_4(sc, SK_GPIO); 2009 if (sc_if->sk_port == SK_PORT_A) 2010 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2011 else 2012 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2013 sk_win_write_4(sc, SK_GPIO, val); 2014 2015 /* Enable GMII mode on the XMAC. */ 2016 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2017 2018 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2019 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2020 DELAY(10000); 2021 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2022 BRGPHY_MII_IMR, 0xFFF0); 2023 2024 /* 2025 * Early versions of the BCM5400 apparently have 2026 * a bug that requires them to have their reserved 2027 * registers initialized to some magic values. I don't 2028 * know what the numbers do, I'm just the messenger. 2029 */ 2030 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2031 == 0x6041) { 2032 while(bhack[i].reg) { 2033 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2034 bhack[i].reg, bhack[i].val); 2035 i++; 2036 } 2037 } 2038 } 2039 2040 /* Set station address */ 2041 SK_XM_WRITE_2(sc_if, XM_PAR0, 2042 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2043 SK_XM_WRITE_2(sc_if, XM_PAR1, 2044 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2045 SK_XM_WRITE_2(sc_if, XM_PAR2, 2046 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2047 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2048 2049 if (ifp->if_flags & IFF_BROADCAST) 2050 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2051 else 2052 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2053 2054 /* We don't need the FCS appended to the packet. */ 2055 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2056 2057 /* We want short frames padded to 60 bytes. */ 2058 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2059 2060 /* 2061 * Enable the reception of all error frames. This is is 2062 * a necessary evil due to the design of the XMAC. The 2063 * XMAC's receive FIFO is only 8K in size, however jumbo 2064 * frames can be up to 9000 bytes in length. When bad 2065 * frame filtering is enabled, the XMAC's RX FIFO operates 2066 * in 'store and forward' mode. For this to work, the 2067 * entire frame has to fit into the FIFO, but that means 2068 * that jumbo frames larger than 8192 bytes will be 2069 * truncated. Disabling all bad frame filtering causes 2070 * the RX FIFO to operate in streaming mode, in which 2071 * case the XMAC will start transfering frames out of the 2072 * RX FIFO as soon as the FIFO threshold is reached. 2073 */ 2074 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2075 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2076 XM_MODE_RX_INRANGELEN); 2077 2078 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2079 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2080 else 2081 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2082 2083 /* 2084 * Bump up the transmit threshold. This helps hold off transmit 2085 * underruns when we're blasting traffic from both ports at once. 2086 */ 2087 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2088 2089 /* Set promiscuous mode */ 2090 sk_setpromisc(sc_if); 2091 2092 /* Set multicast filter */ 2093 sk_setmulti(sc_if); 2094 2095 /* Clear and enable interrupts */ 2096 SK_XM_READ_2(sc_if, XM_ISR); 2097 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2098 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2099 else 2100 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2101 2102 /* Configure MAC arbiter */ 2103 switch(sc_if->sk_xmac_rev) { 2104 case XM_XMAC_REV_B2: 2105 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2106 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2107 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2108 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2109 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2110 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2111 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2112 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2113 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2114 break; 2115 case XM_XMAC_REV_C1: 2116 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2117 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2118 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2119 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2120 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2121 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2122 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2123 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2124 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2125 break; 2126 default: 2127 break; 2128 } 2129 sk_win_write_2(sc, SK_MACARB_CTL, 2130 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2131 2132 sc_if->sk_link = 1; 2133 } 2134 2135 static void 2136 sk_init_yukon(struct sk_if_softc *sc_if) 2137 { 2138 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2139 uint32_t phy; 2140 uint16_t reg; 2141 int i; 2142 2143 /* GMAC and GPHY Reset */ 2144 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2145 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2146 DELAY(1000); 2147 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2148 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2149 DELAY(1000); 2150 2151 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2152 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2153 2154 switch(sc_if->sk_softc->sk_pmd) { 2155 case IFM_1000_SX: 2156 case IFM_1000_LX: 2157 phy |= SK_GPHY_FIBER; 2158 break; 2159 2160 case IFM_1000_CX: 2161 case IFM_1000_T: 2162 phy |= SK_GPHY_COPPER; 2163 break; 2164 } 2165 2166 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2167 DELAY(1000); 2168 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2169 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2170 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2171 2172 /* unused read of the interrupt source register */ 2173 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2174 2175 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2176 2177 /* MIB Counter Clear Mode set */ 2178 reg |= YU_PAR_MIB_CLR; 2179 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2180 2181 /* MIB Counter Clear Mode clear */ 2182 reg &= ~YU_PAR_MIB_CLR; 2183 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2184 2185 /* receive control reg */ 2186 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2187 2188 /* transmit parameter register */ 2189 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2190 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2191 2192 /* serial mode register */ 2193 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 2194 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2195 reg |= YU_SMR_MFL_JUMBO; 2196 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2197 2198 /* Setup Yukon's address */ 2199 for (i = 0; i < 3; i++) { 2200 /* Write Source Address 1 (unicast filter) */ 2201 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2202 sc_if->arpcom.ac_enaddr[i * 2] | 2203 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2204 } 2205 2206 for (i = 0; i < 3; i++) { 2207 reg = sk_win_read_2(sc_if->sk_softc, 2208 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2209 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2210 } 2211 2212 /* Set promiscuous mode */ 2213 sk_setpromisc(sc_if); 2214 2215 /* Set multicast filter */ 2216 sk_setmulti(sc_if); 2217 2218 /* enable interrupt mask for counter overflows */ 2219 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2220 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2221 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2222 2223 /* Configure RX MAC FIFO */ 2224 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2225 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2226 2227 /* Configure TX MAC FIFO */ 2228 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2229 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2230 } 2231 2232 /* 2233 * Note that to properly initialize any part of the GEnesis chip, 2234 * you first have to take it out of reset mode. 2235 */ 2236 static void 2237 sk_init(void *xsc) 2238 { 2239 struct sk_if_softc *sc_if = xsc; 2240 struct sk_softc *sc = sc_if->sk_softc; 2241 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2242 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 2243 uint16_t reg; 2244 2245 crit_enter(); 2246 2247 /* Cancel pending I/O and free all RX/TX buffers. */ 2248 sk_stop(sc_if); 2249 2250 if (sc->sk_type == SK_GENESIS) { 2251 /* Configure LINK_SYNC LED */ 2252 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2253 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2254 SK_LINKLED_LINKSYNC_ON); 2255 2256 /* Configure RX LED */ 2257 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2258 SK_RXLEDCTL_COUNTER_START); 2259 2260 /* Configure TX LED */ 2261 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2262 SK_TXLEDCTL_COUNTER_START); 2263 } 2264 2265 /* Configure I2C registers */ 2266 2267 /* Configure XMAC(s) */ 2268 switch (sc->sk_type) { 2269 case SK_GENESIS: 2270 sk_init_xmac(sc_if); 2271 break; 2272 case SK_YUKON: 2273 sk_init_yukon(sc_if); 2274 break; 2275 } 2276 mii_mediachg(mii); 2277 2278 if (sc->sk_type == SK_GENESIS) { 2279 /* Configure MAC FIFOs */ 2280 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2281 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2282 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2283 2284 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2285 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2286 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2287 } 2288 2289 /* Configure transmit arbiter(s) */ 2290 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2291 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2292 2293 /* Configure RAMbuffers */ 2294 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2295 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2296 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2297 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2298 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2299 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2300 2301 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2302 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2303 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2304 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2305 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2306 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2307 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2308 2309 /* Configure BMUs */ 2310 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2311 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2312 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2313 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2314 2315 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2316 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2317 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2318 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2319 2320 /* Init descriptors */ 2321 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2322 printf("sk%d: initialization failed: no " 2323 "memory for rx buffers\n", sc_if->sk_unit); 2324 sk_stop(sc_if); 2325 crit_exit(); 2326 return; 2327 } 2328 sk_init_tx_ring(sc_if); 2329 2330 /* Configure interrupt handling */ 2331 CSR_READ_4(sc, SK_ISSR); 2332 if (sc_if->sk_port == SK_PORT_A) 2333 sc->sk_intrmask |= SK_INTRS1; 2334 else 2335 sc->sk_intrmask |= SK_INTRS2; 2336 2337 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2338 2339 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2340 2341 /* Start BMUs. */ 2342 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2343 2344 switch(sc->sk_type) { 2345 case SK_GENESIS: 2346 /* Enable XMACs TX and RX state machines */ 2347 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2348 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2349 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2350 break; 2351 case SK_YUKON: 2352 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2353 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2354 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2355 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2356 } 2357 2358 ifp->if_flags |= IFF_RUNNING; 2359 ifp->if_flags &= ~IFF_OACTIVE; 2360 2361 crit_exit(); 2362 } 2363 2364 static void 2365 sk_stop(struct sk_if_softc *sc_if) 2366 { 2367 int i; 2368 struct sk_softc *sc = sc_if->sk_softc; 2369 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2370 2371 callout_stop(&sc_if->sk_tick_timer); 2372 2373 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2374 uint32_t val; 2375 2376 /* Put PHY back into reset. */ 2377 val = sk_win_read_4(sc, SK_GPIO); 2378 if (sc_if->sk_port == SK_PORT_A) { 2379 val |= SK_GPIO_DIR0; 2380 val &= ~SK_GPIO_DAT0; 2381 } else { 2382 val |= SK_GPIO_DIR2; 2383 val &= ~SK_GPIO_DAT2; 2384 } 2385 sk_win_write_4(sc, SK_GPIO, val); 2386 } 2387 2388 /* Turn off various components of this interface. */ 2389 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2390 switch (sc->sk_type) { 2391 case SK_GENESIS: 2392 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2393 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2394 break; 2395 case SK_YUKON: 2396 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2397 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2398 break; 2399 } 2400 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2401 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2402 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2403 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, 2404 SK_RBCTL_RESET | SK_RBCTL_OFF); 2405 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2406 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2407 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2408 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2409 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2410 2411 /* Disable interrupts */ 2412 if (sc_if->sk_port == SK_PORT_A) 2413 sc->sk_intrmask &= ~SK_INTRS1; 2414 else 2415 sc->sk_intrmask &= ~SK_INTRS2; 2416 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2417 2418 SK_XM_READ_2(sc_if, XM_ISR); 2419 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2420 2421 /* Free RX and TX mbufs still in the queues. */ 2422 for (i = 0; i < SK_RX_RING_CNT; i++) { 2423 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2424 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2425 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2426 } 2427 } 2428 2429 for (i = 0; i < SK_TX_RING_CNT; i++) { 2430 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2431 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2432 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2433 } 2434 } 2435 2436 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2437 } 2438