1 /* 2 * Copyright (c) 1997, 1998, 1999, 2000 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $OpenBSD: if_sk.c,v 1.129 2006/10/16 12:30:08 tom Exp $ 33 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 34 * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.56 2008/05/14 11:59:22 sephe Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include <sys/param.h> 90 #include <sys/bus.h> 91 #include <sys/endian.h> 92 #include <sys/in_cksum.h> 93 #include <sys/kernel.h> 94 #include <sys/interrupt.h> 95 #include <sys/mbuf.h> 96 #include <sys/malloc.h> 97 #include <sys/queue.h> 98 #include <sys/rman.h> 99 #include <sys/serialize.h> 100 #include <sys/socket.h> 101 #include <sys/sockio.h> 102 #include <sys/sysctl.h> 103 104 #include <net/bpf.h> 105 #include <net/ethernet.h> 106 #include <net/if.h> 107 #include <net/if_arp.h> 108 #include <net/if_dl.h> 109 #include <net/if_media.h> 110 #include <net/ifq_var.h> 111 #include <net/vlan/if_vlan_var.h> 112 113 #include <netinet/ip.h> 114 #include <netinet/udp.h> 115 116 #include <dev/netif/mii_layer/mii.h> 117 #include <dev/netif/mii_layer/miivar.h> 118 #include <dev/netif/mii_layer/brgphyreg.h> 119 120 #include <bus/pci/pcireg.h> 121 #include <bus/pci/pcivar.h> 122 #include <bus/pci/pcidevs.h> 123 124 #include <dev/netif/sk/if_skreg.h> 125 #include <dev/netif/sk/yukonreg.h> 126 #include <dev/netif/sk/xmaciireg.h> 127 #include <dev/netif/sk/if_skvar.h> 128 129 #include "miibus_if.h" 130 131 #if 0 132 #define SK_DEBUG 133 #endif 134 135 #if 0 136 #define SK_RXCSUM 137 #endif 138 139 /* supported device vendors */ 140 static const struct skc_type { 141 uint16_t skc_vid; 142 uint16_t skc_did; 143 const char *skc_name; 144 } skc_devs[] = { 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, 146 "3Com 3C940" }, 147 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940B, 148 "3Com 3C940B" }, 149 150 { PCI_VENDOR_CNET, PCI_PRODUCT_CNET_GIGACARD, 151 "CNet GigaCard" }, 152 153 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_A1, 154 "D-Link DGE-530T A1" }, 155 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_B1, 156 "D-Link DGE-530T B1" }, 157 158 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, 159 "Linksys EG1032 v2" }, 160 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, 161 "Linksys EG1064" }, 162 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON, 164 "Marvell Yukon 88E8001/8003/8010" }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_BELKIN, 166 "Belkin F5D5005" }, 167 168 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, 169 "SysKonnect SK-NET" }, 170 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, 171 "SysKonnect SK9821 v2" }, 172 173 { 0, 0, NULL } 174 }; 175 176 static int skc_probe(device_t); 177 static int skc_attach(device_t); 178 static int skc_detach(device_t); 179 static void skc_shutdown(device_t); 180 static int skc_sysctl_imtime(SYSCTL_HANDLER_ARGS); 181 182 static int sk_probe(device_t); 183 static int sk_attach(device_t); 184 static int sk_detach(device_t); 185 static void sk_tick(void *); 186 static void sk_yukon_tick(void *); 187 static void sk_intr(void *); 188 static void sk_intr_bcom(struct sk_if_softc *); 189 static void sk_intr_xmac(struct sk_if_softc *); 190 static void sk_intr_yukon(struct sk_if_softc *); 191 static void sk_rxeof(struct sk_if_softc *); 192 static void sk_txeof(struct sk_if_softc *); 193 static int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 194 static void sk_start(struct ifnet *); 195 static int sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 196 static void sk_init(void *); 197 static void sk_init_xmac(struct sk_if_softc *); 198 static void sk_init_yukon(struct sk_if_softc *); 199 static void sk_stop(struct sk_if_softc *); 200 static void sk_watchdog(struct ifnet *); 201 static int sk_ifmedia_upd(struct ifnet *); 202 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 203 static void sk_reset(struct sk_softc *); 204 static int sk_newbuf_jumbo(struct sk_if_softc *, int, int); 205 static int sk_newbuf_std(struct sk_if_softc *, int, int); 206 static int sk_jpool_alloc(device_t); 207 static void sk_jpool_free(struct sk_if_softc *); 208 static struct sk_jpool_entry 209 *sk_jalloc(struct sk_if_softc *); 210 static void sk_jfree(void *); 211 static void sk_jref(void *); 212 static int sk_init_rx_ring(struct sk_if_softc *); 213 static int sk_init_tx_ring(struct sk_if_softc *); 214 215 static int sk_miibus_readreg(device_t, int, int); 216 static int sk_miibus_writereg(device_t, int, int, int); 217 static void sk_miibus_statchg(device_t); 218 219 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 220 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int); 221 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 222 223 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 224 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int); 225 static void sk_marv_miibus_statchg(struct sk_if_softc *); 226 227 static void sk_setfilt(struct sk_if_softc *, caddr_t, int); 228 static void sk_setmulti(struct sk_if_softc *); 229 static void sk_setpromisc(struct sk_if_softc *); 230 231 #ifdef SK_RXCSUM 232 static void sk_rxcsum(struct ifnet *, struct mbuf *, const uint16_t, 233 const uint16_t); 234 #endif 235 static int sk_dma_alloc(device_t); 236 static void sk_dma_free(device_t); 237 238 static void sk_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t, 239 int); 240 static void sk_dmamem_addr(void *, bus_dma_segment_t *, int, int); 241 242 #ifdef SK_DEBUG 243 #define DPRINTF(x) if (skdebug) kprintf x 244 #define DPRINTFN(n,x) if (skdebug >= (n)) kprintf x 245 static int skdebug = 2; 246 247 static void sk_dump_txdesc(struct sk_tx_desc *, int); 248 static void sk_dump_mbuf(struct mbuf *); 249 static void sk_dump_bytes(const char *, int); 250 #else 251 #define DPRINTF(x) 252 #define DPRINTFN(n,x) 253 #endif 254 255 /* Interrupt moderation time. */ 256 static int skc_imtime = SK_IMTIME_DEFAULT; 257 TUNABLE_INT("hw.skc.imtime", &skc_imtime); 258 259 /* 260 * Note that we have newbus methods for both the GEnesis controller 261 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 262 * the miibus code is a child of the XMACs. We need to do it this way 263 * so that the miibus drivers can access the PHY registers on the 264 * right PHY. It's not quite what I had in mind, but it's the only 265 * design that achieves the desired effect. 266 */ 267 static device_method_t skc_methods[] = { 268 /* Device interface */ 269 DEVMETHOD(device_probe, skc_probe), 270 DEVMETHOD(device_attach, skc_attach), 271 DEVMETHOD(device_detach, skc_detach), 272 DEVMETHOD(device_shutdown, skc_shutdown), 273 274 /* bus interface */ 275 DEVMETHOD(bus_print_child, bus_generic_print_child), 276 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 277 278 { 0, 0 } 279 }; 280 281 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc)); 282 static devclass_t skc_devclass; 283 284 static device_method_t sk_methods[] = { 285 /* Device interface */ 286 DEVMETHOD(device_probe, sk_probe), 287 DEVMETHOD(device_attach, sk_attach), 288 DEVMETHOD(device_detach, sk_detach), 289 DEVMETHOD(device_shutdown, bus_generic_shutdown), 290 291 /* bus interface */ 292 DEVMETHOD(bus_print_child, bus_generic_print_child), 293 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 294 295 /* MII interface */ 296 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 297 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 298 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 299 300 { 0, 0 } 301 }; 302 303 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc)); 304 static devclass_t sk_devclass; 305 306 DECLARE_DUMMY_MODULE(if_sk); 307 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0); 308 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0); 309 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 310 311 static __inline uint32_t 312 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 313 { 314 return CSR_READ_4(sc, reg); 315 } 316 317 static __inline uint16_t 318 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 319 { 320 return CSR_READ_2(sc, reg); 321 } 322 323 static __inline uint8_t 324 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 325 { 326 return CSR_READ_1(sc, reg); 327 } 328 329 static __inline void 330 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 331 { 332 CSR_WRITE_4(sc, reg, x); 333 } 334 335 static __inline void 336 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 337 { 338 CSR_WRITE_2(sc, reg, x); 339 } 340 341 static __inline void 342 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 343 { 344 CSR_WRITE_1(sc, reg, x); 345 } 346 347 static __inline int 348 sk_newbuf(struct sk_if_softc *sc_if, int idx, int wait) 349 { 350 int ret; 351 352 if (sc_if->sk_use_jumbo) 353 ret = sk_newbuf_jumbo(sc_if, idx, wait); 354 else 355 ret = sk_newbuf_std(sc_if, idx, wait); 356 return ret; 357 } 358 359 static int 360 sk_miibus_readreg(device_t dev, int phy, int reg) 361 { 362 struct sk_if_softc *sc_if = device_get_softc(dev); 363 364 if (SK_IS_GENESIS(sc_if->sk_softc)) 365 return sk_xmac_miibus_readreg(sc_if, phy, reg); 366 else 367 return sk_marv_miibus_readreg(sc_if, phy, reg); 368 } 369 370 static int 371 sk_miibus_writereg(device_t dev, int phy, int reg, int val) 372 { 373 struct sk_if_softc *sc_if = device_get_softc(dev); 374 375 if (SK_IS_GENESIS(sc_if->sk_softc)) 376 return sk_xmac_miibus_writereg(sc_if, phy, reg, val); 377 else 378 return sk_marv_miibus_writereg(sc_if, phy, reg, val); 379 } 380 381 static void 382 sk_miibus_statchg(device_t dev) 383 { 384 struct sk_if_softc *sc_if = device_get_softc(dev); 385 386 if (SK_IS_GENESIS(sc_if->sk_softc)) 387 sk_xmac_miibus_statchg(sc_if); 388 else 389 sk_marv_miibus_statchg(sc_if); 390 } 391 392 static int 393 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 394 { 395 int i; 396 397 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 398 399 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 400 return(0); 401 402 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 403 SK_XM_READ_2(sc_if, XM_PHY_DATA); 404 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 405 for (i = 0; i < SK_TIMEOUT; i++) { 406 DELAY(1); 407 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 408 XM_MMUCMD_PHYDATARDY) 409 break; 410 } 411 412 if (i == SK_TIMEOUT) { 413 if_printf(&sc_if->arpcom.ac_if, 414 "phy failed to come ready\n"); 415 return(0); 416 } 417 } 418 DELAY(1); 419 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 420 } 421 422 static int 423 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 424 { 425 int i; 426 427 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 428 429 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 430 for (i = 0; i < SK_TIMEOUT; i++) { 431 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0) 432 break; 433 } 434 435 if (i == SK_TIMEOUT) { 436 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n"); 437 return(ETIMEDOUT); 438 } 439 440 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 441 for (i = 0; i < SK_TIMEOUT; i++) { 442 DELAY(1); 443 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0) 444 break; 445 } 446 447 if (i == SK_TIMEOUT) 448 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n"); 449 return(0); 450 } 451 452 static void 453 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if) 454 { 455 struct mii_data *mii; 456 457 mii = device_get_softc(sc_if->sk_miibus); 458 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 459 460 /* 461 * If this is a GMII PHY, manually set the XMAC's 462 * duplex mode accordingly. 463 */ 464 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 465 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 466 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 467 else 468 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 469 } 470 } 471 472 static int 473 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 474 { 475 uint16_t val; 476 int i; 477 478 if (phy != 0 || 479 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 480 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 481 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 482 phy, reg)); 483 return(0); 484 } 485 486 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 487 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 488 489 for (i = 0; i < SK_TIMEOUT; i++) { 490 DELAY(1); 491 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 492 if (val & YU_SMICR_READ_VALID) 493 break; 494 } 495 496 if (i == SK_TIMEOUT) { 497 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n"); 498 return(0); 499 } 500 501 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 502 SK_TIMEOUT)); 503 504 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 505 506 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 507 phy, reg, val)); 508 509 return(val); 510 } 511 512 static int 513 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 514 { 515 int i; 516 517 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 518 phy, reg, val)); 519 520 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 521 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 522 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 523 524 for (i = 0; i < SK_TIMEOUT; i++) { 525 DELAY(1); 526 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 527 break; 528 } 529 530 if (i == SK_TIMEOUT) 531 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n"); 532 533 return(0); 534 } 535 536 static void 537 sk_marv_miibus_statchg(struct sk_if_softc *sc_if) 538 { 539 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 540 SK_YU_READ_2(sc_if, YUKON_GPCR))); 541 } 542 543 #define HASH_BITS 6 544 545 static uint32_t 546 sk_xmac_hash(caddr_t addr) 547 { 548 uint32_t crc; 549 550 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 551 return (~crc & ((1 << HASH_BITS) - 1)); 552 } 553 554 static uint32_t 555 sk_yukon_hash(caddr_t addr) 556 { 557 uint32_t crc; 558 559 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 560 return (crc & ((1 << HASH_BITS) - 1)); 561 } 562 563 static void 564 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 565 { 566 int base; 567 568 base = XM_RXFILT_ENTRY(slot); 569 570 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 571 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 572 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 573 } 574 575 static void 576 sk_setmulti(struct sk_if_softc *sc_if) 577 { 578 struct sk_softc *sc = sc_if->sk_softc; 579 struct ifnet *ifp = &sc_if->arpcom.ac_if; 580 uint32_t hashes[2] = { 0, 0 }; 581 int h = 0, i; 582 struct ifmultiaddr *ifma; 583 uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 584 585 /* First, zot all the existing filters. */ 586 switch(sc->sk_type) { 587 case SK_GENESIS: 588 for (i = 1; i < XM_RXFILT_MAX; i++) 589 sk_setfilt(sc_if, (caddr_t)&dummy, i); 590 591 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 592 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 593 break; 594 case SK_YUKON: 595 case SK_YUKON_LITE: 596 case SK_YUKON_LP: 597 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 598 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 599 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 600 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 601 break; 602 } 603 604 /* Now program new ones. */ 605 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 606 hashes[0] = 0xFFFFFFFF; 607 hashes[1] = 0xFFFFFFFF; 608 } else { 609 i = 1; 610 /* First find the tail of the list. */ 611 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 612 if (ifma->ifma_link.le_next == NULL) 613 break; 614 } 615 /* Now traverse the list backwards. */ 616 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 617 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 618 caddr_t maddr; 619 620 if (ifma->ifma_addr->sa_family != AF_LINK) 621 continue; 622 623 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 624 625 /* 626 * Program the first XM_RXFILT_MAX multicast groups 627 * into the perfect filter. For all others, 628 * use the hash table. 629 */ 630 if (SK_IS_GENESIS(sc) && i < XM_RXFILT_MAX) { 631 sk_setfilt(sc_if, maddr, i); 632 i++; 633 continue; 634 } 635 636 switch(sc->sk_type) { 637 case SK_GENESIS: 638 h = sk_xmac_hash(maddr); 639 break; 640 641 case SK_YUKON: 642 case SK_YUKON_LITE: 643 case SK_YUKON_LP: 644 h = sk_yukon_hash(maddr); 645 break; 646 } 647 if (h < 32) 648 hashes[0] |= (1 << h); 649 else 650 hashes[1] |= (1 << (h - 32)); 651 } 652 } 653 654 switch(sc->sk_type) { 655 case SK_GENESIS: 656 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 657 XM_MODE_RX_USE_PERFECT); 658 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 659 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 660 break; 661 case SK_YUKON: 662 case SK_YUKON_LITE: 663 case SK_YUKON_LP: 664 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 665 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 666 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 667 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 668 break; 669 } 670 } 671 672 static void 673 sk_setpromisc(struct sk_if_softc *sc_if) 674 { 675 struct sk_softc *sc = sc_if->sk_softc; 676 struct ifnet *ifp = &sc_if->arpcom.ac_if; 677 678 switch(sc->sk_type) { 679 case SK_GENESIS: 680 if (ifp->if_flags & IFF_PROMISC) 681 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 682 else 683 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 684 break; 685 case SK_YUKON: 686 case SK_YUKON_LITE: 687 case SK_YUKON_LP: 688 if (ifp->if_flags & IFF_PROMISC) { 689 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 690 YU_RCR_UFLEN | YU_RCR_MUFLEN); 691 } else { 692 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 693 YU_RCR_UFLEN | YU_RCR_MUFLEN); 694 } 695 break; 696 } 697 } 698 699 static int 700 sk_init_rx_ring(struct sk_if_softc *sc_if) 701 { 702 struct sk_chain_data *cd = &sc_if->sk_cdata; 703 struct sk_ring_data *rd = sc_if->sk_rdata; 704 int i, nexti, error; 705 706 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 707 708 for (i = 0; i < SK_RX_RING_CNT; i++) { 709 if (i == (SK_RX_RING_CNT - 1)) 710 nexti = 0; 711 else 712 nexti = i + 1; 713 rd->sk_rx_ring[i].sk_next = 714 htole32(SK_RX_RING_ADDR(sc_if, nexti)); 715 rd->sk_rx_ring[i].sk_csum1_start = htole16(ETHER_HDR_LEN); 716 rd->sk_rx_ring[i].sk_csum2_start = 717 htole16(ETHER_HDR_LEN + sizeof(struct ip)); 718 719 error = sk_newbuf(sc_if, i, 1); 720 if (error) { 721 if_printf(&sc_if->arpcom.ac_if, 722 "failed alloc of %dth mbuf\n", i); 723 return error; 724 } 725 } 726 727 cd->sk_rx_prod = 0; 728 cd->sk_rx_cons = 0; 729 730 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 731 BUS_DMASYNC_PREWRITE); 732 733 return (0); 734 } 735 736 static int 737 sk_init_tx_ring(struct sk_if_softc *sc_if) 738 { 739 struct sk_ring_data *rd = sc_if->sk_rdata; 740 int i, nexti; 741 742 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 743 744 for (i = 0; i < SK_TX_RING_CNT; i++) { 745 if (i == (SK_TX_RING_CNT - 1)) 746 nexti = 0; 747 else 748 nexti = i + 1; 749 rd->sk_tx_ring[i].sk_next = htole32(SK_TX_RING_ADDR(sc_if, nexti)); 750 } 751 752 sc_if->sk_cdata.sk_tx_prod = 0; 753 sc_if->sk_cdata.sk_tx_cons = 0; 754 sc_if->sk_cdata.sk_tx_cnt = 0; 755 756 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 757 BUS_DMASYNC_PREWRITE); 758 759 return (0); 760 } 761 762 static int 763 sk_newbuf_jumbo(struct sk_if_softc *sc_if, int idx, int wait) 764 { 765 struct sk_jpool_entry *entry; 766 struct mbuf *m_new = NULL; 767 struct sk_rx_desc *r; 768 769 KKASSERT(idx < SK_RX_RING_CNT && idx >= 0); 770 771 MGETHDR(m_new, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA); 772 if (m_new == NULL) 773 return ENOBUFS; 774 775 /* Allocate the jumbo buffer */ 776 entry = sk_jalloc(sc_if); 777 if (entry == NULL) { 778 m_freem(m_new); 779 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 780 "dropped!\n", sc_if->arpcom.ac_if.if_xname)); 781 return ENOBUFS; 782 } 783 784 m_new->m_ext.ext_arg = entry; 785 m_new->m_ext.ext_buf = entry->buf; 786 m_new->m_ext.ext_free = sk_jfree; 787 m_new->m_ext.ext_ref = sk_jref; 788 m_new->m_ext.ext_size = SK_JLEN; 789 790 m_new->m_flags |= M_EXT; 791 792 m_new->m_data = m_new->m_ext.ext_buf; 793 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 794 795 /* 796 * Adjust alignment so packet payload begins on a 797 * longword boundary. Mandatory for Alpha, useful on 798 * x86 too. 799 */ 800 m_adj(m_new, ETHER_ALIGN); 801 802 sc_if->sk_cdata.sk_rx_mbuf[idx] = m_new; 803 804 r = &sc_if->sk_rdata->sk_rx_ring[idx]; 805 r->sk_data_lo = htole32(entry->paddr + ETHER_ALIGN); 806 r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT); 807 808 return 0; 809 } 810 811 static int 812 sk_newbuf_std(struct sk_if_softc *sc_if, int idx, int wait) 813 { 814 struct mbuf *m_new = NULL; 815 struct sk_chain_data *cd = &sc_if->sk_cdata; 816 struct sk_rx_desc *r; 817 struct sk_dma_ctx ctx; 818 bus_dma_segment_t seg; 819 bus_dmamap_t map; 820 int error; 821 822 KKASSERT(idx < SK_RX_RING_CNT && idx >= 0); 823 824 m_new = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 825 if (m_new == NULL) 826 return ENOBUFS; 827 828 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 829 830 /* 831 * Adjust alignment so packet payload begins on a 832 * longword boundary. Mandatory for Alpha, useful on 833 * x86 too. 834 */ 835 m_adj(m_new, ETHER_ALIGN); 836 837 bzero(&ctx, sizeof(ctx)); 838 ctx.nsegs = 1; 839 ctx.segs = &seg; 840 error = bus_dmamap_load_mbuf(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp, 841 m_new, sk_buf_dma_addr, &ctx, 842 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT); 843 if (error) { 844 if_printf(&sc_if->arpcom.ac_if, "could not map RX mbuf\n"); 845 m_freem(m_new); 846 return error; 847 } 848 849 /* Unload originally mapped mbuf */ 850 if (cd->sk_rx_mbuf[idx] != NULL) 851 bus_dmamap_unload(cd->sk_rx_dtag, cd->sk_rx_dmap[idx]); 852 853 /* Switch DMA map with tmp DMA map */ 854 map = cd->sk_rx_dmap_tmp; 855 cd->sk_rx_dmap_tmp = cd->sk_rx_dmap[idx]; 856 cd->sk_rx_dmap[idx] = map; 857 858 cd->sk_rx_mbuf[idx] = m_new; 859 860 r = &sc_if->sk_rdata->sk_rx_ring[idx]; 861 r->sk_data_lo = htole32(seg.ds_addr); 862 r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT); 863 864 return 0; 865 } 866 867 /* 868 * Allocate a jumbo buffer. 869 */ 870 struct sk_jpool_entry * 871 sk_jalloc(struct sk_if_softc *sc_if) 872 { 873 struct sk_chain_data *cd = &sc_if->sk_cdata; 874 struct sk_jpool_entry *entry; 875 876 lwkt_serialize_enter(&cd->sk_jpool_serializer); 877 878 entry = SLIST_FIRST(&cd->sk_jpool_free_ent); 879 if (entry != NULL) { 880 SLIST_REMOVE_HEAD(&cd->sk_jpool_free_ent, entry_next); 881 entry->inuse = 1; 882 } else { 883 DPRINTF(("no free jumbo buffer\n")); 884 } 885 886 lwkt_serialize_exit(&cd->sk_jpool_serializer); 887 return entry; 888 } 889 890 /* 891 * Release a jumbo buffer. 892 */ 893 void 894 sk_jfree(void *arg) 895 { 896 struct sk_jpool_entry *entry = arg; 897 struct sk_chain_data *cd = &entry->sc_if->sk_cdata; 898 899 if (&cd->sk_jpool_ent[entry->slot] != entry) 900 panic("%s: free wrong jumbo buffer\n", __func__); 901 else if (entry->inuse == 0) 902 panic("%s: jumbo buffer already freed\n", __func__); 903 904 lwkt_serialize_enter(&cd->sk_jpool_serializer); 905 906 atomic_subtract_int(&entry->inuse, 1); 907 if (entry->inuse == 0) 908 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next); 909 910 lwkt_serialize_exit(&cd->sk_jpool_serializer); 911 } 912 913 static void 914 sk_jref(void *arg) 915 { 916 struct sk_jpool_entry *entry = arg; 917 struct sk_chain_data *cd = &entry->sc_if->sk_cdata; 918 919 if (&cd->sk_jpool_ent[entry->slot] != entry) 920 panic("%s: free wrong jumbo buffer\n", __func__); 921 else if (entry->inuse == 0) 922 panic("%s: jumbo buffer already freed\n", __func__); 923 924 atomic_add_int(&entry->inuse, 1); 925 } 926 927 /* 928 * Set media options. 929 */ 930 static int 931 sk_ifmedia_upd(struct ifnet *ifp) 932 { 933 struct sk_if_softc *sc_if = ifp->if_softc; 934 struct mii_data *mii; 935 936 mii = device_get_softc(sc_if->sk_miibus); 937 sk_init(sc_if); 938 mii_mediachg(mii); 939 940 return(0); 941 } 942 943 /* 944 * Report current media status. 945 */ 946 static void 947 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 948 { 949 struct sk_if_softc *sc_if; 950 struct mii_data *mii; 951 952 sc_if = ifp->if_softc; 953 mii = device_get_softc(sc_if->sk_miibus); 954 955 mii_pollstat(mii); 956 ifmr->ifm_active = mii->mii_media_active; 957 ifmr->ifm_status = mii->mii_media_status; 958 } 959 960 static int 961 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 962 { 963 struct sk_if_softc *sc_if = ifp->if_softc; 964 struct ifreq *ifr = (struct ifreq *)data; 965 struct mii_data *mii; 966 int error = 0; 967 968 ASSERT_SERIALIZED(ifp->if_serializer); 969 970 switch(command) { 971 case SIOCSIFMTU: 972 if (ifr->ifr_mtu > SK_JUMBO_MTU) 973 error = EINVAL; 974 else { 975 ifp->if_mtu = ifr->ifr_mtu; 976 ifp->if_flags &= ~IFF_RUNNING; 977 sk_init(sc_if); 978 } 979 break; 980 case SIOCSIFFLAGS: 981 if (ifp->if_flags & IFF_UP) { 982 if (ifp->if_flags & IFF_RUNNING) { 983 if ((ifp->if_flags ^ sc_if->sk_if_flags) 984 & IFF_PROMISC) { 985 sk_setpromisc(sc_if); 986 sk_setmulti(sc_if); 987 } 988 } else 989 sk_init(sc_if); 990 } else { 991 if (ifp->if_flags & IFF_RUNNING) 992 sk_stop(sc_if); 993 } 994 sc_if->sk_if_flags = ifp->if_flags; 995 break; 996 case SIOCADDMULTI: 997 case SIOCDELMULTI: 998 sk_setmulti(sc_if); 999 break; 1000 case SIOCGIFMEDIA: 1001 case SIOCSIFMEDIA: 1002 mii = device_get_softc(sc_if->sk_miibus); 1003 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1004 break; 1005 default: 1006 error = ether_ioctl(ifp, command, data); 1007 break; 1008 } 1009 1010 return(error); 1011 } 1012 1013 /* 1014 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1015 * IDs against our list and return a device name if we find a match. 1016 */ 1017 static int 1018 skc_probe(device_t dev) 1019 { 1020 const struct skc_type *t; 1021 uint16_t vid, did; 1022 1023 vid = pci_get_vendor(dev); 1024 did = pci_get_device(dev); 1025 1026 /* 1027 * Only attach to rev.2 of the Linksys EG1032 adapter. 1028 * Rev.3 is supported by re(4). 1029 */ 1030 if (vid == PCI_VENDOR_LINKSYS && 1031 did == PCI_PRODUCT_LINKSYS_EG1032 && 1032 pci_get_subdevice(dev) != SUBDEVICEID_LINKSYS_EG1032_REV2) 1033 return ENXIO; 1034 1035 for (t = skc_devs; t->skc_name != NULL; t++) { 1036 if (vid == t->skc_vid && did == t->skc_did) { 1037 device_set_desc(dev, t->skc_name); 1038 return 0; 1039 } 1040 } 1041 return ENXIO; 1042 } 1043 1044 /* 1045 * Force the GEnesis into reset, then bring it out of reset. 1046 */ 1047 static void 1048 sk_reset(struct sk_softc *sc) 1049 { 1050 DPRINTFN(2, ("sk_reset\n")); 1051 1052 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1053 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1054 if (SK_IS_YUKON(sc)) 1055 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1056 1057 DELAY(1000); 1058 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1059 DELAY(2); 1060 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1061 if (SK_IS_YUKON(sc)) 1062 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1063 1064 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1065 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1066 CSR_READ_2(sc, SK_LINK_CTRL))); 1067 1068 if (SK_IS_GENESIS(sc)) { 1069 /* Configure packet arbiter */ 1070 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1071 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1072 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1073 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1074 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1075 } 1076 1077 /* Enable RAM interface */ 1078 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1079 1080 /* 1081 * Configure interrupt moderation. The moderation timer 1082 * defers interrupts specified in the interrupt moderation 1083 * timer mask based on the timeout specified in the interrupt 1084 * moderation timer init register. Each bit in the timer 1085 * register represents one tick, so to specify a timeout in 1086 * microseconds, we have to multiply by the correct number of 1087 * ticks-per-microsecond. 1088 */ 1089 KKASSERT(sc->sk_imtimer_ticks != 0 && sc->sk_imtime != 0); 1090 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc, sc->sk_imtime)); 1091 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1092 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1093 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1094 } 1095 1096 static int 1097 sk_probe(device_t dev) 1098 { 1099 struct sk_softc *sc = device_get_softc(device_get_parent(dev)); 1100 const char *revstr = "", *name = NULL; 1101 char devname[80]; 1102 1103 switch (sc->sk_type) { 1104 case SK_GENESIS: 1105 name = "SysKonnect GEnesis"; 1106 break; 1107 case SK_YUKON: 1108 name = "Marvell Yukon"; 1109 break; 1110 case SK_YUKON_LITE: 1111 name = "Marvell Yukon Lite"; 1112 switch (sc->sk_rev) { 1113 case SK_YUKON_LITE_REV_A0: 1114 revstr = " rev.A0"; 1115 break; 1116 case SK_YUKON_LITE_REV_A1: 1117 revstr = " rev.A1"; 1118 break; 1119 case SK_YUKON_LITE_REV_A3: 1120 revstr = " rev.A3"; 1121 break; 1122 } 1123 break; 1124 case SK_YUKON_LP: 1125 name = "Marvell Yukon LP"; 1126 break; 1127 default: 1128 return ENXIO; 1129 } 1130 1131 ksnprintf(devname, sizeof(devname), "%s%s (0x%x)", 1132 name, revstr, sc->sk_rev); 1133 device_set_desc_copy(dev, devname); 1134 return 0; 1135 } 1136 1137 /* 1138 * Each XMAC chip is attached as a separate logical IP interface. 1139 * Single port cards will have only one logical interface of course. 1140 */ 1141 static int 1142 sk_attach(device_t dev) 1143 { 1144 struct sk_softc *sc = device_get_softc(device_get_parent(dev)); 1145 struct sk_if_softc *sc_if = device_get_softc(dev); 1146 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1147 int i, error; 1148 1149 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1150 1151 sc_if->sk_port = *(int *)device_get_ivars(dev); 1152 KKASSERT(sc_if->sk_port == SK_PORT_A || sc_if->sk_port == SK_PORT_B); 1153 1154 sc_if->sk_softc = sc; 1155 sc->sk_if[sc_if->sk_port] = sc_if; 1156 1157 kfree(device_get_ivars(dev), M_DEVBUF); 1158 device_set_ivars(dev, NULL); 1159 1160 if (sc_if->sk_port == SK_PORT_A) 1161 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1162 if (sc_if->sk_port == SK_PORT_B) 1163 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1164 1165 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1166 1167 /* 1168 * Get station address for this interface. Note that 1169 * dual port cards actually come with three station 1170 * addresses: one for each port, plus an extra. The 1171 * extra one is used by the SysKonnect driver software 1172 * as a 'virtual' station address for when both ports 1173 * are operating in failover mode. Currently we don't 1174 * use this extra address. 1175 */ 1176 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1177 /* XXX */ 1178 sc_if->arpcom.ac_enaddr[i] = 1179 sk_win_read_1(sc, SK_MAC0_0 + (sc_if->sk_port * 8) + i); 1180 } 1181 1182 /* 1183 * Set up RAM buffer addresses. The NIC will have a certain 1184 * amount of SRAM on it, somewhere between 512K and 2MB. We 1185 * need to divide this up a) between the transmitter and 1186 * receiver and b) between the two XMACs, if this is a 1187 * dual port NIC. Our algorithm is to divide up the memory 1188 * evenly so that everyone gets a fair share. 1189 */ 1190 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1191 uint32_t chunk, val; 1192 1193 chunk = sc->sk_ramsize / 2; 1194 val = sc->sk_rboff / sizeof(uint64_t); 1195 sc_if->sk_rx_ramstart = val; 1196 val += (chunk / sizeof(uint64_t)); 1197 sc_if->sk_rx_ramend = val - 1; 1198 sc_if->sk_tx_ramstart = val; 1199 val += (chunk / sizeof(uint64_t)); 1200 sc_if->sk_tx_ramend = val - 1; 1201 } else { 1202 uint32_t chunk, val; 1203 1204 chunk = sc->sk_ramsize / 4; 1205 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1206 sizeof(uint64_t); 1207 sc_if->sk_rx_ramstart = val; 1208 val += (chunk / sizeof(uint64_t)); 1209 sc_if->sk_rx_ramend = val - 1; 1210 sc_if->sk_tx_ramstart = val; 1211 val += (chunk / sizeof(uint64_t)); 1212 sc_if->sk_tx_ramend = val - 1; 1213 } 1214 1215 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1216 " tx_ramstart=%#x tx_ramend=%#x\n", 1217 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1218 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1219 1220 /* Read and save PHY type */ 1221 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1222 1223 /* Set PHY address */ 1224 if (SK_IS_GENESIS(sc)) { 1225 switch (sc_if->sk_phytype) { 1226 case SK_PHYTYPE_XMAC: 1227 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1228 break; 1229 case SK_PHYTYPE_BCOM: 1230 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1231 break; 1232 default: 1233 device_printf(dev, "unsupported PHY type: %d\n", 1234 sc_if->sk_phytype); 1235 error = ENXIO; 1236 goto fail; 1237 } 1238 } 1239 1240 if (SK_IS_YUKON(sc)) { 1241 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1242 sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) { 1243 /* not initialized, punt */ 1244 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1245 sc->sk_coppertype = 1; 1246 } 1247 1248 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1249 1250 if (!(sc->sk_coppertype)) 1251 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 1252 } 1253 1254 error = sk_dma_alloc(dev); 1255 if (error) 1256 goto fail; 1257 1258 ifp->if_softc = sc_if; 1259 ifp->if_mtu = ETHERMTU; 1260 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1261 ifp->if_ioctl = sk_ioctl; 1262 ifp->if_start = sk_start; 1263 ifp->if_watchdog = sk_watchdog; 1264 ifp->if_init = sk_init; 1265 ifp->if_baudrate = 1000000000; 1266 ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1); 1267 ifq_set_ready(&ifp->if_snd); 1268 1269 ifp->if_capabilities = IFCAP_VLAN_MTU; 1270 1271 /* Don't use jumbo buffers by default */ 1272 sc_if->sk_use_jumbo = 0; 1273 1274 /* 1275 * Do miibus setup. 1276 */ 1277 switch (sc->sk_type) { 1278 case SK_GENESIS: 1279 sk_init_xmac(sc_if); 1280 break; 1281 case SK_YUKON: 1282 case SK_YUKON_LITE: 1283 case SK_YUKON_LP: 1284 sk_init_yukon(sc_if); 1285 break; 1286 default: 1287 device_printf(dev, "unknown device type %d\n", sc->sk_type); 1288 error = ENXIO; 1289 goto fail; 1290 } 1291 1292 DPRINTFN(2, ("sk_attach: 1\n")); 1293 1294 error = mii_phy_probe(dev, &sc_if->sk_miibus, 1295 sk_ifmedia_upd, sk_ifmedia_sts); 1296 if (error) { 1297 device_printf(dev, "no PHY found!\n"); 1298 goto fail; 1299 } 1300 1301 callout_init(&sc_if->sk_tick_timer); 1302 1303 /* 1304 * Call MI attach routines. 1305 */ 1306 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr, &sc->sk_serializer); 1307 1308 DPRINTFN(2, ("sk_attach: end\n")); 1309 return 0; 1310 fail: 1311 sk_detach(dev); 1312 sc->sk_if[sc_if->sk_port] = NULL; 1313 return error; 1314 } 1315 1316 /* 1317 * Attach the interface. Allocate softc structures, do ifmedia 1318 * setup and ethernet/BPF attach. 1319 */ 1320 static int 1321 skc_attach(device_t dev) 1322 { 1323 struct sk_softc *sc = device_get_softc(dev); 1324 uint8_t skrs; 1325 int *port; 1326 int error, cpuid; 1327 1328 DPRINTFN(2, ("begin skc_attach\n")); 1329 1330 sc->sk_dev = dev; 1331 lwkt_serialize_init(&sc->sk_serializer); 1332 1333 #ifndef BURN_BRIDGES 1334 /* 1335 * Handle power management nonsense. 1336 */ 1337 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1338 uint32_t iobase, membase, irq; 1339 1340 /* Save important PCI config data. */ 1341 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1342 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1343 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1344 1345 /* Reset the power state. */ 1346 device_printf(dev, "chip is in D%d power mode " 1347 "-- setting to D0\n", pci_get_powerstate(dev)); 1348 1349 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1350 1351 /* Restore PCI config data. */ 1352 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1353 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1354 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1355 } 1356 #endif /* BURN_BRIDGES */ 1357 1358 /* 1359 * Map control/status registers. 1360 */ 1361 pci_enable_busmaster(dev); 1362 1363 sc->sk_res_rid = SK_PCI_LOMEM; 1364 sc->sk_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1365 &sc->sk_res_rid, RF_ACTIVE); 1366 if (sc->sk_res == NULL) { 1367 device_printf(dev, "couldn't map memory\n"); 1368 error = ENXIO; 1369 goto fail; 1370 } 1371 sc->sk_btag = rman_get_bustag(sc->sk_res); 1372 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1373 1374 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1375 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1376 1377 /* Bail out here if chip is not recognized */ 1378 if (!SK_IS_GENESIS(sc) && !SK_IS_YUKON(sc)) { 1379 device_printf(dev, "unknown chip type: %d\n", sc->sk_type); 1380 error = ENXIO; 1381 goto fail; 1382 } 1383 1384 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1385 1386 /* Allocate interrupt */ 1387 sc->sk_irq_rid = 0; 1388 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sk_irq_rid, 1389 RF_SHAREABLE | RF_ACTIVE); 1390 if (sc->sk_irq == NULL) { 1391 device_printf(dev, "couldn't map interrupt\n"); 1392 error = ENXIO; 1393 goto fail; 1394 } 1395 1396 switch (sc->sk_type) { 1397 case SK_GENESIS: 1398 sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1399 break; 1400 default: 1401 sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1402 break; 1403 } 1404 sc->sk_imtime = skc_imtime; 1405 1406 /* Reset the adapter. */ 1407 sk_reset(sc); 1408 1409 skrs = sk_win_read_1(sc, SK_EPROM0); 1410 if (SK_IS_GENESIS(sc)) { 1411 /* Read and save RAM size and RAMbuffer offset */ 1412 switch(skrs) { 1413 case SK_RAMSIZE_512K_64: 1414 sc->sk_ramsize = 0x80000; 1415 sc->sk_rboff = SK_RBOFF_0; 1416 break; 1417 case SK_RAMSIZE_1024K_64: 1418 sc->sk_ramsize = 0x100000; 1419 sc->sk_rboff = SK_RBOFF_80000; 1420 break; 1421 case SK_RAMSIZE_1024K_128: 1422 sc->sk_ramsize = 0x100000; 1423 sc->sk_rboff = SK_RBOFF_0; 1424 break; 1425 case SK_RAMSIZE_2048K_128: 1426 sc->sk_ramsize = 0x200000; 1427 sc->sk_rboff = SK_RBOFF_0; 1428 break; 1429 default: 1430 device_printf(dev, "unknown ram size: %d\n", skrs); 1431 error = ENXIO; 1432 goto fail; 1433 } 1434 } else { 1435 if (skrs == 0x00) 1436 sc->sk_ramsize = 0x20000; 1437 else 1438 sc->sk_ramsize = skrs * (1<<12); 1439 sc->sk_rboff = SK_RBOFF_0; 1440 } 1441 1442 DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n", 1443 sc->sk_ramsize, sc->sk_ramsize / 1024, 1444 sc->sk_rboff)); 1445 1446 /* Read and save physical media type */ 1447 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1448 1449 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1') 1450 sc->sk_coppertype = 1; 1451 else 1452 sc->sk_coppertype = 0; 1453 1454 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1455 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1456 uint32_t flashaddr; 1457 uint8_t testbyte; 1458 1459 flashaddr = sk_win_read_4(sc, SK_EP_ADDR); 1460 1461 /* Test Flash-Address Register */ 1462 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff); 1463 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1464 1465 if (testbyte != 0) { 1466 /* This is a Yukon Lite Rev A0 */ 1467 sc->sk_type = SK_YUKON_LITE; 1468 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1469 /* Restore Flash-Address Register */ 1470 sk_win_write_4(sc, SK_EP_ADDR, flashaddr); 1471 } 1472 } 1473 1474 /* 1475 * Create sysctl nodes. 1476 */ 1477 sysctl_ctx_init(&sc->sk_sysctl_ctx); 1478 sc->sk_sysctl_tree = SYSCTL_ADD_NODE(&sc->sk_sysctl_ctx, 1479 SYSCTL_STATIC_CHILDREN(_hw), 1480 OID_AUTO, 1481 device_get_nameunit(dev), 1482 CTLFLAG_RD, 0, ""); 1483 if (sc->sk_sysctl_tree == NULL) { 1484 device_printf(dev, "can't add sysctl node\n"); 1485 error = ENXIO; 1486 goto fail; 1487 } 1488 SYSCTL_ADD_PROC(&sc->sk_sysctl_ctx, 1489 SYSCTL_CHILDREN(sc->sk_sysctl_tree), 1490 OID_AUTO, "imtime", CTLTYPE_INT | CTLFLAG_RW, 1491 sc, 0, skc_sysctl_imtime, "I", 1492 "Interrupt moderation time (usec)."); 1493 1494 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1495 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK); 1496 *port = SK_PORT_A; 1497 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1498 1499 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1500 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1501 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK); 1502 *port = SK_PORT_B; 1503 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1504 } 1505 1506 /* Turn on the 'driver is loaded' LED. */ 1507 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1508 1509 bus_generic_attach(dev); 1510 1511 error = bus_setup_intr(dev, sc->sk_irq, INTR_NETSAFE, sk_intr, sc, 1512 &sc->sk_intrhand, &sc->sk_serializer); 1513 if (error) { 1514 device_printf(dev, "couldn't set up irq\n"); 1515 goto fail; 1516 } 1517 1518 cpuid = ithread_cpuid(rman_get_start(sc->sk_irq)); 1519 KKASSERT(cpuid >= 0 && cpuid < ncpus); 1520 1521 if (sc->sk_if[0] != NULL) 1522 sc->sk_if[0]->arpcom.ac_if.if_cpuid = cpuid; 1523 if (sc->sk_if[1] != NULL) 1524 sc->sk_if[1]->arpcom.ac_if.if_cpuid = cpuid; 1525 1526 return 0; 1527 fail: 1528 skc_detach(dev); 1529 return error; 1530 } 1531 1532 static int 1533 sk_detach(device_t dev) 1534 { 1535 struct sk_if_softc *sc_if = device_get_softc(dev); 1536 1537 if (device_is_attached(dev)) { 1538 struct sk_softc *sc = sc_if->sk_softc; 1539 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1540 1541 lwkt_serialize_enter(ifp->if_serializer); 1542 1543 if (sc->sk_intrhand != NULL) { 1544 if (sc->sk_if[SK_PORT_A] != NULL) 1545 sk_stop(sc->sk_if[SK_PORT_A]); 1546 if (sc->sk_if[SK_PORT_B] != NULL) 1547 sk_stop(sc->sk_if[SK_PORT_B]); 1548 1549 bus_teardown_intr(sc->sk_dev, sc->sk_irq, 1550 sc->sk_intrhand); 1551 sc->sk_intrhand = NULL; 1552 } 1553 1554 lwkt_serialize_exit(ifp->if_serializer); 1555 1556 ether_ifdetach(ifp); 1557 } 1558 1559 if (sc_if->sk_miibus != NULL) 1560 device_delete_child(dev, sc_if->sk_miibus); 1561 1562 sk_dma_free(dev); 1563 return 0; 1564 } 1565 1566 static int 1567 skc_detach(device_t dev) 1568 { 1569 struct sk_softc *sc = device_get_softc(dev); 1570 int *port; 1571 1572 #ifdef INVARIANTS 1573 if (device_is_attached(dev)) { 1574 KASSERT(sc->sk_intrhand == NULL, 1575 ("intr has not been torn down yet")); 1576 } 1577 #endif 1578 1579 if (sc->sk_devs[SK_PORT_A] != NULL) { 1580 port = device_get_ivars(sc->sk_devs[SK_PORT_A]); 1581 if (port != NULL) { 1582 kfree(port, M_DEVBUF); 1583 device_set_ivars(sc->sk_devs[SK_PORT_A], NULL); 1584 } 1585 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1586 } 1587 if (sc->sk_devs[SK_PORT_B] != NULL) { 1588 port = device_get_ivars(sc->sk_devs[SK_PORT_B]); 1589 if (port != NULL) { 1590 kfree(port, M_DEVBUF); 1591 device_set_ivars(sc->sk_devs[SK_PORT_B], NULL); 1592 } 1593 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1594 } 1595 1596 if (sc->sk_irq != NULL) { 1597 bus_release_resource(dev, SYS_RES_IRQ, sc->sk_irq_rid, 1598 sc->sk_irq); 1599 } 1600 if (sc->sk_res != NULL) { 1601 bus_release_resource(dev, SYS_RES_MEMORY, sc->sk_res_rid, 1602 sc->sk_res); 1603 } 1604 1605 if (sc->sk_sysctl_tree != NULL) 1606 sysctl_ctx_free(&sc->sk_sysctl_ctx); 1607 1608 return 0; 1609 } 1610 1611 static int 1612 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1613 { 1614 struct sk_chain_data *cd = &sc_if->sk_cdata; 1615 struct sk_ring_data *rd = sc_if->sk_rdata; 1616 struct sk_tx_desc *f = NULL; 1617 uint32_t frag, cur, sk_ctl; 1618 struct sk_dma_ctx ctx; 1619 bus_dma_segment_t segs[SK_NTXSEG]; 1620 bus_dmamap_t map; 1621 int i, error; 1622 1623 DPRINTFN(2, ("sk_encap\n")); 1624 1625 cur = frag = *txidx; 1626 1627 #ifdef SK_DEBUG 1628 if (skdebug >= 2) 1629 sk_dump_mbuf(m_head); 1630 #endif 1631 1632 map = cd->sk_tx_dmap[*txidx]; 1633 1634 /* 1635 * Start packing the mbufs in this chain into 1636 * the fragment pointers. Stop when we run out 1637 * of fragments or hit the end of the mbuf chain. 1638 */ 1639 ctx.nsegs = SK_NTXSEG; 1640 ctx.segs = segs; 1641 error = bus_dmamap_load_mbuf(cd->sk_tx_dtag, map, m_head, 1642 sk_buf_dma_addr, &ctx, BUS_DMA_NOWAIT); 1643 if (error) { 1644 if_printf(&sc_if->arpcom.ac_if, "could not map TX mbuf\n"); 1645 return ENOBUFS; 1646 } 1647 1648 if ((SK_TX_RING_CNT - (cd->sk_tx_cnt + ctx.nsegs)) < 2) { 1649 bus_dmamap_unload(cd->sk_tx_dtag, map); 1650 DPRINTFN(2, ("sk_encap: too few descriptors free\n")); 1651 return ENOBUFS; 1652 } 1653 1654 DPRINTFN(2, ("sk_encap: nsegs=%d\n", ctx.nsegs)); 1655 1656 /* Sync the DMA map. */ 1657 bus_dmamap_sync(cd->sk_tx_dtag, map, BUS_DMASYNC_PREWRITE); 1658 1659 for (i = 0; i < ctx.nsegs; i++) { 1660 f = &rd->sk_tx_ring[frag]; 1661 f->sk_data_lo = htole32(segs[i].ds_addr); 1662 sk_ctl = segs[i].ds_len | SK_OPCODE_DEFAULT; 1663 if (i == 0) 1664 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1665 else 1666 sk_ctl |= SK_TXCTL_OWN; 1667 f->sk_ctl = htole32(sk_ctl); 1668 cur = frag; 1669 SK_INC(frag, SK_TX_RING_CNT); 1670 } 1671 1672 cd->sk_tx_mbuf[cur] = m_head; 1673 /* Switch DMA map */ 1674 cd->sk_tx_dmap[*txidx] = cd->sk_tx_dmap[cur]; 1675 cd->sk_tx_dmap[cur] = map; 1676 1677 rd->sk_tx_ring[cur].sk_ctl |= 1678 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1679 rd->sk_tx_ring[*txidx].sk_ctl |= htole32(SK_TXCTL_OWN); 1680 1681 /* Sync first descriptor to hand it off */ 1682 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 1683 BUS_DMASYNC_PREWRITE); 1684 1685 sc_if->sk_cdata.sk_tx_cnt += ctx.nsegs; 1686 1687 #ifdef SK_DEBUG 1688 if (skdebug >= 2) { 1689 struct sk_tx_desc *desc; 1690 uint32_t idx; 1691 1692 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1693 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1694 sk_dump_txdesc(desc, idx); 1695 } 1696 } 1697 #endif 1698 1699 *txidx = frag; 1700 1701 DPRINTFN(2, ("sk_encap: completed successfully\n")); 1702 1703 return (0); 1704 } 1705 1706 static void 1707 sk_start(struct ifnet *ifp) 1708 { 1709 struct sk_if_softc *sc_if = ifp->if_softc; 1710 struct sk_softc *sc = sc_if->sk_softc; 1711 struct mbuf *m_head = NULL; 1712 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1713 int pkts = 0; 1714 1715 DPRINTFN(2, ("sk_start\n")); 1716 1717 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1718 return; 1719 1720 while (sc_if->sk_cdata.sk_tx_mbuf[idx] == NULL) { 1721 if ((SK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt) <= 2) { 1722 ifp->if_flags |= IFF_OACTIVE; 1723 break; 1724 } 1725 1726 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1727 if (m_head == NULL) 1728 break; 1729 1730 /* 1731 * Pack the data into the transmit ring. If we 1732 * don't have room, set the OACTIVE flag and wait 1733 * for the NIC to drain the ring. 1734 */ 1735 if (sk_encap(sc_if, m_head, &idx)) { 1736 ifp->if_flags |= IFF_OACTIVE; 1737 ifq_prepend(&ifp->if_snd, m_head); 1738 break; 1739 } 1740 1741 pkts++; 1742 BPF_MTAP(ifp, m_head); 1743 } 1744 if (pkts == 0) 1745 return; 1746 1747 /* Transmit */ 1748 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1749 sc_if->sk_cdata.sk_tx_prod = idx; 1750 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1751 1752 /* Set a timeout in case the chip goes out to lunch. */ 1753 ifp->if_timer = 5; 1754 } 1755 } 1756 1757 static void 1758 sk_watchdog(struct ifnet *ifp) 1759 { 1760 struct sk_if_softc *sc_if = ifp->if_softc; 1761 1762 ASSERT_SERIALIZED(ifp->if_serializer); 1763 /* 1764 * Reclaim first as there is a possibility of losing Tx completion 1765 * interrupts. 1766 */ 1767 sk_txeof(sc_if); 1768 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1769 if_printf(&sc_if->arpcom.ac_if, "watchdog timeout\n"); 1770 ifp->if_oerrors++; 1771 ifp->if_flags &= ~IFF_RUNNING; 1772 sk_init(sc_if); 1773 } 1774 } 1775 1776 static void 1777 skc_shutdown(device_t dev) 1778 { 1779 struct sk_softc *sc = device_get_softc(dev); 1780 1781 DPRINTFN(2, ("sk_shutdown\n")); 1782 1783 lwkt_serialize_enter(&sc->sk_serializer); 1784 1785 /* Turn off the 'driver is loaded' LED. */ 1786 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1787 1788 /* 1789 * Reset the GEnesis controller. Doing this should also 1790 * assert the resets on the attached XMAC(s). 1791 */ 1792 sk_reset(sc); 1793 1794 lwkt_serialize_exit(&sc->sk_serializer); 1795 } 1796 1797 static __inline int 1798 sk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len) 1799 { 1800 if (sc->sk_type == SK_GENESIS) { 1801 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 1802 XM_RXSTAT_BYTES(stat) != len) 1803 return (0); 1804 } else { 1805 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1806 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1807 YU_RXSTAT_JABBER)) != 0 || 1808 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1809 YU_RXSTAT_BYTES(stat) != len) 1810 return (0); 1811 } 1812 1813 return (1); 1814 } 1815 1816 static void 1817 sk_rxeof(struct sk_if_softc *sc_if) 1818 { 1819 struct sk_softc *sc = sc_if->sk_softc; 1820 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1821 struct sk_chain_data *cd = &sc_if->sk_cdata; 1822 struct sk_ring_data *rd = sc_if->sk_rdata; 1823 int i, reap, max_frmlen; 1824 1825 DPRINTFN(2, ("sk_rxeof\n")); 1826 1827 i = cd->sk_rx_prod; 1828 1829 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 1830 BUS_DMASYNC_POSTREAD); 1831 if (sc_if->sk_use_jumbo) { 1832 bus_dmamap_sync(cd->sk_jpool_dtag, cd->sk_jpool_dmap, 1833 BUS_DMASYNC_POSTREAD); 1834 max_frmlen = SK_JUMBO_FRAMELEN; 1835 } else { 1836 max_frmlen = ETHER_MAX_LEN; 1837 } 1838 1839 reap = 0; 1840 for (;;) { 1841 struct sk_rx_desc *cur_desc; 1842 uint32_t rxstat, sk_ctl; 1843 #ifdef SK_RXCSUM 1844 uint16_t csum1, csum2; 1845 #endif 1846 int cur, total_len; 1847 struct mbuf *m; 1848 1849 cur = i; 1850 cur_desc = &rd->sk_rx_ring[cur]; 1851 1852 sk_ctl = le32toh(cur_desc->sk_ctl); 1853 if (sk_ctl & SK_RXCTL_OWN) { 1854 /* Invalidate the descriptor -- it's not ready yet */ 1855 cd->sk_rx_prod = cur; 1856 break; 1857 } 1858 1859 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 1860 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 1861 1862 #ifdef SK_RXCSUM 1863 csum1 = le16toh(cur_desc->sk_csum1); 1864 csum2 = le16toh(cur_desc->sk_csum2); 1865 #endif 1866 1867 m = cd->sk_rx_mbuf[cur]; 1868 1869 /* 1870 * Bump 'i' here, so we can keep going, even if the current 1871 * RX descriptor reaping fails later. 'i' shoult NOT be used 1872 * in the following processing any more. 1873 */ 1874 SK_INC(i, SK_RX_RING_CNT); 1875 reap = 1; 1876 1877 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 1878 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 1879 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 1880 total_len < SK_MIN_FRAMELEN || total_len > max_frmlen || 1881 sk_rxvalid(sc, rxstat, total_len) == 0) { 1882 ifp->if_ierrors++; 1883 cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT); 1884 continue; 1885 } 1886 1887 if (!sc_if->sk_use_jumbo) { 1888 bus_dmamap_sync(cd->sk_rx_dtag, cd->sk_rx_dmap[cur], 1889 BUS_DMASYNC_POSTREAD); 1890 } 1891 1892 /* 1893 * Try to allocate a new RX buffer. If that fails, 1894 * copy the packet to mbufs and put the RX buffer 1895 * back in the ring so it can be re-used. If 1896 * allocating mbufs fails, then we have to drop 1897 * the packet. 1898 */ 1899 if (sk_newbuf(sc_if, cur, 0)) { 1900 struct mbuf *m0; 1901 1902 cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT); 1903 1904 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1905 total_len + ETHER_ALIGN, 0, ifp, NULL); 1906 if (m0 == NULL) { 1907 ifp->if_ierrors++; 1908 continue; 1909 } 1910 m_adj(m0, ETHER_ALIGN); 1911 m = m0; 1912 } else { 1913 m->m_pkthdr.rcvif = ifp; 1914 m->m_pkthdr.len = m->m_len = total_len; 1915 } 1916 1917 #ifdef SK_RXCSUM 1918 sk_rxcsum(ifp, m, csum1, csum2); 1919 #endif 1920 1921 ifp->if_ipackets++; 1922 ifp->if_input(ifp, m); 1923 } 1924 1925 if (reap) { 1926 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 1927 BUS_DMASYNC_PREWRITE); 1928 } 1929 } 1930 1931 #ifdef SK_RXCSUM 1932 static void 1933 sk_rxcsum(struct ifnet *ifp, struct mbuf *m, 1934 const uint16_t csum1, const uint16_t csum2) 1935 { 1936 struct ether_header *eh; 1937 struct ip *ip; 1938 uint8_t *pp; 1939 int hlen, len, plen; 1940 uint16_t iph_csum, ipo_csum, ipd_csum, csum; 1941 1942 pp = mtod(m, uint8_t *); 1943 plen = m->m_pkthdr.len; 1944 if (plen < sizeof(*eh)) 1945 return; 1946 eh = (struct ether_header *)pp; 1947 iph_csum = in_addword(csum1, (~csum2 & 0xffff)); 1948 1949 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1950 uint16_t *xp = (uint16_t *)pp; 1951 1952 xp = (uint16_t *)pp; 1953 if (xp[1] != htons(ETHERTYPE_IP)) 1954 return; 1955 iph_csum = in_addword(iph_csum, (~xp[0] & 0xffff)); 1956 iph_csum = in_addword(iph_csum, (~xp[1] & 0xffff)); 1957 xp = (uint16_t *)(pp + sizeof(struct ip)); 1958 iph_csum = in_addword(iph_csum, xp[0]); 1959 iph_csum = in_addword(iph_csum, xp[1]); 1960 pp += EVL_ENCAPLEN; 1961 } else if (eh->ether_type != htons(ETHERTYPE_IP)) { 1962 return; 1963 } 1964 1965 pp += sizeof(*eh); 1966 plen -= sizeof(*eh); 1967 1968 ip = (struct ip *)pp; 1969 1970 if (ip->ip_v != IPVERSION) 1971 return; 1972 1973 hlen = ip->ip_hl << 2; 1974 if (hlen < sizeof(struct ip)) 1975 return; 1976 if (hlen > ntohs(ip->ip_len)) 1977 return; 1978 1979 /* Don't deal with truncated or padded packets. */ 1980 if (plen != ntohs(ip->ip_len)) 1981 return; 1982 1983 len = hlen - sizeof(struct ip); 1984 if (len > 0) { 1985 uint16_t *p; 1986 1987 p = (uint16_t *)(ip + 1); 1988 ipo_csum = 0; 1989 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++) 1990 ipo_csum = in_addword(ipo_csum, *p); 1991 iph_csum = in_addword(iph_csum, ipo_csum); 1992 ipd_csum = in_addword(csum2, (~ipo_csum & 0xffff)); 1993 } else { 1994 ipd_csum = csum2; 1995 } 1996 1997 if (iph_csum != 0xffff) 1998 return; 1999 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID; 2000 2001 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 2002 return; /* ip frag, we're done for now */ 2003 2004 pp += hlen; 2005 2006 /* Only know checksum protocol for udp/tcp */ 2007 if (ip->ip_p == IPPROTO_UDP) { 2008 struct udphdr *uh = (struct udphdr *)pp; 2009 2010 if (uh->uh_sum == 0) /* udp with no checksum */ 2011 return; 2012 } else if (ip->ip_p != IPPROTO_TCP) { 2013 return; 2014 } 2015 2016 csum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, 2017 htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum); 2018 if (csum == 0xffff) { 2019 m->m_pkthdr.csum_data = csum; 2020 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 2021 } 2022 } 2023 #endif 2024 2025 static void 2026 sk_txeof(struct sk_if_softc *sc_if) 2027 { 2028 struct sk_chain_data *cd = &sc_if->sk_cdata; 2029 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2030 uint32_t idx; 2031 int reap = 0; 2032 2033 DPRINTFN(2, ("sk_txeof\n")); 2034 2035 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 2036 BUS_DMASYNC_POSTREAD); 2037 2038 /* 2039 * Go through our tx ring and free mbufs for those 2040 * frames that have been sent. 2041 */ 2042 idx = cd->sk_tx_cons; 2043 while (idx != cd->sk_tx_prod) { 2044 struct sk_tx_desc *cur_tx; 2045 uint32_t sk_ctl; 2046 2047 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2048 sk_ctl = le32toh(cur_tx->sk_ctl); 2049 #ifdef SK_DEBUG 2050 if (skdebug >= 2) 2051 sk_dump_txdesc(cur_tx, idx); 2052 #endif 2053 if (sk_ctl & SK_TXCTL_OWN) 2054 break; 2055 if (sk_ctl & SK_TXCTL_LASTFRAG) 2056 ifp->if_opackets++; 2057 if (cd->sk_tx_mbuf[idx] != NULL) { 2058 bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[idx]); 2059 m_freem(cd->sk_tx_mbuf[idx]); 2060 cd->sk_tx_mbuf[idx] = NULL; 2061 } 2062 sc_if->sk_cdata.sk_tx_cnt--; 2063 reap = 1; 2064 SK_INC(idx, SK_TX_RING_CNT); 2065 } 2066 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2067 2068 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2069 ifp->if_flags &= ~IFF_OACTIVE; 2070 2071 sc_if->sk_cdata.sk_tx_cons = idx; 2072 2073 if (reap) { 2074 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 2075 BUS_DMASYNC_PREWRITE); 2076 } 2077 } 2078 2079 static void 2080 sk_tick(void *xsc_if) 2081 { 2082 struct sk_if_softc *sc_if = xsc_if; 2083 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2084 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 2085 int i; 2086 2087 DPRINTFN(2, ("sk_tick\n")); 2088 2089 lwkt_serialize_enter(ifp->if_serializer); 2090 2091 if ((ifp->if_flags & IFF_UP) == 0) { 2092 lwkt_serialize_exit(ifp->if_serializer); 2093 return; 2094 } 2095 2096 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2097 sk_intr_bcom(sc_if); 2098 lwkt_serialize_exit(ifp->if_serializer); 2099 return; 2100 } 2101 2102 /* 2103 * According to SysKonnect, the correct way to verify that 2104 * the link has come back up is to poll bit 0 of the GPIO 2105 * register three times. This pin has the signal from the 2106 * link sync pin connected to it; if we read the same link 2107 * state 3 times in a row, we know the link is up. 2108 */ 2109 for (i = 0; i < 3; i++) { 2110 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2111 break; 2112 } 2113 2114 if (i != 3) { 2115 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if); 2116 lwkt_serialize_exit(ifp->if_serializer); 2117 return; 2118 } 2119 2120 /* Turn the GP0 interrupt back on. */ 2121 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2122 SK_XM_READ_2(sc_if, XM_ISR); 2123 mii_tick(mii); 2124 callout_stop(&sc_if->sk_tick_timer); 2125 lwkt_serialize_exit(ifp->if_serializer); 2126 } 2127 2128 static void 2129 sk_yukon_tick(void *xsc_if) 2130 { 2131 struct sk_if_softc *sc_if = xsc_if; 2132 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2133 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 2134 2135 lwkt_serialize_enter(ifp->if_serializer); 2136 mii_tick(mii); 2137 callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if); 2138 lwkt_serialize_exit(ifp->if_serializer); 2139 } 2140 2141 static void 2142 sk_intr_bcom(struct sk_if_softc *sc_if) 2143 { 2144 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 2145 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2146 int status; 2147 2148 DPRINTFN(2, ("sk_intr_bcom\n")); 2149 2150 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2151 2152 /* 2153 * Read the PHY interrupt register to make sure 2154 * we clear any pending interrupts. 2155 */ 2156 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2157 2158 if ((ifp->if_flags & IFF_RUNNING) == 0) { 2159 sk_init_xmac(sc_if); 2160 return; 2161 } 2162 2163 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2164 int lstat; 2165 2166 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 2167 BRGPHY_MII_AUXSTS); 2168 2169 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2170 mii_mediachg(mii); 2171 /* Turn off the link LED. */ 2172 SK_IF_WRITE_1(sc_if, 0, 2173 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2174 sc_if->sk_link = 0; 2175 } else if (status & BRGPHY_ISR_LNK_CHG) { 2176 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2177 BRGPHY_MII_IMR, 0xFF00); 2178 mii_tick(mii); 2179 sc_if->sk_link = 1; 2180 /* Turn on the link LED. */ 2181 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2182 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2183 SK_LINKLED_BLINK_OFF); 2184 } else { 2185 mii_tick(mii); 2186 callout_reset(&sc_if->sk_tick_timer, hz, 2187 sk_tick, sc_if); 2188 } 2189 } 2190 2191 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2192 } 2193 2194 static void 2195 sk_intr_xmac(struct sk_if_softc *sc_if) 2196 { 2197 uint16_t status; 2198 2199 status = SK_XM_READ_2(sc_if, XM_ISR); 2200 DPRINTFN(2, ("sk_intr_xmac\n")); 2201 2202 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && 2203 (status & (XM_ISR_GP0_SET | XM_ISR_AUTONEG_DONE))) { 2204 if (status & XM_ISR_GP0_SET) 2205 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2206 2207 callout_reset(&sc_if->sk_tick_timer, hz, 2208 sk_tick, sc_if); 2209 } 2210 2211 if (status & XM_IMR_TX_UNDERRUN) 2212 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2213 2214 if (status & XM_IMR_RX_OVERRUN) 2215 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2216 } 2217 2218 static void 2219 sk_intr_yukon(struct sk_if_softc *sc_if) 2220 { 2221 uint8_t status; 2222 2223 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2224 /* RX overrun */ 2225 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2226 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2227 SK_RFCTL_RX_FIFO_OVER); 2228 } 2229 /* TX underrun */ 2230 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2231 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2232 SK_TFCTL_TX_FIFO_UNDER); 2233 } 2234 2235 DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status)); 2236 } 2237 2238 static void 2239 sk_intr(void *xsc) 2240 { 2241 struct sk_softc *sc = xsc; 2242 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2243 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2244 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2245 uint32_t status; 2246 2247 ASSERT_SERIALIZED(&sc->sk_serializer); 2248 2249 status = CSR_READ_4(sc, SK_ISSR); 2250 if (status == 0 || status == 0xffffffff) 2251 return; 2252 2253 if (sc_if0 != NULL) 2254 ifp0 = &sc_if0->arpcom.ac_if; 2255 if (sc_if1 != NULL) 2256 ifp1 = &sc_if1->arpcom.ac_if; 2257 2258 for (; (status &= sc->sk_intrmask) != 0;) { 2259 /* Handle receive interrupts first. */ 2260 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2261 sk_rxeof(sc_if0); 2262 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2263 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2264 } 2265 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2266 sk_rxeof(sc_if1); 2267 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2268 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2269 } 2270 2271 /* Then transmit interrupts. */ 2272 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2273 sk_txeof(sc_if0); 2274 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2275 SK_TXBMU_CLR_IRQ_EOF); 2276 } 2277 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2278 sk_txeof(sc_if1); 2279 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2280 SK_TXBMU_CLR_IRQ_EOF); 2281 } 2282 2283 /* Then MAC interrupts. */ 2284 if (sc_if0 && (status & SK_ISR_MAC1) && 2285 (ifp0->if_flags & IFF_RUNNING)) { 2286 if (SK_IS_GENESIS(sc)) 2287 sk_intr_xmac(sc_if0); 2288 else 2289 sk_intr_yukon(sc_if0); 2290 } 2291 2292 if (sc_if1 && (status & SK_ISR_MAC2) && 2293 (ifp1->if_flags & IFF_RUNNING)) { 2294 if (SK_IS_GENESIS(sc)) 2295 sk_intr_xmac(sc_if1); 2296 else 2297 sk_intr_yukon(sc_if1); 2298 } 2299 2300 if (status & SK_ISR_EXTERNAL_REG) { 2301 if (sc_if0 != NULL && 2302 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2303 sk_intr_bcom(sc_if0); 2304 2305 if (sc_if1 != NULL && 2306 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2307 sk_intr_bcom(sc_if1); 2308 } 2309 status = CSR_READ_4(sc, SK_ISSR); 2310 } 2311 2312 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2313 2314 if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd)) 2315 if_devstart(ifp0); 2316 if (ifp1 != NULL && !ifq_is_empty(&ifp1->if_snd)) 2317 if_devstart(ifp1); 2318 } 2319 2320 static void 2321 sk_init_xmac(struct sk_if_softc *sc_if) 2322 { 2323 struct sk_softc *sc = sc_if->sk_softc; 2324 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2325 static const struct sk_bcom_hack bhack[] = { 2326 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2327 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2328 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2329 { 0, 0 } }; 2330 2331 DPRINTFN(2, ("sk_init_xmac\n")); 2332 2333 /* Unreset the XMAC. */ 2334 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2335 DELAY(1000); 2336 2337 /* Reset the XMAC's internal state. */ 2338 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2339 2340 /* Save the XMAC II revision */ 2341 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2342 2343 /* 2344 * Perform additional initialization for external PHYs, 2345 * namely for the 1000baseT cards that use the XMAC's 2346 * GMII mode. 2347 */ 2348 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2349 int i = 0; 2350 uint32_t val; 2351 2352 /* Take PHY out of reset. */ 2353 val = sk_win_read_4(sc, SK_GPIO); 2354 if (sc_if->sk_port == SK_PORT_A) 2355 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2356 else 2357 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2358 sk_win_write_4(sc, SK_GPIO, val); 2359 2360 /* Enable GMII mode on the XMAC. */ 2361 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2362 2363 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2364 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2365 DELAY(10000); 2366 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2367 BRGPHY_MII_IMR, 0xFFF0); 2368 2369 /* 2370 * Early versions of the BCM5400 apparently have 2371 * a bug that requires them to have their reserved 2372 * registers initialized to some magic values. I don't 2373 * know what the numbers do, I'm just the messenger. 2374 */ 2375 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2376 == 0x6041) { 2377 while(bhack[i].reg) { 2378 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2379 bhack[i].reg, bhack[i].val); 2380 i++; 2381 } 2382 } 2383 } 2384 2385 /* Set station address */ 2386 SK_XM_WRITE_2(sc_if, XM_PAR0, 2387 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2388 SK_XM_WRITE_2(sc_if, XM_PAR1, 2389 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2390 SK_XM_WRITE_2(sc_if, XM_PAR2, 2391 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2392 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2393 2394 if (ifp->if_flags & IFF_BROADCAST) 2395 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2396 else 2397 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2398 2399 /* We don't need the FCS appended to the packet. */ 2400 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2401 2402 /* We want short frames padded to 60 bytes. */ 2403 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2404 2405 /* 2406 * Enable the reception of all error frames. This is 2407 * a necessary evil due to the design of the XMAC. The 2408 * XMAC's receive FIFO is only 8K in size, however jumbo 2409 * frames can be up to 9000 bytes in length. When bad 2410 * frame filtering is enabled, the XMAC's RX FIFO operates 2411 * in 'store and forward' mode. For this to work, the 2412 * entire frame has to fit into the FIFO, but that means 2413 * that jumbo frames larger than 8192 bytes will be 2414 * truncated. Disabling all bad frame filtering causes 2415 * the RX FIFO to operate in streaming mode, in which 2416 * case the XMAC will start transfering frames out of the 2417 * RX FIFO as soon as the FIFO threshold is reached. 2418 */ 2419 if (sc_if->sk_use_jumbo) { 2420 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2421 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2422 XM_MODE_RX_INRANGELEN); 2423 } 2424 2425 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2426 2427 /* 2428 * Bump up the transmit threshold. This helps hold off transmit 2429 * underruns when we're blasting traffic from both ports at once. 2430 */ 2431 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2432 2433 /* Set promiscuous mode */ 2434 sk_setpromisc(sc_if); 2435 2436 /* Set multicast filter */ 2437 sk_setmulti(sc_if); 2438 2439 /* Clear and enable interrupts */ 2440 SK_XM_READ_2(sc_if, XM_ISR); 2441 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2442 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2443 else 2444 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2445 2446 /* Configure MAC arbiter */ 2447 switch(sc_if->sk_xmac_rev) { 2448 case XM_XMAC_REV_B2: 2449 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2450 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2451 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2452 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2453 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2454 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2455 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2456 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2457 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2458 break; 2459 case XM_XMAC_REV_C1: 2460 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2461 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2462 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2463 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2464 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2465 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2466 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2467 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2468 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2469 break; 2470 default: 2471 break; 2472 } 2473 sk_win_write_2(sc, SK_MACARB_CTL, 2474 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2475 2476 sc_if->sk_link = 1; 2477 } 2478 2479 static void 2480 sk_init_yukon(struct sk_if_softc *sc_if) 2481 { 2482 uint32_t phy, v; 2483 uint16_t reg; 2484 struct sk_softc *sc; 2485 int i; 2486 2487 sc = sc_if->sk_softc; 2488 2489 DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n", 2490 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2491 2492 if (sc->sk_type == SK_YUKON_LITE && 2493 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2494 /* 2495 * Workaround code for COMA mode, set PHY reset. 2496 * Otherwise it will not correctly take chip out of 2497 * powerdown (coma) 2498 */ 2499 v = sk_win_read_4(sc, SK_GPIO); 2500 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 2501 sk_win_write_4(sc, SK_GPIO, v); 2502 } 2503 2504 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2505 2506 /* GMAC and GPHY Reset */ 2507 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2508 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2509 DELAY(1000); 2510 2511 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2512 2513 if (sc->sk_type == SK_YUKON_LITE && 2514 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2515 /* 2516 * Workaround code for COMA mode, clear PHY reset 2517 */ 2518 v = sk_win_read_4(sc, SK_GPIO); 2519 v |= SK_GPIO_DIR9; 2520 v &= ~SK_GPIO_DAT9; 2521 sk_win_write_4(sc, SK_GPIO, v); 2522 } 2523 2524 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2525 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2526 2527 if (sc->sk_coppertype) 2528 phy |= SK_GPHY_COPPER; 2529 else 2530 phy |= SK_GPHY_FIBER; 2531 2532 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2533 2534 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2535 DELAY(1000); 2536 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2537 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2538 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2539 2540 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2541 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2542 2543 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2544 2545 /* unused read of the interrupt source register */ 2546 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2547 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2548 2549 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2550 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2551 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2552 2553 /* MIB Counter Clear Mode set */ 2554 reg |= YU_PAR_MIB_CLR; 2555 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2556 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2557 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2558 2559 /* MIB Counter Clear Mode clear */ 2560 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2561 reg &= ~YU_PAR_MIB_CLR; 2562 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2563 2564 /* receive control reg */ 2565 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2566 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2567 2568 /* transmit parameter register */ 2569 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2570 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2571 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2572 2573 /* serial mode register */ 2574 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2575 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 2576 if (sc_if->sk_use_jumbo) 2577 reg |= YU_SMR_MFL_JUMBO; 2578 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2579 2580 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2581 /* Setup Yukon's address */ 2582 for (i = 0; i < 3; i++) { 2583 /* Write Source Address 1 (unicast filter) */ 2584 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2585 sc_if->arpcom.ac_enaddr[i * 2] | 2586 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2587 } 2588 2589 for (i = 0; i < 3; i++) { 2590 reg = sk_win_read_2(sc_if->sk_softc, 2591 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2592 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2593 } 2594 2595 /* Set promiscuous mode */ 2596 sk_setpromisc(sc_if); 2597 2598 /* Set multicast filter */ 2599 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2600 sk_setmulti(sc_if); 2601 2602 /* enable interrupt mask for counter overflows */ 2603 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2604 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2605 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2606 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2607 2608 /* Configure RX MAC FIFO Flush Mask */ 2609 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2610 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2611 YU_RXSTAT_JABBER; 2612 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2613 2614 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 2615 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 2616 v = SK_TFCTL_OPERATION_ON; 2617 else 2618 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 2619 /* Configure RX MAC FIFO */ 2620 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2621 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 2622 2623 /* Increase flush threshould to 64 bytes */ 2624 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2625 SK_RFCTL_FIFO_THRESHOLD + 1); 2626 2627 /* Configure TX MAC FIFO */ 2628 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2629 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2630 2631 DPRINTFN(6, ("sk_init_yukon: end\n")); 2632 } 2633 2634 /* 2635 * Note that to properly initialize any part of the GEnesis chip, 2636 * you first have to take it out of reset mode. 2637 */ 2638 static void 2639 sk_init(void *xsc_if) 2640 { 2641 struct sk_if_softc *sc_if = xsc_if; 2642 struct sk_softc *sc = sc_if->sk_softc; 2643 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2644 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 2645 2646 DPRINTFN(2, ("sk_init\n")); 2647 2648 ASSERT_SERIALIZED(ifp->if_serializer); 2649 2650 if (ifp->if_flags & IFF_RUNNING) 2651 return; 2652 2653 /* Cancel pending I/O and free all RX/TX buffers. */ 2654 sk_stop(sc_if); 2655 2656 /* 2657 * NOTE: Change sk_use_jumbo after sk_stop(), 2658 * but before real initialization. 2659 */ 2660 if (ifp->if_mtu > ETHER_MAX_LEN) 2661 sc_if->sk_use_jumbo = 1; 2662 else 2663 sc_if->sk_use_jumbo = 0; 2664 DPRINTF(("use jumbo buffer: %s\n", sc_if->sk_use_jumbo ? "YES" : "NO")); 2665 2666 if (SK_IS_GENESIS(sc)) { 2667 /* Configure LINK_SYNC LED */ 2668 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2669 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2670 SK_LINKLED_LINKSYNC_ON); 2671 2672 /* Configure RX LED */ 2673 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2674 SK_RXLEDCTL_COUNTER_START); 2675 2676 /* Configure TX LED */ 2677 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2678 SK_TXLEDCTL_COUNTER_START); 2679 } 2680 2681 /* 2682 * Configure descriptor poll timer 2683 * 2684 * SK-NET GENESIS data sheet says that possibility of losing Start 2685 * transmit command due to CPU/cache related interim storage problems 2686 * under certain conditions. The document recommends a polling 2687 * mechanism to send a Start transmit command to initiate transfer 2688 * of ready descriptors regulary. To cope with this issue sk(4) now 2689 * enables descriptor poll timer to initiate descriptor processing 2690 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 2691 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 2692 * command instead of waiting for next descriptor polling time. 2693 * The same rule may apply to Rx side too but it seems that is not 2694 * needed at the moment. 2695 * Since sk(4) uses descriptor polling as a last resort there is no 2696 * need to set smaller polling time than maximum allowable one. 2697 */ 2698 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 2699 2700 /* Configure I2C registers */ 2701 2702 /* Configure XMAC(s) */ 2703 switch (sc->sk_type) { 2704 case SK_GENESIS: 2705 sk_init_xmac(sc_if); 2706 break; 2707 case SK_YUKON: 2708 case SK_YUKON_LITE: 2709 case SK_YUKON_LP: 2710 sk_init_yukon(sc_if); 2711 break; 2712 } 2713 mii_mediachg(mii); 2714 2715 if (SK_IS_GENESIS(sc)) { 2716 /* Configure MAC FIFOs */ 2717 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2718 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2719 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2720 2721 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2722 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2723 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2724 } 2725 2726 /* Configure transmit arbiter(s) */ 2727 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2728 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2729 2730 /* Configure RAMbuffers */ 2731 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2732 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2733 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2734 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2735 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2736 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2737 2738 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2739 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2740 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2741 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2742 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2743 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2744 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2745 2746 /* Configure BMUs */ 2747 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2748 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2749 SK_RX_RING_ADDR(sc_if, 0)); 2750 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2751 2752 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2753 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2754 SK_TX_RING_ADDR(sc_if, 0)); 2755 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2756 2757 /* Init descriptors */ 2758 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2759 if_printf(ifp, "initialization failed: " 2760 "no memory for rx buffers\n"); 2761 sk_stop(sc_if); 2762 return; 2763 } 2764 2765 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2766 if_printf(ifp, "initialization failed: " 2767 "no memory for tx buffers\n"); 2768 sk_stop(sc_if); 2769 return; 2770 } 2771 2772 /* Configure interrupt handling */ 2773 CSR_READ_4(sc, SK_ISSR); 2774 if (sc_if->sk_port == SK_PORT_A) 2775 sc->sk_intrmask |= SK_INTRS1; 2776 else 2777 sc->sk_intrmask |= SK_INTRS2; 2778 2779 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2780 2781 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2782 2783 /* Start BMUs. */ 2784 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2785 2786 if (SK_IS_GENESIS(sc)) { 2787 /* Enable XMACs TX and RX state machines */ 2788 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2789 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2790 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2791 } 2792 2793 if (SK_IS_YUKON(sc)) { 2794 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2795 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2796 #if 0 2797 /* XXX disable 100Mbps and full duplex mode? */ 2798 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS); 2799 #endif 2800 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2801 } 2802 2803 /* Activate descriptor polling timer */ 2804 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 2805 /* Start transfer of Tx descriptors */ 2806 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2807 2808 ifp->if_flags |= IFF_RUNNING; 2809 ifp->if_flags &= ~IFF_OACTIVE; 2810 2811 if (SK_IS_YUKON(sc)) 2812 callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if); 2813 } 2814 2815 static void 2816 sk_stop(struct sk_if_softc *sc_if) 2817 { 2818 struct sk_softc *sc = sc_if->sk_softc; 2819 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2820 struct sk_chain_data *cd = &sc_if->sk_cdata; 2821 uint32_t val; 2822 int i; 2823 2824 ASSERT_SERIALIZED(ifp->if_serializer); 2825 2826 DPRINTFN(2, ("sk_stop\n")); 2827 2828 callout_stop(&sc_if->sk_tick_timer); 2829 2830 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2831 2832 /* Stop Tx descriptor polling timer */ 2833 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 2834 2835 /* Stop transfer of Tx descriptors */ 2836 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 2837 for (i = 0; i < SK_TIMEOUT; i++) { 2838 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 2839 if (!(val & SK_TXBMU_TX_STOP)) 2840 break; 2841 DELAY(1); 2842 } 2843 if (i == SK_TIMEOUT) 2844 if_printf(ifp, "cannot stop transfer of Tx descriptors\n"); 2845 2846 /* Stop transfer of Rx descriptors */ 2847 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 2848 for (i = 0; i < SK_TIMEOUT; i++) { 2849 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 2850 if (!(val & SK_RXBMU_RX_STOP)) 2851 break; 2852 DELAY(1); 2853 } 2854 if (i == SK_TIMEOUT) 2855 if_printf(ifp, "cannot stop transfer of Rx descriptors\n"); 2856 2857 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2858 /* Put PHY back into reset. */ 2859 val = sk_win_read_4(sc, SK_GPIO); 2860 if (sc_if->sk_port == SK_PORT_A) { 2861 val |= SK_GPIO_DIR0; 2862 val &= ~SK_GPIO_DAT0; 2863 } else { 2864 val |= SK_GPIO_DIR2; 2865 val &= ~SK_GPIO_DAT2; 2866 } 2867 sk_win_write_4(sc, SK_GPIO, val); 2868 } 2869 2870 /* Turn off various components of this interface. */ 2871 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2872 switch (sc->sk_type) { 2873 case SK_GENESIS: 2874 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2875 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2876 break; 2877 case SK_YUKON: 2878 case SK_YUKON_LITE: 2879 case SK_YUKON_LP: 2880 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2881 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2882 break; 2883 } 2884 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2885 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2886 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2887 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, 2888 SK_RBCTL_RESET | SK_RBCTL_OFF); 2889 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2890 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2891 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2892 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2893 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2894 2895 /* Disable interrupts */ 2896 if (sc_if->sk_port == SK_PORT_A) 2897 sc->sk_intrmask &= ~SK_INTRS1; 2898 else 2899 sc->sk_intrmask &= ~SK_INTRS2; 2900 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2901 2902 SK_XM_READ_2(sc_if, XM_ISR); 2903 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2904 2905 /* Free RX and TX mbufs still in the queues. */ 2906 for (i = 0; i < SK_RX_RING_CNT; i++) { 2907 if (cd->sk_rx_mbuf[i] != NULL) { 2908 if (!sc_if->sk_use_jumbo) { 2909 bus_dmamap_unload(cd->sk_rx_dtag, 2910 cd->sk_rx_dmap[i]); 2911 } 2912 m_freem(cd->sk_rx_mbuf[i]); 2913 cd->sk_rx_mbuf[i] = NULL; 2914 } 2915 } 2916 for (i = 0; i < SK_TX_RING_CNT; i++) { 2917 if (cd->sk_tx_mbuf[i] != NULL) { 2918 bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[i]); 2919 m_freem(cd->sk_tx_mbuf[i]); 2920 cd->sk_tx_mbuf[i] = NULL; 2921 } 2922 } 2923 } 2924 2925 #ifdef SK_DEBUG 2926 static void 2927 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2928 { 2929 #define DESC_PRINT(X) \ 2930 if (X) \ 2931 kprintf("txdesc[%d]." #X "=%#x\n", \ 2932 idx, X); 2933 2934 DESC_PRINT(le32toh(desc->sk_ctl)); 2935 DESC_PRINT(le32toh(desc->sk_next)); 2936 DESC_PRINT(le32toh(desc->sk_data_lo)); 2937 DESC_PRINT(le32toh(desc->sk_data_hi)); 2938 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2939 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2940 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2941 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2942 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2943 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2944 #undef PRINT 2945 } 2946 2947 static void 2948 sk_dump_bytes(const char *data, int len) 2949 { 2950 int c, i, j; 2951 2952 for (i = 0; i < len; i += 16) { 2953 kprintf("%08x ", i); 2954 c = len - i; 2955 if (c > 16) c = 16; 2956 2957 for (j = 0; j < c; j++) { 2958 kprintf("%02x ", data[i + j] & 0xff); 2959 if ((j & 0xf) == 7 && j > 0) 2960 kprintf(" "); 2961 } 2962 2963 for (; j < 16; j++) 2964 kprintf(" "); 2965 kprintf(" "); 2966 2967 for (j = 0; j < c; j++) { 2968 int ch = data[i + j] & 0xff; 2969 kprintf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2970 } 2971 2972 kprintf("\n"); 2973 2974 if (c < 16) 2975 break; 2976 } 2977 } 2978 2979 static void 2980 sk_dump_mbuf(struct mbuf *m) 2981 { 2982 int count = m->m_pkthdr.len; 2983 2984 kprintf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2985 2986 while (count > 0 && m) { 2987 kprintf("m=%p, m->m_data=%p, m->m_len=%d\n", 2988 m, m->m_data, m->m_len); 2989 sk_dump_bytes(mtod(m, char *), m->m_len); 2990 2991 count -= m->m_len; 2992 m = m->m_next; 2993 } 2994 } 2995 #endif 2996 2997 /* 2998 * Allocate jumbo buffer storage. The SysKonnect adapters support 2999 * "jumbograms" (9K frames), although SysKonnect doesn't currently 3000 * use them in their drivers. In order for us to use them, we need 3001 * large 9K receive buffers, however standard mbuf clusters are only 3002 * 2048 bytes in size. Consequently, we need to allocate and manage 3003 * our own jumbo buffer pool. Fortunately, this does not require an 3004 * excessive amount of additional code. 3005 */ 3006 static int 3007 sk_jpool_alloc(device_t dev) 3008 { 3009 struct sk_if_softc *sc_if = device_get_softc(dev); 3010 struct sk_chain_data *cd = &sc_if->sk_cdata; 3011 bus_addr_t paddr; 3012 caddr_t buf; 3013 int error, i; 3014 3015 lwkt_serialize_init(&cd->sk_jpool_serializer); 3016 3017 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, 3018 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 3019 NULL, NULL, SK_JMEM, 1, SK_JMEM, 3020 0, &cd->sk_jpool_dtag); 3021 if (error) { 3022 device_printf(dev, "can't create jpool DMA tag\n"); 3023 return error; 3024 } 3025 3026 error = bus_dmamem_alloc(cd->sk_jpool_dtag, &cd->sk_jpool, 3027 BUS_DMA_WAITOK, &cd->sk_jpool_dmap); 3028 if (error) { 3029 device_printf(dev, "can't alloc jpool DMA mem\n"); 3030 bus_dma_tag_destroy(cd->sk_jpool_dtag); 3031 cd->sk_jpool_dtag = NULL; 3032 return error; 3033 } 3034 3035 error = bus_dmamap_load(cd->sk_jpool_dtag, cd->sk_jpool_dmap, 3036 cd->sk_jpool, SK_JMEM, 3037 sk_dmamem_addr, &paddr, BUS_DMA_WAITOK); 3038 if (error) { 3039 device_printf(dev, "can't load DMA mem\n"); 3040 bus_dmamem_free(cd->sk_jpool_dtag, cd->sk_jpool, 3041 cd->sk_jpool_dmap); 3042 bus_dma_tag_destroy(cd->sk_jpool_dtag); 3043 cd->sk_jpool_dtag = NULL; 3044 return error; 3045 } 3046 3047 SLIST_INIT(&cd->sk_jpool_free_ent); 3048 buf = cd->sk_jpool; 3049 3050 /* 3051 * Now divide it up into SK_JLEN pieces. 3052 */ 3053 for (i = 0; i < SK_JSLOTS; i++) { 3054 struct sk_jpool_entry *entry = &cd->sk_jpool_ent[i]; 3055 3056 entry->sc_if = sc_if; 3057 entry->inuse = 0; 3058 entry->slot = i; 3059 entry->buf = buf; 3060 entry->paddr = paddr; 3061 3062 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next); 3063 3064 buf += SK_JLEN; 3065 paddr += SK_JLEN; 3066 } 3067 return 0; 3068 } 3069 3070 static void 3071 sk_jpool_free(struct sk_if_softc *sc_if) 3072 { 3073 struct sk_chain_data *cd = &sc_if->sk_cdata; 3074 3075 if (cd->sk_jpool_dtag != NULL) { 3076 bus_dmamap_unload(cd->sk_jpool_dtag, cd->sk_jpool_dmap); 3077 bus_dmamem_free(cd->sk_jpool_dtag, cd->sk_jpool, 3078 cd->sk_jpool_dmap); 3079 bus_dma_tag_destroy(cd->sk_jpool_dtag); 3080 cd->sk_jpool_dtag = NULL; 3081 } 3082 } 3083 3084 static int 3085 sk_dma_alloc(device_t dev) 3086 { 3087 struct sk_if_softc *sc_if = device_get_softc(dev); 3088 struct sk_chain_data *cd = &sc_if->sk_cdata; 3089 int i, j, error; 3090 3091 /* 3092 * Allocate the descriptor queues. 3093 * TODO: split into RX/TX rings 3094 */ 3095 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, 3096 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 3097 NULL, NULL, 3098 sizeof(struct sk_ring_data), 1, 3099 sizeof(struct sk_ring_data), 0, 3100 &sc_if->sk_rdata_dtag); 3101 if (error) { 3102 device_printf(dev, "can't create desc DMA tag\n"); 3103 return error; 3104 } 3105 3106 error = bus_dmamem_alloc(sc_if->sk_rdata_dtag, 3107 (void **)&sc_if->sk_rdata, 3108 BUS_DMA_WAITOK | BUS_DMA_ZERO, 3109 &sc_if->sk_rdata_dmap); 3110 if (error) { 3111 device_printf(dev, "can't alloc desc DMA mem\n"); 3112 bus_dma_tag_destroy(sc_if->sk_rdata_dtag); 3113 sc_if->sk_rdata_dtag = NULL; 3114 return error; 3115 } 3116 3117 error = bus_dmamap_load(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 3118 sc_if->sk_rdata, sizeof(struct sk_ring_data), 3119 sk_dmamem_addr, &sc_if->sk_rdata_paddr, 3120 BUS_DMA_WAITOK); 3121 if (error) { 3122 device_printf(dev, "can't load desc DMA mem\n"); 3123 bus_dmamem_free(sc_if->sk_rdata_dtag, sc_if->sk_rdata, 3124 sc_if->sk_rdata_dmap); 3125 bus_dma_tag_destroy(sc_if->sk_rdata_dtag); 3126 sc_if->sk_rdata_dtag = NULL; 3127 return error; 3128 } 3129 3130 /* Try to allocate memory for jumbo buffers. */ 3131 error = sk_jpool_alloc(dev); 3132 if (error) { 3133 device_printf(dev, "jumbo buffer allocation failed\n"); 3134 return error; 3135 } 3136 3137 /* Create DMA tag for TX. */ 3138 error = bus_dma_tag_create(NULL, 1, 0, 3139 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 3140 NULL, NULL, 3141 SK_JLEN, SK_NTXSEG, SK_JLEN, 3142 0, &cd->sk_tx_dtag); 3143 if (error) { 3144 device_printf(dev, "can't create TX DMA tag\n"); 3145 return error; 3146 } 3147 3148 /* Create DMA maps for TX. */ 3149 for (i = 0; i < SK_TX_RING_CNT; i++) { 3150 error = bus_dmamap_create(cd->sk_tx_dtag, 0, 3151 &cd->sk_tx_dmap[i]); 3152 if (error) { 3153 device_printf(dev, "can't create %dth TX DMA map\n", i); 3154 3155 for (j = 0; j < i; ++j) { 3156 bus_dmamap_destroy(cd->sk_tx_dtag, 3157 cd->sk_tx_dmap[i]); 3158 } 3159 bus_dma_tag_destroy(cd->sk_tx_dtag); 3160 cd->sk_tx_dtag = NULL; 3161 return error; 3162 } 3163 } 3164 3165 /* Create DMA tag for RX. */ 3166 error = bus_dma_tag_create(NULL, 1, 0, 3167 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 3168 NULL, NULL, MCLBYTES, 1, MCLBYTES, 3169 0, &cd->sk_rx_dtag); 3170 if (error) { 3171 device_printf(dev, "can't create RX DMA tag\n"); 3172 return error; 3173 } 3174 3175 /* Create a spare RX DMA map. */ 3176 error = bus_dmamap_create(cd->sk_rx_dtag, 0, &cd->sk_rx_dmap_tmp); 3177 if (error) { 3178 device_printf(dev, "can't create spare RX DMA map\n"); 3179 bus_dma_tag_destroy(cd->sk_rx_dtag); 3180 cd->sk_rx_dtag = NULL; 3181 return error; 3182 } 3183 3184 /* Create DMA maps for RX. */ 3185 for (i = 0; i < SK_RX_RING_CNT; ++i) { 3186 error = bus_dmamap_create(cd->sk_rx_dtag, 0, 3187 &cd->sk_rx_dmap[i]); 3188 if (error) { 3189 device_printf(dev, "can't create %dth RX DMA map\n", i); 3190 3191 for (j = 0; j < i; ++j) { 3192 bus_dmamap_destroy(cd->sk_rx_dtag, 3193 cd->sk_rx_dmap[i]); 3194 } 3195 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp); 3196 bus_dma_tag_destroy(cd->sk_rx_dtag); 3197 cd->sk_rx_dtag = NULL; 3198 return error; 3199 } 3200 } 3201 return 0; 3202 } 3203 3204 static void 3205 sk_dma_free(device_t dev) 3206 { 3207 struct sk_if_softc *sc_if = device_get_softc(dev); 3208 struct sk_chain_data *cd = &sc_if->sk_cdata; 3209 int i; 3210 3211 if (cd->sk_tx_dtag != NULL) { 3212 for (i = 0; i < SK_TX_RING_CNT; ++i) { 3213 KASSERT(cd->sk_tx_mbuf[i] == NULL, 3214 ("sk_stop() is not called before %s()", 3215 __func__)); 3216 bus_dmamap_destroy(cd->sk_tx_dtag, cd->sk_tx_dmap[i]); 3217 } 3218 bus_dma_tag_destroy(cd->sk_tx_dtag); 3219 cd->sk_tx_dtag = NULL; 3220 } 3221 3222 if (cd->sk_rx_dtag != NULL) { 3223 for (i = 0; i < SK_RX_RING_CNT; ++i) { 3224 KASSERT(cd->sk_rx_mbuf[i] == NULL, 3225 ("sk_stop() is not called before %s()", 3226 __func__)); 3227 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap[i]); 3228 } 3229 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp); 3230 bus_dma_tag_destroy(cd->sk_rx_dtag); 3231 cd->sk_rx_dtag = NULL; 3232 } 3233 3234 sk_jpool_free(sc_if); 3235 3236 if (sc_if->sk_rdata_dtag != NULL) { 3237 bus_dmamap_unload(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap); 3238 bus_dmamem_free(sc_if->sk_rdata_dtag, sc_if->sk_rdata, 3239 sc_if->sk_rdata_dmap); 3240 bus_dma_tag_destroy(sc_if->sk_rdata_dtag); 3241 sc_if->sk_rdata_dtag = NULL; 3242 } 3243 } 3244 3245 static void 3246 sk_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs, 3247 bus_size_t mapsz __unused, int error) 3248 { 3249 struct sk_dma_ctx *ctx = arg; 3250 int i; 3251 3252 if (error) 3253 return; 3254 3255 KASSERT(nsegs <= ctx->nsegs, 3256 ("too many segments(%d), should be <= %d\n", 3257 nsegs, ctx->nsegs)); 3258 3259 ctx->nsegs = nsegs; 3260 for (i = 0; i < nsegs; ++i) 3261 ctx->segs[i] = segs[i]; 3262 } 3263 3264 static void 3265 sk_dmamem_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 3266 { 3267 KASSERT(nseg == 1, ("too many segments %d", nseg)); 3268 *((bus_addr_t *)arg) = seg->ds_addr; 3269 } 3270 3271 static int 3272 skc_sysctl_imtime(SYSCTL_HANDLER_ARGS) 3273 { 3274 struct sk_softc *sc = arg1; 3275 struct lwkt_serialize *slize = &sc->sk_serializer; 3276 int error = 0, v; 3277 3278 lwkt_serialize_enter(slize); 3279 3280 v = sc->sk_imtime; 3281 error = sysctl_handle_int(oidp, &v, 0, req); 3282 if (error || req->newptr == NULL) 3283 goto back; 3284 if (v <= 0) { 3285 error = EINVAL; 3286 goto back; 3287 } 3288 3289 if (sc->sk_imtime != v) { 3290 sc->sk_imtime = v; 3291 sk_win_write_4(sc, SK_IMTIMERINIT, 3292 SK_IM_USECS(sc, sc->sk_imtime)); 3293 3294 /* 3295 * Force interrupt moderation timer to 3296 * reload new value. 3297 */ 3298 sk_win_write_4(sc, SK_IMTIMER, 0); 3299 } 3300 back: 3301 lwkt_serialize_exit(slize); 3302 return error; 3303 } 3304