1 /* 2 * Copyright (c) 1997, 1998, 1999, 2000 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $ 33 */ 34 35 /* 36 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 37 * the SK-984x series adapters, both single port and dual port. 38 * References: 39 * The XaQti XMAC II datasheet, 40 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 41 * The SysKonnect GEnesis manual, http://www.syskonnect.com 42 * 43 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 44 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 45 * convenience to others until Vitesse corrects this problem: 46 * 47 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 48 * 49 * Written by Bill Paul <wpaul@ee.columbia.edu> 50 * Department of Electrical Engineering 51 * Columbia University, New York City 52 */ 53 54 /* 55 * The SysKonnect gigabit ethernet adapters consist of two main 56 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 57 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 58 * components and a PHY while the GEnesis controller provides a PCI 59 * interface with DMA support. Each card may have between 512K and 60 * 2MB of SRAM on board depending on the configuration. 61 * 62 * The SysKonnect GEnesis controller can have either one or two XMAC 63 * chips connected to it, allowing single or dual port NIC configurations. 64 * SysKonnect has the distinction of being the only vendor on the market 65 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 66 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 67 * XMAC registers. This driver takes advantage of these features to allow 68 * both XMACs to operate as independent interfaces. 69 */ 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/sockio.h> 74 #include <sys/mbuf.h> 75 #include <sys/malloc.h> 76 #include <sys/kernel.h> 77 #include <sys/socket.h> 78 #include <sys/queue.h> 79 80 #include <net/if.h> 81 #include <net/if_arp.h> 82 #include <net/ethernet.h> 83 #include <net/if_dl.h> 84 #include <net/if_media.h> 85 86 #include <net/bpf.h> 87 88 #include <vm/vm.h> /* for vtophys */ 89 #include <vm/pmap.h> /* for vtophys */ 90 #include <machine/clock.h> /* for DELAY */ 91 #include <machine/bus_pio.h> 92 #include <machine/bus_memio.h> 93 #include <machine/bus.h> 94 #include <machine/resource.h> 95 #include <sys/bus.h> 96 #include <sys/rman.h> 97 98 #include <dev/mii/mii.h> 99 #include <dev/mii/miivar.h> 100 #include <dev/mii/brgphyreg.h> 101 102 #include <pci/pcireg.h> 103 #include <pci/pcivar.h> 104 105 #define SK_USEIOSPACE 106 107 #include <pci/if_skreg.h> 108 #include <pci/xmaciireg.h> 109 110 /* "controller miibus0" required. See GENERIC if you get errors here. */ 111 #include "miibus_if.h" 112 113 #ifndef lint 114 static const char rcsid[] = 115 "$FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $"; 116 #endif 117 118 static struct sk_type sk_devs[] = { 119 { SK_VENDORID, SK_DEVICEID_GE, "SysKonnect Gigabit Ethernet" }, 120 { 0, 0, NULL } 121 }; 122 123 static int sk_probe __P((device_t)); 124 static int sk_attach __P((device_t)); 125 static int sk_detach __P((device_t)); 126 static int sk_detach_xmac __P((device_t)); 127 static int sk_probe_xmac __P((device_t)); 128 static int sk_attach_xmac __P((device_t)); 129 static void sk_tick __P((void *)); 130 static void sk_intr __P((void *)); 131 static void sk_intr_xmac __P((struct sk_if_softc *)); 132 static void sk_intr_bcom __P((struct sk_if_softc *)); 133 static void sk_rxeof __P((struct sk_if_softc *)); 134 static void sk_txeof __P((struct sk_if_softc *)); 135 static int sk_encap __P((struct sk_if_softc *, struct mbuf *, 136 u_int32_t *)); 137 static void sk_start __P((struct ifnet *)); 138 static int sk_ioctl __P((struct ifnet *, u_long, caddr_t)); 139 static void sk_init __P((void *)); 140 static void sk_init_xmac __P((struct sk_if_softc *)); 141 static void sk_stop __P((struct sk_if_softc *)); 142 static void sk_watchdog __P((struct ifnet *)); 143 static void sk_shutdown __P((device_t)); 144 static int sk_ifmedia_upd __P((struct ifnet *)); 145 static void sk_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 146 static void sk_reset __P((struct sk_softc *)); 147 static int sk_newbuf __P((struct sk_if_softc *, 148 struct sk_chain *, struct mbuf *)); 149 static int sk_alloc_jumbo_mem __P((struct sk_if_softc *)); 150 static void *sk_jalloc __P((struct sk_if_softc *)); 151 static void sk_jfree __P((caddr_t, u_int)); 152 static void sk_jref __P((caddr_t, u_int)); 153 static int sk_init_rx_ring __P((struct sk_if_softc *)); 154 static void sk_init_tx_ring __P((struct sk_if_softc *)); 155 static u_int32_t sk_win_read_4 __P((struct sk_softc *, int)); 156 static u_int16_t sk_win_read_2 __P((struct sk_softc *, int)); 157 static u_int8_t sk_win_read_1 __P((struct sk_softc *, int)); 158 static void sk_win_write_4 __P((struct sk_softc *, int, u_int32_t)); 159 static void sk_win_write_2 __P((struct sk_softc *, int, u_int32_t)); 160 static void sk_win_write_1 __P((struct sk_softc *, int, u_int32_t)); 161 static u_int8_t sk_vpd_readbyte __P((struct sk_softc *, int)); 162 static void sk_vpd_read_res __P((struct sk_softc *, 163 struct vpd_res *, int)); 164 static void sk_vpd_read __P((struct sk_softc *)); 165 166 static int sk_miibus_readreg __P((device_t, int, int)); 167 static int sk_miibus_writereg __P((device_t, int, int, int)); 168 static void sk_miibus_statchg __P((device_t)); 169 170 static u_int32_t sk_calchash __P((caddr_t)); 171 static void sk_setfilt __P((struct sk_if_softc *, caddr_t, int)); 172 static void sk_setmulti __P((struct sk_if_softc *)); 173 174 #ifdef SK_USEIOSPACE 175 #define SK_RES SYS_RES_IOPORT 176 #define SK_RID SK_PCI_LOIO 177 #else 178 #define SK_RES SYS_RES_MEMORY 179 #define SK_RID SK_PCI_LOMEM 180 #endif 181 182 /* 183 * Note that we have newbus methods for both the GEnesis controller 184 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 185 * the miibus code is a child of the XMACs. We need to do it this way 186 * so that the miibus drivers can access the PHY registers on the 187 * right PHY. It's not quite what I had in mind, but it's the only 188 * design that achieves the desired effect. 189 */ 190 static device_method_t skc_methods[] = { 191 /* Device interface */ 192 DEVMETHOD(device_probe, sk_probe), 193 DEVMETHOD(device_attach, sk_attach), 194 DEVMETHOD(device_detach, sk_detach), 195 DEVMETHOD(device_shutdown, sk_shutdown), 196 197 /* bus interface */ 198 DEVMETHOD(bus_print_child, bus_generic_print_child), 199 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 200 201 { 0, 0 } 202 }; 203 204 static driver_t skc_driver = { 205 "skc", 206 skc_methods, 207 sizeof(struct sk_softc) 208 }; 209 210 static devclass_t skc_devclass; 211 212 static device_method_t sk_methods[] = { 213 /* Device interface */ 214 DEVMETHOD(device_probe, sk_probe_xmac), 215 DEVMETHOD(device_attach, sk_attach_xmac), 216 DEVMETHOD(device_detach, sk_detach_xmac), 217 DEVMETHOD(device_shutdown, bus_generic_shutdown), 218 219 /* bus interface */ 220 DEVMETHOD(bus_print_child, bus_generic_print_child), 221 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 222 223 /* MII interface */ 224 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 225 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 226 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 227 228 { 0, 0 } 229 }; 230 231 static driver_t sk_driver = { 232 "sk", 233 sk_methods, 234 sizeof(struct sk_if_softc) 235 }; 236 237 static devclass_t sk_devclass; 238 239 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0); 240 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 241 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 242 243 #define SK_SETBIT(sc, reg, x) \ 244 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 245 246 #define SK_CLRBIT(sc, reg, x) \ 247 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 248 249 #define SK_WIN_SETBIT_4(sc, reg, x) \ 250 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 251 252 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 253 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 254 255 #define SK_WIN_SETBIT_2(sc, reg, x) \ 256 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 257 258 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 259 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 260 261 static u_int32_t sk_win_read_4(sc, reg) 262 struct sk_softc *sc; 263 int reg; 264 { 265 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 266 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 267 } 268 269 static u_int16_t sk_win_read_2(sc, reg) 270 struct sk_softc *sc; 271 int reg; 272 { 273 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 274 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 275 } 276 277 static u_int8_t sk_win_read_1(sc, reg) 278 struct sk_softc *sc; 279 int reg; 280 { 281 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 282 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 283 } 284 285 static void sk_win_write_4(sc, reg, val) 286 struct sk_softc *sc; 287 int reg; 288 u_int32_t val; 289 { 290 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 291 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 292 return; 293 } 294 295 static void sk_win_write_2(sc, reg, val) 296 struct sk_softc *sc; 297 int reg; 298 u_int32_t val; 299 { 300 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 301 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), (u_int32_t)val); 302 return; 303 } 304 305 static void sk_win_write_1(sc, reg, val) 306 struct sk_softc *sc; 307 int reg; 308 u_int32_t val; 309 { 310 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 311 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 312 return; 313 } 314 315 /* 316 * The VPD EEPROM contains Vital Product Data, as suggested in 317 * the PCI 2.1 specification. The VPD data is separared into areas 318 * denoted by resource IDs. The SysKonnect VPD contains an ID string 319 * resource (the name of the adapter), a read-only area resource 320 * containing various key/data fields and a read/write area which 321 * can be used to store asset management information or log messages. 322 * We read the ID string and read-only into buffers attached to 323 * the controller softc structure for later use. At the moment, 324 * we only use the ID string during sk_attach(). 325 */ 326 static u_int8_t sk_vpd_readbyte(sc, addr) 327 struct sk_softc *sc; 328 int addr; 329 { 330 int i; 331 332 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 333 for (i = 0; i < SK_TIMEOUT; i++) { 334 DELAY(1); 335 if (sk_win_read_2(sc, 336 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 337 break; 338 } 339 340 if (i == SK_TIMEOUT) 341 return(0); 342 343 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 344 } 345 346 static void sk_vpd_read_res(sc, res, addr) 347 struct sk_softc *sc; 348 struct vpd_res *res; 349 int addr; 350 { 351 int i; 352 u_int8_t *ptr; 353 354 ptr = (u_int8_t *)res; 355 for (i = 0; i < sizeof(struct vpd_res); i++) 356 ptr[i] = sk_vpd_readbyte(sc, i + addr); 357 358 return; 359 } 360 361 static void sk_vpd_read(sc) 362 struct sk_softc *sc; 363 { 364 int pos = 0, i; 365 struct vpd_res res; 366 367 if (sc->sk_vpd_prodname != NULL) 368 free(sc->sk_vpd_prodname, M_DEVBUF); 369 if (sc->sk_vpd_readonly != NULL) 370 free(sc->sk_vpd_readonly, M_DEVBUF); 371 sc->sk_vpd_prodname = NULL; 372 sc->sk_vpd_readonly = NULL; 373 374 sk_vpd_read_res(sc, &res, pos); 375 376 if (res.vr_id != VPD_RES_ID) { 377 printf("skc%d: bad VPD resource id: expected %x got %x\n", 378 sc->sk_unit, VPD_RES_ID, res.vr_id); 379 return; 380 } 381 382 pos += sizeof(res); 383 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 384 for (i = 0; i < res.vr_len; i++) 385 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 386 sc->sk_vpd_prodname[i] = '\0'; 387 pos += i; 388 389 sk_vpd_read_res(sc, &res, pos); 390 391 if (res.vr_id != VPD_RES_READ) { 392 printf("skc%d: bad VPD resource id: expected %x got %x\n", 393 sc->sk_unit, VPD_RES_READ, res.vr_id); 394 return; 395 } 396 397 pos += sizeof(res); 398 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 399 for (i = 0; i < res.vr_len + 1; i++) 400 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 401 402 return; 403 } 404 405 static int sk_miibus_readreg(dev, phy, reg) 406 device_t dev; 407 int phy, reg; 408 { 409 struct sk_if_softc *sc_if; 410 int i; 411 412 sc_if = device_get_softc(dev); 413 414 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 415 return(0); 416 417 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 418 SK_XM_READ_2(sc_if, XM_PHY_DATA); 419 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 420 for (i = 0; i < SK_TIMEOUT; i++) { 421 DELAY(1); 422 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 423 XM_MMUCMD_PHYDATARDY) 424 break; 425 } 426 427 if (i == SK_TIMEOUT) { 428 printf("sk%d: phy failed to come ready\n", 429 sc_if->sk_unit); 430 return(0); 431 } 432 } 433 DELAY(1); 434 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 435 } 436 437 static int sk_miibus_writereg(dev, phy, reg, val) 438 device_t dev; 439 int phy, reg, val; 440 { 441 struct sk_if_softc *sc_if; 442 int i; 443 444 sc_if = device_get_softc(dev); 445 446 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 447 for (i = 0; i < SK_TIMEOUT; i++) { 448 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 449 break; 450 } 451 452 if (i == SK_TIMEOUT) { 453 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 454 return(ETIMEDOUT); 455 } 456 457 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 458 for (i = 0; i < SK_TIMEOUT; i++) { 459 DELAY(1); 460 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 461 break; 462 } 463 464 if (i == SK_TIMEOUT) 465 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 466 467 return(0); 468 } 469 470 static void sk_miibus_statchg(dev) 471 device_t dev; 472 { 473 struct sk_if_softc *sc_if; 474 struct mii_data *mii; 475 476 sc_if = device_get_softc(dev); 477 mii = device_get_softc(sc_if->sk_miibus); 478 479 /* 480 * If this is a GMII PHY, manually set the XMAC's 481 * duplex mode accordingly. 482 */ 483 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 484 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 485 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 486 } else { 487 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 488 } 489 } 490 491 return; 492 } 493 494 #define SK_POLY 0xEDB88320 495 #define SK_BITS 6 496 497 static u_int32_t sk_calchash(addr) 498 caddr_t addr; 499 { 500 u_int32_t idx, bit, data, crc; 501 502 /* Compute CRC for the address value. */ 503 crc = 0xFFFFFFFF; /* initial value */ 504 505 for (idx = 0; idx < 6; idx++) { 506 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 507 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0); 508 } 509 510 return (~crc & ((1 << SK_BITS) - 1)); 511 } 512 513 static void sk_setfilt(sc_if, addr, slot) 514 struct sk_if_softc *sc_if; 515 caddr_t addr; 516 int slot; 517 { 518 int base; 519 520 base = XM_RXFILT_ENTRY(slot); 521 522 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 523 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 524 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 525 526 return; 527 } 528 529 static void sk_setmulti(sc_if) 530 struct sk_if_softc *sc_if; 531 { 532 struct ifnet *ifp; 533 u_int32_t hashes[2] = { 0, 0 }; 534 int h, i; 535 struct ifmultiaddr *ifma; 536 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 537 538 ifp = &sc_if->arpcom.ac_if; 539 540 /* First, zot all the existing filters. */ 541 for (i = 1; i < XM_RXFILT_MAX; i++) 542 sk_setfilt(sc_if, (caddr_t)&dummy, i); 543 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 544 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 545 546 /* Now program new ones. */ 547 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 548 hashes[0] = 0xFFFFFFFF; 549 hashes[1] = 0xFFFFFFFF; 550 } else { 551 i = 1; 552 /* First find the tail of the list. */ 553 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 554 ifma = ifma->ifma_link.le_next) { 555 if (ifma->ifma_link.le_next == NULL) 556 break; 557 } 558 /* Now traverse the list backwards. */ 559 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 560 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 561 if (ifma->ifma_addr->sa_family != AF_LINK) 562 continue; 563 /* 564 * Program the first XM_RXFILT_MAX multicast groups 565 * into the perfect filter. For all others, 566 * use the hash table. 567 */ 568 if (i < XM_RXFILT_MAX) { 569 sk_setfilt(sc_if, 570 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 571 i++; 572 continue; 573 } 574 575 h = sk_calchash( 576 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 577 if (h < 32) 578 hashes[0] |= (1 << h); 579 else 580 hashes[1] |= (1 << (h - 32)); 581 } 582 } 583 584 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 585 XM_MODE_RX_USE_PERFECT); 586 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 587 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 588 589 return; 590 } 591 592 static int sk_init_rx_ring(sc_if) 593 struct sk_if_softc *sc_if; 594 { 595 struct sk_chain_data *cd; 596 struct sk_ring_data *rd; 597 int i; 598 599 cd = &sc_if->sk_cdata; 600 rd = sc_if->sk_rdata; 601 602 bzero((char *)rd->sk_rx_ring, 603 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 604 605 for (i = 0; i < SK_RX_RING_CNT; i++) { 606 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 607 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 608 return(ENOBUFS); 609 if (i == (SK_RX_RING_CNT - 1)) { 610 cd->sk_rx_chain[i].sk_next = 611 &cd->sk_rx_chain[0]; 612 rd->sk_rx_ring[i].sk_next = 613 vtophys(&rd->sk_rx_ring[0]); 614 } else { 615 cd->sk_rx_chain[i].sk_next = 616 &cd->sk_rx_chain[i + 1]; 617 rd->sk_rx_ring[i].sk_next = 618 vtophys(&rd->sk_rx_ring[i + 1]); 619 } 620 } 621 622 sc_if->sk_cdata.sk_rx_prod = 0; 623 sc_if->sk_cdata.sk_rx_cons = 0; 624 625 return(0); 626 } 627 628 static void sk_init_tx_ring(sc_if) 629 struct sk_if_softc *sc_if; 630 { 631 struct sk_chain_data *cd; 632 struct sk_ring_data *rd; 633 int i; 634 635 cd = &sc_if->sk_cdata; 636 rd = sc_if->sk_rdata; 637 638 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 639 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 640 641 for (i = 0; i < SK_TX_RING_CNT; i++) { 642 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 643 if (i == (SK_TX_RING_CNT - 1)) { 644 cd->sk_tx_chain[i].sk_next = 645 &cd->sk_tx_chain[0]; 646 rd->sk_tx_ring[i].sk_next = 647 vtophys(&rd->sk_tx_ring[0]); 648 } else { 649 cd->sk_tx_chain[i].sk_next = 650 &cd->sk_tx_chain[i + 1]; 651 rd->sk_tx_ring[i].sk_next = 652 vtophys(&rd->sk_tx_ring[i + 1]); 653 } 654 } 655 656 sc_if->sk_cdata.sk_tx_prod = 0; 657 sc_if->sk_cdata.sk_tx_cons = 0; 658 sc_if->sk_cdata.sk_tx_cnt = 0; 659 660 return; 661 } 662 663 static int sk_newbuf(sc_if, c, m) 664 struct sk_if_softc *sc_if; 665 struct sk_chain *c; 666 struct mbuf *m; 667 { 668 struct mbuf *m_new = NULL; 669 struct sk_rx_desc *r; 670 671 if (m == NULL) { 672 caddr_t *buf = NULL; 673 674 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 675 if (m_new == NULL) 676 return(ENOBUFS); 677 678 /* Allocate the jumbo buffer */ 679 buf = sk_jalloc(sc_if); 680 if (buf == NULL) { 681 m_freem(m_new); 682 #ifdef SK_VERBOSE 683 printf("sk%d: jumbo allocation failed " 684 "-- packet dropped!\n", sc_if->sk_unit); 685 #endif 686 return(ENOBUFS); 687 } 688 689 /* Attach the buffer to the mbuf */ 690 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 691 m_new->m_flags |= M_EXT; 692 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 693 m_new->m_len = SK_MCLBYTES; 694 m_new->m_ext.ext_free = sk_jfree; 695 m_new->m_ext.ext_ref = sk_jref; 696 } else { 697 /* 698 * We're re-using a previously allocated mbuf; 699 * be sure to re-init pointers and lengths to 700 * default values. 701 */ 702 m_new = m; 703 m_new->m_len = m_new->m_pkthdr.len = SK_MCLBYTES; 704 m_new->m_data = m_new->m_ext.ext_buf; 705 } 706 707 /* 708 * Adjust alignment so packet payload begins on a 709 * longword boundary. Mandatory for Alpha, useful on 710 * x86 too. 711 */ 712 m_adj(m_new, ETHER_ALIGN); 713 714 r = c->sk_desc; 715 c->sk_mbuf = m_new; 716 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 717 r->sk_ctl = m_new->m_len | SK_RXSTAT; 718 719 return(0); 720 } 721 722 /* 723 * Allocate jumbo buffer storage. The SysKonnect adapters support 724 * "jumbograms" (9K frames), although SysKonnect doesn't currently 725 * use them in their drivers. In order for us to use them, we need 726 * large 9K receive buffers, however standard mbuf clusters are only 727 * 2048 bytes in size. Consequently, we need to allocate and manage 728 * our own jumbo buffer pool. Fortunately, this does not require an 729 * excessive amount of additional code. 730 */ 731 static int sk_alloc_jumbo_mem(sc_if) 732 struct sk_if_softc *sc_if; 733 { 734 caddr_t ptr; 735 register int i; 736 struct sk_jpool_entry *entry; 737 738 /* Grab a big chunk o' storage. */ 739 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 740 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 741 742 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 743 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 744 return(ENOBUFS); 745 } 746 747 SLIST_INIT(&sc_if->sk_jfree_listhead); 748 SLIST_INIT(&sc_if->sk_jinuse_listhead); 749 750 /* 751 * Now divide it up into 9K pieces and save the addresses 752 * in an array. Note that we play an evil trick here by using 753 * the first few bytes in the buffer to hold the the address 754 * of the softc structure for this interface. This is because 755 * sk_jfree() needs it, but it is called by the mbuf management 756 * code which will not pass it to us explicitly. 757 */ 758 ptr = sc_if->sk_cdata.sk_jumbo_buf; 759 for (i = 0; i < SK_JSLOTS; i++) { 760 u_int64_t **aptr; 761 aptr = (u_int64_t **)ptr; 762 aptr[0] = (u_int64_t *)sc_if; 763 ptr += sizeof(u_int64_t); 764 sc_if->sk_cdata.sk_jslots[i].sk_buf = ptr; 765 sc_if->sk_cdata.sk_jslots[i].sk_inuse = 0; 766 ptr += SK_MCLBYTES; 767 entry = malloc(sizeof(struct sk_jpool_entry), 768 M_DEVBUF, M_NOWAIT); 769 if (entry == NULL) { 770 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF); 771 sc_if->sk_cdata.sk_jumbo_buf = NULL; 772 printf("sk%d: no memory for jumbo " 773 "buffer queue!\n", sc_if->sk_unit); 774 return(ENOBUFS); 775 } 776 entry->slot = i; 777 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 778 entry, jpool_entries); 779 } 780 781 return(0); 782 } 783 784 /* 785 * Allocate a jumbo buffer. 786 */ 787 static void *sk_jalloc(sc_if) 788 struct sk_if_softc *sc_if; 789 { 790 struct sk_jpool_entry *entry; 791 792 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 793 794 if (entry == NULL) { 795 #ifdef SK_VERBOSE 796 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 797 #endif 798 return(NULL); 799 } 800 801 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 802 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 803 sc_if->sk_cdata.sk_jslots[entry->slot].sk_inuse = 1; 804 return(sc_if->sk_cdata.sk_jslots[entry->slot].sk_buf); 805 } 806 807 /* 808 * Adjust usage count on a jumbo buffer. In general this doesn't 809 * get used much because our jumbo buffers don't get passed around 810 * a lot, but it's implemented for correctness. 811 */ 812 static void sk_jref(buf, size) 813 caddr_t buf; 814 u_int size; 815 { 816 struct sk_if_softc *sc_if; 817 u_int64_t **aptr; 818 register int i; 819 820 /* Extract the softc struct pointer. */ 821 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 822 sc_if = (struct sk_if_softc *)(aptr[0]); 823 824 if (sc_if == NULL) 825 panic("sk_jref: can't find softc pointer!"); 826 827 if (size != SK_MCLBYTES) 828 panic("sk_jref: adjusting refcount of buf of wrong size!"); 829 830 /* calculate the slot this buffer belongs to */ 831 832 i = ((vm_offset_t)aptr 833 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 834 835 if ((i < 0) || (i >= SK_JSLOTS)) 836 panic("sk_jref: asked to reference buffer " 837 "that we don't manage!"); 838 else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) 839 panic("sk_jref: buffer already free!"); 840 else 841 sc_if->sk_cdata.sk_jslots[i].sk_inuse++; 842 843 return; 844 } 845 846 /* 847 * Release a jumbo buffer. 848 */ 849 static void sk_jfree(buf, size) 850 caddr_t buf; 851 u_int size; 852 { 853 struct sk_if_softc *sc_if; 854 u_int64_t **aptr; 855 int i; 856 struct sk_jpool_entry *entry; 857 858 /* Extract the softc struct pointer. */ 859 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 860 sc_if = (struct sk_if_softc *)(aptr[0]); 861 862 if (sc_if == NULL) 863 panic("sk_jfree: can't find softc pointer!"); 864 865 if (size != SK_MCLBYTES) 866 panic("sk_jfree: freeing buffer of wrong size!"); 867 868 /* calculate the slot this buffer belongs to */ 869 870 i = ((vm_offset_t)aptr 871 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 872 873 if ((i < 0) || (i >= SK_JSLOTS)) 874 panic("sk_jfree: asked to free buffer that we don't manage!"); 875 else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) 876 panic("sk_jfree: buffer already free!"); 877 else { 878 sc_if->sk_cdata.sk_jslots[i].sk_inuse--; 879 if(sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) { 880 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 881 if (entry == NULL) 882 panic("sk_jfree: buffer not in use!"); 883 entry->slot = i; 884 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, 885 jpool_entries); 886 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 887 entry, jpool_entries); 888 } 889 } 890 891 return; 892 } 893 894 /* 895 * Set media options. 896 */ 897 static int sk_ifmedia_upd(ifp) 898 struct ifnet *ifp; 899 { 900 struct sk_if_softc *sc_if; 901 struct mii_data *mii; 902 903 sc_if = ifp->if_softc; 904 mii = device_get_softc(sc_if->sk_miibus); 905 sk_init(sc_if); 906 mii_mediachg(mii); 907 908 return(0); 909 } 910 911 /* 912 * Report current media status. 913 */ 914 static void sk_ifmedia_sts(ifp, ifmr) 915 struct ifnet *ifp; 916 struct ifmediareq *ifmr; 917 { 918 struct sk_if_softc *sc_if; 919 struct mii_data *mii; 920 921 sc_if = ifp->if_softc; 922 mii = device_get_softc(sc_if->sk_miibus); 923 924 mii_pollstat(mii); 925 ifmr->ifm_active = mii->mii_media_active; 926 ifmr->ifm_status = mii->mii_media_status; 927 928 return; 929 } 930 931 static int sk_ioctl(ifp, command, data) 932 struct ifnet *ifp; 933 u_long command; 934 caddr_t data; 935 { 936 struct sk_if_softc *sc_if = ifp->if_softc; 937 struct ifreq *ifr = (struct ifreq *) data; 938 int s, error = 0; 939 struct mii_data *mii; 940 941 s = splimp(); 942 943 switch(command) { 944 case SIOCSIFADDR: 945 case SIOCGIFADDR: 946 error = ether_ioctl(ifp, command, data); 947 break; 948 case SIOCSIFMTU: 949 if (ifr->ifr_mtu > SK_JUMBO_MTU) 950 error = EINVAL; 951 else { 952 ifp->if_mtu = ifr->ifr_mtu; 953 sk_init(sc_if); 954 } 955 break; 956 case SIOCSIFFLAGS: 957 if (ifp->if_flags & IFF_UP) { 958 if (ifp->if_flags & IFF_RUNNING && 959 ifp->if_flags & IFF_PROMISC && 960 !(sc_if->sk_if_flags & IFF_PROMISC)) { 961 SK_XM_SETBIT_4(sc_if, XM_MODE, 962 XM_MODE_RX_PROMISC); 963 sk_setmulti(sc_if); 964 } else if (ifp->if_flags & IFF_RUNNING && 965 !(ifp->if_flags & IFF_PROMISC) && 966 sc_if->sk_if_flags & IFF_PROMISC) { 967 SK_XM_CLRBIT_4(sc_if, XM_MODE, 968 XM_MODE_RX_PROMISC); 969 sk_setmulti(sc_if); 970 } else 971 sk_init(sc_if); 972 } else { 973 if (ifp->if_flags & IFF_RUNNING) 974 sk_stop(sc_if); 975 } 976 sc_if->sk_if_flags = ifp->if_flags; 977 error = 0; 978 break; 979 case SIOCADDMULTI: 980 case SIOCDELMULTI: 981 sk_setmulti(sc_if); 982 error = 0; 983 break; 984 case SIOCGIFMEDIA: 985 case SIOCSIFMEDIA: 986 mii = device_get_softc(sc_if->sk_miibus); 987 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 988 break; 989 default: 990 error = EINVAL; 991 break; 992 } 993 994 (void)splx(s); 995 996 return(error); 997 } 998 999 /* 1000 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1001 * IDs against our list and return a device name if we find a match. 1002 */ 1003 static int sk_probe(dev) 1004 device_t dev; 1005 { 1006 struct sk_type *t; 1007 1008 t = sk_devs; 1009 1010 while(t->sk_name != NULL) { 1011 if ((pci_get_vendor(dev) == t->sk_vid) && 1012 (pci_get_device(dev) == t->sk_did)) { 1013 device_set_desc(dev, t->sk_name); 1014 return(0); 1015 } 1016 t++; 1017 } 1018 1019 return(ENXIO); 1020 } 1021 1022 /* 1023 * Force the GEnesis into reset, then bring it out of reset. 1024 */ 1025 static void sk_reset(sc) 1026 struct sk_softc *sc; 1027 { 1028 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_RESET); 1029 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_RESET); 1030 DELAY(1000); 1031 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_UNRESET); 1032 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1033 1034 /* Configure packet arbiter */ 1035 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1036 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1037 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1038 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1039 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1040 1041 /* Enable RAM interface */ 1042 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1043 1044 /* 1045 * Configure interrupt moderation. The moderation timer 1046 * defers interrupts specified in the interrupt moderation 1047 * timer mask based on the timeout specified in the interrupt 1048 * moderation timer init register. Each bit in the timer 1049 * register represents 18.825ns, so to specify a timeout in 1050 * microseconds, we have to multiply by 54. 1051 */ 1052 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1053 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1054 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1055 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1056 1057 return; 1058 } 1059 1060 static int sk_probe_xmac(dev) 1061 device_t dev; 1062 { 1063 /* 1064 * Not much to do here. We always know there will be 1065 * at least one XMAC present, and if there are two, 1066 * sk_attach() will create a second device instance 1067 * for us. 1068 */ 1069 device_set_desc(dev, "XaQti Corp. XMAC II"); 1070 1071 return(0); 1072 } 1073 1074 /* 1075 * Each XMAC chip is attached as a separate logical IP interface. 1076 * Single port cards will have only one logical interface of course. 1077 */ 1078 static int sk_attach_xmac(dev) 1079 device_t dev; 1080 { 1081 struct sk_softc *sc; 1082 struct sk_if_softc *sc_if; 1083 struct ifnet *ifp; 1084 int i, port; 1085 1086 if (dev == NULL) 1087 return(EINVAL); 1088 1089 sc_if = device_get_softc(dev); 1090 sc = device_get_softc(device_get_parent(dev)); 1091 port = *(int *)device_get_ivars(dev); 1092 free(device_get_ivars(dev), M_DEVBUF); 1093 device_set_ivars(dev, NULL); 1094 sc_if->sk_dev = dev; 1095 1096 bzero((char *)sc_if, sizeof(struct sk_if_softc)); 1097 1098 sc_if->sk_dev = dev; 1099 sc_if->sk_unit = device_get_unit(dev); 1100 sc_if->sk_port = port; 1101 sc_if->sk_softc = sc; 1102 sc->sk_if[port] = sc_if; 1103 if (port == SK_PORT_A) 1104 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1105 if (port == SK_PORT_B) 1106 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1107 1108 /* 1109 * Get station address for this interface. Note that 1110 * dual port cards actually come with three station 1111 * addresses: one for each port, plus an extra. The 1112 * extra one is used by the SysKonnect driver software 1113 * as a 'virtual' station address for when both ports 1114 * are operating in failover mode. Currently we don't 1115 * use this extra address. 1116 */ 1117 for (i = 0; i < ETHER_ADDR_LEN; i++) 1118 sc_if->arpcom.ac_enaddr[i] = 1119 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1120 1121 printf("sk%d: Ethernet address: %6D\n", 1122 sc_if->sk_unit, sc_if->arpcom.ac_enaddr, ":"); 1123 1124 /* 1125 * Set up RAM buffer addresses. The NIC will have a certain 1126 * amount of SRAM on it, somewhere between 512K and 2MB. We 1127 * need to divide this up a) between the transmitter and 1128 * receiver and b) between the two XMACs, if this is a 1129 * dual port NIC. Our algotithm is to divide up the memory 1130 * evenly so that everyone gets a fair share. 1131 */ 1132 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1133 u_int32_t chunk, val; 1134 1135 chunk = sc->sk_ramsize / 2; 1136 val = sc->sk_rboff / sizeof(u_int64_t); 1137 sc_if->sk_rx_ramstart = val; 1138 val += (chunk / sizeof(u_int64_t)); 1139 sc_if->sk_rx_ramend = val - 1; 1140 sc_if->sk_tx_ramstart = val; 1141 val += (chunk / sizeof(u_int64_t)); 1142 sc_if->sk_tx_ramend = val - 1; 1143 } else { 1144 u_int32_t chunk, val; 1145 1146 chunk = sc->sk_ramsize / 4; 1147 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1148 sizeof(u_int64_t); 1149 sc_if->sk_rx_ramstart = val; 1150 val += (chunk / sizeof(u_int64_t)); 1151 sc_if->sk_rx_ramend = val - 1; 1152 sc_if->sk_tx_ramstart = val; 1153 val += (chunk / sizeof(u_int64_t)); 1154 sc_if->sk_tx_ramend = val - 1; 1155 } 1156 1157 /* Read and save PHY type and set PHY address */ 1158 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1159 switch(sc_if->sk_phytype) { 1160 case SK_PHYTYPE_XMAC: 1161 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1162 break; 1163 case SK_PHYTYPE_BCOM: 1164 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1165 break; 1166 default: 1167 printf("skc%d: unsupported PHY type: %d\n", 1168 sc->sk_unit, sc_if->sk_phytype); 1169 return(ENODEV); 1170 } 1171 1172 /* Allocate the descriptor queues. */ 1173 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1174 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1175 1176 if (sc_if->sk_rdata == NULL) { 1177 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1178 sc->sk_if[port] = NULL; 1179 return(ENOMEM); 1180 } 1181 1182 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1183 1184 /* Try to allocate memory for jumbo buffers. */ 1185 if (sk_alloc_jumbo_mem(sc_if)) { 1186 printf("sk%d: jumbo buffer allocation failed\n", 1187 sc_if->sk_unit); 1188 contigfree(sc_if->sk_rdata, 1189 sizeof(struct sk_ring_data), M_DEVBUF); 1190 sc->sk_if[port] = NULL; 1191 return(ENOMEM); 1192 } 1193 1194 ifp = &sc_if->arpcom.ac_if; 1195 ifp->if_softc = sc_if; 1196 ifp->if_unit = sc_if->sk_unit; 1197 ifp->if_name = "sk"; 1198 ifp->if_mtu = ETHERMTU; 1199 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1200 ifp->if_ioctl = sk_ioctl; 1201 ifp->if_output = ether_output; 1202 ifp->if_start = sk_start; 1203 ifp->if_watchdog = sk_watchdog; 1204 ifp->if_init = sk_init; 1205 ifp->if_baudrate = 1000000000; 1206 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1; 1207 1208 /* 1209 * Do miibus setup. 1210 */ 1211 sk_init_xmac(sc_if); 1212 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1213 sk_ifmedia_upd, sk_ifmedia_sts)) { 1214 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1215 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, 1216 M_DEVBUF); 1217 contigfree(sc_if->sk_rdata, 1218 sizeof(struct sk_ring_data), M_DEVBUF); 1219 return(ENXIO); 1220 } 1221 1222 /* 1223 * Call MI attach routine. 1224 */ 1225 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1226 callout_handle_init(&sc_if->sk_tick_ch); 1227 1228 return(0); 1229 } 1230 1231 /* 1232 * Attach the interface. Allocate softc structures, do ifmedia 1233 * setup and ethernet/BPF attach. 1234 */ 1235 static int sk_attach(dev) 1236 device_t dev; 1237 { 1238 int s; 1239 u_int32_t command; 1240 struct sk_softc *sc; 1241 int unit, error = 0, rid, *port; 1242 1243 s = splimp(); 1244 1245 sc = device_get_softc(dev); 1246 unit = device_get_unit(dev); 1247 bzero(sc, sizeof(struct sk_softc)); 1248 1249 /* 1250 * Handle power management nonsense. 1251 */ 1252 command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF; 1253 if (command == 0x01) { 1254 1255 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4); 1256 if (command & SK_PSTATE_MASK) { 1257 u_int32_t iobase, membase, irq; 1258 1259 /* Save important PCI config data. */ 1260 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1261 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1262 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1263 1264 /* Reset the power state. */ 1265 printf("skc%d: chip is in D%d power mode " 1266 "-- setting to D0\n", unit, command & SK_PSTATE_MASK); 1267 command &= 0xFFFFFFFC; 1268 pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4); 1269 1270 /* Restore PCI config data. */ 1271 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1272 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1273 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1274 } 1275 } 1276 1277 /* 1278 * Map control/status registers. 1279 */ 1280 command = pci_read_config(dev, PCIR_COMMAND, 4); 1281 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1282 pci_write_config(dev, PCIR_COMMAND, command, 4); 1283 command = pci_read_config(dev, PCIR_COMMAND, 4); 1284 1285 #ifdef SK_USEIOSPACE 1286 if (!(command & PCIM_CMD_PORTEN)) { 1287 printf("skc%d: failed to enable I/O ports!\n", unit); 1288 error = ENXIO; 1289 goto fail; 1290 } 1291 #else 1292 if (!(command & PCIM_CMD_MEMEN)) { 1293 printf("skc%d: failed to enable memory mapping!\n", unit); 1294 error = ENXIO; 1295 goto fail; 1296 } 1297 #endif 1298 1299 rid = SK_RID; 1300 sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid, 1301 0, ~0, 1, RF_ACTIVE); 1302 1303 if (sc->sk_res == NULL) { 1304 printf("sk%d: couldn't map ports/memory\n", unit); 1305 error = ENXIO; 1306 goto fail; 1307 } 1308 1309 sc->sk_btag = rman_get_bustag(sc->sk_res); 1310 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1311 1312 /* Allocate interrupt */ 1313 rid = 0; 1314 sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1315 RF_SHAREABLE | RF_ACTIVE); 1316 1317 if (sc->sk_irq == NULL) { 1318 printf("skc%d: couldn't map interrupt\n", unit); 1319 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1320 error = ENXIO; 1321 goto fail; 1322 } 1323 1324 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET, 1325 sk_intr, sc, &sc->sk_intrhand); 1326 1327 if (error) { 1328 printf("skc%d: couldn't set up irq\n", unit); 1329 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1330 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1331 goto fail; 1332 } 1333 1334 /* Reset the adapter. */ 1335 sk_reset(sc); 1336 1337 sc->sk_unit = unit; 1338 1339 /* Read and save vital product data from EEPROM. */ 1340 sk_vpd_read(sc); 1341 1342 /* Read and save RAM size and RAMbuffer offset */ 1343 switch(sk_win_read_1(sc, SK_EPROM0)) { 1344 case SK_RAMSIZE_512K_64: 1345 sc->sk_ramsize = 0x80000; 1346 sc->sk_rboff = SK_RBOFF_0; 1347 break; 1348 case SK_RAMSIZE_1024K_64: 1349 sc->sk_ramsize = 0x100000; 1350 sc->sk_rboff = SK_RBOFF_80000; 1351 break; 1352 case SK_RAMSIZE_1024K_128: 1353 sc->sk_ramsize = 0x100000; 1354 sc->sk_rboff = SK_RBOFF_0; 1355 break; 1356 case SK_RAMSIZE_2048K_128: 1357 sc->sk_ramsize = 0x200000; 1358 sc->sk_rboff = SK_RBOFF_0; 1359 break; 1360 default: 1361 printf("skc%d: unknown ram size: %d\n", 1362 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1363 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1364 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1365 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1366 error = ENXIO; 1367 goto fail; 1368 break; 1369 } 1370 1371 /* Read and save physical media type */ 1372 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1373 case SK_PMD_1000BASESX: 1374 sc->sk_pmd = IFM_1000_SX; 1375 break; 1376 case SK_PMD_1000BASELX: 1377 sc->sk_pmd = IFM_1000_LX; 1378 break; 1379 case SK_PMD_1000BASECX: 1380 sc->sk_pmd = IFM_1000_CX; 1381 break; 1382 case SK_PMD_1000BASETX: 1383 sc->sk_pmd = IFM_1000_TX; 1384 break; 1385 default: 1386 printf("skc%d: unknown media type: 0x%x\n", 1387 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1388 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1389 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1390 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1391 error = ENXIO; 1392 goto fail; 1393 } 1394 1395 /* Announce the product name. */ 1396 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1397 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1398 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1399 *port = SK_PORT_A; 1400 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1401 1402 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1403 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1404 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1405 *port = SK_PORT_B; 1406 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1407 } 1408 1409 /* Turn on the 'driver is loaded' LED. */ 1410 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1411 1412 bus_generic_attach(dev); 1413 1414 fail: 1415 splx(s); 1416 return(error); 1417 } 1418 1419 static int sk_detach_xmac(dev) 1420 device_t dev; 1421 { 1422 struct sk_softc *sc; 1423 struct sk_if_softc *sc_if; 1424 struct ifnet *ifp; 1425 int s; 1426 1427 s = splimp(); 1428 1429 sc = device_get_softc(device_get_parent(dev)); 1430 sc_if = device_get_softc(dev); 1431 ifp = &sc_if->arpcom.ac_if; 1432 sk_stop(sc_if); 1433 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1434 bus_generic_detach(dev); 1435 if (sc_if->sk_miibus != NULL) 1436 device_delete_child(dev, sc_if->sk_miibus); 1437 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1438 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF); 1439 1440 return(0); 1441 } 1442 1443 static int sk_detach(dev) 1444 device_t dev; 1445 { 1446 struct sk_softc *sc; 1447 int s; 1448 1449 s = splimp(); 1450 1451 sc = device_get_softc(dev); 1452 1453 bus_generic_detach(dev); 1454 if (sc->sk_devs[SK_PORT_A] != NULL) 1455 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1456 if (sc->sk_devs[SK_PORT_B] != NULL) 1457 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1458 1459 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1460 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1461 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1462 1463 splx(s); 1464 1465 return(0); 1466 } 1467 1468 static int sk_encap(sc_if, m_head, txidx) 1469 struct sk_if_softc *sc_if; 1470 struct mbuf *m_head; 1471 u_int32_t *txidx; 1472 { 1473 struct sk_tx_desc *f = NULL; 1474 struct mbuf *m; 1475 u_int32_t frag, cur, cnt = 0; 1476 1477 m = m_head; 1478 cur = frag = *txidx; 1479 1480 /* 1481 * Start packing the mbufs in this chain into 1482 * the fragment pointers. Stop when we run out 1483 * of fragments or hit the end of the mbuf chain. 1484 */ 1485 for (m = m_head; m != NULL; m = m->m_next) { 1486 if (m->m_len != 0) { 1487 if ((SK_TX_RING_CNT - 1488 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1489 return(ENOBUFS); 1490 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1491 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1492 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1493 if (cnt == 0) 1494 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1495 else 1496 f->sk_ctl |= SK_TXCTL_OWN; 1497 cur = frag; 1498 SK_INC(frag, SK_TX_RING_CNT); 1499 cnt++; 1500 } 1501 } 1502 1503 if (m != NULL) 1504 return(ENOBUFS); 1505 1506 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1507 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1508 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1509 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1510 sc_if->sk_cdata.sk_tx_cnt += cnt; 1511 1512 *txidx = frag; 1513 1514 return(0); 1515 } 1516 1517 static void sk_start(ifp) 1518 struct ifnet *ifp; 1519 { 1520 struct sk_softc *sc; 1521 struct sk_if_softc *sc_if; 1522 struct mbuf *m_head = NULL; 1523 u_int32_t idx; 1524 1525 sc_if = ifp->if_softc; 1526 sc = sc_if->sk_softc; 1527 1528 idx = sc_if->sk_cdata.sk_tx_prod; 1529 1530 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1531 IF_DEQUEUE(&ifp->if_snd, m_head); 1532 if (m_head == NULL) 1533 break; 1534 1535 /* 1536 * Pack the data into the transmit ring. If we 1537 * don't have room, set the OACTIVE flag and wait 1538 * for the NIC to drain the ring. 1539 */ 1540 if (sk_encap(sc_if, m_head, &idx)) { 1541 IF_PREPEND(&ifp->if_snd, m_head); 1542 ifp->if_flags |= IFF_OACTIVE; 1543 break; 1544 } 1545 1546 /* 1547 * If there's a BPF listener, bounce a copy of this frame 1548 * to him. 1549 */ 1550 if (ifp->if_bpf) 1551 bpf_mtap(ifp, m_head); 1552 } 1553 1554 /* Transmit */ 1555 sc_if->sk_cdata.sk_tx_prod = idx; 1556 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1557 1558 /* Set a timeout in case the chip goes out to lunch. */ 1559 ifp->if_timer = 5; 1560 1561 return; 1562 } 1563 1564 1565 static void sk_watchdog(ifp) 1566 struct ifnet *ifp; 1567 { 1568 struct sk_if_softc *sc_if; 1569 1570 sc_if = ifp->if_softc; 1571 1572 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1573 sk_init(sc_if); 1574 1575 return; 1576 } 1577 1578 static void sk_shutdown(dev) 1579 device_t dev; 1580 { 1581 struct sk_softc *sc; 1582 1583 sc = device_get_softc(dev); 1584 1585 /* Turn off the 'driver is loaded' LED. */ 1586 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1587 1588 /* 1589 * Reset the GEnesis controller. Doing this should also 1590 * assert the resets on the attached XMAC(s). 1591 */ 1592 sk_reset(sc); 1593 1594 return; 1595 } 1596 1597 static void sk_rxeof(sc_if) 1598 struct sk_if_softc *sc_if; 1599 { 1600 struct ether_header *eh; 1601 struct mbuf *m; 1602 struct ifnet *ifp; 1603 struct sk_chain *cur_rx; 1604 int total_len = 0; 1605 int i; 1606 u_int32_t rxstat; 1607 1608 ifp = &sc_if->arpcom.ac_if; 1609 i = sc_if->sk_cdata.sk_rx_prod; 1610 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1611 1612 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1613 1614 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1615 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1616 m = cur_rx->sk_mbuf; 1617 cur_rx->sk_mbuf = NULL; 1618 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1619 SK_INC(i, SK_RX_RING_CNT); 1620 1621 if (rxstat & XM_RXSTAT_ERRFRAME) { 1622 ifp->if_ierrors++; 1623 sk_newbuf(sc_if, cur_rx, m); 1624 continue; 1625 } 1626 1627 /* 1628 * Try to allocate a new jumbo buffer. If that 1629 * fails, copy the packet to mbufs and put the 1630 * jumbo buffer back in the ring so it can be 1631 * re-used. If allocating mbufs fails, then we 1632 * have to drop the packet. 1633 */ 1634 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1635 struct mbuf *m0; 1636 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1637 total_len + ETHER_ALIGN, 0, ifp, NULL); 1638 sk_newbuf(sc_if, cur_rx, m); 1639 if (m0 == NULL) { 1640 printf("sk%d: no receive buffers " 1641 "available -- packet dropped!\n", 1642 sc_if->sk_unit); 1643 ifp->if_ierrors++; 1644 continue; 1645 } 1646 m_adj(m0, ETHER_ALIGN); 1647 m = m0; 1648 } else { 1649 m->m_pkthdr.rcvif = ifp; 1650 m->m_pkthdr.len = m->m_len = total_len; 1651 } 1652 1653 ifp->if_ipackets++; 1654 eh = mtod(m, struct ether_header *); 1655 1656 /* Remove header from mbuf and pass it on. */ 1657 m_adj(m, sizeof(struct ether_header)); 1658 ether_input(ifp, eh, m); 1659 } 1660 1661 sc_if->sk_cdata.sk_rx_prod = i; 1662 1663 return; 1664 } 1665 1666 static void sk_txeof(sc_if) 1667 struct sk_if_softc *sc_if; 1668 { 1669 struct sk_tx_desc *cur_tx = NULL; 1670 struct ifnet *ifp; 1671 u_int32_t idx; 1672 1673 ifp = &sc_if->arpcom.ac_if; 1674 1675 /* 1676 * Go through our tx ring and free mbufs for those 1677 * frames that have been sent. 1678 */ 1679 idx = sc_if->sk_cdata.sk_tx_cons; 1680 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1681 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1682 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1683 break; 1684 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1685 ifp->if_opackets++; 1686 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1687 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1688 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1689 } 1690 sc_if->sk_cdata.sk_tx_cnt--; 1691 SK_INC(idx, SK_TX_RING_CNT); 1692 ifp->if_timer = 0; 1693 } 1694 1695 sc_if->sk_cdata.sk_tx_cons = idx; 1696 1697 if (cur_tx != NULL) 1698 ifp->if_flags &= ~IFF_OACTIVE; 1699 1700 return; 1701 } 1702 1703 static void sk_tick(xsc_if) 1704 void *xsc_if; 1705 { 1706 struct sk_if_softc *sc_if; 1707 struct mii_data *mii; 1708 struct ifnet *ifp; 1709 int i; 1710 1711 sc_if = xsc_if; 1712 ifp = &sc_if->arpcom.ac_if; 1713 mii = device_get_softc(sc_if->sk_miibus); 1714 1715 if (!(ifp->if_flags & IFF_UP)) 1716 return; 1717 1718 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1719 sk_intr_bcom(sc_if); 1720 return; 1721 } 1722 1723 /* 1724 * According to SysKonnect, the correct way to verify that 1725 * the link has come back up is to poll bit 0 of the GPIO 1726 * register three times. This pin has the signal from the 1727 * link_sync pin connected to it; if we read the same link 1728 * state 3 times in a row, we know the link is up. 1729 */ 1730 for (i = 0; i < 3; i++) { 1731 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1732 break; 1733 } 1734 1735 if (i != 3) { 1736 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1737 return; 1738 } 1739 1740 /* Turn the GP0 interrupt back on. */ 1741 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1742 SK_XM_READ_2(sc_if, XM_ISR); 1743 mii_tick(mii); 1744 mii_pollstat(mii); 1745 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 1746 1747 return; 1748 } 1749 1750 static void sk_intr_bcom(sc_if) 1751 struct sk_if_softc *sc_if; 1752 { 1753 struct sk_softc *sc; 1754 struct mii_data *mii; 1755 struct ifnet *ifp; 1756 int status; 1757 1758 sc = sc_if->sk_softc; 1759 mii = device_get_softc(sc_if->sk_miibus); 1760 ifp = &sc_if->arpcom.ac_if; 1761 1762 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1763 1764 /* 1765 * Read the PHY interrupt register to make sure 1766 * we clear any pending interrupts. 1767 */ 1768 status = sk_miibus_readreg(sc_if->sk_dev, 1769 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1770 1771 if (!(ifp->if_flags & IFF_RUNNING)) { 1772 sk_init_xmac(sc_if); 1773 return; 1774 } 1775 1776 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1777 int lstat; 1778 lstat = sk_miibus_readreg(sc_if->sk_dev, 1779 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 1780 1781 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1782 mii_mediachg(mii); 1783 /* Turn off the link LED. */ 1784 SK_IF_WRITE_1(sc_if, 0, 1785 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1786 sc_if->sk_link = 0; 1787 } else if (status & BRGPHY_ISR_LNK_CHG) { 1788 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM, 1789 BRGPHY_MII_IMR, 0xFF00); 1790 mii_tick(mii); 1791 sc_if->sk_link = 1; 1792 /* Turn on the link LED. */ 1793 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1794 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1795 SK_LINKLED_BLINK_OFF); 1796 mii_pollstat(mii); 1797 } else { 1798 mii_tick(mii); 1799 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1800 } 1801 } 1802 1803 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1804 1805 return; 1806 } 1807 1808 static void sk_intr_xmac(sc_if) 1809 struct sk_if_softc *sc_if; 1810 { 1811 struct sk_softc *sc; 1812 u_int16_t status; 1813 struct mii_data *mii; 1814 1815 sc = sc_if->sk_softc; 1816 mii = device_get_softc(sc_if->sk_miibus); 1817 status = SK_XM_READ_2(sc_if, XM_ISR); 1818 1819 /* 1820 * Link has gone down. Start MII tick timeout to 1821 * watch for link resync. 1822 */ 1823 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1824 if (status & XM_ISR_GP0_SET) { 1825 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1826 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1827 } 1828 1829 if (status & XM_ISR_AUTONEG_DONE) { 1830 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1831 } 1832 } 1833 1834 if (status & XM_IMR_TX_UNDERRUN) 1835 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1836 1837 if (status & XM_IMR_RX_OVERRUN) 1838 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1839 1840 status = SK_XM_READ_2(sc_if, XM_ISR); 1841 1842 return; 1843 } 1844 1845 static void sk_intr(xsc) 1846 void *xsc; 1847 { 1848 struct sk_softc *sc = xsc; 1849 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 1850 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1851 u_int32_t status; 1852 1853 sc_if0 = sc->sk_if[SK_PORT_A]; 1854 sc_if1 = sc->sk_if[SK_PORT_B]; 1855 1856 if (sc_if0 != NULL) 1857 ifp0 = &sc_if0->arpcom.ac_if; 1858 if (sc_if1 != NULL) 1859 ifp1 = &sc_if1->arpcom.ac_if; 1860 1861 for (;;) { 1862 status = CSR_READ_4(sc, SK_ISSR); 1863 if (!(status & sc->sk_intrmask)) 1864 break; 1865 1866 /* Handle receive interrupts first. */ 1867 if (status & SK_ISR_RX1_EOF) { 1868 sk_rxeof(sc_if0); 1869 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1870 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1871 } 1872 if (status & SK_ISR_RX2_EOF) { 1873 sk_rxeof(sc_if1); 1874 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1875 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1876 } 1877 1878 /* Then transmit interrupts. */ 1879 if (status & SK_ISR_TX1_S_EOF) { 1880 sk_txeof(sc_if0); 1881 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1882 SK_TXBMU_CLR_IRQ_EOF); 1883 } 1884 if (status & SK_ISR_TX2_S_EOF) { 1885 sk_txeof(sc_if1); 1886 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1887 SK_TXBMU_CLR_IRQ_EOF); 1888 } 1889 1890 /* Then MAC interrupts. */ 1891 if (status & SK_ISR_MAC1 && 1892 ifp0->if_flags & IFF_RUNNING) 1893 sk_intr_xmac(sc_if0); 1894 1895 if (status & SK_ISR_MAC2 && 1896 ifp1->if_flags & IFF_RUNNING) 1897 sk_intr_xmac(sc_if1); 1898 1899 if (status & SK_ISR_EXTERNAL_REG) { 1900 if (ifp0 != NULL) 1901 sk_intr_bcom(sc_if0); 1902 if (ifp1 != NULL) 1903 sk_intr_bcom(sc_if1); 1904 } 1905 } 1906 1907 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1908 1909 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL) 1910 sk_start(ifp0); 1911 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL) 1912 sk_start(ifp1); 1913 1914 return; 1915 } 1916 1917 static void sk_init_xmac(sc_if) 1918 struct sk_if_softc *sc_if; 1919 { 1920 struct sk_softc *sc; 1921 struct ifnet *ifp; 1922 struct sk_bcom_hack bhack[] = { 1923 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 1924 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 1925 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 1926 { 0, 0 } }; 1927 1928 sc = sc_if->sk_softc; 1929 ifp = &sc_if->arpcom.ac_if; 1930 1931 /* Unreset the XMAC. */ 1932 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 1933 DELAY(1000); 1934 1935 /* Reset the XMAC's internal state. */ 1936 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 1937 1938 /* Save the XMAC II revision */ 1939 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 1940 1941 /* 1942 * Perform additional initialization for external PHYs, 1943 * namely for the 1000baseTX cards that use the XMAC's 1944 * GMII mode. 1945 */ 1946 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1947 int i = 0; 1948 u_int32_t val; 1949 1950 /* Take PHY out of reset. */ 1951 val = sk_win_read_4(sc, SK_GPIO); 1952 if (sc_if->sk_port == SK_PORT_A) 1953 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 1954 else 1955 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 1956 sk_win_write_4(sc, SK_GPIO, val); 1957 1958 /* Enable GMII mode on the XMAC. */ 1959 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 1960 1961 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM, 1962 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 1963 DELAY(10000); 1964 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM, 1965 BRGPHY_MII_IMR, 0xFFF0); 1966 1967 /* 1968 * Early versions of the BCM5400 apparently have 1969 * a bug that requires them to have their reserved 1970 * registers initialized to some magic values. I don't 1971 * know what the numbers do, I'm just the messenger. 1972 */ 1973 if (sk_miibus_readreg(sc_if->sk_dev, 1974 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 1975 while(bhack[i].reg) { 1976 sk_miibus_writereg(sc_if->sk_dev, 1977 SK_PHYADDR_BCOM, bhack[i].reg, 1978 bhack[i].val); 1979 i++; 1980 } 1981 } 1982 } 1983 1984 /* Set station address */ 1985 SK_XM_WRITE_2(sc_if, XM_PAR0, 1986 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 1987 SK_XM_WRITE_2(sc_if, XM_PAR1, 1988 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 1989 SK_XM_WRITE_2(sc_if, XM_PAR2, 1990 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 1991 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 1992 1993 if (ifp->if_flags & IFF_PROMISC) { 1994 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1995 } else { 1996 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1997 } 1998 1999 if (ifp->if_flags & IFF_BROADCAST) { 2000 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2001 } else { 2002 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2003 } 2004 2005 /* We don't need the FCS appended to the packet. */ 2006 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2007 2008 /* We want short frames padded to 60 bytes. */ 2009 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2010 2011 /* 2012 * Enable the reception of all error frames. This is is 2013 * a necessary evil due to the design of the XMAC. The 2014 * XMAC's receive FIFO is only 8K in size, however jumbo 2015 * frames can be up to 9000 bytes in length. When bad 2016 * frame filtering is enabled, the XMAC's RX FIFO operates 2017 * in 'store and forward' mode. For this to work, the 2018 * entire frame has to fit into the FIFO, but that means 2019 * that jumbo frames larger than 8192 bytes will be 2020 * truncated. Disabling all bad frame filtering causes 2021 * the RX FIFO to operate in streaming mode, in which 2022 * case the XMAC will start transfering frames out of the 2023 * RX FIFO as soon as the FIFO threshold is reached. 2024 */ 2025 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2026 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2027 XM_MODE_RX_INRANGELEN); 2028 2029 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2030 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2031 else 2032 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2033 2034 /* 2035 * Bump up the transmit threshold. This helps hold off transmit 2036 * underruns when we're blasting traffic from both ports at once. 2037 */ 2038 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2039 2040 /* Set multicast filter */ 2041 sk_setmulti(sc_if); 2042 2043 /* Clear and enable interrupts */ 2044 SK_XM_READ_2(sc_if, XM_ISR); 2045 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2046 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2047 else 2048 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2049 2050 /* Configure MAC arbiter */ 2051 switch(sc_if->sk_xmac_rev) { 2052 case XM_XMAC_REV_B2: 2053 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2054 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2055 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2056 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2057 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2058 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2059 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2060 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2061 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2062 break; 2063 case XM_XMAC_REV_C1: 2064 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2065 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2066 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2067 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2068 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2069 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2070 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2071 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2072 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2073 break; 2074 default: 2075 break; 2076 } 2077 sk_win_write_2(sc, SK_MACARB_CTL, 2078 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2079 2080 sc_if->sk_link = 1; 2081 2082 return; 2083 } 2084 2085 /* 2086 * Note that to properly initialize any part of the GEnesis chip, 2087 * you first have to take it out of reset mode. 2088 */ 2089 static void sk_init(xsc) 2090 void *xsc; 2091 { 2092 struct sk_if_softc *sc_if = xsc; 2093 struct sk_softc *sc; 2094 struct ifnet *ifp; 2095 struct mii_data *mii; 2096 int s; 2097 2098 s = splimp(); 2099 2100 ifp = &sc_if->arpcom.ac_if; 2101 sc = sc_if->sk_softc; 2102 mii = device_get_softc(sc_if->sk_miibus); 2103 2104 /* Cancel pending I/O and free all RX/TX buffers. */ 2105 sk_stop(sc_if); 2106 2107 /* Configure LINK_SYNC LED */ 2108 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2109 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_ON); 2110 2111 /* Configure RX LED */ 2112 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_START); 2113 2114 /* Configure TX LED */ 2115 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_START); 2116 2117 /* Configure I2C registers */ 2118 2119 /* Configure XMAC(s) */ 2120 sk_init_xmac(sc_if); 2121 mii_mediachg(mii); 2122 2123 /* Configure MAC FIFOs */ 2124 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2125 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2126 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2127 2128 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2129 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2130 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2131 2132 /* Configure transmit arbiter(s) */ 2133 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2134 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2135 2136 /* Configure RAMbuffers */ 2137 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2138 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2139 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2140 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2141 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2142 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2143 2144 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2145 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2146 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2147 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2148 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2149 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2150 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2151 2152 /* Configure BMUs */ 2153 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2154 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2155 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2156 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2157 2158 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2159 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2160 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2161 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2162 2163 /* Init descriptors */ 2164 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2165 printf("sk%d: initialization failed: no " 2166 "memory for rx buffers\n", sc_if->sk_unit); 2167 sk_stop(sc_if); 2168 (void)splx(s); 2169 return; 2170 } 2171 sk_init_tx_ring(sc_if); 2172 2173 /* Configure interrupt handling */ 2174 CSR_READ_4(sc, SK_ISSR); 2175 if (sc_if->sk_port == SK_PORT_A) 2176 sc->sk_intrmask |= SK_INTRS1; 2177 else 2178 sc->sk_intrmask |= SK_INTRS2; 2179 2180 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2181 2182 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2183 2184 /* Start BMUs. */ 2185 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2186 2187 /* Enable XMACs TX and RX state machines */ 2188 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2189 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2190 2191 ifp->if_flags |= IFF_RUNNING; 2192 ifp->if_flags &= ~IFF_OACTIVE; 2193 2194 splx(s); 2195 2196 return; 2197 } 2198 2199 static void sk_stop(sc_if) 2200 struct sk_if_softc *sc_if; 2201 { 2202 int i; 2203 struct sk_softc *sc; 2204 struct ifnet *ifp; 2205 2206 sc = sc_if->sk_softc; 2207 ifp = &sc_if->arpcom.ac_if; 2208 2209 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2210 2211 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2212 u_int32_t val; 2213 2214 /* Put PHY back into reset. */ 2215 val = sk_win_read_4(sc, SK_GPIO); 2216 if (sc_if->sk_port == SK_PORT_A) { 2217 val |= SK_GPIO_DIR0; 2218 val &= ~SK_GPIO_DAT0; 2219 } else { 2220 val |= SK_GPIO_DIR2; 2221 val &= ~SK_GPIO_DAT2; 2222 } 2223 sk_win_write_4(sc, SK_GPIO, val); 2224 } 2225 2226 /* Turn off various components of this interface. */ 2227 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2228 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2229 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2230 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2231 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2232 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2233 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2234 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2235 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2236 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2237 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2238 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2239 2240 /* Disable interrupts */ 2241 if (sc_if->sk_port == SK_PORT_A) 2242 sc->sk_intrmask &= ~SK_INTRS1; 2243 else 2244 sc->sk_intrmask &= ~SK_INTRS2; 2245 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2246 2247 SK_XM_READ_2(sc_if, XM_ISR); 2248 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2249 2250 /* Free RX and TX mbufs still in the queues. */ 2251 for (i = 0; i < SK_RX_RING_CNT; i++) { 2252 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2253 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2254 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2255 } 2256 } 2257 2258 for (i = 0; i < SK_TX_RING_CNT; i++) { 2259 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2260 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2261 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2262 } 2263 } 2264 2265 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2266 2267 return; 2268 } 2269