1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_stereg.h,v 1.5.2.3 2002/08/21 15:26:01 ambrisko Exp $ 33 */ 34 35 /* 36 * Sundance PCI device/vendor ID for the 37 * ST201 chip. 38 */ 39 #define ST_VENDORID 0x13F0 40 #define ST_DEVICEID_ST201 0x0201 41 42 /* 43 * D-Link PCI device/vendor ID for the DFE-550TX. 44 */ 45 #define DL_VENDORID 0x1186 46 #define DL_DEVICEID_550TX 0x1002 47 48 /* 49 * Register definitions for the Sundance Technologies ST201 PCI 50 * fast ethernet controller. The register space is 128 bytes long and 51 * can be accessed using either PCI I/O space or PCI memory mapping. 52 * There are 32-bit, 16-bit and 8-bit registers. 53 */ 54 55 #define STE_DMACTL 0x00 56 #define STE_TX_DMALIST_PTR 0x04 57 #define STE_TX_DMABURST_THRESH 0x08 58 #define STE_TX_DMAURG_THRESH 0x09 59 #define STE_TX_DMAPOLL_PERIOD 0x0A 60 #define STE_RX_DMASTATUS 0x0C 61 #define STE_RX_DMALIST_PTR 0x10 62 #define STE_RX_DMABURST_THRESH 0x14 63 #define STE_RX_DMAURG_THRESH 0x15 64 #define STE_RX_DMAPOLL_PERIOD 0x16 65 #define STE_DEBUGCTL 0x1A 66 #define STE_ASICCTL 0x30 67 #define STE_EEPROM_DATA 0x34 68 #define STE_EEPROM_CTL 0x36 69 #define STE_FIFOCTL 0x3A 70 #define STE_TX_STARTTHRESH 0x3C 71 #define STE_RX_EARLYTHRESH 0x3E 72 #define STE_EXT_ROMADDR 0x40 73 #define STE_EXT_ROMDATA 0x44 74 #define STE_WAKE_EVENT 0x45 75 #define STE_TX_STATUS 0x46 76 #define STE_TX_FRAMEID 0x47 77 #define STE_COUNTDOWN 0x48 78 #define STE_ISR_ACK 0x4A 79 #define STE_IMR 0x4C 80 #define STE_ISR 0x4E 81 #define STE_MACCTL0 0x50 82 #define STE_MACCTL1 0x52 83 #define STE_PAR0 0x54 84 #define STE_PAR1 0x56 85 #define STE_PAR2 0x58 86 #define STE_MAX_FRAMELEN 0x5A 87 #define STE_RX_MODE 0x5C 88 #define STE_TX_RECLAIM_THRESH 0x5D 89 #define STE_PHYCTL 0x5E 90 #define STE_MAR0 0x60 91 #define STE_MAR1 0x62 92 #define STE_MAR2 0x64 93 #define STE_MAR3 0x66 94 #define STE_STATS 0x68 95 96 #define STE_LATE_COLLS 0x75 97 #define STE_MULTI_COLLS 0x76 98 #define STE_SINGLE_COLLS 0x77 99 100 #define STE_DMACTL_RXDMA_STOPPED 0x00000001 101 #define STE_DMACTL_TXDMA_CMPREQ 0x00000002 102 #define STE_DMACTL_TXDMA_STOPPED 0x00000004 103 #define STE_DMACTL_RXDMA_COMPLETE 0x00000008 104 #define STE_DMACTL_TXDMA_COMPLETE 0x00000010 105 #define STE_DMACTL_RXDMA_STALL 0x00000100 106 #define STE_DMACTL_RXDMA_UNSTALL 0x00000200 107 #define STE_DMACTL_TXDMA_STALL 0x00000400 108 #define STE_DMACTL_TXDMA_UNSTALL 0x00000800 109 #define STE_DMACTL_TXDMA_INPROG 0x00004000 110 #define STE_DMACTL_DMA_HALTINPROG 0x00008000 111 #define STE_DMACTL_RXEARLY_ENABLE 0x00020000 112 #define STE_DMACTL_COUNTDOWN_SPEED 0x00040000 113 #define STE_DMACTL_COUNTDOWN_MODE 0x00080000 114 #define STE_DMACTL_MWI_DISABLE 0x00100000 115 #define STE_DMACTL_RX_DISCARD_OFLOWS 0x00400000 116 #define STE_DMACTL_COUNTDOWN_ENABLE 0x00800000 117 #define STE_DMACTL_TARGET_ABORT 0x40000000 118 #define STE_DMACTL_MASTER_ABORT 0x80000000 119 120 /* 121 * TX DMA burst thresh is the number of 32-byte blocks that 122 * must be loaded into the TX Fifo before a TXDMA burst request 123 * will be issued. 124 */ 125 #define STE_TXDMABURST_THRESH 0x1F 126 127 /* 128 * The number of 32-byte blocks in the TX FIFO falls below the 129 * TX DMA urgent threshold, a TX DMA urgent request will be 130 * generated. 131 */ 132 #define STE_TXDMAURG_THRESH 0x3F 133 134 /* 135 * Number of 320ns intervals between polls of the TXDMA next 136 * descriptor pointer (if we're using polling mode). 137 */ 138 #define STE_TXDMA_POLL_PERIOD 0x7F 139 140 #define STE_RX_DMASTATUS_FRAMELEN 0x00001FFF 141 #define STE_RX_DMASTATUS_RXERR 0x00004000 142 #define STE_RX_DMASTATUS_DMADONE 0x00008000 143 #define STE_RX_DMASTATUS_FIFO_OFLOW 0x00010000 144 #define STE_RX_DMASTATUS_RUNT 0x00020000 145 #define STE_RX_DMASTATUS_ALIGNERR 0x00040000 146 #define STE_RX_DMASTATUS_CRCERR 0x00080000 147 #define STE_RX_DMASTATUS_GIANT 0x00100000 148 #define STE_RX_DMASTATUS_DRIBBLE 0x00800000 149 #define STE_RX_DMASTATUS_DMA_OFLOW 0x01000000 150 151 /* 152 * RX DMA burst thresh is the number of 32-byte blocks that 153 * must be present in the RX FIFO before a RXDMA bus master 154 * request will be issued. 155 */ 156 #define STE_RXDMABURST_THRESH 0xFF 157 158 /* 159 * The number of 32-byte blocks in the RX FIFO falls below the 160 * RX DMA urgent threshold, a RX DMA urgent request will be 161 * generated. 162 */ 163 #define STE_RXDMAURG_THRESH 0x1F 164 165 /* 166 * Number of 320ns intervals between polls of the RXDMA complete 167 * bit in the status field on the current RX descriptor (if we're 168 * using polling mode). 169 */ 170 #define STE_RXDMA_POLL_PERIOD 0x7F 171 172 #define STE_DEBUGCTL_GPIO0_CTL 0x0001 173 #define STE_DEBUGCTL_GPIO1_CTL 0x0002 174 #define STE_DEBUGCTL_GPIO0_DATA 0x0004 175 #define STE_DEBUGCTL_GPIO1_DATA 0x0008 176 177 #define STE_ASICCTL_ROMSIZE 0x00000002 178 #define STE_ASICCTL_TX_LARGEPKTS 0x00000004 179 #define STE_ASICCTL_RX_LARGEPKTS 0x00000008 180 #define STE_ASICCTL_EXTROM_DISABLE 0x00000010 181 #define STE_ASICCTL_PHYSPEED_10 0x00000020 182 #define STE_ASICCTL_PHYSPEED_100 0x00000040 183 #define STE_ASICCTL_PHYMEDIA 0x00000080 184 #define STE_ASICCTL_FORCEDCONFIG 0x00000700 185 #define STE_ASICCTL_D3RESET_DISABLE 0x00000800 186 #define STE_ASICCTL_SPEEDUPMODE 0x00002000 187 #define STE_ASICCTL_LEDMODE 0x00004000 188 #define STE_ASICCTL_RSTOUT_POLARITY 0x00008000 189 #define STE_ASICCTL_GLOBAL_RESET 0x00010000 190 #define STE_ASICCTL_RX_RESET 0x00020000 191 #define STE_ASICCTL_TX_RESET 0x00040000 192 #define STE_ASICCTL_DMA_RESET 0x00080000 193 #define STE_ASICCTL_FIFO_RESET 0x00100000 194 #define STE_ASICCTL_NETWORK_RESET 0x00200000 195 #define STE_ASICCTL_HOST_RESET 0x00400000 196 #define STE_ASICCTL_AUTOINIT_RESET 0x00800000 197 #define STE_ASICCTL_EXTRESET_RESET 0x01000000 198 #define STE_ASICCTL_SOFTINTR 0x02000000 199 #define STE_ASICCTL_RESET_BUSY 0x04000000 200 201 #define STE_ASICCTL1_GLOBAL_RESET 0x0001 202 #define STE_ASICCTL1_RX_RESET 0x0002 203 #define STE_ASICCTL1_TX_RESET 0x0004 204 #define STE_ASICCTL1_DMA_RESET 0x0008 205 #define STE_ASICCTL1_FIFO_RESET 0x0010 206 #define STE_ASICCTL1_NETWORK_RESET 0x0020 207 #define STE_ASICCTL1_HOST_RESET 0x0040 208 #define STE_ASICCTL1_AUTOINIT_RESET 0x0080 209 #define STE_ASICCTL1_EXTRESET_RESET 0x0100 210 #define STE_ASICCTL1_SOFTINTR 0x0200 211 #define STE_ASICCTL1_RESET_BUSY 0x0400 212 213 #define STE_EECTL_ADDR 0x00FF 214 #define STE_EECTL_OPCODE 0x0300 215 #define STE_EECTL_BUSY 0x1000 216 217 #define STE_EEOPCODE_WRITE 0x0100 218 #define STE_EEOPCODE_READ 0x0200 219 #define STE_EEOPCODE_ERASE 0x0300 220 221 #define STE_FIFOCTL_RAMTESTMODE 0x0001 222 #define STE_FIFOCTL_OVERRUNMODE 0x0200 223 #define STE_FIFOCTL_RXFIFOFULL 0x0800 224 #define STE_FIFOCTL_TX_BUSY 0x4000 225 #define STE_FIFOCTL_RX_BUSY 0x8000 226 227 /* 228 * The number of bytes that must in present in the TX FIFO before 229 * transmission begins. Value should be in increments of 4 bytes. 230 */ 231 #define STE_TXSTART_THRESH 0x1FFC 232 233 /* 234 * Number of bytes that must be present in the RX FIFO before 235 * an RX EARLY interrupt is generated. 236 */ 237 #define STE_RXEARLY_THRESH 0x1FFC 238 239 #define STE_WAKEEVENT_WAKEPKT_ENB 0x01 240 #define STE_WAKEEVENT_MAGICPKT_ENB 0x02 241 #define STE_WAKEEVENT_LINKEVT_ENB 0x04 242 #define STE_WAKEEVENT_WAKEPOLARITY 0x08 243 #define STE_WAKEEVENT_WAKEPKTEVENT 0x10 244 #define STE_WAKEEVENT_MAGICPKTEVENT 0x20 245 #define STE_WAKEEVENT_LINKEVENT 0x40 246 #define STE_WAKEEVENT_WAKEONLAN_ENB 0x80 247 248 #define STE_TXSTATUS_RECLAIMERR 0x02 249 #define STE_TXSTATUS_STATSOFLOW 0x04 250 #define STE_TXSTATUS_EXCESSCOLLS 0x08 251 #define STE_TXSTATUS_UNDERRUN 0x10 252 #define STE_TXSTATUS_TXINTR_REQ 0x40 253 #define STE_TXSTATUS_TXDONE 0x80 254 255 #define STE_ISRACK_INTLATCH 0x0001 256 #define STE_ISRACK_HOSTERR 0x0002 257 #define STE_ISRACK_TX_DONE 0x0004 258 #define STE_ISRACK_MACCTL_FRAME 0x0008 259 #define STE_ISRACK_RX_DONE 0x0010 260 #define STE_ISRACK_RX_EARLY 0x0020 261 #define STE_ISRACK_SOFTINTR 0x0040 262 #define STE_ISRACK_STATS_OFLOW 0x0080 263 #define STE_ISRACK_LINKEVENT 0x0100 264 #define STE_ISRACK_TX_DMADONE 0x0200 265 #define STE_ISRACK_RX_DMADONE 0x0400 266 267 #define STE_IMR_HOSTERR 0x0002 268 #define STE_IMR_TX_DONE 0x0004 269 #define STE_IMR_MACCTL_FRAME 0x0008 270 #define STE_IMR_RX_DONE 0x0010 271 #define STE_IMR_RX_EARLY 0x0020 272 #define STE_IMR_SOFTINTR 0x0040 273 #define STE_IMR_STATS_OFLOW 0x0080 274 #define STE_IMR_LINKEVENT 0x0100 275 #define STE_IMR_TX_DMADONE 0x0200 276 #define STE_IMR_RX_DMADONE 0x0400 277 278 #define STE_INTRS \ 279 (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \ 280 STE_IMR_TX_DONE|STE_IMR_HOSTERR| \ 281 STE_IMR_LINKEVENT) 282 283 #define STE_ISR_INTLATCH 0x0001 284 #define STE_ISR_HOSTERR 0x0002 285 #define STE_ISR_TX_DONE 0x0004 286 #define STE_ISR_MACCTL_FRAME 0x0008 287 #define STE_ISR_RX_DONE 0x0010 288 #define STE_ISR_RX_EARLY 0x0020 289 #define STE_ISR_SOFTINTR 0x0040 290 #define STE_ISR_STATS_OFLOW 0x0080 291 #define STE_ISR_LINKEVENT 0x0100 292 #define STE_ISR_TX_DMADONE 0x0200 293 #define STE_ISR_RX_DMADONE 0x0400 294 295 /* 296 * Note: the Sundance manual gives the impression that the's 297 * only one 32-bit MACCTL register. In fact, there are two 298 * 16-bit registers side by side, and you have to access them 299 * separately. 300 */ 301 #define STE_MACCTL0_IPG 0x0003 302 #define STE_MACCTL0_FULLDUPLEX 0x0020 303 #define STE_MACCTL0_RX_GIANTS 0x0040 304 #define STE_MACCTL0_FLOWCTL_ENABLE 0x0100 305 #define STE_MACCTL0_RX_FCS 0x0200 306 #define STE_MACCTL0_FIFOLOOPBK 0x0400 307 #define STE_MACCTL0_MACLOOPBK 0x0800 308 309 #define STE_MACCTL1_COLLDETECT 0x0001 310 #define STE_MACCTL1_CARRSENSE 0x0002 311 #define STE_MACCTL1_TX_BUSY 0x0004 312 #define STE_MACCTL1_TX_ERROR 0x0008 313 #define STE_MACCTL1_STATS_ENABLE 0x0020 314 #define STE_MACCTL1_STATS_DISABLE 0x0040 315 #define STE_MACCTL1_STATS_ENABLED 0x0080 316 #define STE_MACCTL1_TX_ENABLE 0x0100 317 #define STE_MACCTL1_TX_DISABLE 0x0200 318 #define STE_MACCTL1_TX_ENABLED 0x0400 319 #define STE_MACCTL1_RX_ENABLE 0x0800 320 #define STE_MACCTL1_RX_DISABLE 0x1000 321 #define STE_MACCTL1_RX_ENABLED 0x2000 322 #define STE_MACCTL1_PAUSED 0x4000 323 324 #define STE_IPG_96BT 0x00000000 325 #define STE_IPG_128BT 0x00000001 326 #define STE_IPG_224BT 0x00000002 327 #define STE_IPG_544BT 0x00000003 328 329 #define STE_RXMODE_UNICAST 0x01 330 #define STE_RXMODE_ALLMULTI 0x02 331 #define STE_RXMODE_BROADCAST 0x04 332 #define STE_RXMODE_PROMISC 0x08 333 #define STE_RXMODE_MULTIHASH 0x10 334 #define STE_RXMODE_ALLIPMULTI 0x20 335 336 #define STE_PHYCTL_MCLK 0x01 337 #define STE_PHYCTL_MDATA 0x02 338 #define STE_PHYCTL_MDIR 0x04 339 #define STE_PHYCTL_CLK25_DISABLE 0x08 340 #define STE_PHYCTL_DUPLEXPOLARITY 0x10 341 #define STE_PHYCTL_DUPLEXSTAT 0x20 342 #define STE_PHYCTL_SPEEDSTAT 0x40 343 #define STE_PHYCTL_LINKSTAT 0x80 344 345 /* 346 * EEPROM offsets. 347 */ 348 #define STE_EEADDR_CONFIGPARM 0x00 349 #define STE_EEADDR_ASICCTL 0x02 350 #define STE_EEADDR_SUBSYS_ID 0x04 351 #define STE_EEADDR_SUBVEN_ID 0x08 352 353 #define STE_EEADDR_NODE0 0x10 354 #define STE_EEADDR_NODE1 0x12 355 #define STE_EEADDR_NODE2 0x14 356 357 /* PCI registers */ 358 #define STE_PCI_VENDOR_ID 0x00 359 #define STE_PCI_DEVICE_ID 0x02 360 #define STE_PCI_COMMAND 0x04 361 #define STE_PCI_STATUS 0x06 362 #define STE_PCI_CLASSCODE 0x09 363 #define STE_PCI_LATENCY_TIMER 0x0D 364 #define STE_PCI_HEADER_TYPE 0x0E 365 #define STE_PCI_LOIO 0x10 366 #define STE_PCI_LOMEM 0x14 367 #define STE_PCI_BIOSROM 0x30 368 #define STE_PCI_INTLINE 0x3C 369 #define STE_PCI_INTPIN 0x3D 370 #define STE_PCI_MINGNT 0x3E 371 #define STE_PCI_MINLAT 0x0F 372 373 #define STE_PCI_CAPID 0x50 /* 8 bits */ 374 #define STE_PCI_NEXTPTR 0x51 /* 8 bits */ 375 #define STE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 376 #define STE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 377 378 #define STE_PSTATE_MASK 0x0003 379 #define STE_PSTATE_D0 0x0000 380 #define STE_PSTATE_D1 0x0002 381 #define STE_PSTATE_D2 0x0002 382 #define STE_PSTATE_D3 0x0003 383 #define STE_PME_EN 0x0010 384 #define STE_PME_STATUS 0x8000 385 386 387 struct ste_stats { 388 u_int32_t ste_rx_bytes; 389 u_int32_t ste_tx_bytes; 390 u_int16_t ste_tx_frames; 391 u_int16_t ste_rx_frames; 392 u_int8_t ste_carrsense_errs; 393 u_int8_t ste_late_colls; 394 u_int8_t ste_multi_colls; 395 u_int8_t ste_single_colls; 396 u_int8_t ste_tx_frames_defered; 397 u_int8_t ste_rx_lost_frames; 398 u_int8_t ste_tx_excess_defers; 399 u_int8_t ste_tx_abort_excess_colls; 400 u_int8_t ste_tx_bcast_frames; 401 u_int8_t ste_rx_bcast_frames; 402 u_int8_t ste_tx_mcast_frames; 403 u_int8_t ste_rx_mcast_frames; 404 }; 405 406 struct ste_frag { 407 u_int32_t ste_addr; 408 u_int32_t ste_len; 409 }; 410 411 #define STE_FRAG_LAST 0x80000000 412 #define STE_FRAG_LEN 0x00001FFF 413 414 #define STE_MAXFRAGS 8 415 416 struct ste_desc { 417 u_int32_t ste_next; 418 u_int32_t ste_ctl; 419 struct ste_frag ste_frags[STE_MAXFRAGS]; 420 }; 421 422 struct ste_desc_onefrag { 423 u_int32_t ste_next; 424 u_int32_t ste_status; 425 struct ste_frag ste_frag; 426 }; 427 428 #define STE_TXCTL_WORDALIGN 0x00000003 429 #define STE_TXCTL_FRAMEID 0x000003FC 430 #define STE_TXCTL_NOCRC 0x00002000 431 #define STE_TXCTL_TXINTR 0x00008000 432 #define STE_TXCTL_DMADONE 0x00010000 433 #define STE_TXCTL_DMAINTR 0x80000000 434 435 #define STE_RXSTAT_FRAMELEN 0x00001FFF 436 #define STE_RXSTAT_FRAME_ERR 0x00004000 437 #define STE_RXSTAT_DMADONE 0x00008000 438 #define STE_RXSTAT_FIFO_OFLOW 0x00010000 439 #define STE_RXSTAT_RUNT 0x00020000 440 #define STE_RXSTAT_ALIGNERR 0x00040000 441 #define STE_RXSTAT_CRCERR 0x00080000 442 #define STE_RXSTAT_GIANT 0x00100000 443 #define STE_RXSTAT_DRIBBLEBITS 0x00800000 444 #define STE_RXSTAT_DMA_OFLOW 0x01000000 445 #define STE_RXATAT_ONEBUF 0x10000000 446 447 /* 448 * register space access macros 449 */ 450 #define CSR_WRITE_4(sc, reg, val) \ 451 bus_space_write_4(sc->ste_btag, sc->ste_bhandle, reg, val) 452 #define CSR_WRITE_2(sc, reg, val) \ 453 bus_space_write_2(sc->ste_btag, sc->ste_bhandle, reg, val) 454 #define CSR_WRITE_1(sc, reg, val) \ 455 bus_space_write_1(sc->ste_btag, sc->ste_bhandle, reg, val) 456 457 #define CSR_READ_4(sc, reg) \ 458 bus_space_read_4(sc->ste_btag, sc->ste_bhandle, reg) 459 #define CSR_READ_2(sc, reg) \ 460 bus_space_read_2(sc->ste_btag, sc->ste_bhandle, reg) 461 #define CSR_READ_1(sc, reg) \ 462 bus_space_read_1(sc->ste_btag, sc->ste_bhandle, reg) 463 464 #define STE_TIMEOUT 1000 465 #define STE_MIN_FRAMELEN 60 466 #define STE_PACKET_SIZE 1536 467 #define ETHER_ALIGN 2 468 #define STE_RX_LIST_CNT 64 469 #define STE_TX_LIST_CNT 64 470 #define STE_INC(x, y) (x) = (x + 1) % y 471 #define STE_NEXT(x, y) (x + 1) % y 472 473 struct ste_type { 474 u_int16_t ste_vid; 475 u_int16_t ste_did; 476 char *ste_name; 477 }; 478 479 struct ste_list_data { 480 struct ste_desc_onefrag ste_rx_list[STE_RX_LIST_CNT]; 481 struct ste_desc ste_tx_list[STE_TX_LIST_CNT]; 482 u_int8_t ste_pad[STE_MIN_FRAMELEN]; 483 }; 484 485 struct ste_chain { 486 struct ste_desc *ste_ptr; 487 struct mbuf *ste_mbuf; 488 struct ste_chain *ste_next; 489 struct ste_chain *ste_prev; 490 u_int32_t ste_phys; 491 }; 492 493 struct ste_chain_onefrag { 494 struct ste_desc_onefrag *ste_ptr; 495 struct mbuf *ste_mbuf; 496 struct ste_chain_onefrag *ste_next; 497 }; 498 499 struct ste_chain_data { 500 struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT]; 501 struct ste_chain ste_tx_chain[STE_TX_LIST_CNT]; 502 struct ste_chain_onefrag *ste_rx_head; 503 504 int ste_tx_prod; 505 int ste_tx_cons; 506 int ste_tx_cnt; 507 }; 508 509 struct ste_softc { 510 struct arpcom arpcom; 511 bus_space_tag_t ste_btag; 512 bus_space_handle_t ste_bhandle; 513 struct resource *ste_res; 514 struct resource *ste_irq; 515 void *ste_intrhand; 516 struct ste_type *ste_info; 517 device_t ste_miibus; 518 device_t ste_dev; 519 int ste_unit; 520 int ste_tx_thresh; 521 u_int8_t ste_link; 522 int ste_if_flags; 523 int ste_tx_prev_idx; 524 struct ste_list_data *ste_ldata; 525 struct ste_chain_data ste_cdata; 526 struct callout_handle ste_stat_ch; 527 u_int8_t ste_one_phy; 528 }; 529 530 struct ste_mii_frame { 531 u_int8_t mii_stdelim; 532 u_int8_t mii_opcode; 533 u_int8_t mii_phyaddr; 534 u_int8_t mii_regaddr; 535 u_int8_t mii_turnaround; 536 u_int16_t mii_data; 537 }; 538 539 /* 540 * MII constants 541 */ 542 #define STE_MII_STARTDELIM 0x01 543 #define STE_MII_READOP 0x02 544 #define STE_MII_WRITEOP 0x01 545 #define STE_MII_TURNAROUND 0x02 546 547 #ifdef __alpha__ 548 #undef vtophys 549 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 550 #endif 551