1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */ 2 /* $FreeBSD: src/sys/dev/stge/if_stge.c,v 1.2 2006/08/12 01:21:36 yongari Exp $ */ 3 4 /*- 5 * Copyright (c) 2001 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Device driver for the Sundance Tech. TC9021 10/100/1000 42 * Ethernet controller. 43 */ 44 45 #include "opt_ifpoll.h" 46 47 #include <sys/param.h> 48 #include <sys/bus.h> 49 #include <sys/endian.h> 50 #include <sys/kernel.h> 51 #include <sys/interrupt.h> 52 #include <sys/malloc.h> 53 #include <sys/mbuf.h> 54 #include <sys/module.h> 55 #include <sys/rman.h> 56 #include <sys/serialize.h> 57 #include <sys/socket.h> 58 #include <sys/sockio.h> 59 #include <sys/sysctl.h> 60 61 #include <net/bpf.h> 62 #include <net/ethernet.h> 63 #include <net/if.h> 64 #include <net/if_arp.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_poll.h> 68 #include <net/if_types.h> 69 #include <net/ifq_var.h> 70 #include <net/vlan/if_vlan_var.h> 71 #include <net/vlan/if_vlan_ether.h> 72 73 #include <dev/netif/mii_layer/mii.h> 74 #include <dev/netif/mii_layer/miivar.h> 75 76 #include <bus/pci/pcireg.h> 77 #include <bus/pci/pcivar.h> 78 79 #include "if_stgereg.h" 80 #include "if_stgevar.h" 81 82 #define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 83 84 /* "device miibus" required. See GENERIC if you get errors here. */ 85 #include "miibus_if.h" 86 87 /* 88 * Devices supported by this driver. 89 */ 90 static struct stge_product { 91 uint16_t stge_vendorid; 92 uint16_t stge_deviceid; 93 const char *stge_name; 94 } stge_products[] = { 95 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023, 96 "Sundance ST-1023 Gigabit Ethernet" }, 97 98 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021, 99 "Sundance ST-2021 Gigabit Ethernet" }, 100 101 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021, 102 "Tamarack TC9021 Gigabit Ethernet" }, 103 104 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT, 105 "Tamarack TC9021 Gigabit Ethernet" }, 106 107 /* 108 * The Sundance sample boards use the Sundance vendor ID, 109 * but the Tamarack product ID. 110 */ 111 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021, 112 "Sundance TC9021 Gigabit Ethernet" }, 113 114 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT, 115 "Sundance TC9021 Gigabit Ethernet" }, 116 117 { VENDOR_DLINK, DEVICEID_DLINK_DL2000, 118 "D-Link DL-2000 Gigabit Ethernet" }, 119 120 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021, 121 "Antares Gigabit Ethernet" }, 122 123 { 0, 0, NULL } 124 }; 125 126 static int stge_probe(device_t); 127 static int stge_attach(device_t); 128 static int stge_detach(device_t); 129 static void stge_shutdown(device_t); 130 static int stge_suspend(device_t); 131 static int stge_resume(device_t); 132 133 static int stge_encap(struct stge_softc *, struct mbuf **); 134 static void stge_start(struct ifnet *, struct ifaltq_subque *); 135 static void stge_watchdog(struct ifnet *); 136 static int stge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 137 static void stge_init(void *); 138 static void stge_vlan_setup(struct stge_softc *); 139 static void stge_stop(struct stge_softc *); 140 static void stge_start_tx(struct stge_softc *); 141 static void stge_start_rx(struct stge_softc *); 142 static void stge_stop_tx(struct stge_softc *); 143 static void stge_stop_rx(struct stge_softc *); 144 145 static void stge_reset(struct stge_softc *, uint32_t); 146 static int stge_eeprom_wait(struct stge_softc *); 147 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 148 static void stge_tick(void *); 149 static void stge_stats_update(struct stge_softc *); 150 static void stge_set_filter(struct stge_softc *); 151 static void stge_set_multi(struct stge_softc *); 152 153 static void stge_link(struct stge_softc *); 154 static void stge_intr(void *); 155 static __inline int stge_tx_error(struct stge_softc *); 156 static void stge_txeof(struct stge_softc *); 157 static void stge_rxeof(struct stge_softc *, int); 158 static __inline void stge_discard_rxbuf(struct stge_softc *, int); 159 static int stge_newbuf(struct stge_softc *, int, int); 160 #ifndef __x86_64__ 161 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *); 162 #endif 163 164 static void stge_mii_sync(struct stge_softc *); 165 static void stge_mii_send(struct stge_softc *, uint32_t, int); 166 static int stge_mii_readreg(struct stge_softc *, struct stge_mii_frame *); 167 static int stge_mii_writereg(struct stge_softc *, struct stge_mii_frame *); 168 static int stge_miibus_readreg(device_t, int, int); 169 static int stge_miibus_writereg(device_t, int, int, int); 170 static void stge_miibus_statchg(device_t); 171 static int stge_mediachange(struct ifnet *); 172 static void stge_mediastatus(struct ifnet *, struct ifmediareq *); 173 174 static int stge_dma_alloc(struct stge_softc *); 175 static void stge_dma_free(struct stge_softc *); 176 static void stge_dma_wait(struct stge_softc *); 177 static void stge_init_tx_ring(struct stge_softc *); 178 static int stge_init_rx_ring(struct stge_softc *); 179 #ifdef IFPOLL_ENABLE 180 static void stge_npoll(struct ifnet *, struct ifpoll_info *); 181 static void stge_npoll_compat(struct ifnet *, void *, int); 182 #endif 183 184 static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS); 185 static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS); 186 187 static device_method_t stge_methods[] = { 188 /* Device interface */ 189 DEVMETHOD(device_probe, stge_probe), 190 DEVMETHOD(device_attach, stge_attach), 191 DEVMETHOD(device_detach, stge_detach), 192 DEVMETHOD(device_shutdown, stge_shutdown), 193 DEVMETHOD(device_suspend, stge_suspend), 194 DEVMETHOD(device_resume, stge_resume), 195 196 /* MII interface */ 197 DEVMETHOD(miibus_readreg, stge_miibus_readreg), 198 DEVMETHOD(miibus_writereg, stge_miibus_writereg), 199 DEVMETHOD(miibus_statchg, stge_miibus_statchg), 200 201 DEVMETHOD_END 202 203 }; 204 205 static driver_t stge_driver = { 206 "stge", 207 stge_methods, 208 sizeof(struct stge_softc) 209 }; 210 211 static devclass_t stge_devclass; 212 213 DECLARE_DUMMY_MODULE(if_stge); 214 MODULE_DEPEND(if_stge, miibus, 1, 1, 1); 215 DRIVER_MODULE(if_stge, pci, stge_driver, stge_devclass, NULL, NULL); 216 DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, NULL, NULL); 217 218 #define MII_SET(x) \ 219 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) | (x)) 220 #define MII_CLR(x) \ 221 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) & ~(x)) 222 223 /* 224 * Sync the PHYs by setting data bit and strobing the clock 32 times. 225 */ 226 static void 227 stge_mii_sync(struct stge_softc *sc) 228 { 229 int i; 230 231 MII_SET(PC_MgmtDir | PC_MgmtData); 232 233 for (i = 0; i < 32; i++) { 234 MII_SET(PC_MgmtClk); 235 DELAY(1); 236 MII_CLR(PC_MgmtClk); 237 DELAY(1); 238 } 239 } 240 241 /* 242 * Clock a series of bits through the MII. 243 */ 244 static void 245 stge_mii_send(struct stge_softc *sc, uint32_t bits, int cnt) 246 { 247 int i; 248 249 MII_CLR(PC_MgmtClk); 250 251 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 252 if (bits & i) 253 MII_SET(PC_MgmtData); 254 else 255 MII_CLR(PC_MgmtData); 256 DELAY(1); 257 MII_CLR(PC_MgmtClk); 258 DELAY(1); 259 MII_SET(PC_MgmtClk); 260 } 261 } 262 263 /* 264 * Read an PHY register through the MII. 265 */ 266 static int 267 stge_mii_readreg(struct stge_softc *sc, struct stge_mii_frame *frame) 268 { 269 int i, ack; 270 271 /* 272 * Set up frame for RX. 273 */ 274 frame->mii_stdelim = STGE_MII_STARTDELIM; 275 frame->mii_opcode = STGE_MII_READOP; 276 frame->mii_turnaround = 0; 277 frame->mii_data = 0; 278 279 CSR_WRITE_1(sc, STGE_PhyCtrl, 0 | sc->sc_PhyCtrl); 280 /* 281 * Turn on data xmit. 282 */ 283 MII_SET(PC_MgmtDir); 284 285 stge_mii_sync(sc); 286 287 /* 288 * Send command/address info. 289 */ 290 stge_mii_send(sc, frame->mii_stdelim, 2); 291 stge_mii_send(sc, frame->mii_opcode, 2); 292 stge_mii_send(sc, frame->mii_phyaddr, 5); 293 stge_mii_send(sc, frame->mii_regaddr, 5); 294 295 /* Turn off xmit. */ 296 MII_CLR(PC_MgmtDir); 297 298 /* Idle bit */ 299 MII_CLR((PC_MgmtClk | PC_MgmtData)); 300 DELAY(1); 301 MII_SET(PC_MgmtClk); 302 DELAY(1); 303 304 /* Check for ack */ 305 MII_CLR(PC_MgmtClk); 306 DELAY(1); 307 ack = CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData; 308 MII_SET(PC_MgmtClk); 309 DELAY(1); 310 311 /* 312 * Now try reading data bits. If the ack failed, we still 313 * need to clock through 16 cycles to keep the PHY(s) in sync. 314 */ 315 if (ack) { 316 for(i = 0; i < 16; i++) { 317 MII_CLR(PC_MgmtClk); 318 DELAY(1); 319 MII_SET(PC_MgmtClk); 320 DELAY(1); 321 } 322 goto fail; 323 } 324 325 for (i = 0x8000; i; i >>= 1) { 326 MII_CLR(PC_MgmtClk); 327 DELAY(1); 328 if (!ack) { 329 if (CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData) 330 frame->mii_data |= i; 331 DELAY(1); 332 } 333 MII_SET(PC_MgmtClk); 334 DELAY(1); 335 } 336 337 fail: 338 MII_CLR(PC_MgmtClk); 339 DELAY(1); 340 MII_SET(PC_MgmtClk); 341 DELAY(1); 342 343 if (ack) 344 return(1); 345 return(0); 346 } 347 348 /* 349 * Write to a PHY register through the MII. 350 */ 351 static int 352 stge_mii_writereg(struct stge_softc *sc, struct stge_mii_frame *frame) 353 { 354 355 /* 356 * Set up frame for TX. 357 */ 358 frame->mii_stdelim = STGE_MII_STARTDELIM; 359 frame->mii_opcode = STGE_MII_WRITEOP; 360 frame->mii_turnaround = STGE_MII_TURNAROUND; 361 362 /* 363 * Turn on data output. 364 */ 365 MII_SET(PC_MgmtDir); 366 367 stge_mii_sync(sc); 368 369 stge_mii_send(sc, frame->mii_stdelim, 2); 370 stge_mii_send(sc, frame->mii_opcode, 2); 371 stge_mii_send(sc, frame->mii_phyaddr, 5); 372 stge_mii_send(sc, frame->mii_regaddr, 5); 373 stge_mii_send(sc, frame->mii_turnaround, 2); 374 stge_mii_send(sc, frame->mii_data, 16); 375 376 /* Idle bit. */ 377 MII_SET(PC_MgmtClk); 378 DELAY(1); 379 MII_CLR(PC_MgmtClk); 380 DELAY(1); 381 382 /* 383 * Turn off xmit. 384 */ 385 MII_CLR(PC_MgmtDir); 386 387 return(0); 388 } 389 390 /* 391 * sc_miibus_readreg: [mii interface function] 392 * 393 * Read a PHY register on the MII of the TC9021. 394 */ 395 static int 396 stge_miibus_readreg(device_t dev, int phy, int reg) 397 { 398 struct stge_softc *sc; 399 struct stge_mii_frame frame; 400 int error; 401 402 sc = device_get_softc(dev); 403 404 if (reg == STGE_PhyCtrl) { 405 /* XXX allow ip1000phy read STGE_PhyCtrl register. */ 406 error = CSR_READ_1(sc, STGE_PhyCtrl); 407 return (error); 408 } 409 bzero(&frame, sizeof(frame)); 410 frame.mii_phyaddr = phy; 411 frame.mii_regaddr = reg; 412 413 error = stge_mii_readreg(sc, &frame); 414 415 if (error != 0) { 416 /* Don't show errors for PHY probe request */ 417 if (reg != 1) 418 device_printf(sc->sc_dev, "phy read fail\n"); 419 return (0); 420 } 421 return (frame.mii_data); 422 } 423 424 /* 425 * stge_miibus_writereg: [mii interface function] 426 * 427 * Write a PHY register on the MII of the TC9021. 428 */ 429 static int 430 stge_miibus_writereg(device_t dev, int phy, int reg, int val) 431 { 432 struct stge_softc *sc; 433 struct stge_mii_frame frame; 434 int error; 435 436 sc = device_get_softc(dev); 437 438 bzero(&frame, sizeof(frame)); 439 frame.mii_phyaddr = phy; 440 frame.mii_regaddr = reg; 441 frame.mii_data = val; 442 443 error = stge_mii_writereg(sc, &frame); 444 445 if (error != 0) 446 device_printf(sc->sc_dev, "phy write fail\n"); 447 return (0); 448 } 449 450 /* 451 * stge_miibus_statchg: [mii interface function] 452 * 453 * Callback from MII layer when media changes. 454 */ 455 static void 456 stge_miibus_statchg(device_t dev) 457 { 458 struct stge_softc *sc; 459 struct mii_data *mii; 460 461 sc = device_get_softc(dev); 462 mii = device_get_softc(sc->sc_miibus); 463 464 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE) 465 return; 466 467 sc->sc_MACCtrl = 0; 468 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 469 sc->sc_MACCtrl |= MC_DuplexSelect; 470 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) != 0) 471 sc->sc_MACCtrl |= MC_RxFlowControlEnable; 472 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) != 0) 473 sc->sc_MACCtrl |= MC_TxFlowControlEnable; 474 475 stge_link(sc); 476 } 477 478 /* 479 * stge_mediastatus: [ifmedia interface function] 480 * 481 * Get the current interface media status. 482 */ 483 static void 484 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 485 { 486 struct stge_softc *sc; 487 struct mii_data *mii; 488 489 sc = ifp->if_softc; 490 mii = device_get_softc(sc->sc_miibus); 491 492 mii_pollstat(mii); 493 ifmr->ifm_status = mii->mii_media_status; 494 ifmr->ifm_active = mii->mii_media_active; 495 } 496 497 /* 498 * stge_mediachange: [ifmedia interface function] 499 * 500 * Set hardware to newly-selected media. 501 */ 502 static int 503 stge_mediachange(struct ifnet *ifp) 504 { 505 struct stge_softc *sc; 506 struct mii_data *mii; 507 508 sc = ifp->if_softc; 509 mii = device_get_softc(sc->sc_miibus); 510 mii_mediachg(mii); 511 512 return (0); 513 } 514 515 static int 516 stge_eeprom_wait(struct stge_softc *sc) 517 { 518 int i; 519 520 for (i = 0; i < STGE_TIMEOUT; i++) { 521 DELAY(1000); 522 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0) 523 return (0); 524 } 525 return (1); 526 } 527 528 /* 529 * stge_read_eeprom: 530 * 531 * Read data from the serial EEPROM. 532 */ 533 static void 534 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 535 { 536 537 if (stge_eeprom_wait(sc)) 538 device_printf(sc->sc_dev, "EEPROM failed to come ready\n"); 539 540 CSR_WRITE_2(sc, STGE_EepromCtrl, 541 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 542 if (stge_eeprom_wait(sc)) 543 device_printf(sc->sc_dev, "EEPROM read timed out\n"); 544 *data = CSR_READ_2(sc, STGE_EepromData); 545 } 546 547 548 static int 549 stge_probe(device_t dev) 550 { 551 struct stge_product *sp; 552 uint16_t vendor, devid; 553 554 vendor = pci_get_vendor(dev); 555 devid = pci_get_device(dev); 556 557 for (sp = stge_products; sp->stge_name != NULL; sp++) { 558 if (vendor == sp->stge_vendorid && 559 devid == sp->stge_deviceid) { 560 device_set_desc(dev, sp->stge_name); 561 return (0); 562 } 563 } 564 565 return (ENXIO); 566 } 567 568 static int 569 stge_attach(device_t dev) 570 { 571 struct stge_softc *sc; 572 struct ifnet *ifp; 573 struct sysctl_ctx_list *ctx; 574 struct sysctl_oid *tree; 575 uint8_t enaddr[ETHER_ADDR_LEN]; 576 int error, i; 577 uint16_t cmd; 578 uint32_t val; 579 580 error = 0; 581 sc = device_get_softc(dev); 582 sc->sc_dev = dev; 583 ifp = &sc->arpcom.ac_if; 584 585 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 586 587 callout_init(&sc->sc_tick_ch); 588 589 #ifndef BURN_BRIDGES 590 /* 591 * Handle power management nonsense. 592 */ 593 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 594 uint32_t iobase, membase, irq; 595 596 /* Save important PCI config data. */ 597 iobase = pci_read_config(dev, STGE_PCIR_LOIO, 4); 598 membase = pci_read_config(dev, STGE_PCIR_LOMEM, 4); 599 irq = pci_read_config(dev, PCIR_INTLINE, 4); 600 601 /* Reset the power state. */ 602 device_printf(dev, "chip is in D%d power mode " 603 "-- setting to D0\n", pci_get_powerstate(dev)); 604 605 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 606 607 /* Restore PCI config data. */ 608 pci_write_config(dev, STGE_PCIR_LOIO, iobase, 4); 609 pci_write_config(dev, STGE_PCIR_LOMEM, membase, 4); 610 pci_write_config(dev, PCIR_INTLINE, irq, 4); 611 } 612 #endif 613 614 /* 615 * Map the device. 616 */ 617 pci_enable_busmaster(dev); 618 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 619 val = pci_read_config(dev, STGE_PCIR_LOMEM, 4); 620 621 if ((val & 0x01) != 0) { 622 sc->sc_res_rid = STGE_PCIR_LOMEM; 623 sc->sc_res_type = SYS_RES_MEMORY; 624 } else { 625 sc->sc_res_rid = STGE_PCIR_LOIO; 626 sc->sc_res_type = SYS_RES_IOPORT; 627 628 val = pci_read_config(dev, sc->sc_res_rid, 4); 629 if ((val & 0x01) == 0) { 630 device_printf(dev, "couldn't locate IO BAR\n"); 631 return ENXIO; 632 } 633 } 634 635 sc->sc_res = bus_alloc_resource_any(dev, sc->sc_res_type, 636 &sc->sc_res_rid, RF_ACTIVE); 637 if (sc->sc_res == NULL) { 638 device_printf(dev, "couldn't allocate resource\n"); 639 return ENXIO; 640 } 641 sc->sc_btag = rman_get_bustag(sc->sc_res); 642 sc->sc_bhandle = rman_get_bushandle(sc->sc_res); 643 644 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 645 &sc->sc_irq_rid, 646 RF_ACTIVE | RF_SHAREABLE); 647 if (sc->sc_irq == NULL) { 648 device_printf(dev, "couldn't allocate IRQ\n"); 649 error = ENXIO; 650 goto fail; 651 } 652 653 sc->sc_rev = pci_get_revid(dev); 654 655 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT; 656 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT; 657 658 ctx = device_get_sysctl_ctx(dev); 659 tree = device_get_sysctl_tree(dev); 660 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 661 "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0, 662 sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe"); 663 664 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 665 "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0, 666 sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait"); 667 668 error = stge_dma_alloc(sc); 669 if (error != 0) 670 goto fail; 671 672 /* 673 * Determine if we're copper or fiber. It affects how we 674 * reset the card. 675 */ 676 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) 677 sc->sc_usefiber = 1; 678 else 679 sc->sc_usefiber = 0; 680 681 /* Load LED configuration from EEPROM. */ 682 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led); 683 684 /* 685 * Reset the chip to a known state. 686 */ 687 stge_reset(sc, STGE_RESET_FULL); 688 689 /* 690 * Reading the station address from the EEPROM doesn't seem 691 * to work, at least on my sample boards. Instead, since 692 * the reset sequence does AutoInit, read it from the station 693 * address registers. For Sundance 1023 you can only read it 694 * from EEPROM. 695 */ 696 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) { 697 uint16_t v; 698 699 v = CSR_READ_2(sc, STGE_StationAddress0); 700 enaddr[0] = v & 0xff; 701 enaddr[1] = v >> 8; 702 v = CSR_READ_2(sc, STGE_StationAddress1); 703 enaddr[2] = v & 0xff; 704 enaddr[3] = v >> 8; 705 v = CSR_READ_2(sc, STGE_StationAddress2); 706 enaddr[4] = v & 0xff; 707 enaddr[5] = v >> 8; 708 sc->sc_stge1023 = 0; 709 } else { 710 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 711 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 712 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 713 &myaddr[i]); 714 myaddr[i] = le16toh(myaddr[i]); 715 } 716 bcopy(myaddr, enaddr, sizeof(enaddr)); 717 sc->sc_stge1023 = 1; 718 } 719 720 ifp->if_softc = sc; 721 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 722 ifp->if_ioctl = stge_ioctl; 723 ifp->if_start = stge_start; 724 ifp->if_watchdog = stge_watchdog; 725 ifp->if_init = stge_init; 726 #ifdef IFPOLL_ENABLE 727 ifp->if_npoll = stge_npoll; 728 #endif 729 ifp->if_mtu = ETHERMTU; 730 ifq_set_maxlen(&ifp->if_snd, STGE_TX_RING_CNT - 1); 731 ifq_set_ready(&ifp->if_snd); 732 /* Revision B3 and earlier chips have checksum bug. */ 733 if (sc->sc_rev >= 0x0c) { 734 ifp->if_hwassist = STGE_CSUM_FEATURES; 735 ifp->if_capabilities = IFCAP_HWCSUM; 736 } else { 737 ifp->if_hwassist = 0; 738 ifp->if_capabilities = 0; 739 } 740 ifp->if_capenable = ifp->if_capabilities; 741 742 /* 743 * Read some important bits from the PhyCtrl register. 744 */ 745 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & 746 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 747 748 /* Set up MII bus. */ 749 if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, stge_mediachange, 750 stge_mediastatus)) != 0) { 751 device_printf(sc->sc_dev, "no PHY found!\n"); 752 goto fail; 753 } 754 755 ether_ifattach(ifp, enaddr, NULL); 756 757 #ifdef IFPOLL_ENABLE 758 ifpoll_compat_setup(&sc->sc_npoll, ctx, (struct sysctl_oid *)tree, 759 device_get_unit(dev), ifp->if_serializer); 760 #endif 761 762 /* VLAN capability setup */ 763 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 764 #ifdef notyet 765 if (sc->sc_rev >= 0x0c) 766 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 767 #endif 768 ifp->if_capenable = ifp->if_capabilities; 769 770 /* 771 * Tell the upper layer(s) we support long frames. 772 * Must appear after the call to ether_ifattach() because 773 * ether_ifattach() sets ifi_hdrlen to the default value. 774 */ 775 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 776 777 /* 778 * The manual recommends disabling early transmit, so we 779 * do. It's disabled anyway, if using IP checksumming, 780 * since the entire packet must be in the FIFO in order 781 * for the chip to perform the checksum. 782 */ 783 sc->sc_txthresh = 0x0fff; 784 785 /* 786 * Disable MWI if the PCI layer tells us to. 787 */ 788 sc->sc_DMACtrl = 0; 789 if ((cmd & PCIM_CMD_MWRICEN) == 0) 790 sc->sc_DMACtrl |= DMAC_MWIDisable; 791 792 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq)); 793 794 /* 795 * Hookup IRQ 796 */ 797 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, stge_intr, sc, 798 &sc->sc_ih, ifp->if_serializer); 799 if (error != 0) { 800 ether_ifdetach(ifp); 801 device_printf(sc->sc_dev, "couldn't set up IRQ\n"); 802 goto fail; 803 } 804 805 fail: 806 if (error != 0) 807 stge_detach(dev); 808 809 return (error); 810 } 811 812 static int 813 stge_detach(device_t dev) 814 { 815 struct stge_softc *sc = device_get_softc(dev); 816 struct ifnet *ifp = &sc->arpcom.ac_if; 817 818 if (device_is_attached(dev)) { 819 lwkt_serialize_enter(ifp->if_serializer); 820 /* XXX */ 821 sc->sc_detach = 1; 822 stge_stop(sc); 823 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 824 lwkt_serialize_exit(ifp->if_serializer); 825 826 ether_ifdetach(ifp); 827 } 828 829 if (sc->sc_miibus != NULL) 830 device_delete_child(dev, sc->sc_miibus); 831 bus_generic_detach(dev); 832 833 stge_dma_free(sc); 834 835 if (sc->sc_irq != NULL) { 836 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 837 sc->sc_irq); 838 } 839 if (sc->sc_res != NULL) { 840 bus_release_resource(dev, sc->sc_res_type, sc->sc_res_rid, 841 sc->sc_res); 842 } 843 844 return (0); 845 } 846 847 static int 848 stge_dma_alloc(struct stge_softc *sc) 849 { 850 struct stge_txdesc *txd; 851 struct stge_rxdesc *rxd; 852 int error, i; 853 854 /* create parent tag. */ 855 error = bus_dma_tag_create(NULL, /* parent */ 856 1, 0, /* algnmnt, boundary */ 857 STGE_DMA_MAXADDR, /* lowaddr */ 858 BUS_SPACE_MAXADDR, /* highaddr */ 859 NULL, NULL, /* filter, filterarg */ 860 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 861 0, /* nsegments */ 862 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 863 0, /* flags */ 864 &sc->sc_cdata.stge_parent_tag); 865 if (error != 0) { 866 device_printf(sc->sc_dev, "failed to create parent DMA tag\n"); 867 return error; 868 } 869 870 /* allocate Tx ring. */ 871 sc->sc_rdata.stge_tx_ring = 872 bus_dmamem_coherent_any(sc->sc_cdata.stge_parent_tag, 873 STGE_RING_ALIGN, STGE_TX_RING_SZ, 874 BUS_DMA_WAITOK | BUS_DMA_ZERO, 875 &sc->sc_cdata.stge_tx_ring_tag, 876 &sc->sc_cdata.stge_tx_ring_map, 877 &sc->sc_rdata.stge_tx_ring_paddr); 878 if (sc->sc_rdata.stge_tx_ring == NULL) { 879 device_printf(sc->sc_dev, 880 "failed to allocate Tx ring\n"); 881 return ENOMEM; 882 } 883 884 /* allocate Rx ring. */ 885 sc->sc_rdata.stge_rx_ring = 886 bus_dmamem_coherent_any(sc->sc_cdata.stge_parent_tag, 887 STGE_RING_ALIGN, STGE_RX_RING_SZ, 888 BUS_DMA_WAITOK | BUS_DMA_ZERO, 889 &sc->sc_cdata.stge_rx_ring_tag, 890 &sc->sc_cdata.stge_rx_ring_map, 891 &sc->sc_rdata.stge_rx_ring_paddr); 892 if (sc->sc_rdata.stge_rx_ring == NULL) { 893 device_printf(sc->sc_dev, 894 "failed to allocate Rx ring\n"); 895 return ENOMEM; 896 } 897 898 /* create tag for Tx buffers. */ 899 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 900 1, 0, /* algnmnt, boundary */ 901 BUS_SPACE_MAXADDR, /* lowaddr */ 902 BUS_SPACE_MAXADDR, /* highaddr */ 903 NULL, NULL, /* filter, filterarg */ 904 STGE_JUMBO_FRAMELEN, /* maxsize */ 905 STGE_MAXTXSEGS, /* nsegments */ 906 STGE_MAXSGSIZE, /* maxsegsize */ 907 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */ 908 &sc->sc_cdata.stge_tx_tag); 909 if (error != 0) { 910 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n"); 911 return error; 912 } 913 914 /* create DMA maps for Tx buffers. */ 915 for (i = 0; i < STGE_TX_RING_CNT; i++) { 916 txd = &sc->sc_cdata.stge_txdesc[i]; 917 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 918 BUS_DMA_WAITOK, &txd->tx_dmamap); 919 if (error != 0) { 920 int j; 921 922 for (j = 0; j < i; ++j) { 923 txd = &sc->sc_cdata.stge_txdesc[j]; 924 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag, 925 txd->tx_dmamap); 926 } 927 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag); 928 sc->sc_cdata.stge_tx_tag = NULL; 929 930 device_printf(sc->sc_dev, 931 "failed to create Tx dmamap\n"); 932 return error; 933 } 934 } 935 936 /* create tag for Rx buffers. */ 937 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 938 1, 0, /* algnmnt, boundary */ 939 BUS_SPACE_MAXADDR, /* lowaddr */ 940 BUS_SPACE_MAXADDR, /* highaddr */ 941 NULL, NULL, /* filter, filterarg */ 942 MCLBYTES, /* maxsize */ 943 1, /* nsegments */ 944 MCLBYTES, /* maxsegsize */ 945 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */ 946 &sc->sc_cdata.stge_rx_tag); 947 if (error != 0) { 948 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n"); 949 return error; 950 } 951 952 /* create DMA maps for Rx buffers. */ 953 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, BUS_DMA_WAITOK, 954 &sc->sc_cdata.stge_rx_sparemap); 955 if (error != 0) { 956 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n"); 957 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag); 958 sc->sc_cdata.stge_rx_tag = NULL; 959 return error; 960 } 961 for (i = 0; i < STGE_RX_RING_CNT; i++) { 962 rxd = &sc->sc_cdata.stge_rxdesc[i]; 963 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 964 BUS_DMA_WAITOK, &rxd->rx_dmamap); 965 if (error != 0) { 966 int j; 967 968 for (j = 0; j < i; ++j) { 969 rxd = &sc->sc_cdata.stge_rxdesc[j]; 970 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 971 rxd->rx_dmamap); 972 } 973 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 974 sc->sc_cdata.stge_rx_sparemap); 975 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag); 976 sc->sc_cdata.stge_rx_tag = NULL; 977 978 device_printf(sc->sc_dev, 979 "failed to create Rx dmamap\n"); 980 return error; 981 } 982 } 983 return 0; 984 } 985 986 static void 987 stge_dma_free(struct stge_softc *sc) 988 { 989 struct stge_txdesc *txd; 990 struct stge_rxdesc *rxd; 991 int i; 992 993 /* Tx ring */ 994 if (sc->sc_cdata.stge_tx_ring_tag) { 995 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag, 996 sc->sc_cdata.stge_tx_ring_map); 997 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag, 998 sc->sc_rdata.stge_tx_ring, 999 sc->sc_cdata.stge_tx_ring_map); 1000 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag); 1001 } 1002 1003 /* Rx ring */ 1004 if (sc->sc_cdata.stge_rx_ring_tag) { 1005 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag, 1006 sc->sc_cdata.stge_rx_ring_map); 1007 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag, 1008 sc->sc_rdata.stge_rx_ring, 1009 sc->sc_cdata.stge_rx_ring_map); 1010 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag); 1011 } 1012 1013 /* Tx buffers */ 1014 if (sc->sc_cdata.stge_tx_tag) { 1015 for (i = 0; i < STGE_TX_RING_CNT; i++) { 1016 txd = &sc->sc_cdata.stge_txdesc[i]; 1017 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag, 1018 txd->tx_dmamap); 1019 } 1020 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag); 1021 } 1022 1023 /* Rx buffers */ 1024 if (sc->sc_cdata.stge_rx_tag) { 1025 for (i = 0; i < STGE_RX_RING_CNT; i++) { 1026 rxd = &sc->sc_cdata.stge_rxdesc[i]; 1027 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 1028 rxd->rx_dmamap); 1029 } 1030 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 1031 sc->sc_cdata.stge_rx_sparemap); 1032 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag); 1033 } 1034 1035 /* Top level tag */ 1036 if (sc->sc_cdata.stge_parent_tag) 1037 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag); 1038 } 1039 1040 /* 1041 * stge_shutdown: 1042 * 1043 * Make sure the interface is stopped at reboot time. 1044 */ 1045 static void 1046 stge_shutdown(device_t dev) 1047 { 1048 struct stge_softc *sc = device_get_softc(dev); 1049 struct ifnet *ifp = &sc->arpcom.ac_if; 1050 1051 lwkt_serialize_enter(ifp->if_serializer); 1052 stge_stop(sc); 1053 lwkt_serialize_exit(ifp->if_serializer); 1054 } 1055 1056 static int 1057 stge_suspend(device_t dev) 1058 { 1059 struct stge_softc *sc = device_get_softc(dev); 1060 struct ifnet *ifp = &sc->arpcom.ac_if; 1061 1062 lwkt_serialize_enter(ifp->if_serializer); 1063 stge_stop(sc); 1064 sc->sc_suspended = 1; 1065 lwkt_serialize_exit(ifp->if_serializer); 1066 1067 return (0); 1068 } 1069 1070 static int 1071 stge_resume(device_t dev) 1072 { 1073 struct stge_softc *sc = device_get_softc(dev); 1074 struct ifnet *ifp = &sc->arpcom.ac_if; 1075 1076 lwkt_serialize_enter(ifp->if_serializer); 1077 if (ifp->if_flags & IFF_UP) 1078 stge_init(sc); 1079 sc->sc_suspended = 0; 1080 lwkt_serialize_exit(ifp->if_serializer); 1081 1082 return (0); 1083 } 1084 1085 static void 1086 stge_dma_wait(struct stge_softc *sc) 1087 { 1088 int i; 1089 1090 for (i = 0; i < STGE_TIMEOUT; i++) { 1091 DELAY(2); 1092 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) 1093 break; 1094 } 1095 1096 if (i == STGE_TIMEOUT) 1097 device_printf(sc->sc_dev, "DMA wait timed out\n"); 1098 } 1099 1100 static int 1101 stge_encap(struct stge_softc *sc, struct mbuf **m_head) 1102 { 1103 struct stge_txdesc *txd; 1104 struct stge_tfd *tfd; 1105 struct mbuf *m; 1106 bus_dma_segment_t txsegs[STGE_MAXTXSEGS]; 1107 int error, i, si, nsegs; 1108 uint64_t csum_flags, tfc; 1109 1110 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq); 1111 KKASSERT(txd != NULL); 1112 1113 error = bus_dmamap_load_mbuf_defrag(sc->sc_cdata.stge_tx_tag, 1114 txd->tx_dmamap, m_head, 1115 txsegs, STGE_MAXTXSEGS, &nsegs, BUS_DMA_NOWAIT); 1116 if (error) { 1117 m_freem(*m_head); 1118 *m_head = NULL; 1119 return (error); 1120 } 1121 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap, 1122 BUS_DMASYNC_PREWRITE); 1123 1124 m = *m_head; 1125 1126 csum_flags = 0; 1127 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) { 1128 if (m->m_pkthdr.csum_flags & CSUM_IP) 1129 csum_flags |= TFD_IPChecksumEnable; 1130 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1131 csum_flags |= TFD_TCPChecksumEnable; 1132 else if (m->m_pkthdr.csum_flags & CSUM_UDP) 1133 csum_flags |= TFD_UDPChecksumEnable; 1134 } 1135 1136 si = sc->sc_cdata.stge_tx_prod; 1137 tfd = &sc->sc_rdata.stge_tx_ring[si]; 1138 for (i = 0; i < nsegs; i++) { 1139 tfd->tfd_frags[i].frag_word0 = 1140 htole64(FRAG_ADDR(txsegs[i].ds_addr) | 1141 FRAG_LEN(txsegs[i].ds_len)); 1142 } 1143 sc->sc_cdata.stge_tx_cnt++; 1144 1145 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) | 1146 TFD_FragCount(nsegs) | csum_flags; 1147 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) 1148 tfc |= TFD_TxDMAIndicate; 1149 1150 /* Update producer index. */ 1151 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT; 1152 1153 /* Check if we have a VLAN tag to insert. */ 1154 if (m->m_flags & M_VLANTAG) 1155 tfc |= TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vlantag); 1156 tfd->tfd_control = htole64(tfc); 1157 1158 /* Update Tx Queue. */ 1159 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q); 1160 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q); 1161 txd->tx_m = m; 1162 1163 return (0); 1164 } 1165 1166 /* 1167 * stge_start: [ifnet interface function] 1168 * 1169 * Start packet transmission on the interface. 1170 */ 1171 static void 1172 stge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1173 { 1174 struct stge_softc *sc; 1175 struct mbuf *m_head; 1176 int enq; 1177 1178 sc = ifp->if_softc; 1179 1180 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1181 ASSERT_SERIALIZED(ifp->if_serializer); 1182 1183 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1184 return; 1185 1186 enq = 0; 1187 while (!ifq_is_empty(&ifp->if_snd)) { 1188 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) { 1189 ifq_set_oactive(&ifp->if_snd); 1190 break; 1191 } 1192 1193 m_head = ifq_dequeue(&ifp->if_snd); 1194 if (m_head == NULL) 1195 break; 1196 1197 /* 1198 * Pack the data into the transmit ring. If we 1199 * don't have room, set the OACTIVE flag and wait 1200 * for the NIC to drain the ring. 1201 */ 1202 if (stge_encap(sc, &m_head)) { 1203 if (sc->sc_cdata.stge_tx_cnt == 0) { 1204 continue; 1205 } else { 1206 ifq_set_oactive(&ifp->if_snd); 1207 break; 1208 } 1209 } 1210 enq = 1; 1211 1212 /* 1213 * If there's a BPF listener, bounce a copy of this frame 1214 * to him. 1215 */ 1216 ETHER_BPF_MTAP(ifp, m_head); 1217 } 1218 1219 if (enq) { 1220 /* Transmit */ 1221 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow); 1222 1223 /* Set a timeout in case the chip goes out to lunch. */ 1224 ifp->if_timer = 5; 1225 } 1226 } 1227 1228 /* 1229 * stge_watchdog: [ifnet interface function] 1230 * 1231 * Watchdog timer handler. 1232 */ 1233 static void 1234 stge_watchdog(struct ifnet *ifp) 1235 { 1236 ASSERT_SERIALIZED(ifp->if_serializer); 1237 1238 if_printf(ifp, "device timeout\n"); 1239 IFNET_STAT_INC(ifp, oerrors, 1); 1240 stge_init(ifp->if_softc); 1241 } 1242 1243 /* 1244 * stge_ioctl: [ifnet interface function] 1245 * 1246 * Handle control requests from the operator. 1247 */ 1248 static int 1249 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1250 { 1251 struct stge_softc *sc; 1252 struct ifreq *ifr; 1253 struct mii_data *mii; 1254 int error, mask; 1255 1256 ASSERT_SERIALIZED(ifp->if_serializer); 1257 1258 sc = ifp->if_softc; 1259 ifr = (struct ifreq *)data; 1260 error = 0; 1261 switch (cmd) { 1262 case SIOCSIFMTU: 1263 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU) 1264 error = EINVAL; 1265 else if (ifp->if_mtu != ifr->ifr_mtu) { 1266 ifp->if_mtu = ifr->ifr_mtu; 1267 stge_init(sc); 1268 } 1269 break; 1270 case SIOCSIFFLAGS: 1271 if ((ifp->if_flags & IFF_UP) != 0) { 1272 if ((ifp->if_flags & IFF_RUNNING) != 0) { 1273 if (((ifp->if_flags ^ sc->sc_if_flags) 1274 & IFF_PROMISC) != 0) 1275 stge_set_filter(sc); 1276 } else { 1277 if (sc->sc_detach == 0) 1278 stge_init(sc); 1279 } 1280 } else { 1281 if ((ifp->if_flags & IFF_RUNNING) != 0) 1282 stge_stop(sc); 1283 } 1284 sc->sc_if_flags = ifp->if_flags; 1285 break; 1286 case SIOCADDMULTI: 1287 case SIOCDELMULTI: 1288 if ((ifp->if_flags & IFF_RUNNING) != 0) 1289 stge_set_multi(sc); 1290 break; 1291 case SIOCSIFMEDIA: 1292 case SIOCGIFMEDIA: 1293 mii = device_get_softc(sc->sc_miibus); 1294 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1295 break; 1296 case SIOCSIFCAP: 1297 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1298 if ((mask & IFCAP_HWCSUM) != 0) { 1299 ifp->if_capenable ^= IFCAP_HWCSUM; 1300 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 && 1301 (IFCAP_HWCSUM & ifp->if_capabilities) != 0) 1302 ifp->if_hwassist = STGE_CSUM_FEATURES; 1303 else 1304 ifp->if_hwassist = 0; 1305 } 1306 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 1307 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1308 if (ifp->if_flags & IFF_RUNNING) 1309 stge_vlan_setup(sc); 1310 } 1311 #if 0 1312 VLAN_CAPABILITIES(ifp); 1313 #endif 1314 break; 1315 default: 1316 error = ether_ioctl(ifp, cmd, data); 1317 break; 1318 } 1319 1320 return (error); 1321 } 1322 1323 static void 1324 stge_link(struct stge_softc *sc) 1325 { 1326 uint32_t v, ac; 1327 int i; 1328 1329 /* 1330 * Update STGE_MACCtrl register depending on link status. 1331 * (duplex, flow control etc) 1332 */ 1333 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 1334 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable); 1335 v |= sc->sc_MACCtrl; 1336 CSR_WRITE_4(sc, STGE_MACCtrl, v); 1337 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) { 1338 /* Duplex setting changed, reset Tx/Rx functions. */ 1339 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1340 ac |= AC_TxReset | AC_RxReset; 1341 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1342 for (i = 0; i < STGE_TIMEOUT; i++) { 1343 DELAY(100); 1344 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1345 break; 1346 } 1347 if (i == STGE_TIMEOUT) 1348 device_printf(sc->sc_dev, "reset failed to complete\n"); 1349 } 1350 } 1351 1352 static __inline int 1353 stge_tx_error(struct stge_softc *sc) 1354 { 1355 uint32_t txstat; 1356 int error; 1357 1358 for (error = 0;;) { 1359 txstat = CSR_READ_4(sc, STGE_TxStatus); 1360 if ((txstat & TS_TxComplete) == 0) 1361 break; 1362 /* Tx underrun */ 1363 if ((txstat & TS_TxUnderrun) != 0) { 1364 /* 1365 * XXX 1366 * There should be a more better way to recover 1367 * from Tx underrun instead of a full reset. 1368 */ 1369 if (sc->sc_nerr++ < STGE_MAXERR) 1370 device_printf(sc->sc_dev, "Tx underrun, " 1371 "resetting...\n"); 1372 if (sc->sc_nerr == STGE_MAXERR) 1373 device_printf(sc->sc_dev, "too many errors; " 1374 "not reporting any more\n"); 1375 error = -1; 1376 break; 1377 } 1378 /* Maximum/Late collisions, Re-enable Tx MAC. */ 1379 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0) 1380 CSR_WRITE_4(sc, STGE_MACCtrl, 1381 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) | 1382 MC_TxEnable); 1383 } 1384 1385 return (error); 1386 } 1387 1388 /* 1389 * stge_intr: 1390 * 1391 * Interrupt service routine. 1392 */ 1393 static void 1394 stge_intr(void *arg) 1395 { 1396 struct stge_softc *sc = arg; 1397 struct ifnet *ifp = &sc->arpcom.ac_if; 1398 int reinit; 1399 uint16_t status; 1400 1401 ASSERT_SERIALIZED(ifp->if_serializer); 1402 1403 status = CSR_READ_2(sc, STGE_IntStatus); 1404 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0) 1405 return; 1406 1407 /* Disable interrupts. */ 1408 for (reinit = 0;;) { 1409 status = CSR_READ_2(sc, STGE_IntStatusAck); 1410 status &= sc->sc_IntEnable; 1411 if (status == 0) 1412 break; 1413 /* Host interface errors. */ 1414 if ((status & IS_HostError) != 0) { 1415 device_printf(sc->sc_dev, 1416 "Host interface error, resetting...\n"); 1417 reinit = 1; 1418 goto force_init; 1419 } 1420 1421 /* Receive interrupts. */ 1422 if ((status & IS_RxDMAComplete) != 0) { 1423 stge_rxeof(sc, -1); 1424 if ((status & IS_RFDListEnd) != 0) 1425 CSR_WRITE_4(sc, STGE_DMACtrl, 1426 DMAC_RxDMAPollNow); 1427 } 1428 1429 /* Transmit interrupts. */ 1430 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0) 1431 stge_txeof(sc); 1432 1433 /* Transmission errors.*/ 1434 if ((status & IS_TxComplete) != 0) { 1435 if ((reinit = stge_tx_error(sc)) != 0) 1436 break; 1437 } 1438 } 1439 1440 force_init: 1441 if (reinit != 0) 1442 stge_init(sc); 1443 1444 /* Re-enable interrupts. */ 1445 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1446 1447 /* Try to get more packets going. */ 1448 if (!ifq_is_empty(&ifp->if_snd)) 1449 if_devstart(ifp); 1450 } 1451 1452 /* 1453 * stge_txeof: 1454 * 1455 * Helper; handle transmit interrupts. 1456 */ 1457 static void 1458 stge_txeof(struct stge_softc *sc) 1459 { 1460 struct ifnet *ifp = &sc->arpcom.ac_if; 1461 struct stge_txdesc *txd; 1462 uint64_t control; 1463 int cons; 1464 1465 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1466 if (txd == NULL) 1467 return; 1468 1469 /* 1470 * Go through our Tx list and free mbufs for those 1471 * frames which have been transmitted. 1472 */ 1473 for (cons = sc->sc_cdata.stge_tx_cons;; 1474 cons = (cons + 1) % STGE_TX_RING_CNT) { 1475 if (sc->sc_cdata.stge_tx_cnt <= 0) 1476 break; 1477 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control); 1478 if ((control & TFD_TFDDone) == 0) 1479 break; 1480 sc->sc_cdata.stge_tx_cnt--; 1481 1482 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap); 1483 1484 /* Output counter is updated with statistics register */ 1485 m_freem(txd->tx_m); 1486 txd->tx_m = NULL; 1487 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q); 1488 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 1489 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1490 } 1491 sc->sc_cdata.stge_tx_cons = cons; 1492 1493 if (sc->sc_cdata.stge_tx_cnt < STGE_TX_HIWAT) 1494 ifq_clr_oactive(&ifp->if_snd); 1495 if (sc->sc_cdata.stge_tx_cnt == 0) 1496 ifp->if_timer = 0; 1497 } 1498 1499 static __inline void 1500 stge_discard_rxbuf(struct stge_softc *sc, int idx) 1501 { 1502 struct stge_rfd *rfd; 1503 1504 rfd = &sc->sc_rdata.stge_rx_ring[idx]; 1505 rfd->rfd_status = 0; 1506 } 1507 1508 #ifndef __x86_64__ 1509 /* 1510 * It seems that TC9021's DMA engine has alignment restrictions in 1511 * DMA scatter operations. The first DMA segment has no address 1512 * alignment restrictins but the rest should be aligned on 4(?) bytes 1513 * boundary. Otherwise it would corrupt random memory. Since we don't 1514 * know which one is used for the first segment in advance we simply 1515 * don't align at all. 1516 * To avoid copying over an entire frame to align, we allocate a new 1517 * mbuf and copy ethernet header to the new mbuf. The new mbuf is 1518 * prepended into the existing mbuf chain. 1519 */ 1520 static __inline struct mbuf * 1521 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m) 1522 { 1523 struct mbuf *n; 1524 1525 n = NULL; 1526 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 1527 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 1528 m->m_data += ETHER_HDR_LEN; 1529 n = m; 1530 } else { 1531 MGETHDR(n, M_NOWAIT, MT_DATA); 1532 if (n != NULL) { 1533 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 1534 m->m_data += ETHER_HDR_LEN; 1535 m->m_len -= ETHER_HDR_LEN; 1536 n->m_len = ETHER_HDR_LEN; 1537 M_MOVE_PKTHDR(n, m); 1538 n->m_next = m; 1539 } else 1540 m_freem(m); 1541 } 1542 1543 return (n); 1544 } 1545 #endif 1546 1547 /* 1548 * stge_rxeof: 1549 * 1550 * Helper; handle receive interrupts. 1551 */ 1552 static void 1553 stge_rxeof(struct stge_softc *sc, int count) 1554 { 1555 struct ifnet *ifp = &sc->arpcom.ac_if; 1556 struct stge_rxdesc *rxd; 1557 struct mbuf *mp, *m; 1558 uint64_t status64; 1559 uint32_t status; 1560 int cons, prog; 1561 1562 prog = 0; 1563 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT; 1564 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) { 1565 #ifdef IFPOLL_ENABLE 1566 if (count >= 0 && count-- == 0) 1567 break; 1568 #endif 1569 1570 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status); 1571 status = RFD_RxStatus(status64); 1572 if ((status & RFD_RFDDone) == 0) 1573 break; 1574 1575 prog++; 1576 rxd = &sc->sc_cdata.stge_rxdesc[cons]; 1577 mp = rxd->rx_m; 1578 1579 /* 1580 * If the packet had an error, drop it. Note we count 1581 * the error later in the periodic stats update. 1582 */ 1583 if ((status & RFD_FrameEnd) != 0 && (status & 1584 (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1585 RFD_RxAlignmentError | RFD_RxFCSError | 1586 RFD_RxLengthError)) != 0) { 1587 stge_discard_rxbuf(sc, cons); 1588 if (sc->sc_cdata.stge_rxhead != NULL) { 1589 m_freem(sc->sc_cdata.stge_rxhead); 1590 STGE_RXCHAIN_RESET(sc); 1591 } 1592 continue; 1593 } 1594 /* 1595 * Add a new receive buffer to the ring. 1596 */ 1597 if (stge_newbuf(sc, cons, 0) != 0) { 1598 IFNET_STAT_INC(ifp, iqdrops, 1); 1599 stge_discard_rxbuf(sc, cons); 1600 if (sc->sc_cdata.stge_rxhead != NULL) { 1601 m_freem(sc->sc_cdata.stge_rxhead); 1602 STGE_RXCHAIN_RESET(sc); 1603 } 1604 continue; 1605 } 1606 1607 if ((status & RFD_FrameEnd) != 0) 1608 mp->m_len = RFD_RxDMAFrameLen(status) - 1609 sc->sc_cdata.stge_rxlen; 1610 sc->sc_cdata.stge_rxlen += mp->m_len; 1611 1612 /* Chain mbufs. */ 1613 if (sc->sc_cdata.stge_rxhead == NULL) { 1614 sc->sc_cdata.stge_rxhead = mp; 1615 sc->sc_cdata.stge_rxtail = mp; 1616 } else { 1617 mp->m_flags &= ~M_PKTHDR; 1618 sc->sc_cdata.stge_rxtail->m_next = mp; 1619 sc->sc_cdata.stge_rxtail = mp; 1620 } 1621 1622 if ((status & RFD_FrameEnd) != 0) { 1623 m = sc->sc_cdata.stge_rxhead; 1624 m->m_pkthdr.rcvif = ifp; 1625 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen; 1626 1627 if (m->m_pkthdr.len > sc->sc_if_framesize) { 1628 m_freem(m); 1629 STGE_RXCHAIN_RESET(sc); 1630 continue; 1631 } 1632 /* 1633 * Set the incoming checksum information for 1634 * the packet. 1635 */ 1636 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1637 if ((status & RFD_IPDetected) != 0) { 1638 m->m_pkthdr.csum_flags |= 1639 CSUM_IP_CHECKED; 1640 if ((status & RFD_IPError) == 0) 1641 m->m_pkthdr.csum_flags |= 1642 CSUM_IP_VALID; 1643 } 1644 if (((status & RFD_TCPDetected) != 0 && 1645 (status & RFD_TCPError) == 0) || 1646 ((status & RFD_UDPDetected) != 0 && 1647 (status & RFD_UDPError) == 0)) { 1648 m->m_pkthdr.csum_flags |= 1649 (CSUM_DATA_VALID | 1650 CSUM_PSEUDO_HDR | 1651 CSUM_FRAG_NOT_CHECKED); 1652 m->m_pkthdr.csum_data = 0xffff; 1653 } 1654 } 1655 1656 #ifndef __x86_64__ 1657 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) { 1658 if ((m = stge_fixup_rx(sc, m)) == NULL) { 1659 STGE_RXCHAIN_RESET(sc); 1660 continue; 1661 } 1662 } 1663 #endif 1664 1665 /* Check for VLAN tagged packets. */ 1666 if ((status & RFD_VLANDetected) != 0 && 1667 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 1668 m->m_flags |= M_VLANTAG; 1669 m->m_pkthdr.ether_vlantag = RFD_TCI(status64); 1670 } 1671 /* Pass it on. */ 1672 ifp->if_input(ifp, m, NULL, -1); 1673 1674 STGE_RXCHAIN_RESET(sc); 1675 } 1676 } 1677 1678 if (prog > 0) { 1679 /* Update the consumer index. */ 1680 sc->sc_cdata.stge_rx_cons = cons; 1681 } 1682 } 1683 1684 #ifdef IFPOLL_ENABLE 1685 1686 static void 1687 stge_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 1688 { 1689 struct stge_softc *sc = ifp->if_softc; 1690 1691 ASSERT_SERIALIZED(ifp->if_serializer); 1692 1693 if (sc->sc_npoll.ifpc_stcount-- == 0) { 1694 uint16_t status; 1695 1696 sc->sc_npoll.ifpc_stcount = sc->sc_npoll.ifpc_stfrac; 1697 1698 status = CSR_READ_2(sc, STGE_IntStatus); 1699 status &= sc->sc_IntEnable; 1700 if (status != 0) { 1701 if (status & IS_HostError) { 1702 device_printf(sc->sc_dev, 1703 "Host interface error, " 1704 "resetting...\n"); 1705 stge_init(sc); 1706 } 1707 if ((status & IS_TxComplete) != 0 && 1708 stge_tx_error(sc) != 0) 1709 stge_init(sc); 1710 } 1711 } 1712 1713 stge_rxeof(sc, count); 1714 stge_txeof(sc); 1715 1716 if (!ifq_is_empty(&ifp->if_snd)) 1717 if_devstart(ifp); 1718 } 1719 1720 static void 1721 stge_npoll(struct ifnet *ifp, struct ifpoll_info *info) 1722 { 1723 struct stge_softc *sc = ifp->if_softc; 1724 1725 ASSERT_SERIALIZED(ifp->if_serializer); 1726 1727 if (info != NULL) { 1728 int cpuid = sc->sc_npoll.ifpc_cpuid; 1729 1730 info->ifpi_rx[cpuid].poll_func = stge_npoll_compat; 1731 info->ifpi_rx[cpuid].arg = NULL; 1732 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 1733 1734 if (ifp->if_flags & IFF_RUNNING) { 1735 CSR_WRITE_2(sc, STGE_IntEnable, 0); 1736 sc->sc_npoll.ifpc_stcount = 0; 1737 } 1738 ifq_set_cpuid(&ifp->if_snd, cpuid); 1739 } else { 1740 if (ifp->if_flags & IFF_RUNNING) 1741 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1742 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq)); 1743 } 1744 } 1745 1746 #endif /* IFPOLL_ENABLE */ 1747 1748 /* 1749 * stge_tick: 1750 * 1751 * One second timer, used to tick the MII. 1752 */ 1753 static void 1754 stge_tick(void *arg) 1755 { 1756 struct stge_softc *sc = arg; 1757 struct ifnet *ifp = &sc->arpcom.ac_if; 1758 struct mii_data *mii; 1759 1760 lwkt_serialize_enter(ifp->if_serializer); 1761 1762 mii = device_get_softc(sc->sc_miibus); 1763 mii_tick(mii); 1764 1765 /* Update statistics counters. */ 1766 stge_stats_update(sc); 1767 1768 /* 1769 * Relcaim any pending Tx descriptors to release mbufs in a 1770 * timely manner as we don't generate Tx completion interrupts 1771 * for every frame. This limits the delay to a maximum of one 1772 * second. 1773 */ 1774 if (sc->sc_cdata.stge_tx_cnt != 0) 1775 stge_txeof(sc); 1776 1777 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1778 1779 lwkt_serialize_exit(ifp->if_serializer); 1780 } 1781 1782 /* 1783 * stge_stats_update: 1784 * 1785 * Read the TC9021 statistics counters. 1786 */ 1787 static void 1788 stge_stats_update(struct stge_softc *sc) 1789 { 1790 struct ifnet *ifp = &sc->arpcom.ac_if; 1791 1792 CSR_READ_4(sc,STGE_OctetRcvOk); 1793 1794 IFNET_STAT_INC(ifp, ipackets, CSR_READ_4(sc, STGE_FramesRcvdOk)); 1795 1796 IFNET_STAT_INC(ifp, ierrors, CSR_READ_2(sc, STGE_FramesLostRxErrors)); 1797 1798 CSR_READ_4(sc, STGE_OctetXmtdOk); 1799 1800 IFNET_STAT_INC(ifp, opackets, CSR_READ_4(sc, STGE_FramesXmtdOk)); 1801 1802 IFNET_STAT_INC(ifp, collisions, 1803 CSR_READ_4(sc, STGE_LateCollisions) + 1804 CSR_READ_4(sc, STGE_MultiColFrames) + 1805 CSR_READ_4(sc, STGE_SingleColFrames)); 1806 1807 IFNET_STAT_INC(ifp, oerrors, 1808 CSR_READ_2(sc, STGE_FramesAbortXSColls) + 1809 CSR_READ_2(sc, STGE_FramesWEXDeferal)); 1810 } 1811 1812 /* 1813 * stge_reset: 1814 * 1815 * Perform a soft reset on the TC9021. 1816 */ 1817 static void 1818 stge_reset(struct stge_softc *sc, uint32_t how) 1819 { 1820 uint32_t ac; 1821 uint8_t v; 1822 int i, dv; 1823 1824 dv = 5000; 1825 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1826 switch (how) { 1827 case STGE_RESET_TX: 1828 ac |= AC_TxReset | AC_FIFO; 1829 dv = 100; 1830 break; 1831 case STGE_RESET_RX: 1832 ac |= AC_RxReset | AC_FIFO; 1833 dv = 100; 1834 break; 1835 case STGE_RESET_FULL: 1836 default: 1837 /* 1838 * Only assert RstOut if we're fiber. We need GMII clocks 1839 * to be present in order for the reset to complete on fiber 1840 * cards. 1841 */ 1842 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset | 1843 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1844 (sc->sc_usefiber ? AC_RstOut : 0); 1845 break; 1846 } 1847 1848 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1849 1850 /* Account for reset problem at 10Mbps. */ 1851 DELAY(dv); 1852 1853 for (i = 0; i < STGE_TIMEOUT; i++) { 1854 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1855 break; 1856 DELAY(dv); 1857 } 1858 1859 if (i == STGE_TIMEOUT) 1860 device_printf(sc->sc_dev, "reset failed to complete\n"); 1861 1862 /* Set LED, from Linux IPG driver. */ 1863 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1864 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1); 1865 if ((sc->sc_led & 0x01) != 0) 1866 ac |= AC_LEDMode; 1867 if ((sc->sc_led & 0x03) != 0) 1868 ac |= AC_LEDModeBit1; 1869 if ((sc->sc_led & 0x08) != 0) 1870 ac |= AC_LEDSpeed; 1871 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1872 1873 /* Set PHY, from Linux IPG driver */ 1874 v = CSR_READ_1(sc, STGE_PhySet); 1875 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet); 1876 v |= ((sc->sc_led & 0x70) >> 4); 1877 CSR_WRITE_1(sc, STGE_PhySet, v); 1878 } 1879 1880 /* 1881 * stge_init: [ ifnet interface function ] 1882 * 1883 * Initialize the interface. 1884 */ 1885 static void 1886 stge_init(void *xsc) 1887 { 1888 struct stge_softc *sc = xsc; 1889 struct ifnet *ifp = &sc->arpcom.ac_if; 1890 struct mii_data *mii; 1891 uint16_t eaddr[3]; 1892 uint32_t v; 1893 int error; 1894 1895 ASSERT_SERIALIZED(ifp->if_serializer); 1896 1897 mii = device_get_softc(sc->sc_miibus); 1898 1899 /* 1900 * Cancel any pending I/O. 1901 */ 1902 stge_stop(sc); 1903 1904 /* Init descriptors. */ 1905 error = stge_init_rx_ring(sc); 1906 if (error != 0) { 1907 device_printf(sc->sc_dev, 1908 "initialization failed: no memory for rx buffers\n"); 1909 stge_stop(sc); 1910 goto out; 1911 } 1912 stge_init_tx_ring(sc); 1913 1914 /* Set the station address. */ 1915 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 1916 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0])); 1917 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1])); 1918 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2])); 1919 1920 /* 1921 * Set the statistics masks. Disable all the RMON stats, 1922 * and disable selected stats in the non-RMON stats registers. 1923 */ 1924 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); 1925 CSR_WRITE_4(sc, STGE_StatisticsMask, 1926 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1927 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1928 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1929 (1U << 21)); 1930 1931 /* Set up the receive filter. */ 1932 stge_set_filter(sc); 1933 /* Program multicast filter. */ 1934 stge_set_multi(sc); 1935 1936 /* 1937 * Give the transmit and receive ring to the chip. 1938 */ 1939 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 1940 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0))); 1941 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 1942 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0))); 1943 1944 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 1945 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0))); 1946 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 1947 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0))); 1948 1949 /* 1950 * Initialize the Tx auto-poll period. It's OK to make this number 1951 * large (255 is the max, but we use 127) -- we explicitly kick the 1952 * transmit engine when there's actually a packet. 1953 */ 1954 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 1955 1956 /* ..and the Rx auto-poll period. */ 1957 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 1958 1959 /* Initialize the Tx start threshold. */ 1960 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); 1961 1962 /* Rx DMA thresholds, from Linux */ 1963 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); 1964 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); 1965 1966 /* Rx early threhold, from Linux */ 1967 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); 1968 1969 /* Tx DMA thresholds, from Linux */ 1970 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); 1971 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); 1972 1973 /* 1974 * Initialize the Rx DMA interrupt control register. We 1975 * request an interrupt after every incoming packet, but 1976 * defer it for sc_rxint_dmawait us. When the number of 1977 * interrupts pending reaches STGE_RXINT_NFRAME, we stop 1978 * deferring the interrupt, and signal it immediately. 1979 */ 1980 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, 1981 RDIC_RxFrameCount(sc->sc_rxint_nframe) | 1982 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait))); 1983 1984 /* 1985 * Initialize the interrupt mask. 1986 */ 1987 sc->sc_IntEnable = IS_HostError | IS_TxComplete | 1988 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1989 #ifdef IFPOLL_ENABLE 1990 /* Disable interrupts if we are polling. */ 1991 if (ifp->if_flags & IFF_NPOLLING) { 1992 CSR_WRITE_2(sc, STGE_IntEnable, 0); 1993 sc->sc_npoll.ifpc_stcount = 0; 1994 } else 1995 #endif 1996 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1997 1998 /* 1999 * Configure the DMA engine. 2000 * XXX Should auto-tune TxBurstLimit. 2001 */ 2002 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3)); 2003 2004 /* 2005 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 2006 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes 2007 * in the Rx FIFO. 2008 */ 2009 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16); 2010 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16); 2011 2012 /* 2013 * Set the maximum frame size. 2014 */ 2015 sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2016 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize); 2017 2018 /* 2019 * Initialize MacCtrl -- do it before setting the media, 2020 * as setting the media will actually program the register. 2021 * 2022 * Note: We have to poke the IFS value before poking 2023 * anything else. 2024 */ 2025 /* Tx/Rx MAC should be disabled before programming IFS.*/ 2026 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit)); 2027 2028 stge_vlan_setup(sc); 2029 2030 if (sc->sc_rev >= 6) { /* >= B.2 */ 2031 /* Multi-frag frame bug work-around. */ 2032 CSR_WRITE_2(sc, STGE_DebugCtrl, 2033 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200); 2034 2035 /* Tx Poll Now bug work-around. */ 2036 CSR_WRITE_2(sc, STGE_DebugCtrl, 2037 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010); 2038 /* Tx Poll Now bug work-around. */ 2039 CSR_WRITE_2(sc, STGE_DebugCtrl, 2040 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020); 2041 } 2042 2043 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2044 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 2045 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2046 /* 2047 * It seems that transmitting frames without checking the state of 2048 * Rx/Tx MAC wedge the hardware. 2049 */ 2050 stge_start_tx(sc); 2051 stge_start_rx(sc); 2052 2053 /* 2054 * Set the current media. 2055 */ 2056 mii_mediachg(mii); 2057 2058 /* 2059 * Start the one second MII clock. 2060 */ 2061 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 2062 2063 /* 2064 * ...all done! 2065 */ 2066 ifp->if_flags |= IFF_RUNNING; 2067 ifq_clr_oactive(&ifp->if_snd); 2068 2069 out: 2070 if (error != 0) 2071 device_printf(sc->sc_dev, "interface not running\n"); 2072 } 2073 2074 static void 2075 stge_vlan_setup(struct stge_softc *sc) 2076 { 2077 struct ifnet *ifp = &sc->arpcom.ac_if; 2078 uint32_t v; 2079 2080 /* 2081 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl 2082 * MC_AutoVLANuntagging bit. 2083 * MC_AutoVLANtagging bit selects which VLAN source to use 2084 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert 2085 * bit has priority over MC_AutoVLANtagging bit. So we always 2086 * use TFC instead of STGE_VLANTag register. 2087 */ 2088 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2089 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2090 v |= MC_AutoVLANuntagging; 2091 else 2092 v &= ~MC_AutoVLANuntagging; 2093 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2094 } 2095 2096 /* 2097 * Stop transmission on the interface. 2098 */ 2099 static void 2100 stge_stop(struct stge_softc *sc) 2101 { 2102 struct ifnet *ifp = &sc->arpcom.ac_if; 2103 struct stge_txdesc *txd; 2104 struct stge_rxdesc *rxd; 2105 uint32_t v; 2106 int i; 2107 2108 ASSERT_SERIALIZED(ifp->if_serializer); 2109 2110 /* 2111 * Stop the one second clock. 2112 */ 2113 callout_stop(&sc->sc_tick_ch); 2114 2115 /* 2116 * Reset the chip to a known state. 2117 */ 2118 stge_reset(sc, STGE_RESET_FULL); 2119 2120 /* 2121 * Disable interrupts. 2122 */ 2123 CSR_WRITE_2(sc, STGE_IntEnable, 0); 2124 2125 /* 2126 * Stop receiver, transmitter, and stats update. 2127 */ 2128 stge_stop_rx(sc); 2129 stge_stop_tx(sc); 2130 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2131 v |= MC_StatisticsDisable; 2132 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2133 2134 /* 2135 * Stop the transmit and receive DMA. 2136 */ 2137 stge_dma_wait(sc); 2138 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); 2139 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0); 2140 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); 2141 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0); 2142 2143 /* 2144 * Free RX and TX mbufs still in the queues. 2145 */ 2146 for (i = 0; i < STGE_RX_RING_CNT; i++) { 2147 rxd = &sc->sc_cdata.stge_rxdesc[i]; 2148 if (rxd->rx_m != NULL) { 2149 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, 2150 rxd->rx_dmamap); 2151 m_freem(rxd->rx_m); 2152 rxd->rx_m = NULL; 2153 } 2154 } 2155 for (i = 0; i < STGE_TX_RING_CNT; i++) { 2156 txd = &sc->sc_cdata.stge_txdesc[i]; 2157 if (txd->tx_m != NULL) { 2158 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, 2159 txd->tx_dmamap); 2160 m_freem(txd->tx_m); 2161 txd->tx_m = NULL; 2162 } 2163 } 2164 2165 /* 2166 * Mark the interface down and cancel the watchdog timer. 2167 */ 2168 ifp->if_flags &= ~IFF_RUNNING; 2169 ifq_clr_oactive(&ifp->if_snd); 2170 ifp->if_timer = 0; 2171 } 2172 2173 static void 2174 stge_start_tx(struct stge_softc *sc) 2175 { 2176 uint32_t v; 2177 int i; 2178 2179 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2180 if ((v & MC_TxEnabled) != 0) 2181 return; 2182 v |= MC_TxEnable; 2183 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2184 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 2185 for (i = STGE_TIMEOUT; i > 0; i--) { 2186 DELAY(10); 2187 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2188 if ((v & MC_TxEnabled) != 0) 2189 break; 2190 } 2191 if (i == 0) 2192 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n"); 2193 } 2194 2195 static void 2196 stge_start_rx(struct stge_softc *sc) 2197 { 2198 uint32_t v; 2199 int i; 2200 2201 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2202 if ((v & MC_RxEnabled) != 0) 2203 return; 2204 v |= MC_RxEnable; 2205 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2206 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 2207 for (i = STGE_TIMEOUT; i > 0; i--) { 2208 DELAY(10); 2209 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2210 if ((v & MC_RxEnabled) != 0) 2211 break; 2212 } 2213 if (i == 0) 2214 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n"); 2215 } 2216 2217 static void 2218 stge_stop_tx(struct stge_softc *sc) 2219 { 2220 uint32_t v; 2221 int i; 2222 2223 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2224 if ((v & MC_TxEnabled) == 0) 2225 return; 2226 v |= MC_TxDisable; 2227 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2228 for (i = STGE_TIMEOUT; i > 0; i--) { 2229 DELAY(10); 2230 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2231 if ((v & MC_TxEnabled) == 0) 2232 break; 2233 } 2234 if (i == 0) 2235 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n"); 2236 } 2237 2238 static void 2239 stge_stop_rx(struct stge_softc *sc) 2240 { 2241 uint32_t v; 2242 int i; 2243 2244 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2245 if ((v & MC_RxEnabled) == 0) 2246 return; 2247 v |= MC_RxDisable; 2248 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2249 for (i = STGE_TIMEOUT; i > 0; i--) { 2250 DELAY(10); 2251 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2252 if ((v & MC_RxEnabled) == 0) 2253 break; 2254 } 2255 if (i == 0) 2256 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n"); 2257 } 2258 2259 static void 2260 stge_init_tx_ring(struct stge_softc *sc) 2261 { 2262 struct stge_ring_data *rd; 2263 struct stge_txdesc *txd; 2264 bus_addr_t addr; 2265 int i; 2266 2267 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq); 2268 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq); 2269 2270 sc->sc_cdata.stge_tx_prod = 0; 2271 sc->sc_cdata.stge_tx_cons = 0; 2272 sc->sc_cdata.stge_tx_cnt = 0; 2273 2274 rd = &sc->sc_rdata; 2275 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ); 2276 for (i = 0; i < STGE_TX_RING_CNT; i++) { 2277 if (i == (STGE_TX_RING_CNT - 1)) 2278 addr = STGE_TX_RING_ADDR(sc, 0); 2279 else 2280 addr = STGE_TX_RING_ADDR(sc, i + 1); 2281 rd->stge_tx_ring[i].tfd_next = htole64(addr); 2282 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone); 2283 txd = &sc->sc_cdata.stge_txdesc[i]; 2284 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 2285 } 2286 } 2287 2288 static int 2289 stge_init_rx_ring(struct stge_softc *sc) 2290 { 2291 struct stge_ring_data *rd; 2292 bus_addr_t addr; 2293 int i; 2294 2295 sc->sc_cdata.stge_rx_cons = 0; 2296 STGE_RXCHAIN_RESET(sc); 2297 2298 rd = &sc->sc_rdata; 2299 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ); 2300 for (i = 0; i < STGE_RX_RING_CNT; i++) { 2301 if (stge_newbuf(sc, i, 1) != 0) 2302 return (ENOBUFS); 2303 if (i == (STGE_RX_RING_CNT - 1)) 2304 addr = STGE_RX_RING_ADDR(sc, 0); 2305 else 2306 addr = STGE_RX_RING_ADDR(sc, i + 1); 2307 rd->stge_rx_ring[i].rfd_next = htole64(addr); 2308 rd->stge_rx_ring[i].rfd_status = 0; 2309 } 2310 return (0); 2311 } 2312 2313 /* 2314 * stge_newbuf: 2315 * 2316 * Add a receive buffer to the indicated descriptor. 2317 */ 2318 static int 2319 stge_newbuf(struct stge_softc *sc, int idx, int waitok) 2320 { 2321 struct stge_rxdesc *rxd; 2322 struct stge_rfd *rfd; 2323 struct mbuf *m; 2324 bus_dma_segment_t seg; 2325 bus_dmamap_t map; 2326 int error, nseg; 2327 2328 m = m_getcl(waitok ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR); 2329 if (m == NULL) 2330 return ENOBUFS; 2331 m->m_len = m->m_pkthdr.len = MCLBYTES; 2332 2333 /* 2334 * The hardware requires 4bytes aligned DMA address when JUMBO 2335 * frame is used. 2336 */ 2337 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN)) 2338 m_adj(m, ETHER_ALIGN); 2339 2340 error = bus_dmamap_load_mbuf_segment(sc->sc_cdata.stge_rx_tag, 2341 sc->sc_cdata.stge_rx_sparemap, m, 2342 &seg, 1, &nseg, BUS_DMA_NOWAIT); 2343 if (error) { 2344 m_freem(m); 2345 return error; 2346 } 2347 2348 rxd = &sc->sc_cdata.stge_rxdesc[idx]; 2349 if (rxd->rx_m != NULL) { 2350 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap, 2351 BUS_DMASYNC_POSTREAD); 2352 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap); 2353 } 2354 2355 map = rxd->rx_dmamap; 2356 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap; 2357 sc->sc_cdata.stge_rx_sparemap = map; 2358 2359 rxd->rx_m = m; 2360 2361 rfd = &sc->sc_rdata.stge_rx_ring[idx]; 2362 rfd->rfd_frag.frag_word0 = 2363 htole64(FRAG_ADDR(seg.ds_addr) | FRAG_LEN(seg.ds_len)); 2364 rfd->rfd_status = 0; 2365 2366 return 0; 2367 } 2368 2369 /* 2370 * stge_set_filter: 2371 * 2372 * Set up the receive filter. 2373 */ 2374 static void 2375 stge_set_filter(struct stge_softc *sc) 2376 { 2377 struct ifnet *ifp = &sc->arpcom.ac_if; 2378 uint16_t mode; 2379 2380 mode = CSR_READ_2(sc, STGE_ReceiveMode); 2381 mode |= RM_ReceiveUnicast; 2382 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2383 mode |= RM_ReceiveBroadcast; 2384 else 2385 mode &= ~RM_ReceiveBroadcast; 2386 if ((ifp->if_flags & IFF_PROMISC) != 0) 2387 mode |= RM_ReceiveAllFrames; 2388 else 2389 mode &= ~RM_ReceiveAllFrames; 2390 2391 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2392 } 2393 2394 static void 2395 stge_set_multi(struct stge_softc *sc) 2396 { 2397 struct ifnet *ifp = &sc->arpcom.ac_if; 2398 struct ifmultiaddr *ifma; 2399 uint32_t crc; 2400 uint32_t mchash[2]; 2401 uint16_t mode; 2402 int count; 2403 2404 mode = CSR_READ_2(sc, STGE_ReceiveMode); 2405 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2406 if ((ifp->if_flags & IFF_PROMISC) != 0) 2407 mode |= RM_ReceiveAllFrames; 2408 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2409 mode |= RM_ReceiveMulticast; 2410 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2411 return; 2412 } 2413 2414 /* clear existing filters. */ 2415 CSR_WRITE_4(sc, STGE_HashTable0, 0); 2416 CSR_WRITE_4(sc, STGE_HashTable1, 0); 2417 2418 /* 2419 * Set up the multicast address filter by passing all multicast 2420 * addresses through a CRC generator, and then using the low-order 2421 * 6 bits as an index into the 64 bit multicast hash table. The 2422 * high order bits select the register, while the rest of the bits 2423 * select the bit within the register. 2424 */ 2425 2426 bzero(mchash, sizeof(mchash)); 2427 2428 count = 0; 2429 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2430 if (ifma->ifma_addr->sa_family != AF_LINK) 2431 continue; 2432 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 2433 ifma->ifma_addr), ETHER_ADDR_LEN); 2434 2435 /* Just want the 6 least significant bits. */ 2436 crc &= 0x3f; 2437 2438 /* Set the corresponding bit in the hash table. */ 2439 mchash[crc >> 5] |= 1 << (crc & 0x1f); 2440 count++; 2441 } 2442 2443 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames); 2444 if (count > 0) 2445 mode |= RM_ReceiveMulticastHash; 2446 else 2447 mode &= ~RM_ReceiveMulticastHash; 2448 2449 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]); 2450 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]); 2451 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2452 } 2453 2454 static int 2455 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS) 2456 { 2457 return (sysctl_int_range(oidp, arg1, arg2, req, 2458 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX)); 2459 } 2460 2461 static int 2462 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS) 2463 { 2464 return (sysctl_int_range(oidp, arg1, arg2, req, 2465 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX)); 2466 } 2467