1 /*- 2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/tx/if_tx.c,v 1.61.2.1 2002/10/29 01:43:49 semenu Exp $ 27 * $DragonFly: src/sys/dev/netif/tx/if_tx.c,v 1.13 2004/07/23 07:16:29 joerg Exp $ 28 */ 29 30 /* 31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie) 32 * 33 * These cards are based on SMC83c17x (EPIC) chip and one of the various 34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on 35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full- 36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also 37 * supports fibre optics. 38 * 39 * Thanks are going to Steve Bauer and Jason Wright. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/queue.h> 50 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 57 #include <net/bpf.h> 58 59 #include <net/vlan/if_vlan_var.h> 60 61 #include <vm/vm.h> /* for vtophys */ 62 #include <vm/pmap.h> /* for vtophys */ 63 #include <machine/bus_memio.h> 64 #include <machine/bus_pio.h> 65 #include <machine/bus.h> 66 #include <machine/resource.h> 67 #include <machine/clock.h> /* for DELAY */ 68 #include <sys/bus.h> 69 #include <sys/rman.h> 70 71 #include <bus/pci/pcireg.h> 72 #include <bus/pci/pcivar.h> 73 74 #include "../mii_layer/mii.h" 75 #include "../mii_layer/miivar.h" 76 #include "../mii_layer/miidevs.h" 77 #include "../mii_layer/lxtphyreg.h" 78 79 #include "miibus_if.h" 80 81 #include "if_txreg.h" 82 #include "if_txvar.h" 83 84 static int epic_ifioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 85 static void epic_intr(void *); 86 static void epic_tx_underrun(epic_softc_t *); 87 static int epic_common_attach(epic_softc_t *); 88 static void epic_ifstart(struct ifnet *); 89 static void epic_ifwatchdog(struct ifnet *); 90 static void epic_stats_update(epic_softc_t *); 91 static int epic_init(epic_softc_t *); 92 static void epic_stop(epic_softc_t *); 93 static void epic_rx_done(epic_softc_t *); 94 static void epic_tx_done(epic_softc_t *); 95 static int epic_init_rings(epic_softc_t *); 96 static void epic_free_rings(epic_softc_t *); 97 static void epic_stop_activity(epic_softc_t *); 98 static int epic_queue_last_packet(epic_softc_t *); 99 static void epic_start_activity(epic_softc_t *); 100 static void epic_set_rx_mode(epic_softc_t *); 101 static void epic_set_tx_mode(epic_softc_t *); 102 static void epic_set_mc_table(epic_softc_t *); 103 static u_int8_t epic_calchash(caddr_t); 104 static int epic_read_eeprom(epic_softc_t *,u_int16_t); 105 static void epic_output_eepromw(epic_softc_t *, u_int16_t); 106 static u_int16_t epic_input_eepromw(epic_softc_t *); 107 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t); 108 static void epic_write_eepromreg(epic_softc_t *,u_int8_t); 109 static u_int8_t epic_read_eepromreg(epic_softc_t *); 110 111 static int epic_read_phy_reg(epic_softc_t *, int, int); 112 static void epic_write_phy_reg(epic_softc_t *, int, int, int); 113 114 static int epic_miibus_readreg(device_t, int, int); 115 static int epic_miibus_writereg(device_t, int, int, int); 116 static void epic_miibus_statchg(device_t); 117 static void epic_miibus_mediainit(device_t); 118 119 static int epic_ifmedia_upd(struct ifnet *); 120 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *); 121 122 static int epic_probe(device_t); 123 static int epic_attach(device_t); 124 static void epic_shutdown(device_t); 125 static int epic_detach(device_t); 126 static struct epic_type *epic_devtype(device_t); 127 128 static device_method_t epic_methods[] = { 129 /* Device interface */ 130 DEVMETHOD(device_probe, epic_probe), 131 DEVMETHOD(device_attach, epic_attach), 132 DEVMETHOD(device_detach, epic_detach), 133 DEVMETHOD(device_shutdown, epic_shutdown), 134 135 /* MII interface */ 136 DEVMETHOD(miibus_readreg, epic_miibus_readreg), 137 DEVMETHOD(miibus_writereg, epic_miibus_writereg), 138 DEVMETHOD(miibus_statchg, epic_miibus_statchg), 139 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit), 140 141 { 0, 0 } 142 }; 143 144 static driver_t epic_driver = { 145 "tx", 146 epic_methods, 147 sizeof(epic_softc_t) 148 }; 149 150 static devclass_t epic_devclass; 151 152 DECLARE_DUMMY_MODULE(if_tx); 153 MODULE_DEPEND(if_tx, miibus, 1, 1, 1); 154 DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, 0, 0); 155 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0); 156 157 static struct epic_type epic_devs[] = { 158 { SMC_VENDORID, SMC_DEVICEID_83C170, 159 "SMC EtherPower II 10/100" }, 160 { 0, 0, NULL } 161 }; 162 163 static int 164 epic_probe(dev) 165 device_t dev; 166 { 167 struct epic_type *t; 168 169 t = epic_devtype(dev); 170 171 if (t != NULL) { 172 device_set_desc(dev, t->name); 173 return(0); 174 } 175 176 return(ENXIO); 177 } 178 179 static struct epic_type * 180 epic_devtype(dev) 181 device_t dev; 182 { 183 struct epic_type *t; 184 185 t = epic_devs; 186 187 while(t->name != NULL) { 188 if ((pci_get_vendor(dev) == t->ven_id) && 189 (pci_get_device(dev) == t->dev_id)) { 190 return(t); 191 } 192 t++; 193 } 194 return (NULL); 195 } 196 197 #if defined(EPIC_USEIOSPACE) 198 #define EPIC_RES SYS_RES_IOPORT 199 #define EPIC_RID PCIR_BASEIO 200 #else 201 #define EPIC_RES SYS_RES_MEMORY 202 #define EPIC_RID PCIR_BASEMEM 203 #endif 204 205 /* 206 * Attach routine: map registers, allocate softc, rings and descriptors. 207 * Reset to known state. 208 */ 209 static int 210 epic_attach(dev) 211 device_t dev; 212 { 213 struct ifnet *ifp; 214 epic_softc_t *sc; 215 u_int32_t command; 216 int unit, error; 217 int i, s, rid, tmp; 218 219 s = splimp (); 220 221 sc = device_get_softc(dev); 222 unit = device_get_unit(dev); 223 224 /* Preinitialize softc structure */ 225 bzero(sc, sizeof(epic_softc_t)); 226 sc->unit = unit; 227 sc->dev = dev; 228 229 /* Fill ifnet structure */ 230 ifp = &sc->sc_if; 231 if_initname(ifp, "tx", unit); 232 ifp->if_softc = sc; 233 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST; 234 ifp->if_ioctl = epic_ifioctl; 235 ifp->if_start = epic_ifstart; 236 ifp->if_watchdog = epic_ifwatchdog; 237 ifp->if_init = (if_init_f_t*)epic_init; 238 ifp->if_timer = 0; 239 ifp->if_baudrate = 10000000; 240 ifp->if_snd.ifq_maxlen = TX_RING_SIZE - 1; 241 242 /* Enable ports, memory and busmastering */ 243 command = pci_read_config(dev, PCIR_COMMAND, 4); 244 command |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 245 pci_write_config(dev, PCIR_COMMAND, command, 4); 246 command = pci_read_config(dev, PCIR_COMMAND, 4); 247 248 #if defined(EPIC_USEIOSPACE) 249 if ((command & PCIM_CMD_PORTEN) == 0) { 250 device_printf(dev, "failed to enable I/O mapping!\n"); 251 error = ENXIO; 252 goto fail; 253 } 254 #else 255 if ((command & PCIM_CMD_MEMEN) == 0) { 256 device_printf(dev, "failed to enable memory mapping!\n"); 257 error = ENXIO; 258 goto fail; 259 } 260 #endif 261 262 rid = EPIC_RID; 263 sc->res = bus_alloc_resource(dev, EPIC_RES, &rid, 0, ~0, 1, 264 RF_ACTIVE); 265 266 if (sc->res == NULL) { 267 device_printf(dev, "couldn't map ports/memory\n"); 268 error = ENXIO; 269 goto fail; 270 } 271 272 sc->sc_st = rman_get_bustag(sc->res); 273 sc->sc_sh = rman_get_bushandle(sc->res); 274 275 /* Allocate interrupt */ 276 rid = 0; 277 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 278 RF_SHAREABLE | RF_ACTIVE); 279 280 if (sc->irq == NULL) { 281 device_printf(dev, "couldn't map interrupt\n"); 282 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res); 283 error = ENXIO; 284 goto fail; 285 } 286 287 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 288 epic_intr, sc, &sc->sc_ih); 289 290 if (error) { 291 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 292 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res); 293 device_printf(dev, "couldn't set up irq\n"); 294 goto fail; 295 } 296 297 /* Do OS independent part, including chip wakeup and reset */ 298 error = epic_common_attach(sc); 299 if (error) { 300 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 301 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 302 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res); 303 error = ENXIO; 304 goto fail; 305 } 306 307 /* Do ifmedia setup */ 308 if (mii_phy_probe(dev, &sc->miibus, 309 epic_ifmedia_upd, epic_ifmedia_sts)) { 310 device_printf(dev, "ERROR! MII without any PHY!?\n"); 311 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 312 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 313 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res); 314 error = ENXIO; 315 goto fail; 316 } 317 318 /* board type and ... */ 319 printf(" type "); 320 for(i=0x2c;i<0x32;i++) { 321 tmp = epic_read_eeprom(sc, i); 322 if (' ' == (u_int8_t)tmp) break; 323 printf("%c", (u_int8_t)tmp); 324 tmp >>= 8; 325 if (' ' == (u_int8_t)tmp) break; 326 printf("%c", (u_int8_t)tmp); 327 } 328 printf("\n"); 329 330 /* Attach to OS's managers */ 331 ether_ifattach(ifp, sc->sc_macaddr); 332 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 333 callout_handle_init(&sc->stat_ch); 334 335 fail: 336 splx(s); 337 338 return(error); 339 } 340 341 /* 342 * Detach driver and free resources 343 */ 344 static int 345 epic_detach(dev) 346 device_t dev; 347 { 348 struct ifnet *ifp; 349 epic_softc_t *sc; 350 int s; 351 352 s = splimp(); 353 354 sc = device_get_softc(dev); 355 ifp = &sc->arpcom.ac_if; 356 357 ether_ifdetach(ifp); 358 359 epic_stop(sc); 360 361 bus_generic_detach(dev); 362 device_delete_child(dev, sc->miibus); 363 364 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 365 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 366 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res); 367 368 free(sc->tx_flist, M_DEVBUF); 369 free(sc->tx_desc, M_DEVBUF); 370 free(sc->rx_desc, M_DEVBUF); 371 372 splx(s); 373 374 return(0); 375 } 376 377 #undef EPIC_RES 378 #undef EPIC_RID 379 380 /* 381 * Stop all chip I/O so that the kernel's probe routines don't 382 * get confused by errant DMAs when rebooting. 383 */ 384 static void 385 epic_shutdown(dev) 386 device_t dev; 387 { 388 epic_softc_t *sc; 389 390 sc = device_get_softc(dev); 391 392 epic_stop(sc); 393 394 return; 395 } 396 397 /* 398 * This is if_ioctl handler. 399 */ 400 static int 401 epic_ifioctl(ifp, command, data, cr) 402 struct ifnet *ifp; 403 u_long command; 404 caddr_t data; 405 struct ucred *cr; 406 { 407 epic_softc_t *sc = ifp->if_softc; 408 struct mii_data *mii; 409 struct ifreq *ifr = (struct ifreq *) data; 410 int x, error = 0; 411 412 x = splimp(); 413 414 switch (command) { 415 case SIOCSIFADDR: 416 case SIOCGIFADDR: 417 error = ether_ioctl(ifp, command, data); 418 break; 419 case SIOCSIFMTU: 420 if (ifp->if_mtu == ifr->ifr_mtu) 421 break; 422 423 /* XXX Though the datasheet doesn't imply any 424 * limitations on RX and TX sizes beside max 64Kb 425 * DMA transfer, seems we can't send more then 1600 426 * data bytes per ethernet packet. (Transmitter hangs 427 * up if more data is sent) 428 */ 429 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) { 430 ifp->if_mtu = ifr->ifr_mtu; 431 epic_stop(sc); 432 epic_init(sc); 433 } else 434 error = EINVAL; 435 break; 436 437 case SIOCSIFFLAGS: 438 /* 439 * If the interface is marked up and stopped, then start it. 440 * If it is marked down and running, then stop it. 441 */ 442 if (ifp->if_flags & IFF_UP) { 443 if ((ifp->if_flags & IFF_RUNNING) == 0) { 444 epic_init(sc); 445 break; 446 } 447 } else { 448 if (ifp->if_flags & IFF_RUNNING) { 449 epic_stop(sc); 450 break; 451 } 452 } 453 454 /* Handle IFF_PROMISC and IFF_ALLMULTI flags */ 455 epic_stop_activity(sc); 456 epic_set_mc_table(sc); 457 epic_set_rx_mode(sc); 458 epic_start_activity(sc); 459 break; 460 461 case SIOCADDMULTI: 462 case SIOCDELMULTI: 463 epic_set_mc_table(sc); 464 error = 0; 465 break; 466 467 case SIOCSIFMEDIA: 468 case SIOCGIFMEDIA: 469 mii = device_get_softc(sc->miibus); 470 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 471 break; 472 473 default: 474 error = EINVAL; 475 } 476 splx(x); 477 478 return error; 479 } 480 481 /* 482 * OS-independed part of attach process. allocate memory for descriptors 483 * and frag lists, wake up chip, read MAC address and PHY identyfier. 484 * Return -1 on failure. 485 */ 486 static int 487 epic_common_attach(sc) 488 epic_softc_t *sc; 489 { 490 int i; 491 492 sc->tx_flist = malloc(sizeof(struct epic_frag_list)*TX_RING_SIZE, 493 M_DEVBUF, M_WAITOK | M_ZERO); 494 sc->tx_desc = malloc(sizeof(struct epic_tx_desc)*TX_RING_SIZE, 495 M_DEVBUF, M_WAITOK | M_ZERO); 496 sc->rx_desc = malloc(sizeof(struct epic_rx_desc)*RX_RING_SIZE, 497 M_DEVBUF, M_WAITOK | M_ZERO); 498 499 /* Bring the chip out of low-power mode. */ 500 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 501 DELAY(500); 502 503 /* Workaround for Application Note 7-15 */ 504 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST); 505 506 /* Read mac address from EEPROM */ 507 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++) 508 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i); 509 510 /* Set Non-Volatile Control Register from EEPROM */ 511 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F); 512 513 /* Set defaults */ 514 sc->tx_threshold = TRANSMIT_THRESHOLD; 515 sc->txcon = TXCON_DEFAULT; 516 sc->miicfg = MIICFG_SMI_ENABLE; 517 sc->phyid = EPIC_UNKN_PHY; 518 sc->serinst = -1; 519 520 /* Fetch card id */ 521 sc->cardvend = pci_read_config(sc->dev, PCIR_SUBVEND_0, 2); 522 sc->cardid = pci_read_config(sc->dev, PCIR_SUBDEV_0, 2); 523 524 if (sc->cardvend != SMC_VENDORID) 525 device_printf(sc->dev, "unknown card vendor %04xh\n", sc->cardvend); 526 527 return 0; 528 } 529 530 /* 531 * This is if_start handler. It takes mbufs from if_snd queue 532 * and queue them for transmit, one by one, until TX ring become full 533 * or queue become empty. 534 */ 535 static void 536 epic_ifstart(ifp) 537 struct ifnet * ifp; 538 { 539 epic_softc_t *sc = ifp->if_softc; 540 struct epic_tx_buffer *buf; 541 struct epic_tx_desc *desc; 542 struct epic_frag_list *flist; 543 struct mbuf *m0; 544 struct mbuf *m; 545 int i; 546 547 while (sc->pending_txs < TX_RING_SIZE) { 548 buf = sc->tx_buffer + sc->cur_tx; 549 desc = sc->tx_desc + sc->cur_tx; 550 flist = sc->tx_flist + sc->cur_tx; 551 552 /* Get next packet to send */ 553 IF_DEQUEUE(&ifp->if_snd, m0); 554 555 /* If nothing to send, return */ 556 if (NULL == m0) return; 557 558 /* Fill fragments list */ 559 for (m = m0, i = 0; 560 (NULL != m) && (i < EPIC_MAX_FRAGS); 561 m = m->m_next, i++) { 562 flist->frag[i].fraglen = m->m_len; 563 flist->frag[i].fragaddr = vtophys(mtod(m, caddr_t)); 564 } 565 flist->numfrags = i; 566 567 /* If packet was more than EPIC_MAX_FRAGS parts, */ 568 /* recopy packet to new allocated mbuf cluster */ 569 if (NULL != m) { 570 EPIC_MGETCLUSTER(m); 571 if (NULL == m) { 572 m_freem(m0); 573 ifp->if_oerrors++; 574 continue; 575 } 576 577 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 578 flist->frag[0].fraglen = 579 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 580 m->m_pkthdr.rcvif = ifp; 581 582 flist->numfrags = 1; 583 flist->frag[0].fragaddr = vtophys(mtod(m, caddr_t)); 584 m_freem(m0); 585 m0 = m; 586 } 587 588 buf->mbuf = m0; 589 sc->pending_txs++; 590 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK; 591 desc->control = 0x01; 592 desc->txlength = 593 max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN); 594 desc->status = 0x8000; 595 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED); 596 597 /* Set watchdog timer */ 598 ifp->if_timer = 8; 599 600 if (ifp->if_bpf) 601 bpf_mtap(ifp, m0); 602 } 603 604 ifp->if_flags |= IFF_OACTIVE; 605 606 return; 607 608 } 609 610 /* 611 * Synopsis: Finish all received frames. 612 */ 613 static void 614 epic_rx_done(sc) 615 epic_softc_t *sc; 616 { 617 u_int16_t len; 618 struct ifnet *ifp = &sc->sc_if; 619 struct epic_rx_buffer *buf; 620 struct epic_rx_desc *desc; 621 struct mbuf *m; 622 623 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) { 624 buf = sc->rx_buffer + sc->cur_rx; 625 desc = sc->rx_desc + sc->cur_rx; 626 627 /* Switch to next descriptor */ 628 sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK; 629 630 /* 631 * Check for RX errors. This should only happen if 632 * SAVE_ERRORED_PACKETS is set. RX errors generate 633 * RXE interrupt usually. 634 */ 635 if ((desc->status & 1) == 0) { 636 sc->sc_if.if_ierrors++; 637 desc->status = 0x8000; 638 continue; 639 } 640 641 /* Save packet length and mbuf contained packet */ 642 len = desc->rxlength - ETHER_CRC_LEN; 643 m = buf->mbuf; 644 645 /* Try to get mbuf cluster */ 646 EPIC_MGETCLUSTER(buf->mbuf); 647 if (NULL == buf->mbuf) { 648 buf->mbuf = m; 649 desc->status = 0x8000; 650 ifp->if_ierrors++; 651 continue; 652 } 653 654 /* Point to new mbuf, and give descriptor to chip */ 655 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t)); 656 desc->status = 0x8000; 657 658 /* First mbuf in packet holds the ethernet and packet headers */ 659 m->m_pkthdr.rcvif = ifp; 660 m->m_pkthdr.len = m->m_len = len; 661 662 /* Give mbuf to OS */ 663 (*ifp->if_input)(ifp, m); 664 665 /* Successfuly received frame */ 666 ifp->if_ipackets++; 667 } 668 669 return; 670 } 671 672 /* 673 * Synopsis: Do last phase of transmission. I.e. if desc is 674 * transmitted, decrease pending_txs counter, free mbuf contained 675 * packet, switch to next descriptor and repeat until no packets 676 * are pending or descriptor is not transmitted yet. 677 */ 678 static void 679 epic_tx_done(sc) 680 epic_softc_t *sc; 681 { 682 struct epic_tx_buffer *buf; 683 struct epic_tx_desc *desc; 684 u_int16_t status; 685 686 while (sc->pending_txs > 0) { 687 buf = sc->tx_buffer + sc->dirty_tx; 688 desc = sc->tx_desc + sc->dirty_tx; 689 status = desc->status; 690 691 /* If packet is not transmitted, thou followed */ 692 /* packets are not transmitted too */ 693 if (status & 0x8000) break; 694 695 /* Packet is transmitted. Switch to next and */ 696 /* free mbuf */ 697 sc->pending_txs--; 698 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK; 699 m_freem(buf->mbuf); 700 buf->mbuf = NULL; 701 702 /* Check for errors and collisions */ 703 if (status & 0x0001) sc->sc_if.if_opackets++; 704 else sc->sc_if.if_oerrors++; 705 sc->sc_if.if_collisions += (status >> 8) & 0x1F; 706 #if defined(EPIC_DIAG) 707 if ((status & 0x1001) == 0x1001) 708 device_printf(sc->dev, "Tx ERROR: excessive coll. number\n"); 709 #endif 710 } 711 712 if (sc->pending_txs < TX_RING_SIZE) 713 sc->sc_if.if_flags &= ~IFF_OACTIVE; 714 } 715 716 /* 717 * Interrupt function 718 */ 719 static void 720 epic_intr(arg) 721 void *arg; 722 { 723 epic_softc_t * sc = (epic_softc_t *) arg; 724 int status, i = 4; 725 726 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) { 727 CSR_WRITE_4(sc, INTSTAT, status); 728 729 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) { 730 epic_rx_done(sc); 731 if (status & (INTSTAT_RQE|INTSTAT_OVW)) { 732 #if defined(EPIC_DIAG) 733 if (status & INTSTAT_OVW) 734 device_printf(sc->dev, "RX buffer overflow\n"); 735 if (status & INTSTAT_RQE) 736 device_printf(sc->dev, "RX FIFO overflow\n"); 737 #endif 738 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0) 739 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED); 740 sc->sc_if.if_ierrors++; 741 } 742 } 743 744 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) { 745 epic_tx_done(sc); 746 if (sc->sc_if.if_snd.ifq_head != NULL) 747 epic_ifstart(&sc->sc_if); 748 } 749 750 /* Check for rare errors */ 751 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA| 752 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) { 753 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA| 754 INTSTAT_APE|INTSTAT_DPE)) { 755 device_printf(sc->dev, "PCI fatal errors occured: %s%s%s%s\n", 756 (status&INTSTAT_PMA)?"PMA ":"", 757 (status&INTSTAT_PTA)?"PTA ":"", 758 (status&INTSTAT_APE)?"APE ":"", 759 (status&INTSTAT_DPE)?"DPE":"" 760 ); 761 762 epic_stop(sc); 763 epic_init(sc); 764 765 break; 766 } 767 768 if (status & INTSTAT_RXE) { 769 #if defined(EPIC_DIAG) 770 device_printf(sc->dev, "CRC/Alignment error\n"); 771 #endif 772 sc->sc_if.if_ierrors++; 773 } 774 775 if (status & INTSTAT_TXU) { 776 epic_tx_underrun(sc); 777 sc->sc_if.if_oerrors++; 778 } 779 } 780 } 781 782 /* If no packets are pending, then no timeouts */ 783 if (sc->pending_txs == 0) sc->sc_if.if_timer = 0; 784 785 return; 786 } 787 788 /* 789 * Handle the TX underrun error: increase the TX threshold 790 * and restart the transmitter. 791 */ 792 static void 793 epic_tx_underrun(sc) 794 epic_softc_t *sc; 795 { 796 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) { 797 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE; 798 #if defined(EPIC_DIAG) 799 device_printf(sc->dev, "Tx UNDERRUN: early TX disabled\n"); 800 #endif 801 } else { 802 sc->tx_threshold += 0x40; 803 #if defined(EPIC_DIAG) 804 device_printf(sc->dev, "Tx UNDERRUN: TX threshold increased to %d\n", 805 sc->tx_threshold); 806 #endif 807 } 808 809 /* We must set TXUGO to reset the stuck transmitter */ 810 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO); 811 812 /* Update the TX threshold */ 813 epic_stop_activity(sc); 814 epic_set_tx_mode(sc); 815 epic_start_activity(sc); 816 817 return; 818 } 819 820 /* 821 * Synopsis: This one is called if packets wasn't transmitted 822 * during timeout. Try to deallocate transmitted packets, and 823 * if success continue to work. 824 */ 825 static void 826 epic_ifwatchdog(ifp) 827 struct ifnet *ifp; 828 { 829 epic_softc_t *sc = ifp->if_softc; 830 int x; 831 832 x = splimp(); 833 834 device_printf(sc->dev, "device timeout %d packets\n", sc->pending_txs); 835 836 /* Try to finish queued packets */ 837 epic_tx_done(sc); 838 839 /* If not successful */ 840 if (sc->pending_txs > 0) { 841 842 ifp->if_oerrors+=sc->pending_txs; 843 844 /* Reinitialize board */ 845 device_printf(sc->dev, "reinitialization\n"); 846 epic_stop(sc); 847 epic_init(sc); 848 849 } else 850 device_printf(sc->dev, "seems we can continue normaly\n"); 851 852 /* Start output */ 853 if (ifp->if_snd.ifq_head) epic_ifstart(ifp); 854 855 splx(x); 856 } 857 858 /* 859 * Despite the name of this function, it doesn't update statistics, it only 860 * helps in autonegotiation process. 861 */ 862 static void 863 epic_stats_update(epic_softc_t * sc) 864 { 865 struct mii_data * mii; 866 int s; 867 868 s = splimp(); 869 870 mii = device_get_softc(sc->miibus); 871 mii_tick(mii); 872 873 sc->stat_ch = timeout((timeout_t *)epic_stats_update, sc, hz); 874 875 splx(s); 876 } 877 878 /* 879 * Set media options. 880 */ 881 static int 882 epic_ifmedia_upd(ifp) 883 struct ifnet *ifp; 884 { 885 epic_softc_t *sc; 886 struct mii_data *mii; 887 struct ifmedia *ifm; 888 struct mii_softc *miisc; 889 int cfg, media; 890 891 sc = ifp->if_softc; 892 mii = device_get_softc(sc->miibus); 893 ifm = &mii->mii_media; 894 media = ifm->ifm_cur->ifm_media; 895 896 /* Do not do anything if interface is not up */ 897 if ((ifp->if_flags & IFF_UP) == 0) 898 return (0); 899 900 /* 901 * Lookup current selected PHY 902 */ 903 if (IFM_INST(media) == sc->serinst) { 904 sc->phyid = EPIC_SERIAL; 905 sc->physc = NULL; 906 } else { 907 /* If we're not selecting serial interface, select MII mode */ 908 sc->miicfg &= ~MIICFG_SERIAL_ENABLE; 909 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 910 911 /* Default to unknown PHY */ 912 sc->phyid = EPIC_UNKN_PHY; 913 914 /* Lookup selected PHY */ 915 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 916 miisc = LIST_NEXT(miisc, mii_list)) { 917 if (IFM_INST(media) == miisc->mii_inst) { 918 sc->physc = miisc; 919 break; 920 } 921 } 922 923 /* Identify selected PHY */ 924 if (sc->physc) { 925 int id1, id2, model, oui; 926 927 id1 = PHY_READ(sc->physc, MII_PHYIDR1); 928 id2 = PHY_READ(sc->physc, MII_PHYIDR2); 929 930 oui = MII_OUI(id1, id2); 931 model = MII_MODEL(id2); 932 switch (oui) { 933 case MII_OUI_QUALSEMI: 934 if (model == MII_MODEL_QUALSEMI_QS6612) 935 sc->phyid = EPIC_QS6612_PHY; 936 break; 937 case MII_OUI_xxALTIMA: 938 if (model == MII_MODEL_xxALTIMA_AC101) 939 sc->phyid = EPIC_AC101_PHY; 940 break; 941 case MII_OUI_xxLEVEL1: 942 if (model == MII_MODEL_xxLEVEL1_LXT970) 943 sc->phyid = EPIC_LXT970_PHY; 944 break; 945 } 946 } 947 } 948 949 /* 950 * Do PHY specific card setup 951 */ 952 953 /* Call this, to isolate all not selected PHYs and 954 * set up selected 955 */ 956 mii_mediachg(mii); 957 958 /* Do our own setup */ 959 switch (sc->phyid) { 960 case EPIC_QS6612_PHY: 961 break; 962 case EPIC_AC101_PHY: 963 /* We have to powerup fiber tranceivers */ 964 if (IFM_SUBTYPE(media) == IFM_100_FX) 965 sc->miicfg |= MIICFG_694_ENABLE; 966 else 967 sc->miicfg &= ~MIICFG_694_ENABLE; 968 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 969 970 break; 971 case EPIC_LXT970_PHY: 972 /* We have to powerup fiber tranceivers */ 973 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG); 974 if (IFM_SUBTYPE(media) == IFM_100_FX) 975 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0; 976 else 977 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 978 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg); 979 980 break; 981 case EPIC_SERIAL: 982 /* Select serial PHY, (10base2/BNC usually) */ 983 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE; 984 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 985 986 /* There is no driver to fill this */ 987 mii->mii_media_active = media; 988 mii->mii_media_status = 0; 989 990 /* We need to call this manualy as i wasn't called 991 * in mii_mediachg() 992 */ 993 epic_miibus_statchg(sc->dev); 994 995 break; 996 default: 997 device_printf(sc->dev, "ERROR! Unknown PHY selected\n"); 998 return (EINVAL); 999 } 1000 1001 return(0); 1002 } 1003 1004 /* 1005 * Report current media status. 1006 */ 1007 static void 1008 epic_ifmedia_sts(ifp, ifmr) 1009 struct ifnet *ifp; 1010 struct ifmediareq *ifmr; 1011 { 1012 epic_softc_t *sc; 1013 struct mii_data *mii; 1014 struct ifmedia *ifm; 1015 1016 sc = ifp->if_softc; 1017 mii = device_get_softc(sc->miibus); 1018 ifm = &mii->mii_media; 1019 1020 /* Nothing should be selected if interface is down */ 1021 if ((ifp->if_flags & IFF_UP) == 0) { 1022 ifmr->ifm_active = IFM_NONE; 1023 ifmr->ifm_status = 0; 1024 1025 return; 1026 } 1027 1028 /* Call underlying pollstat, if not serial PHY */ 1029 if (sc->phyid != EPIC_SERIAL) 1030 mii_pollstat(mii); 1031 1032 /* Simply copy media info */ 1033 ifmr->ifm_active = mii->mii_media_active; 1034 ifmr->ifm_status = mii->mii_media_status; 1035 1036 return; 1037 } 1038 1039 /* 1040 * Callback routine, called on media change. 1041 */ 1042 static void 1043 epic_miibus_statchg(dev) 1044 device_t dev; 1045 { 1046 epic_softc_t *sc; 1047 struct mii_data *mii; 1048 int media; 1049 1050 sc = device_get_softc(dev); 1051 mii = device_get_softc(sc->miibus); 1052 media = mii->mii_media_active; 1053 1054 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX); 1055 1056 /* If we are in full-duplex mode or loopback operation, 1057 * we need to decouple receiver and transmitter. 1058 */ 1059 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP)) 1060 sc->txcon |= TXCON_FULL_DUPLEX; 1061 1062 /* On some cards we need manualy set fullduplex led */ 1063 if (sc->cardid == SMC9432FTX || 1064 sc->cardid == SMC9432FTX_SC) { 1065 if (IFM_OPTIONS(media) & IFM_FDX) 1066 sc->miicfg |= MIICFG_694_ENABLE; 1067 else 1068 sc->miicfg &= ~MIICFG_694_ENABLE; 1069 1070 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 1071 } 1072 1073 /* Update baudrate */ 1074 if (IFM_SUBTYPE(media) == IFM_100_TX || 1075 IFM_SUBTYPE(media) == IFM_100_FX) 1076 sc->sc_if.if_baudrate = 100000000; 1077 else 1078 sc->sc_if.if_baudrate = 10000000; 1079 1080 epic_stop_activity(sc); 1081 epic_set_tx_mode(sc); 1082 epic_start_activity(sc); 1083 1084 return; 1085 } 1086 1087 static void 1088 epic_miibus_mediainit(dev) 1089 device_t dev; 1090 { 1091 epic_softc_t *sc; 1092 struct mii_data *mii; 1093 struct ifmedia *ifm; 1094 int media; 1095 1096 sc = device_get_softc(dev); 1097 mii = device_get_softc(sc->miibus); 1098 ifm = &mii->mii_media; 1099 1100 /* Add Serial Media Interface if present, this applies to 1101 * SMC9432BTX serie 1102 */ 1103 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) { 1104 /* Store its instance */ 1105 sc->serinst = mii->mii_instance++; 1106 1107 /* Add as 10base2/BNC media */ 1108 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst); 1109 ifmedia_add(ifm, media, 0, NULL); 1110 1111 /* Report to user */ 1112 device_printf(sc->dev, "serial PHY detected (10Base2/BNC)\n"); 1113 } 1114 1115 return; 1116 } 1117 1118 /* 1119 * Reset chip, allocate rings, and update media. 1120 */ 1121 static int 1122 epic_init(sc) 1123 epic_softc_t *sc; 1124 { 1125 struct ifnet *ifp = &sc->sc_if; 1126 int s,i; 1127 1128 s = splimp(); 1129 1130 /* If interface is already running, then we need not do anything */ 1131 if (ifp->if_flags & IFF_RUNNING) { 1132 splx(s); 1133 return 0; 1134 } 1135 1136 /* Soft reset the chip (we have to power up card before) */ 1137 CSR_WRITE_4(sc, GENCTL, 0); 1138 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 1139 1140 /* 1141 * Reset takes 15 pci ticks which depends on PCI bus speed. 1142 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec. 1143 */ 1144 DELAY(500); 1145 1146 /* Wake up */ 1147 CSR_WRITE_4(sc, GENCTL, 0); 1148 1149 /* Workaround for Application Note 7-15 */ 1150 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST); 1151 1152 /* Initialize rings */ 1153 if (epic_init_rings(sc)) { 1154 device_printf(sc->dev, "failed to init rings\n"); 1155 splx(s); 1156 return -1; 1157 } 1158 1159 /* Give rings to EPIC */ 1160 CSR_WRITE_4(sc, PRCDAR, vtophys(sc->rx_desc)); 1161 CSR_WRITE_4(sc, PTCDAR, vtophys(sc->tx_desc)); 1162 1163 /* Put node address to EPIC */ 1164 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]); 1165 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]); 1166 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]); 1167 1168 /* Set tx mode, includeing transmit threshold */ 1169 epic_set_tx_mode(sc); 1170 1171 /* Compute and set RXCON. */ 1172 epic_set_rx_mode(sc); 1173 1174 /* Set multicast table */ 1175 epic_set_mc_table(sc); 1176 1177 /* Enable interrupts by setting the interrupt mask. */ 1178 CSR_WRITE_4(sc, INTMASK, 1179 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */ 1180 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU | 1181 INTSTAT_FATAL); 1182 1183 /* Acknowledge all pending interrupts */ 1184 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT)); 1185 1186 /* Enable interrupts, set for PCI read multiple and etc */ 1187 CSR_WRITE_4(sc, GENCTL, 1188 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE | 1189 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64); 1190 1191 /* Mark interface running ... */ 1192 if (ifp->if_flags & IFF_UP) ifp->if_flags |= IFF_RUNNING; 1193 else ifp->if_flags &= ~IFF_RUNNING; 1194 1195 /* ... and free */ 1196 ifp->if_flags &= ~IFF_OACTIVE; 1197 1198 /* Start Rx process */ 1199 epic_start_activity(sc); 1200 1201 /* Set appropriate media */ 1202 epic_ifmedia_upd(ifp); 1203 1204 sc->stat_ch = timeout((timeout_t *)epic_stats_update, sc, hz); 1205 1206 splx(s); 1207 1208 return 0; 1209 } 1210 1211 /* 1212 * Synopsis: calculate and set Rx mode. Chip must be in idle state to 1213 * access RXCON. 1214 */ 1215 static void 1216 epic_set_rx_mode(sc) 1217 epic_softc_t *sc; 1218 { 1219 u_int32_t flags = sc->sc_if.if_flags; 1220 u_int32_t rxcon = RXCON_DEFAULT; 1221 1222 #if defined(EPIC_EARLY_RX) 1223 rxcon |= RXCON_EARLY_RX; 1224 #endif 1225 1226 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0; 1227 1228 CSR_WRITE_4(sc, RXCON, rxcon); 1229 1230 return; 1231 } 1232 1233 /* 1234 * Synopsis: Set transmit control register. Chip must be in idle state to 1235 * access TXCON. 1236 */ 1237 static void 1238 epic_set_tx_mode(sc) 1239 epic_softc_t *sc; 1240 { 1241 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE) 1242 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold); 1243 1244 CSR_WRITE_4(sc, TXCON, sc->txcon); 1245 } 1246 1247 /* 1248 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC 1249 * flags. (Note, that setting PROMISC bit in EPIC's RXCON will only touch 1250 * individual frames, multicast filter must be manually programmed) 1251 * 1252 * Note: EPIC must be in idle state. 1253 */ 1254 static void 1255 epic_set_mc_table(sc) 1256 epic_softc_t *sc; 1257 { 1258 struct ifnet *ifp = &sc->sc_if; 1259 struct ifmultiaddr *ifma; 1260 u_int16_t filter[4]; 1261 u_int8_t h; 1262 1263 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 1264 CSR_WRITE_4(sc, MC0, 0xFFFF); 1265 CSR_WRITE_4(sc, MC1, 0xFFFF); 1266 CSR_WRITE_4(sc, MC2, 0xFFFF); 1267 CSR_WRITE_4(sc, MC3, 0xFFFF); 1268 1269 return; 1270 } 1271 1272 filter[0] = 0; 1273 filter[1] = 0; 1274 filter[2] = 0; 1275 filter[3] = 0; 1276 1277 #if defined(__DragonFly__) || __FreeBSD_version < 500000 1278 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1279 #else 1280 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1281 #endif 1282 if (ifma->ifma_addr->sa_family != AF_LINK) 1283 continue; 1284 h = epic_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1285 filter[h >> 4] |= 1 << (h & 0xF); 1286 } 1287 1288 CSR_WRITE_4(sc, MC0, filter[0]); 1289 CSR_WRITE_4(sc, MC1, filter[1]); 1290 CSR_WRITE_4(sc, MC2, filter[2]); 1291 CSR_WRITE_4(sc, MC3, filter[3]); 1292 1293 return; 1294 } 1295 1296 /* 1297 * Synopsis: calculate EPIC's hash of multicast address. 1298 */ 1299 static u_int8_t 1300 epic_calchash(addr) 1301 caddr_t addr; 1302 { 1303 u_int32_t crc, carry; 1304 int i, j; 1305 u_int8_t c; 1306 1307 /* Compute CRC for the address value. */ 1308 crc = 0xFFFFFFFF; /* initial value */ 1309 1310 for (i = 0; i < 6; i++) { 1311 c = *(addr + i); 1312 for (j = 0; j < 8; j++) { 1313 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1314 crc <<= 1; 1315 c >>= 1; 1316 if (carry) 1317 crc = (crc ^ 0x04c11db6) | carry; 1318 } 1319 } 1320 1321 return ((crc >> 26) & 0x3F); 1322 } 1323 1324 1325 /* 1326 * Synopsis: Start receive process and transmit one, if they need. 1327 */ 1328 static void 1329 epic_start_activity(sc) 1330 epic_softc_t *sc; 1331 { 1332 /* Start rx process */ 1333 CSR_WRITE_4(sc, COMMAND, 1334 COMMAND_RXQUEUED | COMMAND_START_RX | 1335 (sc->pending_txs?COMMAND_TXQUEUED:0)); 1336 } 1337 1338 /* 1339 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional 1340 * packet needs to be queued to stop Tx DMA. 1341 */ 1342 static void 1343 epic_stop_activity(sc) 1344 epic_softc_t *sc; 1345 { 1346 int status, i; 1347 1348 /* Stop Tx and Rx DMA */ 1349 CSR_WRITE_4(sc, COMMAND, 1350 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA); 1351 1352 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */ 1353 for (i=0; i<0x1000; i++) { 1354 status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE); 1355 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE)) 1356 break; 1357 DELAY(1); 1358 } 1359 1360 /* Catch all finished packets */ 1361 epic_rx_done(sc); 1362 epic_tx_done(sc); 1363 1364 status = CSR_READ_4(sc, INTSTAT); 1365 1366 if ((status & INTSTAT_RXIDLE) == 0) 1367 device_printf(sc->dev, "ERROR! Can't stop Rx DMA\n"); 1368 1369 if ((status & INTSTAT_TXIDLE) == 0) 1370 device_printf(sc->dev, "ERROR! Can't stop Tx DMA\n"); 1371 1372 /* 1373 * May need to queue one more packet if TQE, this is rare 1374 * but existing case. 1375 */ 1376 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE)) 1377 (void) epic_queue_last_packet(sc); 1378 1379 } 1380 1381 /* 1382 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until 1383 * a packet from current descriptor will be copied to internal RAM. We 1384 * compose a dummy packet here and queue it for transmission. 1385 * 1386 * XXX the packet will then be actually sent over network... 1387 */ 1388 static int 1389 epic_queue_last_packet(sc) 1390 epic_softc_t *sc; 1391 { 1392 struct epic_tx_desc *desc; 1393 struct epic_frag_list *flist; 1394 struct epic_tx_buffer *buf; 1395 struct mbuf *m0; 1396 int i; 1397 1398 device_printf(sc->dev, "queue last packet\n"); 1399 1400 desc = sc->tx_desc + sc->cur_tx; 1401 flist = sc->tx_flist + sc->cur_tx; 1402 buf = sc->tx_buffer + sc->cur_tx; 1403 1404 if ((desc->status & 0x8000) || (buf->mbuf != NULL)) 1405 return (EBUSY); 1406 1407 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 1408 if (NULL == m0) 1409 return (ENOBUFS); 1410 1411 /* Prepare mbuf */ 1412 m0->m_len = min(MHLEN, ETHER_MIN_LEN-ETHER_CRC_LEN); 1413 flist->frag[0].fraglen = m0->m_len; 1414 m0->m_pkthdr.len = m0->m_len; 1415 m0->m_pkthdr.rcvif = &sc->sc_if; 1416 bzero(mtod(m0,caddr_t), m0->m_len); 1417 1418 /* Fill fragments list */ 1419 flist->frag[0].fraglen = m0->m_len; 1420 flist->frag[0].fragaddr = vtophys(mtod(m0, caddr_t)); 1421 flist->numfrags = 1; 1422 1423 /* Fill in descriptor */ 1424 buf->mbuf = m0; 1425 sc->pending_txs++; 1426 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK; 1427 desc->control = 0x01; 1428 desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN); 1429 desc->status = 0x8000; 1430 1431 /* Launch transmition */ 1432 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED); 1433 1434 /* Wait Tx DMA to stop (for how long??? XXX) */ 1435 for (i=0; i<1000; i++) { 1436 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) 1437 break; 1438 DELAY(1); 1439 } 1440 1441 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0) 1442 device_printf(sc->dev, "ERROR! can't stop Tx DMA (2)\n"); 1443 else 1444 epic_tx_done(sc); 1445 1446 return 0; 1447 } 1448 1449 /* 1450 * Synopsis: Shut down board and deallocates rings. 1451 */ 1452 static void 1453 epic_stop(sc) 1454 epic_softc_t *sc; 1455 { 1456 int s; 1457 1458 s = splimp(); 1459 1460 sc->sc_if.if_timer = 0; 1461 1462 untimeout((timeout_t *)epic_stats_update, sc, sc->stat_ch); 1463 1464 /* Disable interrupts */ 1465 CSR_WRITE_4(sc, INTMASK, 0); 1466 CSR_WRITE_4(sc, GENCTL, 0); 1467 1468 /* Try to stop Rx and TX processes */ 1469 epic_stop_activity(sc); 1470 1471 /* Reset chip */ 1472 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 1473 DELAY(1000); 1474 1475 /* Make chip go to bed */ 1476 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN); 1477 1478 /* Free memory allocated for rings */ 1479 epic_free_rings(sc); 1480 1481 /* Mark as stoped */ 1482 sc->sc_if.if_flags &= ~IFF_RUNNING; 1483 1484 splx(s); 1485 return; 1486 } 1487 1488 /* 1489 * Synopsis: This function should free all memory allocated for rings. 1490 */ 1491 static void 1492 epic_free_rings(sc) 1493 epic_softc_t *sc; 1494 { 1495 int i; 1496 1497 for (i=0; i<RX_RING_SIZE; i++) { 1498 struct epic_rx_buffer *buf = sc->rx_buffer + i; 1499 struct epic_rx_desc *desc = sc->rx_desc + i; 1500 1501 desc->status = 0; 1502 desc->buflength = 0; 1503 desc->bufaddr = 0; 1504 1505 if (buf->mbuf) m_freem(buf->mbuf); 1506 buf->mbuf = NULL; 1507 } 1508 1509 for (i=0; i<TX_RING_SIZE; i++) { 1510 struct epic_tx_buffer *buf = sc->tx_buffer + i; 1511 struct epic_tx_desc *desc = sc->tx_desc + i; 1512 1513 desc->status = 0; 1514 desc->buflength = 0; 1515 desc->bufaddr = 0; 1516 1517 if (buf->mbuf) m_freem(buf->mbuf); 1518 buf->mbuf = NULL; 1519 } 1520 } 1521 1522 /* 1523 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them. 1524 * Point Tx descs to fragment lists. Check that all descs and fraglists 1525 * are bounded and aligned properly. 1526 */ 1527 static int 1528 epic_init_rings(sc) 1529 epic_softc_t *sc; 1530 { 1531 int i; 1532 1533 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0; 1534 1535 for (i = 0; i < RX_RING_SIZE; i++) { 1536 struct epic_rx_buffer *buf = sc->rx_buffer + i; 1537 struct epic_rx_desc *desc = sc->rx_desc + i; 1538 1539 desc->status = 0; /* Owned by driver */ 1540 desc->next = vtophys(sc->rx_desc + ((i+1) & RX_RING_MASK)); 1541 1542 if ((desc->next & 3) || 1543 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) { 1544 epic_free_rings(sc); 1545 return EFAULT; 1546 } 1547 1548 EPIC_MGETCLUSTER(buf->mbuf); 1549 if (NULL == buf->mbuf) { 1550 epic_free_rings(sc); 1551 return ENOBUFS; 1552 } 1553 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t)); 1554 1555 desc->buflength = MCLBYTES; /* Max RX buffer length */ 1556 desc->status = 0x8000; /* Set owner bit to NIC */ 1557 } 1558 1559 for (i = 0; i < TX_RING_SIZE; i++) { 1560 struct epic_tx_buffer *buf = sc->tx_buffer + i; 1561 struct epic_tx_desc *desc = sc->tx_desc + i; 1562 1563 desc->status = 0; 1564 desc->next = vtophys(sc->tx_desc + ((i+1) & TX_RING_MASK)); 1565 1566 if ((desc->next & 3) || 1567 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) { 1568 epic_free_rings(sc); 1569 return EFAULT; 1570 } 1571 1572 buf->mbuf = NULL; 1573 desc->bufaddr = vtophys(sc->tx_flist + i); 1574 1575 if ((desc->bufaddr & 3) || 1576 ((desc->bufaddr & PAGE_MASK) + sizeof(struct epic_frag_list)) > PAGE_SIZE) { 1577 epic_free_rings(sc); 1578 return EFAULT; 1579 } 1580 } 1581 1582 return 0; 1583 } 1584 1585 /* 1586 * EEPROM operation functions 1587 */ 1588 static void 1589 epic_write_eepromreg(sc, val) 1590 epic_softc_t *sc; 1591 u_int8_t val; 1592 { 1593 u_int16_t i; 1594 1595 CSR_WRITE_1(sc, EECTL, val); 1596 1597 for (i=0; i<0xFF; i++) 1598 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) break; 1599 1600 return; 1601 } 1602 1603 static u_int8_t 1604 epic_read_eepromreg(sc) 1605 epic_softc_t *sc; 1606 { 1607 return CSR_READ_1(sc, EECTL); 1608 } 1609 1610 static u_int8_t 1611 epic_eeprom_clock(sc, val) 1612 epic_softc_t *sc; 1613 u_int8_t val; 1614 { 1615 epic_write_eepromreg(sc, val); 1616 epic_write_eepromreg(sc, (val | 0x4)); 1617 epic_write_eepromreg(sc, val); 1618 1619 return epic_read_eepromreg(sc); 1620 } 1621 1622 static void 1623 epic_output_eepromw(sc, val) 1624 epic_softc_t *sc; 1625 u_int16_t val; 1626 { 1627 int i; 1628 1629 for (i = 0xF; i >= 0; i--) { 1630 if (val & (1 << i)) 1631 epic_eeprom_clock(sc, 0x0B); 1632 else 1633 epic_eeprom_clock(sc, 0x03); 1634 } 1635 } 1636 1637 static u_int16_t 1638 epic_input_eepromw(sc) 1639 epic_softc_t *sc; 1640 { 1641 u_int16_t retval = 0; 1642 int i; 1643 1644 for (i = 0xF; i >= 0; i--) { 1645 if (epic_eeprom_clock(sc, 0x3) & 0x10) 1646 retval |= (1 << i); 1647 } 1648 1649 return retval; 1650 } 1651 1652 static int 1653 epic_read_eeprom(sc, loc) 1654 epic_softc_t *sc; 1655 u_int16_t loc; 1656 { 1657 u_int16_t dataval; 1658 u_int16_t read_cmd; 1659 1660 epic_write_eepromreg(sc, 3); 1661 1662 if (epic_read_eepromreg(sc) & 0x40) 1663 read_cmd = (loc & 0x3F) | 0x180; 1664 else 1665 read_cmd = (loc & 0xFF) | 0x600; 1666 1667 epic_output_eepromw(sc, read_cmd); 1668 1669 dataval = epic_input_eepromw(sc); 1670 1671 epic_write_eepromreg(sc, 1); 1672 1673 return dataval; 1674 } 1675 1676 /* 1677 * Here goes MII read/write routines 1678 */ 1679 static int 1680 epic_read_phy_reg(sc, phy, reg) 1681 epic_softc_t *sc; 1682 int phy, reg; 1683 { 1684 int i; 1685 1686 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01)); 1687 1688 for (i = 0; i < 0x100; i++) { 1689 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break; 1690 DELAY(1); 1691 } 1692 1693 return (CSR_READ_4(sc, MIIDATA)); 1694 } 1695 1696 static void 1697 epic_write_phy_reg(sc, phy, reg, val) 1698 epic_softc_t *sc; 1699 int phy, reg, val; 1700 { 1701 int i; 1702 1703 CSR_WRITE_4(sc, MIIDATA, val); 1704 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02)); 1705 1706 for(i=0;i<0x100;i++) { 1707 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break; 1708 DELAY(1); 1709 } 1710 1711 return; 1712 } 1713 1714 static int 1715 epic_miibus_readreg(dev, phy, reg) 1716 device_t dev; 1717 int phy, reg; 1718 { 1719 epic_softc_t *sc; 1720 1721 sc = device_get_softc(dev); 1722 1723 return (PHY_READ_2(sc, phy, reg)); 1724 } 1725 1726 static int 1727 epic_miibus_writereg(dev, phy, reg, data) 1728 device_t dev; 1729 int phy, reg, data; 1730 { 1731 epic_softc_t *sc; 1732 1733 sc = device_get_softc(dev); 1734 1735 PHY_WRITE_2(sc, phy, reg, data); 1736 1737 return (0); 1738 } 1739