1*86d7f5d3SJohn Marino /*- 2*86d7f5d3SJohn Marino * Copyright (c) 1997 Semen Ustimenko 3*86d7f5d3SJohn Marino * All rights reserved. 4*86d7f5d3SJohn Marino * 5*86d7f5d3SJohn Marino * Redistribution and use in source and binary forms, with or without 6*86d7f5d3SJohn Marino * modification, are permitted provided that the following conditions 7*86d7f5d3SJohn Marino * are met: 8*86d7f5d3SJohn Marino * 1. Redistributions of source code must retain the above copyright 9*86d7f5d3SJohn Marino * notice, this list of conditions and the following disclaimer. 10*86d7f5d3SJohn Marino * 2. Redistributions in binary form must reproduce the above copyright 11*86d7f5d3SJohn Marino * notice, this list of conditions and the following disclaimer in the 12*86d7f5d3SJohn Marino * documentation and/or other materials provided with the distribution. 13*86d7f5d3SJohn Marino * 14*86d7f5d3SJohn Marino * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15*86d7f5d3SJohn Marino * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16*86d7f5d3SJohn Marino * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17*86d7f5d3SJohn Marino * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18*86d7f5d3SJohn Marino * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19*86d7f5d3SJohn Marino * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20*86d7f5d3SJohn Marino * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21*86d7f5d3SJohn Marino * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22*86d7f5d3SJohn Marino * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23*86d7f5d3SJohn Marino * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24*86d7f5d3SJohn Marino * SUCH DAMAGE. 25*86d7f5d3SJohn Marino * 26*86d7f5d3SJohn Marino * $FreeBSD: src/sys/dev/tx/if_txvar.h,v 1.14.2.1 2002/10/29 01:43:50 semenu Exp $ 27*86d7f5d3SJohn Marino * $DragonFly: src/sys/dev/netif/tx/if_txvar.h,v 1.7 2005/11/20 13:08:35 sephe Exp $ 28*86d7f5d3SJohn Marino */ 29*86d7f5d3SJohn Marino 30*86d7f5d3SJohn Marino /* 31*86d7f5d3SJohn Marino * Configuration 32*86d7f5d3SJohn Marino */ 33*86d7f5d3SJohn Marino /*#define EPIC_DIAG 1*/ 34*86d7f5d3SJohn Marino /*#define EPIC_USEIOSPACE 1*/ 35*86d7f5d3SJohn Marino /*#define EPIC_EARLY_RX 1*/ 36*86d7f5d3SJohn Marino 37*86d7f5d3SJohn Marino #define TX_RING_SIZE 16 /* Leave this a power of 2 */ 38*86d7f5d3SJohn Marino #define RX_RING_SIZE 16 /* And this too, to do not */ 39*86d7f5d3SJohn Marino /* confuse RX(TX)_RING_MASK */ 40*86d7f5d3SJohn Marino #define TX_RING_MASK (TX_RING_SIZE - 1) 41*86d7f5d3SJohn Marino #define RX_RING_MASK (RX_RING_SIZE - 1) 42*86d7f5d3SJohn Marino #define ETHER_MAX_FRAME_LEN (ETHER_MAX_LEN + ETHER_CRC_LEN) 43*86d7f5d3SJohn Marino 44*86d7f5d3SJohn Marino /* This is driver's structure to define EPIC descriptors */ 45*86d7f5d3SJohn Marino struct epic_rx_buffer { 46*86d7f5d3SJohn Marino struct mbuf *mbuf; /* mbuf receiving packet */ 47*86d7f5d3SJohn Marino }; 48*86d7f5d3SJohn Marino 49*86d7f5d3SJohn Marino struct epic_tx_buffer { 50*86d7f5d3SJohn Marino struct mbuf *mbuf; /* mbuf contained packet */ 51*86d7f5d3SJohn Marino }; 52*86d7f5d3SJohn Marino 53*86d7f5d3SJohn Marino /* PHY, known by tx driver */ 54*86d7f5d3SJohn Marino #define EPIC_UNKN_PHY 0x0000 55*86d7f5d3SJohn Marino #define EPIC_QS6612_PHY 0x0001 56*86d7f5d3SJohn Marino #define EPIC_AC101_PHY 0x0002 57*86d7f5d3SJohn Marino #define EPIC_LXT970_PHY 0x0003 58*86d7f5d3SJohn Marino #define EPIC_SERIAL 0x0004 59*86d7f5d3SJohn Marino 60*86d7f5d3SJohn Marino /* Driver status structure */ 61*86d7f5d3SJohn Marino typedef struct { 62*86d7f5d3SJohn Marino struct arpcom arpcom; 63*86d7f5d3SJohn Marino struct resource *res; 64*86d7f5d3SJohn Marino struct resource *irq; 65*86d7f5d3SJohn Marino 66*86d7f5d3SJohn Marino device_t miibus; 67*86d7f5d3SJohn Marino device_t dev; 68*86d7f5d3SJohn Marino struct callout tx_stat_timer; 69*86d7f5d3SJohn Marino 70*86d7f5d3SJohn Marino void *sc_ih; 71*86d7f5d3SJohn Marino bus_space_tag_t sc_st; 72*86d7f5d3SJohn Marino bus_space_handle_t sc_sh; 73*86d7f5d3SJohn Marino 74*86d7f5d3SJohn Marino struct epic_rx_buffer rx_buffer[RX_RING_SIZE]; 75*86d7f5d3SJohn Marino struct epic_tx_buffer tx_buffer[TX_RING_SIZE]; 76*86d7f5d3SJohn Marino 77*86d7f5d3SJohn Marino /* Each element of array MUST be aligned on dword */ 78*86d7f5d3SJohn Marino /* and bounded on PAGE_SIZE */ 79*86d7f5d3SJohn Marino struct epic_rx_desc *rx_desc; 80*86d7f5d3SJohn Marino struct epic_tx_desc *tx_desc; 81*86d7f5d3SJohn Marino struct epic_frag_list *tx_flist; 82*86d7f5d3SJohn Marino u_int32_t flags; 83*86d7f5d3SJohn Marino u_int32_t tx_threshold; 84*86d7f5d3SJohn Marino u_int32_t txcon; 85*86d7f5d3SJohn Marino u_int32_t miicfg; 86*86d7f5d3SJohn Marino u_int32_t cur_tx; 87*86d7f5d3SJohn Marino u_int32_t cur_rx; 88*86d7f5d3SJohn Marino u_int32_t dirty_tx; 89*86d7f5d3SJohn Marino u_int32_t pending_txs; 90*86d7f5d3SJohn Marino struct mii_softc *physc; 91*86d7f5d3SJohn Marino u_int32_t phyid; 92*86d7f5d3SJohn Marino int serinst; 93*86d7f5d3SJohn Marino void *pool; 94*86d7f5d3SJohn Marino u_int16_t cardid; 95*86d7f5d3SJohn Marino } epic_softc_t; 96*86d7f5d3SJohn Marino 97*86d7f5d3SJohn Marino struct epic_type { 98*86d7f5d3SJohn Marino u_int16_t ven_id; 99*86d7f5d3SJohn Marino u_int16_t dev_id; 100*86d7f5d3SJohn Marino char *name; 101*86d7f5d3SJohn Marino }; 102*86d7f5d3SJohn Marino 103*86d7f5d3SJohn Marino #define sc_if arpcom.ac_if 104*86d7f5d3SJohn Marino #define sc_macaddr arpcom.ac_enaddr 105*86d7f5d3SJohn Marino 106*86d7f5d3SJohn Marino #define CSR_WRITE_4(sc, reg, val) \ 107*86d7f5d3SJohn Marino bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 108*86d7f5d3SJohn Marino #define CSR_WRITE_2(sc, reg, val) \ 109*86d7f5d3SJohn Marino bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 110*86d7f5d3SJohn Marino #define CSR_WRITE_1(sc, reg, val) \ 111*86d7f5d3SJohn Marino bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 112*86d7f5d3SJohn Marino #define CSR_READ_4(sc, reg) \ 113*86d7f5d3SJohn Marino bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 114*86d7f5d3SJohn Marino #define CSR_READ_2(sc, reg) \ 115*86d7f5d3SJohn Marino bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 116*86d7f5d3SJohn Marino #define CSR_READ_1(sc, reg) \ 117*86d7f5d3SJohn Marino bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 118*86d7f5d3SJohn Marino 119*86d7f5d3SJohn Marino #define PHY_READ_2(sc, phy, reg) \ 120*86d7f5d3SJohn Marino epic_read_phy_reg((sc), (phy), (reg)) 121*86d7f5d3SJohn Marino #define PHY_WRITE_2(sc, phy, reg, val) \ 122*86d7f5d3SJohn Marino epic_write_phy_reg((sc), (phy), (reg), (val)) 123