xref: /dragonfly/sys/dev/netif/tx/if_txvar.h (revision 1de703da)
1 /*-
2  * Copyright (c) 1997 Semen Ustimenko
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  *
26  * $FreeBSD: src/sys/dev/tx/if_txvar.h,v 1.14.2.1 2002/10/29 01:43:50 semenu Exp $
27  * $DragonFly: src/sys/dev/netif/tx/if_txvar.h,v 1.2 2003/06/17 04:28:32 dillon Exp $
28  */
29 
30 /*
31  * Configuration
32  */
33 /*#define	EPIC_DIAG	1*/
34 /*#define	EPIC_USEIOSPACE	1*/
35 /*#define	EPIC_EARLY_RX	1*/
36 
37 #ifndef ETHER_MAX_LEN
38 #define ETHER_MAX_LEN		1518
39 #endif
40 #ifndef ETHER_MIN_LEN
41 #define ETHER_MIN_LEN		64
42 #endif
43 #ifndef ETHER_CRC_LEN
44 #define ETHER_CRC_LEN		4
45 #endif
46 #define TX_RING_SIZE		16		/* Leave this a power of 2 */
47 #define RX_RING_SIZE		16		/* And this too, to do not */
48 						/* confuse RX(TX)_RING_MASK */
49 #define TX_RING_MASK		(TX_RING_SIZE - 1)
50 #define RX_RING_MASK		(RX_RING_SIZE - 1)
51 #define ETHER_MAX_FRAME_LEN	(ETHER_MAX_LEN + ETHER_CRC_LEN)
52 
53 /* This is driver's structure to define EPIC descriptors */
54 struct epic_rx_buffer {
55 	struct mbuf *		mbuf;		/* mbuf receiving packet */
56 };
57 
58 struct epic_tx_buffer {
59 	struct mbuf *		mbuf;		/* mbuf contained packet */
60 };
61 
62 /* PHY, known by tx driver */
63 #define	EPIC_UNKN_PHY		0x0000
64 #define	EPIC_QS6612_PHY		0x0001
65 #define	EPIC_AC101_PHY		0x0002
66 #define	EPIC_LXT970_PHY		0x0003
67 #define	EPIC_SERIAL		0x0004
68 
69 /* Driver status structure */
70 typedef struct {
71 	struct arpcom		arpcom;
72 	struct resource		*res;
73 	struct resource		*irq;
74 
75 	device_t		miibus;
76 	device_t		dev;
77 	struct callout_handle	stat_ch;
78 
79 	u_int32_t		unit;
80 	void			*sc_ih;
81 	bus_space_tag_t		sc_st;
82 	bus_space_handle_t	sc_sh;
83 
84 	struct epic_rx_buffer	rx_buffer[RX_RING_SIZE];
85 	struct epic_tx_buffer	tx_buffer[TX_RING_SIZE];
86 
87 	/* Each element of array MUST be aligned on dword  */
88 	/* and bounded on PAGE_SIZE 			   */
89 	struct epic_rx_desc	*rx_desc;
90 	struct epic_tx_desc	*tx_desc;
91 	struct epic_frag_list	*tx_flist;
92 	u_int32_t		flags;
93 	u_int32_t		tx_threshold;
94 	u_int32_t		txcon;
95 	u_int32_t		miicfg;
96 	u_int32_t		cur_tx;
97 	u_int32_t		cur_rx;
98 	u_int32_t		dirty_tx;
99 	u_int32_t		pending_txs;
100 	u_int16_t		cardvend;
101 	u_int16_t		cardid;
102 	struct mii_softc 	*physc;
103 	u_int32_t		phyid;
104 	int			serinst;
105 	void 			*pool;
106 } epic_softc_t;
107 
108 struct epic_type {
109 	u_int16_t	ven_id;
110 	u_int16_t	dev_id;
111 	char		*name;
112 };
113 
114 #define sc_if arpcom.ac_if
115 #define sc_macaddr arpcom.ac_enaddr
116 
117 #define CSR_WRITE_4(sc, reg, val) 					\
118 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
119 #define CSR_WRITE_2(sc, reg, val) 					\
120 	bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
121 #define CSR_WRITE_1(sc, reg, val) 					\
122 	bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
123 #define CSR_READ_4(sc, reg) 						\
124 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
125 #define CSR_READ_2(sc, reg) 						\
126 	bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
127 #define CSR_READ_1(sc, reg) 						\
128 	bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
129 
130 #define	PHY_READ_2(sc, phy, reg)					\
131 	epic_read_phy_reg((sc), (phy), (reg))
132 #define	PHY_WRITE_2(sc, phy, reg, val)					\
133 	epic_write_phy_reg((sc), (phy), (reg), (val))
134 
135 /* Macro to get either mbuf cluster or nothing */
136 #define EPIC_MGETCLUSTER(m)						\
137 	{ MGETHDR((m),M_DONTWAIT,MT_DATA);				\
138 	  if (m) {							\
139 	    MCLGET((m),M_DONTWAIT);					\
140 	    if( 0 == ((m)->m_flags & M_EXT) ) {				\
141 	      m_freem(m);						\
142 	      (m) = NULL;						\
143 	    }								\
144 	  }								\
145 	}
146 
147