1 /* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */ 2 /* $FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $ */ 3 4 /* 5 * Copyright (c) 2001 6 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 7 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Jason L. Wright, 20 * Theo de Raadt and Aaron Campbell. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Driver for 3c990 (Typhoon) Ethernet ASIC 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_ether.h> 62 #include <machine/in_cksum.h> 63 64 #include <net/if_media.h> 65 66 #include <net/bpf.h> 67 68 #include <vm/vm.h> /* for vtophys */ 69 #include <vm/pmap.h> /* for vtophys */ 70 #include <machine/clock.h> /* for DELAY */ 71 #include <machine/bus_pio.h> 72 #include <machine/bus_memio.h> 73 #include <machine/bus.h> 74 #include <machine/resource.h> 75 #include <sys/bus.h> 76 #include <sys/rman.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <pci/pcireg.h> 81 #include <pci/pcivar.h> 82 83 #define TXP_USEIOSPACE 84 #define __STRICT_ALIGNMENT 85 86 #include <dev/txp/if_txpreg.h> 87 #include <dev/txp/3c990img.h> 88 89 #ifndef lint 90 static const char rcsid[] = 91 "$FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $"; 92 #endif 93 94 /* 95 * Various supported device vendors/types and their names. 96 */ 97 static struct txp_type txp_devs[] = { 98 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95, 99 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" }, 100 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97, 101 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" }, 102 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM, 103 "3Com 3cR990B-TXM Etherlink with 3XP Processor" }, 104 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95, 105 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" }, 106 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97, 107 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" }, 108 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV, 109 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" }, 110 { 0, 0, NULL } 111 }; 112 113 static int txp_probe __P((device_t)); 114 static int txp_attach __P((device_t)); 115 static int txp_detach __P((device_t)); 116 static void txp_intr __P((void *)); 117 static void txp_tick __P((void *)); 118 static int txp_shutdown __P((device_t)); 119 static int txp_ioctl __P((struct ifnet *, u_long, caddr_t)); 120 static void txp_start __P((struct ifnet *)); 121 static void txp_stop __P((struct txp_softc *)); 122 static void txp_init __P((void *)); 123 static void txp_watchdog __P((struct ifnet *)); 124 125 static void txp_release_resources __P((struct txp_softc *)); 126 static int txp_chip_init __P((struct txp_softc *)); 127 static int txp_reset_adapter __P((struct txp_softc *)); 128 static int txp_download_fw __P((struct txp_softc *)); 129 static int txp_download_fw_wait __P((struct txp_softc *)); 130 static int txp_download_fw_section __P((struct txp_softc *, 131 struct txp_fw_section_header *, int)); 132 static int txp_alloc_rings __P((struct txp_softc *)); 133 static int txp_rxring_fill __P((struct txp_softc *)); 134 static void txp_rxring_empty __P((struct txp_softc *)); 135 static void txp_set_filter __P((struct txp_softc *)); 136 137 static int txp_cmd_desc_numfree __P((struct txp_softc *)); 138 static int txp_command __P((struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 139 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int)); 140 static int txp_command2 __P((struct txp_softc *, u_int16_t, u_int16_t, 141 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 142 struct txp_rsp_desc **, int)); 143 static int txp_response __P((struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 144 struct txp_rsp_desc **)); 145 static void txp_rsp_fixup __P((struct txp_softc *, struct txp_rsp_desc *, 146 struct txp_rsp_desc *)); 147 static void txp_capabilities __P((struct txp_softc *)); 148 149 static void txp_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 150 static int txp_ifmedia_upd __P((struct ifnet *)); 151 #ifdef TXP_DEBUG 152 static void txp_show_descriptor __P((void *)); 153 #endif 154 static void txp_tx_reclaim __P((struct txp_softc *, struct txp_tx_ring *)); 155 static void txp_rxbuf_reclaim __P((struct txp_softc *)); 156 static void txp_rx_reclaim __P((struct txp_softc *, struct txp_rx_ring *)); 157 158 #ifdef TXP_USEIOSPACE 159 #define TXP_RES SYS_RES_IOPORT 160 #define TXP_RID TXP_PCI_LOIO 161 #else 162 #define TXP_RES SYS_RES_MEMORY 163 #define TXP_RID TXP_PCI_LOMEM 164 #endif 165 166 static device_method_t txp_methods[] = { 167 /* Device interface */ 168 DEVMETHOD(device_probe, txp_probe), 169 DEVMETHOD(device_attach, txp_attach), 170 DEVMETHOD(device_detach, txp_detach), 171 DEVMETHOD(device_shutdown, txp_shutdown), 172 { 0, 0 } 173 }; 174 175 static driver_t txp_driver = { 176 "txp", 177 txp_methods, 178 sizeof(struct txp_softc) 179 }; 180 181 static devclass_t txp_devclass; 182 183 DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0); 184 185 static int 186 txp_probe(dev) 187 device_t dev; 188 { 189 struct txp_type *t; 190 191 t = txp_devs; 192 193 while(t->txp_name != NULL) { 194 if ((pci_get_vendor(dev) == t->txp_vid) && 195 (pci_get_device(dev) == t->txp_did)) { 196 device_set_desc(dev, t->txp_name); 197 return(0); 198 } 199 t++; 200 } 201 202 return(ENXIO); 203 } 204 205 static int 206 txp_attach(dev) 207 device_t dev; 208 { 209 struct txp_softc *sc; 210 struct ifnet *ifp; 211 u_int32_t command; 212 u_int16_t p1; 213 u_int32_t p2; 214 int unit, error = 0, rid; 215 216 sc = device_get_softc(dev); 217 unit = device_get_unit(dev); 218 sc->sc_dev = dev; 219 sc->sc_cold = 1; 220 221 /* 222 * Map control/status registers. 223 */ 224 command = pci_read_config(dev, PCIR_COMMAND, 4); 225 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 226 pci_write_config(dev, PCIR_COMMAND, command, 4); 227 command = pci_read_config(dev, PCIR_COMMAND, 4); 228 229 #ifdef TXP_USEIOSPACE 230 if (!(command & PCIM_CMD_PORTEN)) { 231 device_printf(dev, "failed to enable I/O ports!\n"); 232 error = ENXIO;; 233 goto fail; 234 } 235 #else 236 if (!(command & PCIM_CMD_MEMEN)) { 237 device_printf(dev, "failed to enable memory mapping!\n"); 238 error = ENXIO;; 239 goto fail; 240 } 241 #endif 242 243 rid = TXP_RID; 244 sc->sc_res = bus_alloc_resource(dev, TXP_RES, &rid, 245 0, ~0, 1, RF_ACTIVE); 246 247 if (sc->sc_res == NULL) { 248 device_printf(dev, "couldn't map ports/memory\n"); 249 error = ENXIO; 250 goto fail; 251 } 252 253 sc->sc_bt = rman_get_bustag(sc->sc_res); 254 sc->sc_bh = rman_get_bushandle(sc->sc_res); 255 256 /* Allocate interrupt */ 257 rid = 0; 258 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 259 RF_SHAREABLE | RF_ACTIVE); 260 261 if (sc->sc_irq == NULL) { 262 device_printf(dev, "couldn't map interrupt\n"); 263 txp_release_resources(sc); 264 error = ENXIO; 265 goto fail; 266 } 267 268 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 269 txp_intr, sc, &sc->sc_intrhand); 270 271 if (error) { 272 txp_release_resources(sc); 273 device_printf(dev, "couldn't set up irq\n"); 274 goto fail; 275 } 276 277 if (txp_chip_init(sc)) { 278 txp_release_resources(sc); 279 goto fail; 280 } 281 282 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF, 283 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 284 error = txp_download_fw(sc); 285 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF); 286 sc->sc_fwbuf = NULL; 287 288 if (error) { 289 txp_release_resources(sc); 290 goto fail; 291 } 292 293 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF, 294 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 295 bzero(sc->sc_ldata, sizeof(struct txp_ldata)); 296 297 if (txp_alloc_rings(sc)) { 298 txp_release_resources(sc); 299 goto fail; 300 } 301 302 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 303 NULL, NULL, NULL, 1)) { 304 txp_release_resources(sc); 305 goto fail; 306 } 307 308 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 309 &p1, &p2, NULL, 1)) { 310 txp_release_resources(sc); 311 goto fail; 312 } 313 314 txp_set_filter(sc); 315 316 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 317 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 318 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 319 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 320 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 321 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 322 323 printf("txp%d: Ethernet address %6D\n", unit, 324 sc->sc_arpcom.ac_enaddr, ":"); 325 326 sc->sc_cold = 0; 327 328 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 329 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 330 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 331 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 332 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 333 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 334 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 335 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 336 337 sc->sc_xcvr = TXP_XCVR_AUTO; 338 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 339 NULL, NULL, NULL, 0); 340 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 341 342 ifp = &sc->sc_arpcom.ac_if; 343 ifp->if_softc = sc; 344 ifp->if_unit = unit; 345 ifp->if_name = "txp"; 346 ifp->if_mtu = ETHERMTU; 347 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 348 ifp->if_ioctl = txp_ioctl; 349 ifp->if_output = ether_output; 350 ifp->if_start = txp_start; 351 ifp->if_watchdog = txp_watchdog; 352 ifp->if_init = txp_init; 353 ifp->if_baudrate = 100000000; 354 ifp->if_snd.ifq_maxlen = TX_ENTRIES; 355 ifp->if_hwassist = 0; 356 txp_capabilities(sc); 357 358 /* 359 * Attach us everywhere 360 */ 361 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 362 callout_handle_init(&sc->sc_tick); 363 return(0); 364 365 fail: 366 txp_release_resources(sc); 367 return(error); 368 } 369 370 static int 371 txp_detach(dev) 372 device_t dev; 373 { 374 struct txp_softc *sc; 375 struct ifnet *ifp; 376 int i; 377 378 sc = device_get_softc(dev); 379 ifp = &sc->sc_arpcom.ac_if; 380 381 txp_stop(sc); 382 txp_shutdown(dev); 383 384 ifmedia_removeall(&sc->sc_ifmedia); 385 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 386 387 for (i = 0; i < RXBUF_ENTRIES; i++) 388 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF); 389 390 txp_release_resources(sc); 391 392 return(0); 393 } 394 395 static void 396 txp_release_resources(sc) 397 struct txp_softc *sc; 398 { 399 device_t dev; 400 401 dev = sc->sc_dev; 402 403 if (sc->sc_intrhand != NULL) 404 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 405 406 if (sc->sc_irq != NULL) 407 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 408 409 if (sc->sc_res != NULL) 410 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res); 411 412 if (sc->sc_ldata != NULL) 413 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF); 414 415 return; 416 } 417 418 static int 419 txp_chip_init(sc) 420 struct txp_softc *sc; 421 { 422 /* disable interrupts */ 423 WRITE_REG(sc, TXP_IER, 0); 424 WRITE_REG(sc, TXP_IMR, 425 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 426 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 427 TXP_INT_LATCH); 428 429 /* ack all interrupts */ 430 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 431 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 432 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 433 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 434 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 435 436 if (txp_reset_adapter(sc)) 437 return (-1); 438 439 /* disable interrupts */ 440 WRITE_REG(sc, TXP_IER, 0); 441 WRITE_REG(sc, TXP_IMR, 442 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 443 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 444 TXP_INT_LATCH); 445 446 /* ack all interrupts */ 447 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 448 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 449 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 450 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 451 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 452 453 return (0); 454 } 455 456 static int 457 txp_reset_adapter(sc) 458 struct txp_softc *sc; 459 { 460 u_int32_t r; 461 int i; 462 463 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 464 DELAY(1000); 465 WRITE_REG(sc, TXP_SRR, 0); 466 467 /* Should wait max 6 seconds */ 468 for (i = 0; i < 6000; i++) { 469 r = READ_REG(sc, TXP_A2H_0); 470 if (r == STAT_WAITING_FOR_HOST_REQUEST) 471 break; 472 DELAY(1000); 473 } 474 475 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 476 device_printf(sc->sc_dev, "reset hung\n"); 477 return (-1); 478 } 479 480 return (0); 481 } 482 483 static int 484 txp_download_fw(sc) 485 struct txp_softc *sc; 486 { 487 struct txp_fw_file_header *fileheader; 488 struct txp_fw_section_header *secthead; 489 int sect; 490 u_int32_t r, i, ier, imr; 491 492 ier = READ_REG(sc, TXP_IER); 493 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 494 495 imr = READ_REG(sc, TXP_IMR); 496 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 497 498 for (i = 0; i < 10000; i++) { 499 r = READ_REG(sc, TXP_A2H_0); 500 if (r == STAT_WAITING_FOR_HOST_REQUEST) 501 break; 502 DELAY(50); 503 } 504 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 505 device_printf(sc->sc_dev, "not waiting for host request\n"); 506 return (-1); 507 } 508 509 /* Ack the status */ 510 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 511 512 fileheader = (struct txp_fw_file_header *)tc990image; 513 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 514 device_printf(sc->sc_dev, "fw invalid magic\n"); 515 return (-1); 516 } 517 518 /* Tell boot firmware to get ready for image */ 519 WRITE_REG(sc, TXP_H2A_1, fileheader->addr); 520 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 521 522 if (txp_download_fw_wait(sc)) { 523 device_printf(sc->sc_dev, "fw wait failed, initial\n"); 524 return (-1); 525 } 526 527 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 528 sizeof(struct txp_fw_file_header)); 529 530 for (sect = 0; sect < fileheader->nsections; sect++) { 531 if (txp_download_fw_section(sc, secthead, sect)) 532 return (-1); 533 secthead = (struct txp_fw_section_header *) 534 (((u_int8_t *)secthead) + secthead->nbytes + 535 sizeof(*secthead)); 536 } 537 538 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 539 540 for (i = 0; i < 10000; i++) { 541 r = READ_REG(sc, TXP_A2H_0); 542 if (r == STAT_WAITING_FOR_BOOT) 543 break; 544 DELAY(50); 545 } 546 if (r != STAT_WAITING_FOR_BOOT) { 547 device_printf(sc->sc_dev, "not waiting for boot\n"); 548 return (-1); 549 } 550 551 WRITE_REG(sc, TXP_IER, ier); 552 WRITE_REG(sc, TXP_IMR, imr); 553 554 return (0); 555 } 556 557 static int 558 txp_download_fw_wait(sc) 559 struct txp_softc *sc; 560 { 561 u_int32_t i, r; 562 563 for (i = 0; i < 10000; i++) { 564 r = READ_REG(sc, TXP_ISR); 565 if (r & TXP_INT_A2H_0) 566 break; 567 DELAY(50); 568 } 569 570 if (!(r & TXP_INT_A2H_0)) { 571 device_printf(sc->sc_dev, "fw wait failed comm0\n"); 572 return (-1); 573 } 574 575 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 576 577 r = READ_REG(sc, TXP_A2H_0); 578 if (r != STAT_WAITING_FOR_SEGMENT) { 579 device_printf(sc->sc_dev, "fw not waiting for segment\n"); 580 return (-1); 581 } 582 return (0); 583 } 584 585 static int 586 txp_download_fw_section(sc, sect, sectnum) 587 struct txp_softc *sc; 588 struct txp_fw_section_header *sect; 589 int sectnum; 590 { 591 vm_offset_t dma; 592 int rseg, err = 0; 593 struct mbuf m; 594 u_int16_t csum; 595 596 /* Skip zero length sections */ 597 if (sect->nbytes == 0) 598 return (0); 599 600 /* Make sure we aren't past the end of the image */ 601 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 602 if (rseg >= sizeof(tc990image)) { 603 device_printf(sc->sc_dev, "fw invalid section address, " 604 "section %d\n", sectnum); 605 return (-1); 606 } 607 608 /* Make sure this section doesn't go past the end */ 609 rseg += sect->nbytes; 610 if (rseg >= sizeof(tc990image)) { 611 device_printf(sc->sc_dev, "fw truncated section %d\n", 612 sectnum); 613 return (-1); 614 } 615 616 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes); 617 dma = vtophys(sc->sc_fwbuf); 618 619 /* 620 * dummy up mbuf and verify section checksum 621 */ 622 m.m_type = MT_DATA; 623 m.m_next = m.m_nextpkt = NULL; 624 m.m_len = sect->nbytes; 625 m.m_data = sc->sc_fwbuf; 626 m.m_flags = 0; 627 csum = in_cksum(&m, sect->nbytes); 628 if (csum != sect->cksum) { 629 device_printf(sc->sc_dev, "fw section %d, bad " 630 "cksum (expected 0x%x got 0x%x)\n", 631 sectnum, sect->cksum, csum); 632 err = -1; 633 goto bail; 634 } 635 636 WRITE_REG(sc, TXP_H2A_1, sect->nbytes); 637 WRITE_REG(sc, TXP_H2A_2, sect->cksum); 638 WRITE_REG(sc, TXP_H2A_3, sect->addr); 639 WRITE_REG(sc, TXP_H2A_4, 0); 640 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff); 641 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 642 643 if (txp_download_fw_wait(sc)) { 644 device_printf(sc->sc_dev, "fw wait failed, " 645 "section %d\n", sectnum); 646 err = -1; 647 } 648 649 bail: 650 return (err); 651 } 652 653 static void 654 txp_intr(vsc) 655 void *vsc; 656 { 657 struct txp_softc *sc = vsc; 658 struct txp_hostvar *hv = sc->sc_hostvar; 659 u_int32_t isr; 660 661 /* mask all interrupts */ 662 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 663 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 664 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 665 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 666 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 667 668 isr = READ_REG(sc, TXP_ISR); 669 while (isr) { 670 WRITE_REG(sc, TXP_ISR, isr); 671 672 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 673 txp_rx_reclaim(sc, &sc->sc_rxhir); 674 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 675 txp_rx_reclaim(sc, &sc->sc_rxlor); 676 677 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 678 txp_rxbuf_reclaim(sc); 679 680 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 681 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off)))) 682 txp_tx_reclaim(sc, &sc->sc_txhir); 683 684 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 685 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off)))) 686 txp_tx_reclaim(sc, &sc->sc_txlor); 687 688 isr = READ_REG(sc, TXP_ISR); 689 } 690 691 /* unmask all interrupts */ 692 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 693 694 txp_start(&sc->sc_arpcom.ac_if); 695 696 return; 697 } 698 699 static void 700 txp_rx_reclaim(sc, r) 701 struct txp_softc *sc; 702 struct txp_rx_ring *r; 703 { 704 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 705 struct txp_rx_desc *rxd; 706 struct mbuf *m; 707 struct txp_swdesc *sd = NULL; 708 u_int32_t roff, woff; 709 struct ether_header *eh = NULL; 710 711 roff = *r->r_roff; 712 woff = *r->r_woff; 713 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc)); 714 715 while (roff != woff) { 716 717 if (rxd->rx_flags & RX_FLAGS_ERROR) { 718 device_printf(sc->sc_dev, "error 0x%x\n", 719 rxd->rx_stat); 720 ifp->if_ierrors++; 721 goto next; 722 } 723 724 /* retrieve stashed pointer */ 725 sd = rxd->rx_sd; 726 727 m = sd->sd_mbuf; 728 sd->sd_mbuf = NULL; 729 730 m->m_pkthdr.len = m->m_len = rxd->rx_len; 731 732 #ifdef __STRICT_ALIGNMENT 733 { 734 /* 735 * XXX Nice chip, except it won't accept "off by 2" 736 * buffers, so we're force to copy. Supposedly 737 * this will be fixed in a newer firmware rev 738 * and this will be temporary. 739 */ 740 struct mbuf *mnew; 741 742 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 743 if (mnew == NULL) { 744 m_freem(m); 745 goto next; 746 } 747 if (m->m_len > (MHLEN - 2)) { 748 MCLGET(mnew, M_DONTWAIT); 749 if (!(mnew->m_flags & M_EXT)) { 750 m_freem(mnew); 751 m_freem(m); 752 goto next; 753 } 754 } 755 mnew->m_pkthdr.rcvif = ifp; 756 m_adj(mnew, 2); 757 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 758 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 759 m_freem(m); 760 m = mnew; 761 } 762 #endif 763 764 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD) 765 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 766 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD) 767 m->m_pkthdr.csum_flags |= 768 CSUM_IP_CHECKED|CSUM_IP_VALID; 769 770 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) || 771 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) { 772 m->m_pkthdr.csum_flags |= 773 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 774 m->m_pkthdr.csum_data = 0xffff; 775 } 776 777 eh = mtod(m, struct ether_header *); 778 /* Remove header from mbuf and pass it on. */ 779 m_adj(m, sizeof(struct ether_header)); 780 781 if (rxd->rx_stat & RX_STAT_VLAN) { 782 VLAN_INPUT_TAG(eh, m, htons(rxd->rx_vlan >> 16)); 783 goto next; 784 } 785 786 ether_input(ifp, eh, m); 787 788 next: 789 790 roff += sizeof(struct txp_rx_desc); 791 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 792 roff = 0; 793 rxd = r->r_desc; 794 } else 795 rxd++; 796 woff = *r->r_woff; 797 } 798 799 *r->r_roff = woff; 800 801 return; 802 } 803 804 static void 805 txp_rxbuf_reclaim(sc) 806 struct txp_softc *sc; 807 { 808 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 809 struct txp_hostvar *hv = sc->sc_hostvar; 810 struct txp_rxbuf_desc *rbd; 811 struct txp_swdesc *sd; 812 u_int32_t i; 813 814 if (!(ifp->if_flags & IFF_RUNNING)) 815 return; 816 817 i = sc->sc_rxbufprod; 818 rbd = sc->sc_rxbufs + i; 819 820 while (1) { 821 sd = rbd->rb_sd; 822 if (sd->sd_mbuf != NULL) 823 break; 824 825 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 826 if (sd->sd_mbuf == NULL) 827 goto err_sd; 828 829 MCLGET(sd->sd_mbuf, M_DONTWAIT); 830 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 831 goto err_mbuf; 832 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 833 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 834 835 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t)) 836 & 0xffffffff; 837 rbd->rb_paddrhi = 0; 838 839 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i); 840 841 if (++i == RXBUF_ENTRIES) { 842 i = 0; 843 rbd = sc->sc_rxbufs; 844 } else 845 rbd++; 846 } 847 848 sc->sc_rxbufprod = i; 849 850 return; 851 852 err_mbuf: 853 m_freem(sd->sd_mbuf); 854 err_sd: 855 free(sd, M_DEVBUF); 856 } 857 858 /* 859 * Reclaim mbufs and entries from a transmit ring. 860 */ 861 static void 862 txp_tx_reclaim(sc, r) 863 struct txp_softc *sc; 864 struct txp_tx_ring *r; 865 { 866 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 867 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off)); 868 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 869 struct txp_tx_desc *txd = r->r_desc + cons; 870 struct txp_swdesc *sd = sc->sc_txd + cons; 871 struct mbuf *m; 872 873 while (cons != idx) { 874 if (cnt == 0) 875 break; 876 877 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 878 TX_FLAGS_TYPE_DATA) { 879 m = sd->sd_mbuf; 880 if (m != NULL) { 881 m_freem(m); 882 txd->tx_addrlo = 0; 883 txd->tx_addrhi = 0; 884 ifp->if_opackets++; 885 } 886 } 887 ifp->if_flags &= ~IFF_OACTIVE; 888 889 if (++cons == TX_ENTRIES) { 890 txd = r->r_desc; 891 cons = 0; 892 sd = sc->sc_txd; 893 } else { 894 txd++; 895 sd++; 896 } 897 898 cnt--; 899 } 900 901 r->r_cons = cons; 902 r->r_cnt = cnt; 903 if (cnt == 0) 904 ifp->if_timer = 0; 905 } 906 907 static int 908 txp_shutdown(dev) 909 device_t dev; 910 { 911 struct txp_softc *sc; 912 913 sc = device_get_softc(dev); 914 915 /* mask all interrupts */ 916 WRITE_REG(sc, TXP_IMR, 917 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 918 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 919 TXP_INT_LATCH); 920 921 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 922 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 923 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 924 925 return(0); 926 } 927 928 static int 929 txp_alloc_rings(sc) 930 struct txp_softc *sc; 931 { 932 struct txp_boot_record *boot; 933 struct txp_ldata *ld; 934 u_int32_t r; 935 int i; 936 937 ld = sc->sc_ldata; 938 boot = &ld->txp_boot; 939 940 /* boot record */ 941 sc->sc_boot = boot; 942 943 /* host variables */ 944 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar)); 945 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar); 946 boot->br_hostvar_hi = 0; 947 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar; 948 949 /* hi priority tx ring */ 950 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);; 951 boot->br_txhipri_hi = 0; 952 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 953 sc->sc_txhir.r_reg = TXP_H2A_1; 954 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring; 955 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 956 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 957 958 /* lo priority tx ring */ 959 boot->br_txlopri_lo = vtophys(&ld->txp_txloring); 960 boot->br_txlopri_hi = 0; 961 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 962 sc->sc_txlor.r_reg = TXP_H2A_3; 963 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring; 964 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 965 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 966 967 /* high priority rx ring */ 968 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring); 969 boot->br_rxhipri_hi = 0; 970 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 971 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring; 972 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 973 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 974 975 /* low priority rx ring */ 976 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring); 977 boot->br_rxlopri_hi = 0; 978 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 979 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring; 980 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 981 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 982 983 /* command ring */ 984 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 985 boot->br_cmd_lo = vtophys(&ld->txp_cmdring); 986 boot->br_cmd_hi = 0; 987 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 988 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring; 989 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 990 sc->sc_cmdring.lastwrite = 0; 991 992 /* response ring */ 993 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 994 boot->br_resp_lo = vtophys(&ld->txp_rspring); 995 boot->br_resp_hi = 0; 996 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc); 997 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring; 998 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 999 sc->sc_rspring.lastwrite = 0; 1000 1001 /* receive buffer ring */ 1002 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs); 1003 boot->br_rxbuf_hi = 0; 1004 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc); 1005 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs; 1006 1007 for (i = 0; i < RXBUF_ENTRIES; i++) { 1008 struct txp_swdesc *sd; 1009 if (sc->sc_rxbufs[i].rb_sd != NULL) 1010 continue; 1011 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc), 1012 M_DEVBUF, M_NOWAIT); 1013 if (sc->sc_rxbufs[i].rb_sd == NULL) 1014 return(ENOBUFS); 1015 sd = sc->sc_rxbufs[i].rb_sd; 1016 sd->sd_mbuf = NULL; 1017 } 1018 sc->sc_rxbufprod = 0; 1019 1020 /* zero dma */ 1021 bzero(&ld->txp_zero, sizeof(u_int32_t)); 1022 boot->br_zero_lo = vtophys(&ld->txp_zero); 1023 boot->br_zero_hi = 0; 1024 1025 /* See if it's waiting for boot, and try to boot it */ 1026 for (i = 0; i < 10000; i++) { 1027 r = READ_REG(sc, TXP_A2H_0); 1028 if (r == STAT_WAITING_FOR_BOOT) 1029 break; 1030 DELAY(50); 1031 } 1032 1033 if (r != STAT_WAITING_FOR_BOOT) { 1034 device_printf(sc->sc_dev, "not waiting for boot\n"); 1035 return(ENXIO); 1036 } 1037 1038 WRITE_REG(sc, TXP_H2A_2, 0); 1039 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot)); 1040 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1041 1042 /* See if it booted */ 1043 for (i = 0; i < 10000; i++) { 1044 r = READ_REG(sc, TXP_A2H_0); 1045 if (r == STAT_RUNNING) 1046 break; 1047 DELAY(50); 1048 } 1049 if (r != STAT_RUNNING) { 1050 device_printf(sc->sc_dev, "fw not running\n"); 1051 return(ENXIO); 1052 } 1053 1054 /* Clear TX and CMD ring write registers */ 1055 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1056 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1057 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1058 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1059 1060 return (0); 1061 } 1062 1063 static int 1064 txp_ioctl(ifp, command, data) 1065 struct ifnet *ifp; 1066 u_long command; 1067 caddr_t data; 1068 { 1069 struct txp_softc *sc = ifp->if_softc; 1070 struct ifreq *ifr = (struct ifreq *)data; 1071 int s, error = 0; 1072 1073 s = splnet(); 1074 1075 if ((error = ether_ioctl(ifp, command, data)) > 0) { 1076 splx(s); 1077 return error; 1078 } 1079 1080 switch(command) { 1081 case SIOCSIFADDR: 1082 case SIOCGIFADDR: 1083 case SIOCSIFMTU: 1084 error = ether_ioctl(ifp, command, data); 1085 break; 1086 case SIOCSIFFLAGS: 1087 if (ifp->if_flags & IFF_UP) { 1088 txp_init(sc); 1089 } else { 1090 if (ifp->if_flags & IFF_RUNNING) 1091 txp_stop(sc); 1092 } 1093 break; 1094 case SIOCADDMULTI: 1095 case SIOCDELMULTI: 1096 /* 1097 * Multicast list has changed; set the hardware 1098 * filter accordingly. 1099 */ 1100 txp_set_filter(sc); 1101 error = 0; 1102 break; 1103 case SIOCGIFMEDIA: 1104 case SIOCSIFMEDIA: 1105 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1106 break; 1107 default: 1108 error = EINVAL; 1109 break; 1110 } 1111 1112 (void)splx(s); 1113 1114 return(error); 1115 } 1116 1117 static int 1118 txp_rxring_fill(sc) 1119 struct txp_softc *sc; 1120 { 1121 int i; 1122 struct ifnet *ifp; 1123 struct txp_swdesc *sd; 1124 1125 ifp = &sc->sc_arpcom.ac_if; 1126 1127 for (i = 0; i < RXBUF_ENTRIES; i++) { 1128 sd = sc->sc_rxbufs[i].rb_sd; 1129 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1130 if (sd->sd_mbuf == NULL) 1131 return(ENOBUFS); 1132 1133 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1134 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1135 m_freem(sd->sd_mbuf); 1136 return(ENOBUFS); 1137 } 1138 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1139 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1140 1141 sc->sc_rxbufs[i].rb_paddrlo = 1142 vtophys(mtod(sd->sd_mbuf, vm_offset_t)); 1143 sc->sc_rxbufs[i].rb_paddrhi = 0; 1144 } 1145 1146 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) * 1147 sizeof(struct txp_rxbuf_desc); 1148 1149 return(0); 1150 } 1151 1152 static void 1153 txp_rxring_empty(sc) 1154 struct txp_softc *sc; 1155 { 1156 int i; 1157 struct txp_swdesc *sd; 1158 1159 if (sc->sc_rxbufs == NULL) 1160 return; 1161 1162 for (i = 0; i < RXBUF_ENTRIES; i++) { 1163 if (&sc->sc_rxbufs[i] == NULL) 1164 continue; 1165 sd = sc->sc_rxbufs[i].rb_sd; 1166 if (sd == NULL) 1167 continue; 1168 if (sd->sd_mbuf != NULL) { 1169 m_freem(sd->sd_mbuf); 1170 sd->sd_mbuf = NULL; 1171 } 1172 } 1173 1174 return; 1175 } 1176 1177 static void 1178 txp_init(xsc) 1179 void *xsc; 1180 { 1181 struct txp_softc *sc; 1182 struct ifnet *ifp; 1183 u_int16_t p1; 1184 u_int32_t p2; 1185 int s; 1186 1187 sc = xsc; 1188 ifp = &sc->sc_arpcom.ac_if; 1189 1190 if (ifp->if_flags & IFF_RUNNING) 1191 return; 1192 1193 txp_stop(sc); 1194 1195 s = splnet(); 1196 1197 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 1198 NULL, NULL, NULL, 1); 1199 1200 /* Set station address. */ 1201 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0]; 1202 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1]; 1203 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2]; 1204 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3]; 1205 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4]; 1206 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5]; 1207 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0, 1208 NULL, NULL, NULL, 1); 1209 1210 txp_set_filter(sc); 1211 1212 txp_rxring_fill(sc); 1213 1214 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1215 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1216 1217 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1218 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1219 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1220 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1221 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1222 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1223 1224 ifp->if_flags |= IFF_RUNNING; 1225 ifp->if_flags &= ~IFF_OACTIVE; 1226 ifp->if_timer = 0; 1227 1228 sc->sc_tick = timeout(txp_tick, sc, hz); 1229 1230 splx(s); 1231 } 1232 1233 static void 1234 txp_tick(vsc) 1235 void *vsc; 1236 { 1237 struct txp_softc *sc = vsc; 1238 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1239 struct txp_rsp_desc *rsp = NULL; 1240 struct txp_ext_desc *ext; 1241 int s; 1242 1243 s = splnet(); 1244 txp_rxbuf_reclaim(sc); 1245 1246 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1247 &rsp, 1)) 1248 goto out; 1249 if (rsp->rsp_numdesc != 6) 1250 goto out; 1251 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1252 NULL, NULL, NULL, 1)) 1253 goto out; 1254 ext = (struct txp_ext_desc *)(rsp + 1); 1255 1256 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1257 ext[4].ext_1 + ext[4].ext_4; 1258 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1259 ext[2].ext_1; 1260 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1261 ext[1].ext_3; 1262 ifp->if_opackets += rsp->rsp_par2; 1263 ifp->if_ipackets += ext[2].ext_3; 1264 1265 out: 1266 if (rsp != NULL) 1267 free(rsp, M_DEVBUF); 1268 1269 splx(s); 1270 sc->sc_tick = timeout(txp_tick, sc, hz); 1271 1272 return; 1273 } 1274 1275 static void 1276 txp_start(ifp) 1277 struct ifnet *ifp; 1278 { 1279 struct txp_softc *sc = ifp->if_softc; 1280 struct txp_tx_ring *r = &sc->sc_txhir; 1281 struct txp_tx_desc *txd; 1282 struct txp_frag_desc *fxd; 1283 struct mbuf *m, *m0; 1284 struct txp_swdesc *sd; 1285 u_int32_t firstprod, firstcnt, prod, cnt; 1286 struct ifvlan *ifv; 1287 1288 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1289 return; 1290 1291 prod = r->r_prod; 1292 cnt = r->r_cnt; 1293 1294 while (1) { 1295 IF_DEQUEUE(&ifp->if_snd, m); 1296 if (m == NULL) 1297 break; 1298 1299 firstprod = prod; 1300 firstcnt = cnt; 1301 1302 sd = sc->sc_txd + prod; 1303 sd->sd_mbuf = m; 1304 1305 if ((TX_ENTRIES - cnt) < 4) 1306 goto oactive; 1307 1308 txd = r->r_desc + prod; 1309 1310 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1311 txd->tx_numdesc = 0; 1312 txd->tx_addrlo = 0; 1313 txd->tx_addrhi = 0; 1314 txd->tx_totlen = 0; 1315 txd->tx_pflags = 0; 1316 1317 if (++prod == TX_ENTRIES) 1318 prod = 0; 1319 1320 if (++cnt >= (TX_ENTRIES - 4)) 1321 goto oactive; 1322 1323 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1324 m->m_pkthdr.rcvif != NULL) { 1325 ifv = m->m_pkthdr.rcvif->if_softc; 1326 txd->tx_pflags = TX_PFLAGS_VLAN | 1327 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S); 1328 } 1329 1330 if (m->m_pkthdr.csum_flags & CSUM_IP) 1331 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1332 1333 #if 0 1334 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1335 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1336 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1337 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1338 #endif 1339 1340 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1341 for (m0 = m; m0 != NULL; m0 = m0->m_next) { 1342 if (m0->m_len == 0) 1343 continue; 1344 if (++cnt >= (TX_ENTRIES - 4)) 1345 goto oactive; 1346 1347 txd->tx_numdesc++; 1348 1349 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG; 1350 fxd->frag_rsvd1 = 0; 1351 fxd->frag_len = m0->m_len; 1352 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t)); 1353 fxd->frag_addrhi = 0; 1354 fxd->frag_rsvd2 = 0; 1355 1356 if (++prod == TX_ENTRIES) { 1357 fxd = (struct txp_frag_desc *)r->r_desc; 1358 prod = 0; 1359 } else 1360 fxd++; 1361 1362 } 1363 1364 ifp->if_timer = 5; 1365 1366 if (ifp->if_bpf) 1367 bpf_mtap(ifp, m); 1368 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1369 } 1370 1371 r->r_prod = prod; 1372 r->r_cnt = cnt; 1373 return; 1374 1375 oactive: 1376 ifp->if_flags |= IFF_OACTIVE; 1377 r->r_prod = firstprod; 1378 r->r_cnt = firstcnt; 1379 IF_PREPEND(&ifp->if_snd, m); 1380 return; 1381 } 1382 1383 /* 1384 * Handle simple commands sent to the typhoon 1385 */ 1386 static int 1387 txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1388 struct txp_softc *sc; 1389 u_int16_t id, in1, *out1; 1390 u_int32_t in2, in3, *out2, *out3; 1391 int wait; 1392 { 1393 struct txp_rsp_desc *rsp = NULL; 1394 1395 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1396 return (-1); 1397 1398 if (!wait) 1399 return (0); 1400 1401 if (out1 != NULL) 1402 *out1 = rsp->rsp_par1; 1403 if (out2 != NULL) 1404 *out2 = rsp->rsp_par2; 1405 if (out3 != NULL) 1406 *out3 = rsp->rsp_par3; 1407 free(rsp, M_DEVBUF); 1408 return (0); 1409 } 1410 1411 static int 1412 txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1413 struct txp_softc *sc; 1414 u_int16_t id, in1; 1415 u_int32_t in2, in3; 1416 struct txp_ext_desc *in_extp; 1417 u_int8_t in_extn; 1418 struct txp_rsp_desc **rspp; 1419 int wait; 1420 { 1421 struct txp_hostvar *hv = sc->sc_hostvar; 1422 struct txp_cmd_desc *cmd; 1423 struct txp_ext_desc *ext; 1424 u_int32_t idx, i; 1425 u_int16_t seq; 1426 1427 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1428 device_printf(sc->sc_dev, "no free cmd descriptors\n"); 1429 return (-1); 1430 } 1431 1432 idx = sc->sc_cmdring.lastwrite; 1433 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1434 bzero(cmd, sizeof(*cmd)); 1435 1436 cmd->cmd_numdesc = in_extn; 1437 cmd->cmd_seq = seq = sc->sc_seq++; 1438 cmd->cmd_id = id; 1439 cmd->cmd_par1 = in1; 1440 cmd->cmd_par2 = in2; 1441 cmd->cmd_par3 = in3; 1442 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1443 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1444 1445 idx += sizeof(struct txp_cmd_desc); 1446 if (idx == sc->sc_cmdring.size) 1447 idx = 0; 1448 1449 for (i = 0; i < in_extn; i++) { 1450 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1451 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1452 in_extp++; 1453 idx += sizeof(struct txp_cmd_desc); 1454 if (idx == sc->sc_cmdring.size) 1455 idx = 0; 1456 } 1457 1458 sc->sc_cmdring.lastwrite = idx; 1459 1460 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1461 1462 if (!wait) 1463 return (0); 1464 1465 for (i = 0; i < 10000; i++) { 1466 idx = hv->hv_resp_read_idx; 1467 if (idx != hv->hv_resp_write_idx) { 1468 *rspp = NULL; 1469 if (txp_response(sc, idx, id, seq, rspp)) 1470 return (-1); 1471 if (*rspp != NULL) 1472 break; 1473 } 1474 DELAY(50); 1475 } 1476 if (i == 1000 || (*rspp) == NULL) { 1477 device_printf(sc->sc_dev, "0x%x command failed\n", id); 1478 return (-1); 1479 } 1480 1481 return (0); 1482 } 1483 1484 static int 1485 txp_response(sc, ridx, id, seq, rspp) 1486 struct txp_softc *sc; 1487 u_int32_t ridx; 1488 u_int16_t id; 1489 u_int16_t seq; 1490 struct txp_rsp_desc **rspp; 1491 { 1492 struct txp_hostvar *hv = sc->sc_hostvar; 1493 struct txp_rsp_desc *rsp; 1494 1495 while (ridx != hv->hv_resp_write_idx) { 1496 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1497 1498 if (id == rsp->rsp_id && rsp->rsp_seq == seq) { 1499 *rspp = (struct txp_rsp_desc *)malloc( 1500 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1501 M_DEVBUF, M_NOWAIT); 1502 if ((*rspp) == NULL) 1503 return (-1); 1504 txp_rsp_fixup(sc, rsp, *rspp); 1505 return (0); 1506 } 1507 1508 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1509 device_printf(sc->sc_dev, "response error!\n"); 1510 txp_rsp_fixup(sc, rsp, NULL); 1511 ridx = hv->hv_resp_read_idx; 1512 continue; 1513 } 1514 1515 switch (rsp->rsp_id) { 1516 case TXP_CMD_CYCLE_STATISTICS: 1517 case TXP_CMD_MEDIA_STATUS_READ: 1518 break; 1519 case TXP_CMD_HELLO_RESPONSE: 1520 device_printf(sc->sc_dev, "hello\n"); 1521 break; 1522 default: 1523 device_printf(sc->sc_dev, "unknown id(0x%x)\n", 1524 rsp->rsp_id); 1525 } 1526 1527 txp_rsp_fixup(sc, rsp, NULL); 1528 ridx = hv->hv_resp_read_idx; 1529 hv->hv_resp_read_idx = ridx; 1530 } 1531 1532 return (0); 1533 } 1534 1535 static void 1536 txp_rsp_fixup(sc, rsp, dst) 1537 struct txp_softc *sc; 1538 struct txp_rsp_desc *rsp, *dst; 1539 { 1540 struct txp_rsp_desc *src = rsp; 1541 struct txp_hostvar *hv = sc->sc_hostvar; 1542 u_int32_t i, ridx; 1543 1544 ridx = hv->hv_resp_read_idx; 1545 1546 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1547 if (dst != NULL) 1548 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1549 ridx += sizeof(struct txp_rsp_desc); 1550 if (ridx == sc->sc_rspring.size) { 1551 src = sc->sc_rspring.base; 1552 ridx = 0; 1553 } else 1554 src++; 1555 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx; 1556 } 1557 1558 hv->hv_resp_read_idx = ridx; 1559 } 1560 1561 static int 1562 txp_cmd_desc_numfree(sc) 1563 struct txp_softc *sc; 1564 { 1565 struct txp_hostvar *hv = sc->sc_hostvar; 1566 struct txp_boot_record *br = sc->sc_boot; 1567 u_int32_t widx, ridx, nfree; 1568 1569 widx = sc->sc_cmdring.lastwrite; 1570 ridx = hv->hv_cmd_read_idx; 1571 1572 if (widx == ridx) { 1573 /* Ring is completely free */ 1574 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc); 1575 } else { 1576 if (widx > ridx) 1577 nfree = br->br_cmd_siz - 1578 (widx - ridx + sizeof(struct txp_cmd_desc)); 1579 else 1580 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1581 } 1582 1583 return (nfree / sizeof(struct txp_cmd_desc)); 1584 } 1585 1586 static void 1587 txp_stop(sc) 1588 struct txp_softc *sc; 1589 { 1590 struct ifnet *ifp; 1591 1592 ifp = &sc->sc_arpcom.ac_if; 1593 1594 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1595 1596 untimeout(txp_tick, sc, sc->sc_tick); 1597 1598 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1599 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1600 1601 txp_rxring_empty(sc); 1602 1603 return; 1604 } 1605 1606 static void 1607 txp_watchdog(ifp) 1608 struct ifnet *ifp; 1609 { 1610 return; 1611 } 1612 1613 static int 1614 txp_ifmedia_upd(ifp) 1615 struct ifnet *ifp; 1616 { 1617 struct txp_softc *sc = ifp->if_softc; 1618 struct ifmedia *ifm = &sc->sc_ifmedia; 1619 u_int16_t new_xcvr; 1620 1621 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1622 return (EINVAL); 1623 1624 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1625 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1626 new_xcvr = TXP_XCVR_10_FDX; 1627 else 1628 new_xcvr = TXP_XCVR_10_HDX; 1629 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1630 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1631 new_xcvr = TXP_XCVR_100_FDX; 1632 else 1633 new_xcvr = TXP_XCVR_100_HDX; 1634 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1635 new_xcvr = TXP_XCVR_AUTO; 1636 } else 1637 return (EINVAL); 1638 1639 /* nothing to do */ 1640 if (sc->sc_xcvr == new_xcvr) 1641 return (0); 1642 1643 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1644 NULL, NULL, NULL, 0); 1645 sc->sc_xcvr = new_xcvr; 1646 1647 return (0); 1648 } 1649 1650 static void 1651 txp_ifmedia_sts(ifp, ifmr) 1652 struct ifnet *ifp; 1653 struct ifmediareq *ifmr; 1654 { 1655 struct txp_softc *sc = ifp->if_softc; 1656 struct ifmedia *ifm = &sc->sc_ifmedia; 1657 u_int16_t bmsr, bmcr, anlpar; 1658 1659 ifmr->ifm_status = IFM_AVALID; 1660 ifmr->ifm_active = IFM_ETHER; 1661 1662 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1663 &bmsr, NULL, NULL, 1)) 1664 goto bail; 1665 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1666 &bmsr, NULL, NULL, 1)) 1667 goto bail; 1668 1669 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1670 &bmcr, NULL, NULL, 1)) 1671 goto bail; 1672 1673 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1674 &anlpar, NULL, NULL, 1)) 1675 goto bail; 1676 1677 if (bmsr & BMSR_LINK) 1678 ifmr->ifm_status |= IFM_ACTIVE; 1679 1680 if (bmcr & BMCR_ISO) { 1681 ifmr->ifm_active |= IFM_NONE; 1682 ifmr->ifm_status = 0; 1683 return; 1684 } 1685 1686 if (bmcr & BMCR_LOOP) 1687 ifmr->ifm_active |= IFM_LOOP; 1688 1689 if (bmcr & BMCR_AUTOEN) { 1690 if ((bmsr & BMSR_ACOMP) == 0) { 1691 ifmr->ifm_active |= IFM_NONE; 1692 return; 1693 } 1694 1695 if (anlpar & ANLPAR_T4) 1696 ifmr->ifm_active |= IFM_100_T4; 1697 else if (anlpar & ANLPAR_TX_FD) 1698 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1699 else if (anlpar & ANLPAR_TX) 1700 ifmr->ifm_active |= IFM_100_TX; 1701 else if (anlpar & ANLPAR_10_FD) 1702 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1703 else if (anlpar & ANLPAR_10) 1704 ifmr->ifm_active |= IFM_10_T; 1705 else 1706 ifmr->ifm_active |= IFM_NONE; 1707 } else 1708 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1709 return; 1710 1711 bail: 1712 ifmr->ifm_active |= IFM_NONE; 1713 ifmr->ifm_status &= ~IFM_AVALID; 1714 } 1715 1716 #ifdef TXP_DEBUG 1717 static void 1718 txp_show_descriptor(d) 1719 void *d; 1720 { 1721 struct txp_cmd_desc *cmd = d; 1722 struct txp_rsp_desc *rsp = d; 1723 struct txp_tx_desc *txd = d; 1724 struct txp_frag_desc *frgd = d; 1725 1726 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1727 case CMD_FLAGS_TYPE_CMD: 1728 /* command descriptor */ 1729 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1730 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1731 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1732 break; 1733 case CMD_FLAGS_TYPE_RESP: 1734 /* response descriptor */ 1735 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1736 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq, 1737 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3); 1738 break; 1739 case CMD_FLAGS_TYPE_DATA: 1740 /* data header (assuming tx for now) */ 1741 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1742 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1743 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1744 break; 1745 case CMD_FLAGS_TYPE_FRAG: 1746 /* fragment descriptor */ 1747 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1748 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1749 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1750 break; 1751 default: 1752 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1753 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1754 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1755 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1756 break; 1757 } 1758 } 1759 #endif 1760 1761 static void 1762 txp_set_filter(sc) 1763 struct txp_softc *sc; 1764 { 1765 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1766 u_int32_t crc, carry, hashbit, hash[2]; 1767 u_int16_t filter; 1768 u_int8_t octet; 1769 int i, j, mcnt = 0; 1770 struct ifmultiaddr *ifma; 1771 char *enm; 1772 1773 if (ifp->if_flags & IFF_PROMISC) { 1774 filter = TXP_RXFILT_PROMISC; 1775 goto setit; 1776 } 1777 1778 filter = TXP_RXFILT_DIRECT; 1779 1780 if (ifp->if_flags & IFF_BROADCAST) 1781 filter |= TXP_RXFILT_BROADCAST; 1782 1783 if (ifp->if_flags & IFF_ALLMULTI) 1784 filter |= TXP_RXFILT_ALLMULTI; 1785 else { 1786 hash[0] = hash[1] = 0; 1787 1788 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1789 ifma = ifma->ifma_link.le_next) { 1790 if (ifma->ifma_addr->sa_family != AF_LINK) 1791 continue; 1792 1793 enm = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1794 mcnt++; 1795 crc = 0xffffffff; 1796 1797 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1798 octet = enm[i]; 1799 for (j = 0; j < 8; j++) { 1800 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1801 (octet & 1); 1802 crc <<= 1; 1803 octet >>= 1; 1804 if (carry) 1805 crc = (crc ^ TXP_POLYNOMIAL) | 1806 carry; 1807 } 1808 } 1809 hashbit = (u_int16_t)(crc & (64 - 1)); 1810 hash[hashbit / 32] |= (1 << hashbit % 32); 1811 } 1812 1813 if (mcnt > 0) { 1814 filter |= TXP_RXFILT_HASHMULTI; 1815 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1816 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1817 } 1818 } 1819 1820 setit: 1821 1822 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1823 NULL, NULL, NULL, 1); 1824 1825 return; 1826 } 1827 1828 static void 1829 txp_capabilities(sc) 1830 struct txp_softc *sc; 1831 { 1832 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1833 struct txp_rsp_desc *rsp = NULL; 1834 struct txp_ext_desc *ext; 1835 1836 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1837 goto out; 1838 1839 if (rsp->rsp_numdesc != 1) 1840 goto out; 1841 ext = (struct txp_ext_desc *)(rsp + 1); 1842 1843 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1844 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1845 ifp->if_capabilities = 0; 1846 1847 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1848 sc->sc_tx_capability |= OFFLOAD_VLAN; 1849 sc->sc_rx_capability |= OFFLOAD_VLAN; 1850 } 1851 1852 #if 0 1853 /* not ready yet */ 1854 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1855 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1856 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1857 ifp->if_capabilities |= IFCAP_IPSEC; 1858 } 1859 #endif 1860 1861 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1862 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1863 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1864 ifp->if_capabilities |= IFCAP_HWCSUM; 1865 ifp->if_hwassist |= CSUM_IP; 1866 } 1867 1868 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1869 #if 0 1870 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1871 #endif 1872 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1873 ifp->if_capabilities |= IFCAP_HWCSUM; 1874 } 1875 1876 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1877 #if 0 1878 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1879 #endif 1880 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1881 ifp->if_capabilities |= IFCAP_HWCSUM; 1882 } 1883 ifp->if_capenable = ifp->if_capabilities; 1884 1885 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1886 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1887 goto out; 1888 1889 out: 1890 if (rsp != NULL) 1891 free(rsp, M_DEVBUF); 1892 1893 return; 1894 } 1895