1*86d7f5d3SJohn Marino /* $OpenBSD: if_txpreg.h,v 1.30 2001/06/23 04:18:02 jason Exp $ */ 2*86d7f5d3SJohn Marino /* $FreeBSD: src/sys/dev/txp/if_txpreg.h,v 1.2.2.1 2001/07/30 17:31:39 wpaul Exp $ */ 3*86d7f5d3SJohn Marino /* $DragonFly: src/sys/dev/netif/txp/if_txpreg.h,v 1.6 2006/08/01 18:10:40 swildner Exp $ */ 4*86d7f5d3SJohn Marino 5*86d7f5d3SJohn Marino /* 6*86d7f5d3SJohn Marino * Copyright (c) 2001 Aaron Campbell <aaron@monkey.org>. 7*86d7f5d3SJohn Marino * All rights reserved. 8*86d7f5d3SJohn Marino * 9*86d7f5d3SJohn Marino * Redistribution and use in source and binary forms, with or without 10*86d7f5d3SJohn Marino * modification, are permitted provided that the following conditions 11*86d7f5d3SJohn Marino * are met: 12*86d7f5d3SJohn Marino * 1. Redistributions of source code must retain the above copyright 13*86d7f5d3SJohn Marino * notice, this list of conditions and the following disclaimer. 14*86d7f5d3SJohn Marino * 2. Redistributions in binary form must reproduce the above copyright 15*86d7f5d3SJohn Marino * notice, this list of conditions and the following disclaimer in the 16*86d7f5d3SJohn Marino * documentation and/or other materials provided with the distribution. 17*86d7f5d3SJohn Marino * 3. All advertising materials mentioning features or use of this software 18*86d7f5d3SJohn Marino * must display the following acknowledgement: 19*86d7f5d3SJohn Marino * This product includes software developed by Aaron Campbell. 20*86d7f5d3SJohn Marino * 4. The name of the author may not be used to endorse or promote products 21*86d7f5d3SJohn Marino * derived from this software without specific prior written permission. 22*86d7f5d3SJohn Marino * 23*86d7f5d3SJohn Marino * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24*86d7f5d3SJohn Marino * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25*86d7f5d3SJohn Marino * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26*86d7f5d3SJohn Marino * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 27*86d7f5d3SJohn Marino * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28*86d7f5d3SJohn Marino * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29*86d7f5d3SJohn Marino * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30*86d7f5d3SJohn Marino * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 31*86d7f5d3SJohn Marino * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 32*86d7f5d3SJohn Marino * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33*86d7f5d3SJohn Marino * THE POSSIBILITY OF SUCH DAMAGE. 34*86d7f5d3SJohn Marino */ 35*86d7f5d3SJohn Marino 36*86d7f5d3SJohn Marino #define TXP_PCI_LOMEM 0x14 /* pci conf, memory map BAR */ 37*86d7f5d3SJohn Marino #define TXP_PCI_LOIO 0x10 /* pci conf, IO map BAR */ 38*86d7f5d3SJohn Marino #define TXP_PCI_INTLINE 0x3C 39*86d7f5d3SJohn Marino 40*86d7f5d3SJohn Marino /* 41*86d7f5d3SJohn Marino * Typhoon registers. 42*86d7f5d3SJohn Marino */ 43*86d7f5d3SJohn Marino #define TXP_SRR 0x00 /* soft reset register */ 44*86d7f5d3SJohn Marino #define TXP_ISR 0x04 /* interrupt status register */ 45*86d7f5d3SJohn Marino #define TXP_IER 0x08 /* interrupt enable register */ 46*86d7f5d3SJohn Marino #define TXP_IMR 0x0c /* interrupt mask register */ 47*86d7f5d3SJohn Marino #define TXP_SIR 0x10 /* self interrupt register */ 48*86d7f5d3SJohn Marino #define TXP_H2A_7 0x14 /* host->arm comm 7 */ 49*86d7f5d3SJohn Marino #define TXP_H2A_6 0x18 /* host->arm comm 6 */ 50*86d7f5d3SJohn Marino #define TXP_H2A_5 0x1c /* host->arm comm 5 */ 51*86d7f5d3SJohn Marino #define TXP_H2A_4 0x20 /* host->arm comm 4 */ 52*86d7f5d3SJohn Marino #define TXP_H2A_3 0x24 /* host->arm comm 3 */ 53*86d7f5d3SJohn Marino #define TXP_H2A_2 0x28 /* host->arm comm 2 */ 54*86d7f5d3SJohn Marino #define TXP_H2A_1 0x2c /* host->arm comm 1 */ 55*86d7f5d3SJohn Marino #define TXP_H2A_0 0x30 /* host->arm comm 0 */ 56*86d7f5d3SJohn Marino #define TXP_A2H_3 0x34 /* arm->host comm 3 */ 57*86d7f5d3SJohn Marino #define TXP_A2H_2 0x38 /* arm->host comm 2 */ 58*86d7f5d3SJohn Marino #define TXP_A2H_1 0x3c /* arm->host comm 1 */ 59*86d7f5d3SJohn Marino #define TXP_A2H_0 0x40 /* arm->host comm 0 */ 60*86d7f5d3SJohn Marino 61*86d7f5d3SJohn Marino /* 62*86d7f5d3SJohn Marino * interrupt bits (IMR, ISR, IER) 63*86d7f5d3SJohn Marino */ 64*86d7f5d3SJohn Marino #define TXP_INT_RESERVED 0xffff0000 65*86d7f5d3SJohn Marino #define TXP_INT_A2H_7 0x00008000 /* arm->host comm 7 */ 66*86d7f5d3SJohn Marino #define TXP_INT_A2H_6 0x00004000 /* arm->host comm 6 */ 67*86d7f5d3SJohn Marino #define TXP_INT_A2H_5 0x00002000 /* arm->host comm 5 */ 68*86d7f5d3SJohn Marino #define TXP_INT_A2H_4 0x00001000 /* arm->host comm 4 */ 69*86d7f5d3SJohn Marino #define TXP_INT_SELF 0x00000800 /* self interrupt */ 70*86d7f5d3SJohn Marino #define TXP_INT_PCI_TABORT 0x00000400 /* pci target abort */ 71*86d7f5d3SJohn Marino #define TXP_INT_PCI_MABORT 0x00000200 /* pci master abort */ 72*86d7f5d3SJohn Marino #define TXP_INT_DMA3 0x00000100 /* dma3 done */ 73*86d7f5d3SJohn Marino #define TXP_INT_DMA2 0x00000080 /* dma2 done */ 74*86d7f5d3SJohn Marino #define TXP_INT_DMA1 0x00000040 /* dma1 done */ 75*86d7f5d3SJohn Marino #define TXP_INT_DMA0 0x00000020 /* dma0 done */ 76*86d7f5d3SJohn Marino #define TXP_INT_A2H_3 0x00000010 /* arm->host comm 3 */ 77*86d7f5d3SJohn Marino #define TXP_INT_A2H_2 0x00000008 /* arm->host comm 2 */ 78*86d7f5d3SJohn Marino #define TXP_INT_A2H_1 0x00000004 /* arm->host comm 1 */ 79*86d7f5d3SJohn Marino #define TXP_INT_A2H_0 0x00000002 /* arm->host comm 0 */ 80*86d7f5d3SJohn Marino #define TXP_INT_LATCH 0x00000001 /* interrupt latch */ 81*86d7f5d3SJohn Marino 82*86d7f5d3SJohn Marino /* 83*86d7f5d3SJohn Marino * soft reset register (SRR) 84*86d7f5d3SJohn Marino */ 85*86d7f5d3SJohn Marino #define TXP_SRR_ALL 0x0000007f /* full reset */ 86*86d7f5d3SJohn Marino 87*86d7f5d3SJohn Marino /* 88*86d7f5d3SJohn Marino * Typhoon boot commands. 89*86d7f5d3SJohn Marino */ 90*86d7f5d3SJohn Marino #define TXP_BOOTCMD_NULL 0x00 91*86d7f5d3SJohn Marino #define TXP_BOOTCMD_DOWNLOAD_COMPLETE 0xfb 92*86d7f5d3SJohn Marino #define TXP_BOOTCMD_SEGMENT_AVAILABLE 0xfc 93*86d7f5d3SJohn Marino #define TXP_BOOTCMD_RUNTIME_IMAGE 0xfd 94*86d7f5d3SJohn Marino #define TXP_BOOTCMD_REGISTER_BOOT_RECORD 0xff 95*86d7f5d3SJohn Marino 96*86d7f5d3SJohn Marino /* 97*86d7f5d3SJohn Marino * Typhoon runtime commands. 98*86d7f5d3SJohn Marino */ 99*86d7f5d3SJohn Marino #define TXP_CMD_GLOBAL_RESET 0x00 100*86d7f5d3SJohn Marino #define TXP_CMD_TX_ENABLE 0x01 101*86d7f5d3SJohn Marino #define TXP_CMD_TX_DISABLE 0x02 102*86d7f5d3SJohn Marino #define TXP_CMD_RX_ENABLE 0x03 103*86d7f5d3SJohn Marino #define TXP_CMD_RX_DISABLE 0x04 104*86d7f5d3SJohn Marino #define TXP_CMD_RX_FILTER_WRITE 0x05 105*86d7f5d3SJohn Marino #define TXP_CMD_RX_FILTER_READ 0x06 106*86d7f5d3SJohn Marino #define TXP_CMD_READ_STATISTICS 0x07 107*86d7f5d3SJohn Marino #define TXP_CMD_CYCLE_STATISTICS 0x08 108*86d7f5d3SJohn Marino #define TXP_CMD_CLEAR_STATISTICS 0x09 109*86d7f5d3SJohn Marino #define TXP_CMD_MEMORY_READ 0x0a 110*86d7f5d3SJohn Marino #define TXP_CMD_MEMORY_WRITE_SINGLE 0x0b 111*86d7f5d3SJohn Marino #define TXP_CMD_VARIABLE_SECTION_READ 0x0c 112*86d7f5d3SJohn Marino #define TXP_CMD_VARIABLE_SECTION_WRITE 0x0d 113*86d7f5d3SJohn Marino #define TXP_CMD_STATIC_SECTION_READ 0x0e 114*86d7f5d3SJohn Marino #define TXP_CMD_STATIC_SECTION_WRITE 0x0f 115*86d7f5d3SJohn Marino #define TXP_CMD_IMAGE_SECTION_PROGRAM 0x10 116*86d7f5d3SJohn Marino #define TXP_CMD_NVRAM_PAGE_READ 0x11 117*86d7f5d3SJohn Marino #define TXP_CMD_NVRAM_PAGE_WRITE 0x12 118*86d7f5d3SJohn Marino #define TXP_CMD_XCVR_SELECT 0x13 119*86d7f5d3SJohn Marino #define TXP_CMD_TEST_MUX 0x14 120*86d7f5d3SJohn Marino #define TXP_CMD_PHYLOOPBACK_ENABLE 0x15 121*86d7f5d3SJohn Marino #define TXP_CMD_PHYLOOPBACK_DISABLE 0x16 122*86d7f5d3SJohn Marino #define TXP_CMD_MAC_CONTROL_READ 0x17 123*86d7f5d3SJohn Marino #define TXP_CMD_MAC_CONTROL_WRITE 0x18 124*86d7f5d3SJohn Marino #define TXP_CMD_MAX_PKT_SIZE_READ 0x19 125*86d7f5d3SJohn Marino #define TXP_CMD_MAX_PKT_SIZE_WRITE 0x1a 126*86d7f5d3SJohn Marino #define TXP_CMD_MEDIA_STATUS_READ 0x1b 127*86d7f5d3SJohn Marino #define TXP_CMD_MEDIA_STATUS_WRITE 0x1c 128*86d7f5d3SJohn Marino #define TXP_CMD_NETWORK_DIAGS_READ 0x1d 129*86d7f5d3SJohn Marino #define TXP_CMD_NETWORK_DIAGS_WRITE 0x1e 130*86d7f5d3SJohn Marino #define TXP_CMD_PHY_MGMT_READ 0x1f 131*86d7f5d3SJohn Marino #define TXP_CMD_PHY_MGMT_WRITE 0x20 132*86d7f5d3SJohn Marino #define TXP_CMD_VARIABLE_PARAMETER_READ 0x21 133*86d7f5d3SJohn Marino #define TXP_CMD_VARIABLE_PARAMETER_WRITE 0x22 134*86d7f5d3SJohn Marino #define TXP_CMD_GOTO_SLEEP 0x23 135*86d7f5d3SJohn Marino #define TXP_CMD_FIREWALL_CONTROL 0x24 136*86d7f5d3SJohn Marino #define TXP_CMD_MCAST_HASH_MASK_WRITE 0x25 137*86d7f5d3SJohn Marino #define TXP_CMD_STATION_ADDRESS_WRITE 0x26 138*86d7f5d3SJohn Marino #define TXP_CMD_STATION_ADDRESS_READ 0x27 139*86d7f5d3SJohn Marino #define TXP_CMD_STATION_MASK_WRITE 0x28 140*86d7f5d3SJohn Marino #define TXP_CMD_STATION_MASK_READ 0x29 141*86d7f5d3SJohn Marino #define TXP_CMD_VLAN_ETHER_TYPE_READ 0x2a 142*86d7f5d3SJohn Marino #define TXP_CMD_VLAN_ETHER_TYPE_WRITE 0x2b 143*86d7f5d3SJohn Marino #define TXP_CMD_VLAN_MASK_READ 0x2c 144*86d7f5d3SJohn Marino #define TXP_CMD_VLAN_MASK_WRITE 0x2d 145*86d7f5d3SJohn Marino #define TXP_CMD_BCAST_THROTTLE_WRITE 0x2e 146*86d7f5d3SJohn Marino #define TXP_CMD_BCAST_THROTTLE_READ 0x2f 147*86d7f5d3SJohn Marino #define TXP_CMD_DHCP_PREVENT_WRITE 0x30 148*86d7f5d3SJohn Marino #define TXP_CMD_DHCP_PREVENT_READ 0x31 149*86d7f5d3SJohn Marino #define TXP_CMD_RECV_BUFFER_CONTROL 0x32 150*86d7f5d3SJohn Marino #define TXP_CMD_SOFTWARE_RESET 0x33 151*86d7f5d3SJohn Marino #define TXP_CMD_CREATE_SA 0x34 152*86d7f5d3SJohn Marino #define TXP_CMD_DELETE_SA 0x35 153*86d7f5d3SJohn Marino #define TXP_CMD_ENABLE_RX_IP_OPTION 0x36 154*86d7f5d3SJohn Marino #define TXP_CMD_RANDOM_NUMBER_CONTROL 0x37 155*86d7f5d3SJohn Marino #define TXP_CMD_RANDOM_NUMBER_READ 0x38 156*86d7f5d3SJohn Marino #define TXP_CMD_MATRIX_TABLE_MODE_WRITE 0x39 157*86d7f5d3SJohn Marino #define TXP_CMD_MATRIX_DETAIL_READ 0x3a 158*86d7f5d3SJohn Marino #define TXP_CMD_FILTER_ARRAY_READ 0x3b 159*86d7f5d3SJohn Marino #define TXP_CMD_FILTER_DETAIL_READ 0x3c 160*86d7f5d3SJohn Marino #define TXP_CMD_FILTER_TABLE_MODE_WRITE 0x3d 161*86d7f5d3SJohn Marino #define TXP_CMD_FILTER_TCL_WRITE 0x3e 162*86d7f5d3SJohn Marino #define TXP_CMD_FILTER_TBL_READ 0x3f 163*86d7f5d3SJohn Marino #define TXP_CMD_FILTER_DEFINE 0x45 164*86d7f5d3SJohn Marino #define TXP_CMD_ADD_WAKEUP_PKT 0x46 165*86d7f5d3SJohn Marino #define TXP_CMD_ADD_SLEEP_PKT 0x47 166*86d7f5d3SJohn Marino #define TXP_CMD_ENABLE_SLEEP_EVENTS 0x48 167*86d7f5d3SJohn Marino #define TXP_CMD_ENABLE_WAKEUP_EVENTS 0x49 168*86d7f5d3SJohn Marino #define TXP_CMD_GET_IP_ADDRESS 0x4a 169*86d7f5d3SJohn Marino #define TXP_CMD_READ_PCI_REG 0x4c 170*86d7f5d3SJohn Marino #define TXP_CMD_WRITE_PCI_REG 0x4d 171*86d7f5d3SJohn Marino #define TXP_CMD_OFFLOAD_READ 0x4e 172*86d7f5d3SJohn Marino #define TXP_CMD_OFFLOAD_WRITE 0x4f 173*86d7f5d3SJohn Marino #define TXP_CMD_HELLO_RESPONSE 0x57 174*86d7f5d3SJohn Marino #define TXP_CMD_ENABLE_RX_FILTER 0x58 175*86d7f5d3SJohn Marino #define TXP_CMD_RX_FILTER_CAPABILITY 0x59 176*86d7f5d3SJohn Marino #define TXP_CMD_HALT 0x5d 177*86d7f5d3SJohn Marino #define TXP_CMD_READ_IPSEC_INFO 0x54 178*86d7f5d3SJohn Marino #define TXP_CMD_GET_IPSEC_ENABLE 0x67 179*86d7f5d3SJohn Marino #define TXP_CMD_INVALID 0xffff 180*86d7f5d3SJohn Marino 181*86d7f5d3SJohn Marino #define TXP_FRAGMENT 0x0000 182*86d7f5d3SJohn Marino #define TXP_TXFRAME 0x0001 183*86d7f5d3SJohn Marino #define TXP_COMMAND 0x0002 184*86d7f5d3SJohn Marino #define TXP_OPTION 0x0003 185*86d7f5d3SJohn Marino #define TXP_RECEIVE 0x0004 186*86d7f5d3SJohn Marino #define TXP_RESPONSE 0x0005 187*86d7f5d3SJohn Marino 188*86d7f5d3SJohn Marino #define TXP_TYPE_IPSEC 0x0000 189*86d7f5d3SJohn Marino #define TXP_TYPE_TCPSEGMENT 0x0001 190*86d7f5d3SJohn Marino 191*86d7f5d3SJohn Marino #define TXP_PFLAG_NOCRC 0x0000 192*86d7f5d3SJohn Marino #define TXP_PFLAG_IPCKSUM 0x0001 193*86d7f5d3SJohn Marino #define TXP_PFLAG_TCPCKSUM 0x0002 194*86d7f5d3SJohn Marino #define TXP_PFLAG_TCPSEGMENT 0x0004 195*86d7f5d3SJohn Marino #define TXP_PFLAG_INSERTVLAN 0x0008 196*86d7f5d3SJohn Marino #define TXP_PFLAG_IPSEC 0x0010 197*86d7f5d3SJohn Marino #define TXP_PFLAG_PRIORITY 0x0020 198*86d7f5d3SJohn Marino #define TXP_PFLAG_UDPCKSUM 0x0040 199*86d7f5d3SJohn Marino #define TXP_PFLAG_PADFRAME 0x0080 200*86d7f5d3SJohn Marino 201*86d7f5d3SJohn Marino #define TXP_MISC_FIRSTDESC 0x0000 202*86d7f5d3SJohn Marino #define TXP_MISC_LASTDESC 0x0001 203*86d7f5d3SJohn Marino 204*86d7f5d3SJohn Marino #define TXP_ERR_INTERNAL 0x0000 205*86d7f5d3SJohn Marino #define TXP_ERR_FIFOUNDERRUN 0x0001 206*86d7f5d3SJohn Marino #define TXP_ERR_BADSSD 0x0002 207*86d7f5d3SJohn Marino #define TXP_ERR_RUNT 0x0003 208*86d7f5d3SJohn Marino #define TXP_ERR_CRC 0x0004 209*86d7f5d3SJohn Marino #define TXP_ERR_OVERSIZE 0x0005 210*86d7f5d3SJohn Marino #define TXP_ERR_ALIGNMENT 0x0006 211*86d7f5d3SJohn Marino #define TXP_ERR_DRIBBLEBIT 0x0007 212*86d7f5d3SJohn Marino 213*86d7f5d3SJohn Marino #define TXP_PROTO_UNKNOWN 0x0000 214*86d7f5d3SJohn Marino #define TXP_PROTO_IP 0x0001 215*86d7f5d3SJohn Marino #define TXP_PROTO_IPX 0x0002 216*86d7f5d3SJohn Marino #define TXP_PROTO_RESERVED 0x0003 217*86d7f5d3SJohn Marino 218*86d7f5d3SJohn Marino #define TXP_STAT_PROTO 0x0001 219*86d7f5d3SJohn Marino #define TXP_STAT_VLAN 0x0002 220*86d7f5d3SJohn Marino #define TXP_STAT_IPFRAGMENT 0x0004 221*86d7f5d3SJohn Marino #define TXP_STAT_IPSEC 0x0008 222*86d7f5d3SJohn Marino #define TXP_STAT_IPCKSUMBAD 0x0010 223*86d7f5d3SJohn Marino #define TXP_STAT_TCPCKSUMBAD 0x0020 224*86d7f5d3SJohn Marino #define TXP_STAT_UDPCKSUMBAD 0x0040 225*86d7f5d3SJohn Marino #define TXP_STAT_IPCKSUMGOOD 0x0080 226*86d7f5d3SJohn Marino #define TXP_STAT_TCPCKSUMGOOD 0x0100 227*86d7f5d3SJohn Marino #define TXP_STAT_UDPCKSUMGOOD 0x0200 228*86d7f5d3SJohn Marino 229*86d7f5d3SJohn Marino struct txp_tx_desc { 230*86d7f5d3SJohn Marino volatile u_int8_t tx_flags; /* type/descriptor flags */ 231*86d7f5d3SJohn Marino volatile u_int8_t tx_numdesc; /* number of descriptors */ 232*86d7f5d3SJohn Marino volatile u_int16_t tx_totlen; /* total packet length */ 233*86d7f5d3SJohn Marino volatile u_int32_t tx_addrlo; /* virt addr low word */ 234*86d7f5d3SJohn Marino volatile u_int32_t tx_addrhi; /* virt addr high word */ 235*86d7f5d3SJohn Marino volatile u_int32_t tx_pflags; /* processing flags */ 236*86d7f5d3SJohn Marino }; 237*86d7f5d3SJohn Marino #define TX_FLAGS_TYPE_M 0x07 /* type mask */ 238*86d7f5d3SJohn Marino #define TX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 239*86d7f5d3SJohn Marino #define TX_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 240*86d7f5d3SJohn Marino #define TX_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 241*86d7f5d3SJohn Marino #define TX_FLAGS_TYPE_OPT 0x03 /* type: options */ 242*86d7f5d3SJohn Marino #define TX_FLAGS_TYPE_RX 0x04 /* type: command */ 243*86d7f5d3SJohn Marino #define TX_FLAGS_TYPE_RESP 0x05 /* type: response */ 244*86d7f5d3SJohn Marino #define TX_FLAGS_RESP 0x40 /* response requested */ 245*86d7f5d3SJohn Marino #define TX_FLAGS_VALID 0x80 /* valid descriptor */ 246*86d7f5d3SJohn Marino 247*86d7f5d3SJohn Marino #define TX_PFLAGS_DNAC 0x00000001 /* do not add crc */ 248*86d7f5d3SJohn Marino #define TX_PFLAGS_IPCKSUM 0x00000002 /* ip checksum */ 249*86d7f5d3SJohn Marino #define TX_PFLAGS_TCPCKSUM 0x00000004 /* tcp checksum */ 250*86d7f5d3SJohn Marino #define TX_PFLAGS_TCPSEG 0x00000008 /* tcp segmentation */ 251*86d7f5d3SJohn Marino #define TX_PFLAGS_VLAN 0x00000010 /* insert vlan */ 252*86d7f5d3SJohn Marino #define TX_PFLAGS_IPSEC 0x00000020 /* perform ipsec */ 253*86d7f5d3SJohn Marino #define TX_PFLAGS_PRIO 0x00000040 /* priority field valid */ 254*86d7f5d3SJohn Marino #define TX_PFLAGS_UDPCKSUM 0x00000080 /* udp checksum */ 255*86d7f5d3SJohn Marino #define TX_PFLAGS_PADFRAME 0x00000100 /* pad frame */ 256*86d7f5d3SJohn Marino #define TX_PFLAGS_VLANTAG_M 0x0ffff000 /* vlan tag mask */ 257*86d7f5d3SJohn Marino #define TX_PFLAGS_VLANPRI_M 0x00700000 /* vlan priority mask */ 258*86d7f5d3SJohn Marino #define TX_PFLAGS_VLANTAG_S 12 /* amount to shift tag */ 259*86d7f5d3SJohn Marino 260*86d7f5d3SJohn Marino struct txp_rx_desc { 261*86d7f5d3SJohn Marino volatile u_int8_t rx_flags; /* type/descriptor flags */ 262*86d7f5d3SJohn Marino volatile u_int8_t rx_numdesc; /* number of descriptors */ 263*86d7f5d3SJohn Marino volatile u_int16_t rx_len; /* frame length */ 264*86d7f5d3SJohn Marino #ifdef notdef 265*86d7f5d3SJohn Marino volatile u_int32_t rx_vaddrlo; /* virtual address, lo word */ 266*86d7f5d3SJohn Marino volatile u_int32_t rx_vaddrhi; /* virtual address, hi word */ 267*86d7f5d3SJohn Marino #endif 268*86d7f5d3SJohn Marino union { 269*86d7f5d3SJohn Marino struct txp_swdesc *rx_sd; 270*86d7f5d3SJohn Marino u_int64_t rx_dummy; 271*86d7f5d3SJohn Marino } txp_rx_u; 272*86d7f5d3SJohn Marino volatile u_int32_t rx_stat; /* status */ 273*86d7f5d3SJohn Marino volatile u_int16_t rx_filter; /* filter status */ 274*86d7f5d3SJohn Marino volatile u_int16_t rx_hash; /* hash status */ 275*86d7f5d3SJohn Marino volatile u_int32_t rx_vlan; /* vlan tag/priority */ 276*86d7f5d3SJohn Marino }; 277*86d7f5d3SJohn Marino 278*86d7f5d3SJohn Marino #define rx_sd txp_rx_u.rx_sd 279*86d7f5d3SJohn Marino 280*86d7f5d3SJohn Marino /* txp_rx_desc.rx_flags */ 281*86d7f5d3SJohn Marino #define RX_FLAGS_TYPE_M 0x07 /* type mask */ 282*86d7f5d3SJohn Marino #define RX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 283*86d7f5d3SJohn Marino #define RX_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 284*86d7f5d3SJohn Marino #define RX_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 285*86d7f5d3SJohn Marino #define RX_FLAGS_TYPE_OPT 0x03 /* type: options */ 286*86d7f5d3SJohn Marino #define RX_FLAGS_TYPE_RX 0x04 /* type: command */ 287*86d7f5d3SJohn Marino #define RX_FLAGS_TYPE_RESP 0x05 /* type: response */ 288*86d7f5d3SJohn Marino #define RX_FLAGS_RCV_TYPE_M 0x18 /* rcvtype mask */ 289*86d7f5d3SJohn Marino #define RX_FLAGS_RCV_TYPE_RX 0x00 /* rcvtype: receive */ 290*86d7f5d3SJohn Marino #define RX_FLAGS_RCV_TYPE_RSP 0x08 /* rcvtype: response */ 291*86d7f5d3SJohn Marino #define RX_FLAGS_ERROR 0x40 /* error in packet */ 292*86d7f5d3SJohn Marino 293*86d7f5d3SJohn Marino /* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR bit set) */ 294*86d7f5d3SJohn Marino #define RX_ERROR_ADAPTER 0x00000000 /* adapter internal error */ 295*86d7f5d3SJohn Marino #define RX_ERROR_FIFO 0x00000001 /* fifo underrun */ 296*86d7f5d3SJohn Marino #define RX_ERROR_BADSSD 0x00000002 /* bad ssd */ 297*86d7f5d3SJohn Marino #define RX_ERROR_RUNT 0x00000003 /* runt packet */ 298*86d7f5d3SJohn Marino #define RX_ERROR_CRC 0x00000004 /* bad crc */ 299*86d7f5d3SJohn Marino #define RX_ERROR_OVERSIZE 0x00000005 /* oversized packet */ 300*86d7f5d3SJohn Marino #define RX_ERROR_ALIGN 0x00000006 /* alignment error */ 301*86d7f5d3SJohn Marino #define RX_ERROR_DRIBBLE 0x00000007 /* dribble bit */ 302*86d7f5d3SJohn Marino 303*86d7f5d3SJohn Marino /* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR not bit set) */ 304*86d7f5d3SJohn Marino #define RX_STAT_PROTO_M 0x00000003 /* protocol mask */ 305*86d7f5d3SJohn Marino #define RX_STAT_PROTO_UK 0x00000000 /* unknown protocol */ 306*86d7f5d3SJohn Marino #define RX_STAT_PROTO_IPX 0x00000001 /* IPX */ 307*86d7f5d3SJohn Marino #define RX_STAT_PROTO_IP 0x00000002 /* IP */ 308*86d7f5d3SJohn Marino #define RX_STAT_PROTO_RSV 0x00000003 /* reserved */ 309*86d7f5d3SJohn Marino #define RX_STAT_VLAN 0x00000004 /* vlan tag (in rxd) */ 310*86d7f5d3SJohn Marino #define RX_STAT_IPFRAG 0x00000008 /* fragment, ipsec not done */ 311*86d7f5d3SJohn Marino #define RX_STAT_IPSEC 0x00000010 /* ipsec decoded packet */ 312*86d7f5d3SJohn Marino #define RX_STAT_IPCKSUMBAD 0x00000020 /* ip checksum failed */ 313*86d7f5d3SJohn Marino #define RX_STAT_UDPCKSUMBAD 0x00000040 /* udp checksum failed */ 314*86d7f5d3SJohn Marino #define RX_STAT_TCPCKSUMBAD 0x00000080 /* tcp checksum failed */ 315*86d7f5d3SJohn Marino #define RX_STAT_IPCKSUMGOOD 0x00000100 /* ip checksum succeeded */ 316*86d7f5d3SJohn Marino #define RX_STAT_UDPCKSUMGOOD 0x00000200 /* udp checksum succeeded */ 317*86d7f5d3SJohn Marino #define RX_STAT_TCPCKSUMGOOD 0x00000400 /* tcp checksum succeeded */ 318*86d7f5d3SJohn Marino 319*86d7f5d3SJohn Marino 320*86d7f5d3SJohn Marino struct txp_rxbuf_desc { 321*86d7f5d3SJohn Marino volatile u_int32_t rb_paddrlo; 322*86d7f5d3SJohn Marino volatile u_int32_t rb_paddrhi; 323*86d7f5d3SJohn Marino #ifdef notdef 324*86d7f5d3SJohn Marino volatile u_int32_t rb_vaddrlo; 325*86d7f5d3SJohn Marino volatile u_int32_t rb_vaddrhi; 326*86d7f5d3SJohn Marino #endif 327*86d7f5d3SJohn Marino union { 328*86d7f5d3SJohn Marino struct txp_swdesc *rb_sd; 329*86d7f5d3SJohn Marino u_int64_t rb_dummy; 330*86d7f5d3SJohn Marino } txp_rb_u; 331*86d7f5d3SJohn Marino }; 332*86d7f5d3SJohn Marino 333*86d7f5d3SJohn Marino #define rb_sd txp_rb_u.rb_sd 334*86d7f5d3SJohn Marino 335*86d7f5d3SJohn Marino /* Extension descriptor */ 336*86d7f5d3SJohn Marino struct txp_ext_desc { 337*86d7f5d3SJohn Marino volatile u_int32_t ext_1; 338*86d7f5d3SJohn Marino volatile u_int32_t ext_2; 339*86d7f5d3SJohn Marino volatile u_int32_t ext_3; 340*86d7f5d3SJohn Marino volatile u_int32_t ext_4; 341*86d7f5d3SJohn Marino }; 342*86d7f5d3SJohn Marino 343*86d7f5d3SJohn Marino struct txp_cmd_desc { 344*86d7f5d3SJohn Marino volatile u_int8_t cmd_flags; 345*86d7f5d3SJohn Marino volatile u_int8_t cmd_numdesc; 346*86d7f5d3SJohn Marino volatile u_int16_t cmd_id; 347*86d7f5d3SJohn Marino volatile u_int16_t cmd_seq; 348*86d7f5d3SJohn Marino volatile u_int16_t cmd_par1; 349*86d7f5d3SJohn Marino volatile u_int32_t cmd_par2; 350*86d7f5d3SJohn Marino volatile u_int32_t cmd_par3; 351*86d7f5d3SJohn Marino }; 352*86d7f5d3SJohn Marino #define CMD_FLAGS_TYPE_M 0x07 /* type mask */ 353*86d7f5d3SJohn Marino #define CMD_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 354*86d7f5d3SJohn Marino #define CMD_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 355*86d7f5d3SJohn Marino #define CMD_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 356*86d7f5d3SJohn Marino #define CMD_FLAGS_TYPE_OPT 0x03 /* type: options */ 357*86d7f5d3SJohn Marino #define CMD_FLAGS_TYPE_RX 0x04 /* type: command */ 358*86d7f5d3SJohn Marino #define CMD_FLAGS_TYPE_RESP 0x05 /* type: response */ 359*86d7f5d3SJohn Marino #define CMD_FLAGS_RESP 0x40 /* response requested */ 360*86d7f5d3SJohn Marino #define CMD_FLAGS_VALID 0x80 /* valid descriptor */ 361*86d7f5d3SJohn Marino 362*86d7f5d3SJohn Marino struct txp_rsp_desc { 363*86d7f5d3SJohn Marino volatile u_int8_t rsp_flags; 364*86d7f5d3SJohn Marino volatile u_int8_t rsp_numdesc; 365*86d7f5d3SJohn Marino volatile u_int16_t rsp_id; 366*86d7f5d3SJohn Marino volatile u_int16_t rsp_seq; 367*86d7f5d3SJohn Marino volatile u_int16_t rsp_par1; 368*86d7f5d3SJohn Marino volatile u_int32_t rsp_par2; 369*86d7f5d3SJohn Marino volatile u_int32_t rsp_par3; 370*86d7f5d3SJohn Marino }; 371*86d7f5d3SJohn Marino #define RSP_FLAGS_TYPE_M 0x07 /* type mask */ 372*86d7f5d3SJohn Marino #define RSP_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 373*86d7f5d3SJohn Marino #define RSP_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 374*86d7f5d3SJohn Marino #define RSP_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 375*86d7f5d3SJohn Marino #define RSP_FLAGS_TYPE_OPT 0x03 /* type: options */ 376*86d7f5d3SJohn Marino #define RSP_FLAGS_TYPE_RX 0x04 /* type: command */ 377*86d7f5d3SJohn Marino #define RSP_FLAGS_TYPE_RESP 0x05 /* type: response */ 378*86d7f5d3SJohn Marino #define RSP_FLAGS_ERROR 0x40 /* response error */ 379*86d7f5d3SJohn Marino 380*86d7f5d3SJohn Marino struct txp_frag_desc { 381*86d7f5d3SJohn Marino volatile u_int8_t frag_flags; /* type/descriptor flags */ 382*86d7f5d3SJohn Marino volatile u_int8_t frag_rsvd1; 383*86d7f5d3SJohn Marino volatile u_int16_t frag_len; /* bytes in this fragment */ 384*86d7f5d3SJohn Marino volatile u_int32_t frag_addrlo; /* phys addr low word */ 385*86d7f5d3SJohn Marino volatile u_int32_t frag_addrhi; /* phys addr high word */ 386*86d7f5d3SJohn Marino volatile u_int32_t frag_rsvd2; 387*86d7f5d3SJohn Marino }; 388*86d7f5d3SJohn Marino #define FRAG_FLAGS_TYPE_M 0x07 /* type mask */ 389*86d7f5d3SJohn Marino #define FRAG_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 390*86d7f5d3SJohn Marino #define FRAG_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 391*86d7f5d3SJohn Marino #define FRAG_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 392*86d7f5d3SJohn Marino #define FRAG_FLAGS_TYPE_OPT 0x03 /* type: options */ 393*86d7f5d3SJohn Marino #define FRAG_FLAGS_TYPE_RX 0x04 /* type: command */ 394*86d7f5d3SJohn Marino #define FRAG_FLAGS_TYPE_RESP 0x05 /* type: response */ 395*86d7f5d3SJohn Marino 396*86d7f5d3SJohn Marino struct txp_opt_desc { 397*86d7f5d3SJohn Marino u_int8_t opt_desctype:3, 398*86d7f5d3SJohn Marino opt_rsvd:1, 399*86d7f5d3SJohn Marino opt_type:4; 400*86d7f5d3SJohn Marino 401*86d7f5d3SJohn Marino u_int8_t opt_num; 402*86d7f5d3SJohn Marino u_int16_t opt_dep1; 403*86d7f5d3SJohn Marino u_int32_t opt_dep2; 404*86d7f5d3SJohn Marino u_int32_t opt_dep3; 405*86d7f5d3SJohn Marino u_int32_t opt_dep4; 406*86d7f5d3SJohn Marino }; 407*86d7f5d3SJohn Marino 408*86d7f5d3SJohn Marino struct txp_ipsec_desc { 409*86d7f5d3SJohn Marino u_int8_t ipsec_desctpe:3, 410*86d7f5d3SJohn Marino ipsec_rsvd:1, 411*86d7f5d3SJohn Marino ipsec_type:4; 412*86d7f5d3SJohn Marino 413*86d7f5d3SJohn Marino u_int8_t ipsec_num; 414*86d7f5d3SJohn Marino u_int16_t ipsec_flags; 415*86d7f5d3SJohn Marino u_int16_t ipsec_ah1; 416*86d7f5d3SJohn Marino u_int16_t ipsec_esp1; 417*86d7f5d3SJohn Marino u_int16_t ipsec_ah2; 418*86d7f5d3SJohn Marino u_int16_t ipsec_esp2; 419*86d7f5d3SJohn Marino u_int32_t ipsec_rsvd1; 420*86d7f5d3SJohn Marino }; 421*86d7f5d3SJohn Marino 422*86d7f5d3SJohn Marino struct txp_tcpseg_desc { 423*86d7f5d3SJohn Marino u_int8_t tcpseg_desctype:3, 424*86d7f5d3SJohn Marino tcpseg_rsvd:1, 425*86d7f5d3SJohn Marino tcpseg_type:4; 426*86d7f5d3SJohn Marino 427*86d7f5d3SJohn Marino u_int8_t tcpseg_num; 428*86d7f5d3SJohn Marino 429*86d7f5d3SJohn Marino u_int16_t tcpseg_mss:12, 430*86d7f5d3SJohn Marino tcpseg_misc:4; 431*86d7f5d3SJohn Marino 432*86d7f5d3SJohn Marino u_int32_t tcpseg_respaddr; 433*86d7f5d3SJohn Marino u_int32_t tcpseg_txbytes; 434*86d7f5d3SJohn Marino u_int32_t tcpseg_lss; 435*86d7f5d3SJohn Marino }; 436*86d7f5d3SJohn Marino 437*86d7f5d3SJohn Marino /* 438*86d7f5d3SJohn Marino * Transceiver types 439*86d7f5d3SJohn Marino */ 440*86d7f5d3SJohn Marino #define TXP_XCVR_10_HDX 0 441*86d7f5d3SJohn Marino #define TXP_XCVR_10_FDX 1 442*86d7f5d3SJohn Marino #define TXP_XCVR_100_HDX 2 443*86d7f5d3SJohn Marino #define TXP_XCVR_100_FDX 3 444*86d7f5d3SJohn Marino #define TXP_XCVR_AUTO 4 445*86d7f5d3SJohn Marino 446*86d7f5d3SJohn Marino #define TXP_MEDIA_CRC 0x0004 /* crc strip disable */ 447*86d7f5d3SJohn Marino #define TXP_MEDIA_CD 0x0010 /* collision detection */ 448*86d7f5d3SJohn Marino #define TXP_MEDIA_CS 0x0020 /* carrier sense */ 449*86d7f5d3SJohn Marino #define TXP_MEDIA_POL 0x0400 /* polarity reversed */ 450*86d7f5d3SJohn Marino #define TXP_MEDIA_NOLINK 0x0800 /* 0 = link, 1 = no link */ 451*86d7f5d3SJohn Marino 452*86d7f5d3SJohn Marino /* 453*86d7f5d3SJohn Marino * receive filter bits (par1 to TXP_CMD_RX_FILTER_{READ|WRITE} 454*86d7f5d3SJohn Marino */ 455*86d7f5d3SJohn Marino #define TXP_RXFILT_DIRECT 0x0001 /* directed packets */ 456*86d7f5d3SJohn Marino #define TXP_RXFILT_ALLMULTI 0x0002 /* all multicast packets */ 457*86d7f5d3SJohn Marino #define TXP_RXFILT_BROADCAST 0x0004 /* broadcast packets */ 458*86d7f5d3SJohn Marino #define TXP_RXFILT_PROMISC 0x0008 /* promiscuous mode */ 459*86d7f5d3SJohn Marino #define TXP_RXFILT_HASHMULTI 0x0010 /* use multicast filter */ 460*86d7f5d3SJohn Marino 461*86d7f5d3SJohn Marino /* 462*86d7f5d3SJohn Marino * boot record (pointers to rings) 463*86d7f5d3SJohn Marino */ 464*86d7f5d3SJohn Marino struct txp_boot_record { 465*86d7f5d3SJohn Marino volatile u_int32_t br_hostvar_lo; /* host ring pointer */ 466*86d7f5d3SJohn Marino volatile u_int32_t br_hostvar_hi; 467*86d7f5d3SJohn Marino volatile u_int32_t br_txlopri_lo; /* tx low pri ring */ 468*86d7f5d3SJohn Marino volatile u_int32_t br_txlopri_hi; 469*86d7f5d3SJohn Marino volatile u_int32_t br_txlopri_siz; 470*86d7f5d3SJohn Marino volatile u_int32_t br_txhipri_lo; /* tx high pri ring */ 471*86d7f5d3SJohn Marino volatile u_int32_t br_txhipri_hi; 472*86d7f5d3SJohn Marino volatile u_int32_t br_txhipri_siz; 473*86d7f5d3SJohn Marino volatile u_int32_t br_rxlopri_lo; /* rx low pri ring */ 474*86d7f5d3SJohn Marino volatile u_int32_t br_rxlopri_hi; 475*86d7f5d3SJohn Marino volatile u_int32_t br_rxlopri_siz; 476*86d7f5d3SJohn Marino volatile u_int32_t br_rxbuf_lo; /* rx buffer ring */ 477*86d7f5d3SJohn Marino volatile u_int32_t br_rxbuf_hi; 478*86d7f5d3SJohn Marino volatile u_int32_t br_rxbuf_siz; 479*86d7f5d3SJohn Marino volatile u_int32_t br_cmd_lo; /* command ring */ 480*86d7f5d3SJohn Marino volatile u_int32_t br_cmd_hi; 481*86d7f5d3SJohn Marino volatile u_int32_t br_cmd_siz; 482*86d7f5d3SJohn Marino volatile u_int32_t br_resp_lo; /* response ring */ 483*86d7f5d3SJohn Marino volatile u_int32_t br_resp_hi; 484*86d7f5d3SJohn Marino volatile u_int32_t br_resp_siz; 485*86d7f5d3SJohn Marino volatile u_int32_t br_zero_lo; /* zero word */ 486*86d7f5d3SJohn Marino volatile u_int32_t br_zero_hi; 487*86d7f5d3SJohn Marino volatile u_int32_t br_rxhipri_lo; /* rx high pri ring */ 488*86d7f5d3SJohn Marino volatile u_int32_t br_rxhipri_hi; 489*86d7f5d3SJohn Marino volatile u_int32_t br_rxhipri_siz; 490*86d7f5d3SJohn Marino }; 491*86d7f5d3SJohn Marino 492*86d7f5d3SJohn Marino /* 493*86d7f5d3SJohn Marino * hostvar structure (shared with typhoon) 494*86d7f5d3SJohn Marino */ 495*86d7f5d3SJohn Marino struct txp_hostvar { 496*86d7f5d3SJohn Marino volatile u_int32_t hv_rx_hi_read_idx; /* host->arm */ 497*86d7f5d3SJohn Marino volatile u_int32_t hv_rx_lo_read_idx; /* host->arm */ 498*86d7f5d3SJohn Marino volatile u_int32_t hv_rx_buf_write_idx; /* host->arm */ 499*86d7f5d3SJohn Marino volatile u_int32_t hv_resp_read_idx; /* host->arm */ 500*86d7f5d3SJohn Marino volatile u_int32_t hv_tx_lo_desc_read_idx; /* arm->host */ 501*86d7f5d3SJohn Marino volatile u_int32_t hv_tx_hi_desc_read_idx; /* arm->host */ 502*86d7f5d3SJohn Marino volatile u_int32_t hv_rx_lo_write_idx; /* arm->host */ 503*86d7f5d3SJohn Marino volatile u_int32_t hv_rx_buf_read_idx; /* arm->host */ 504*86d7f5d3SJohn Marino volatile u_int32_t hv_cmd_read_idx; /* arm->host */ 505*86d7f5d3SJohn Marino volatile u_int32_t hv_resp_write_idx; /* arm->host */ 506*86d7f5d3SJohn Marino volatile u_int32_t hv_rx_hi_write_idx; /* arm->host */ 507*86d7f5d3SJohn Marino }; 508*86d7f5d3SJohn Marino 509*86d7f5d3SJohn Marino /* 510*86d7f5d3SJohn Marino * TYPHOON status register state (in TXP_A2H_0) 511*86d7f5d3SJohn Marino */ 512*86d7f5d3SJohn Marino #define STAT_ROM_CODE 0x00000001 513*86d7f5d3SJohn Marino #define STAT_ROM_EEPROM_LOAD 0x00000002 514*86d7f5d3SJohn Marino #define STAT_WAITING_FOR_BOOT 0x00000007 515*86d7f5d3SJohn Marino #define STAT_RUNNING 0x00000009 516*86d7f5d3SJohn Marino #define STAT_WAITING_FOR_HOST_REQUEST 0x0000000d 517*86d7f5d3SJohn Marino #define STAT_WAITING_FOR_SEGMENT 0x00000010 518*86d7f5d3SJohn Marino #define STAT_SLEEPING 0x00000011 519*86d7f5d3SJohn Marino #define STAT_HALTED 0x00000014 520*86d7f5d3SJohn Marino 521*86d7f5d3SJohn Marino #define TX_ENTRIES 256 522*86d7f5d3SJohn Marino #define RX_ENTRIES 128 523*86d7f5d3SJohn Marino #define RXBUF_ENTRIES 256 524*86d7f5d3SJohn Marino #define CMD_ENTRIES 32 525*86d7f5d3SJohn Marino #define RSP_ENTRIES 32 526*86d7f5d3SJohn Marino 527*86d7f5d3SJohn Marino #define OFFLOAD_TCPCKSUM 0x00000002 /* tcp checksum */ 528*86d7f5d3SJohn Marino #define OFFLOAD_UDPCKSUM 0x00000004 /* udp checksum */ 529*86d7f5d3SJohn Marino #define OFFLOAD_IPCKSUM 0x00000008 /* ip checksum */ 530*86d7f5d3SJohn Marino #define OFFLOAD_IPSEC 0x00000010 /* ipsec enable */ 531*86d7f5d3SJohn Marino #define OFFLOAD_BCAST 0x00000020 /* broadcast throttle */ 532*86d7f5d3SJohn Marino #define OFFLOAD_DHCP 0x00000040 /* dhcp prevention */ 533*86d7f5d3SJohn Marino #define OFFLOAD_VLAN 0x00000080 /* vlan enable */ 534*86d7f5d3SJohn Marino #define OFFLOAD_FILTER 0x00000100 /* filter enable */ 535*86d7f5d3SJohn Marino #define OFFLOAD_TCPSEG 0x00000200 /* tcp segmentation */ 536*86d7f5d3SJohn Marino #define OFFLOAD_MASK 0xfffffffe /* mask off low bit */ 537*86d7f5d3SJohn Marino 538*86d7f5d3SJohn Marino /* 539*86d7f5d3SJohn Marino * Macros for converting array indices to offsets within the descriptor 540*86d7f5d3SJohn Marino * arrays. The chip operates on offsets, but it's much easier for us 541*86d7f5d3SJohn Marino * to operate on indices. Assumes descriptor entries are 16 bytes. 542*86d7f5d3SJohn Marino */ 543*86d7f5d3SJohn Marino #define TXP_IDX2OFFSET(idx) ((idx) << 4) 544*86d7f5d3SJohn Marino #define TXP_OFFSET2IDX(off) ((off) >> 4) 545*86d7f5d3SJohn Marino 546*86d7f5d3SJohn Marino struct txp_cmd_ring { 547*86d7f5d3SJohn Marino struct txp_cmd_desc *base; 548*86d7f5d3SJohn Marino u_int32_t lastwrite; 549*86d7f5d3SJohn Marino u_int32_t size; 550*86d7f5d3SJohn Marino }; 551*86d7f5d3SJohn Marino 552*86d7f5d3SJohn Marino struct txp_rsp_ring { 553*86d7f5d3SJohn Marino struct txp_rsp_desc *base; 554*86d7f5d3SJohn Marino u_int32_t lastwrite; 555*86d7f5d3SJohn Marino u_int32_t size; 556*86d7f5d3SJohn Marino }; 557*86d7f5d3SJohn Marino 558*86d7f5d3SJohn Marino struct txp_tx_ring { 559*86d7f5d3SJohn Marino struct txp_tx_desc *r_desc; /* base address of descs */ 560*86d7f5d3SJohn Marino u_int32_t r_reg; /* register to activate */ 561*86d7f5d3SJohn Marino u_int32_t r_prod; /* producer */ 562*86d7f5d3SJohn Marino u_int32_t r_cons; /* consumer */ 563*86d7f5d3SJohn Marino u_int32_t r_cnt; /* # descs in use */ 564*86d7f5d3SJohn Marino volatile u_int32_t *r_off; /* hostvar index pointer */ 565*86d7f5d3SJohn Marino }; 566*86d7f5d3SJohn Marino 567*86d7f5d3SJohn Marino struct txp_swdesc { 568*86d7f5d3SJohn Marino struct mbuf * sd_mbuf; 569*86d7f5d3SJohn Marino bus_dmamap_t sd_map; 570*86d7f5d3SJohn Marino }; 571*86d7f5d3SJohn Marino 572*86d7f5d3SJohn Marino struct txp_rx_ring { 573*86d7f5d3SJohn Marino struct txp_rx_desc *r_desc; /* base address of descs */ 574*86d7f5d3SJohn Marino volatile u_int32_t *r_roff; /* hv read offset ptr */ 575*86d7f5d3SJohn Marino volatile u_int32_t *r_woff; /* hv write offset ptr */ 576*86d7f5d3SJohn Marino }; 577*86d7f5d3SJohn Marino 578*86d7f5d3SJohn Marino struct txp_ldata { 579*86d7f5d3SJohn Marino struct txp_boot_record txp_boot; 580*86d7f5d3SJohn Marino struct txp_hostvar txp_hostvar; 581*86d7f5d3SJohn Marino struct txp_tx_desc txp_txhiring[TX_ENTRIES]; 582*86d7f5d3SJohn Marino struct txp_tx_desc txp_txloring[TX_ENTRIES]; 583*86d7f5d3SJohn Marino struct txp_rxbuf_desc txp_rxbufs[RXBUF_ENTRIES]; 584*86d7f5d3SJohn Marino struct txp_rx_desc txp_rxhiring[RX_ENTRIES]; 585*86d7f5d3SJohn Marino struct txp_rx_desc txp_rxloring[RX_ENTRIES]; 586*86d7f5d3SJohn Marino struct txp_cmd_desc txp_cmdring[CMD_ENTRIES]; 587*86d7f5d3SJohn Marino struct txp_rsp_desc txp_rspring[RSP_ENTRIES]; 588*86d7f5d3SJohn Marino u_int32_t txp_zero; 589*86d7f5d3SJohn Marino }; 590*86d7f5d3SJohn Marino 591*86d7f5d3SJohn Marino struct txp_softc { 592*86d7f5d3SJohn Marino struct arpcom sc_arpcom; /* ethernet common */ 593*86d7f5d3SJohn Marino struct txp_hostvar *sc_hostvar; 594*86d7f5d3SJohn Marino struct txp_boot_record *sc_boot; 595*86d7f5d3SJohn Marino bus_space_handle_t sc_bh; /* bus handle (regs) */ 596*86d7f5d3SJohn Marino bus_space_tag_t sc_bt; /* bus tag (regs) */ 597*86d7f5d3SJohn Marino struct resource *sc_res; 598*86d7f5d3SJohn Marino struct resource *sc_irq; 599*86d7f5d3SJohn Marino void *sc_intrhand; 600*86d7f5d3SJohn Marino struct txp_ldata *sc_ldata; 601*86d7f5d3SJohn Marino void *sc_fwbuf; 602*86d7f5d3SJohn Marino int sc_rxbufprod; 603*86d7f5d3SJohn Marino struct txp_cmd_ring sc_cmdring; 604*86d7f5d3SJohn Marino struct txp_rsp_ring sc_rspring; 605*86d7f5d3SJohn Marino struct txp_swdesc sc_txd[TX_ENTRIES]; 606*86d7f5d3SJohn Marino struct callout txp_stat_timer; 607*86d7f5d3SJohn Marino struct ifmedia sc_ifmedia; 608*86d7f5d3SJohn Marino struct txp_tx_ring sc_txhir, sc_txlor; 609*86d7f5d3SJohn Marino struct txp_rxbuf_desc *sc_rxbufs; 610*86d7f5d3SJohn Marino struct txp_rx_ring sc_rxhir, sc_rxlor; 611*86d7f5d3SJohn Marino u_int16_t sc_xcvr; 612*86d7f5d3SJohn Marino u_int16_t sc_seq; 613*86d7f5d3SJohn Marino u_int32_t sc_rx_capability, sc_tx_capability; 614*86d7f5d3SJohn Marino }; 615*86d7f5d3SJohn Marino 616*86d7f5d3SJohn Marino struct txp_fw_file_header { 617*86d7f5d3SJohn Marino u_int8_t magicid[8]; /* TYPHOON\0 */ 618*86d7f5d3SJohn Marino u_int32_t version; 619*86d7f5d3SJohn Marino u_int32_t nsections; 620*86d7f5d3SJohn Marino u_int32_t addr; 621*86d7f5d3SJohn Marino }; 622*86d7f5d3SJohn Marino 623*86d7f5d3SJohn Marino struct txp_fw_section_header { 624*86d7f5d3SJohn Marino u_int32_t nbytes; 625*86d7f5d3SJohn Marino u_int16_t cksum; 626*86d7f5d3SJohn Marino u_int16_t reserved; 627*86d7f5d3SJohn Marino u_int32_t addr; 628*86d7f5d3SJohn Marino }; 629*86d7f5d3SJohn Marino 630*86d7f5d3SJohn Marino #define TXP_MAX_SEGLEN 0xffff 631*86d7f5d3SJohn Marino #define TXP_MAX_PKTLEN 0x0800 632*86d7f5d3SJohn Marino 633*86d7f5d3SJohn Marino #define WRITE_REG(sc,reg,val) \ 634*86d7f5d3SJohn Marino bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val) 635*86d7f5d3SJohn Marino #define READ_REG(sc,reg) \ 636*86d7f5d3SJohn Marino bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, reg) 637*86d7f5d3SJohn Marino 638*86d7f5d3SJohn Marino struct txp_type { 639*86d7f5d3SJohn Marino u_int16_t txp_vid; 640*86d7f5d3SJohn Marino u_int16_t txp_did; 641*86d7f5d3SJohn Marino char *txp_name; 642*86d7f5d3SJohn Marino }; 643