1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $ 33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.5 2003/08/27 09:38:33 rob Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $ 36 */ 37 38 /* 39 * VIA Rhine fast ethernet PCI NIC driver 40 * 41 * Supports various network adapters based on the VIA Rhine 42 * and Rhine II PCI controllers, including the D-Link DFE530TX. 43 * Datasheets are available at http://www.via.com.tw. 44 * 45 * Written by Bill Paul <wpaul@ctr.columbia.edu> 46 * Electrical Engineering Department 47 * Columbia University, New York City 48 */ 49 50 /* 51 * The VIA Rhine controllers are similar in some respects to the 52 * the DEC tulip chips, except less complicated. The controller 53 * uses an MII bus and an external physical layer interface. The 54 * receiver has a one entry perfect filter and a 64-bit hash table 55 * multicast filter. Transmit and receive descriptors are similar 56 * to the tulip. 57 * 58 * The Rhine has a serious flaw in its transmit DMA mechanism: 59 * transmit buffers must be longword aligned. Unfortunately, 60 * FreeBSD doesn't guarantee that mbufs will be filled in starting 61 * at longword boundaries, so we have to do a buffer copy before 62 * transmission. 63 */ 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/sockio.h> 68 #include <sys/mbuf.h> 69 #include <sys/malloc.h> 70 #include <sys/kernel.h> 71 #include <sys/socket.h> 72 73 #include <net/if.h> 74 #include <net/if_arp.h> 75 #include <net/ethernet.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 79 #include <net/bpf.h> 80 81 #include <vm/vm.h> /* for vtophys */ 82 #include <vm/pmap.h> /* for vtophys */ 83 #include <machine/clock.h> /* for DELAY */ 84 #include <machine/bus_pio.h> 85 #include <machine/bus_memio.h> 86 #include <machine/bus.h> 87 #include <machine/resource.h> 88 #include <sys/bus.h> 89 #include <sys/rman.h> 90 91 #include "../mii_layer/mii.h" 92 #include "../mii_layer/miivar.h" 93 94 #include <bus/pci/pcireg.h> 95 #include <bus/pci/pcivar.h> 96 97 #define VR_USEIOSPACE 98 99 #include "if_vrreg.h" 100 101 /* "controller miibus0" required. See GENERIC if you get errors here. */ 102 #include "miibus_if.h" 103 104 #undef VR_USESWSHIFT 105 106 /* 107 * Various supported device vendors/types and their names. 108 */ 109 static struct vr_type vr_devs[] = { 110 { VIA_VENDORID, VIA_DEVICEID_RHINE, 111 "VIA VT3043 Rhine I 10/100BaseTX" }, 112 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 113 "VIA VT86C100A Rhine II 10/100BaseTX" }, 114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 115 "VIA VT6102 Rhine II 10/100BaseTX" }, 116 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 117 "VIA VT6105 Rhine III 10/100BaseTX" }, 118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 119 "VIA VT6105M Rhine III 10/100BaseTX" }, 120 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 121 "Delta Electronics Rhine II 10/100BaseTX" }, 122 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 123 "Addtron Technology Rhine II 10/100BaseTX" }, 124 { 0, 0, NULL } 125 }; 126 127 static int vr_probe (device_t); 128 static int vr_attach (device_t); 129 static int vr_detach (device_t); 130 131 static int vr_newbuf (struct vr_softc *, 132 struct vr_chain_onefrag *, 133 struct mbuf *); 134 static int vr_encap (struct vr_softc *, struct vr_chain *, 135 struct mbuf * ); 136 137 static void vr_rxeof (struct vr_softc *); 138 static void vr_rxeoc (struct vr_softc *); 139 static void vr_txeof (struct vr_softc *); 140 static void vr_txeoc (struct vr_softc *); 141 static void vr_tick (void *); 142 static void vr_intr (void *); 143 static void vr_start (struct ifnet *); 144 static int vr_ioctl (struct ifnet *, u_long, caddr_t); 145 static void vr_init (void *); 146 static void vr_stop (struct vr_softc *); 147 static void vr_watchdog (struct ifnet *); 148 static void vr_shutdown (device_t); 149 static int vr_ifmedia_upd (struct ifnet *); 150 static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 151 152 #ifdef VR_USESWSHIFT 153 static void vr_mii_sync (struct vr_softc *); 154 static void vr_mii_send (struct vr_softc *, u_int32_t, int); 155 #endif 156 static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 157 static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 158 static int vr_miibus_readreg (device_t, int, int); 159 static int vr_miibus_writereg (device_t, int, int, int); 160 static void vr_miibus_statchg (device_t); 161 162 static void vr_setcfg (struct vr_softc *, int); 163 static u_int8_t vr_calchash (u_int8_t *); 164 static void vr_setmulti (struct vr_softc *); 165 static void vr_reset (struct vr_softc *); 166 static int vr_list_rx_init (struct vr_softc *); 167 static int vr_list_tx_init (struct vr_softc *); 168 169 #ifdef VR_USEIOSPACE 170 #define VR_RES SYS_RES_IOPORT 171 #define VR_RID VR_PCI_LOIO 172 #else 173 #define VR_RES SYS_RES_MEMORY 174 #define VR_RID VR_PCI_LOMEM 175 #endif 176 177 static device_method_t vr_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, vr_probe), 180 DEVMETHOD(device_attach, vr_attach), 181 DEVMETHOD(device_detach, vr_detach), 182 DEVMETHOD(device_shutdown, vr_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 190 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 191 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 192 193 { 0, 0 } 194 }; 195 196 static driver_t vr_driver = { 197 "vr", 198 vr_methods, 199 sizeof(struct vr_softc) 200 }; 201 202 static devclass_t vr_devclass; 203 204 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 205 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 206 207 #define VR_SETBIT(sc, reg, x) \ 208 CSR_WRITE_1(sc, reg, \ 209 CSR_READ_1(sc, reg) | x) 210 211 #define VR_CLRBIT(sc, reg, x) \ 212 CSR_WRITE_1(sc, reg, \ 213 CSR_READ_1(sc, reg) & ~x) 214 215 #define VR_SETBIT16(sc, reg, x) \ 216 CSR_WRITE_2(sc, reg, \ 217 CSR_READ_2(sc, reg) | x) 218 219 #define VR_CLRBIT16(sc, reg, x) \ 220 CSR_WRITE_2(sc, reg, \ 221 CSR_READ_2(sc, reg) & ~x) 222 223 #define VR_SETBIT32(sc, reg, x) \ 224 CSR_WRITE_4(sc, reg, \ 225 CSR_READ_4(sc, reg) | x) 226 227 #define VR_CLRBIT32(sc, reg, x) \ 228 CSR_WRITE_4(sc, reg, \ 229 CSR_READ_4(sc, reg) & ~x) 230 231 #define SIO_SET(x) \ 232 CSR_WRITE_1(sc, VR_MIICMD, \ 233 CSR_READ_1(sc, VR_MIICMD) | x) 234 235 #define SIO_CLR(x) \ 236 CSR_WRITE_1(sc, VR_MIICMD, \ 237 CSR_READ_1(sc, VR_MIICMD) & ~x) 238 239 #ifdef VR_USESWSHIFT 240 /* 241 * Sync the PHYs by setting data bit and strobing the clock 32 times. 242 */ 243 static void vr_mii_sync(sc) 244 struct vr_softc *sc; 245 { 246 int i; 247 248 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 249 250 for (i = 0; i < 32; i++) { 251 SIO_SET(VR_MIICMD_CLK); 252 DELAY(1); 253 SIO_CLR(VR_MIICMD_CLK); 254 DELAY(1); 255 } 256 257 return; 258 } 259 260 /* 261 * Clock a series of bits through the MII. 262 */ 263 static void vr_mii_send(sc, bits, cnt) 264 struct vr_softc *sc; 265 u_int32_t bits; 266 int cnt; 267 { 268 int i; 269 270 SIO_CLR(VR_MIICMD_CLK); 271 272 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 273 if (bits & i) { 274 SIO_SET(VR_MIICMD_DATAIN); 275 } else { 276 SIO_CLR(VR_MIICMD_DATAIN); 277 } 278 DELAY(1); 279 SIO_CLR(VR_MIICMD_CLK); 280 DELAY(1); 281 SIO_SET(VR_MIICMD_CLK); 282 } 283 } 284 #endif 285 286 /* 287 * Read an PHY register through the MII. 288 */ 289 static int vr_mii_readreg(sc, frame) 290 struct vr_softc *sc; 291 struct vr_mii_frame *frame; 292 293 #ifdef VR_USESWSHIFT 294 { 295 int i, ack, s; 296 297 s = splimp(); 298 299 /* 300 * Set up frame for RX. 301 */ 302 frame->mii_stdelim = VR_MII_STARTDELIM; 303 frame->mii_opcode = VR_MII_READOP; 304 frame->mii_turnaround = 0; 305 frame->mii_data = 0; 306 307 CSR_WRITE_1(sc, VR_MIICMD, 0); 308 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 309 310 /* 311 * Turn on data xmit. 312 */ 313 SIO_SET(VR_MIICMD_DIR); 314 315 vr_mii_sync(sc); 316 317 /* 318 * Send command/address info. 319 */ 320 vr_mii_send(sc, frame->mii_stdelim, 2); 321 vr_mii_send(sc, frame->mii_opcode, 2); 322 vr_mii_send(sc, frame->mii_phyaddr, 5); 323 vr_mii_send(sc, frame->mii_regaddr, 5); 324 325 /* Idle bit */ 326 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 327 DELAY(1); 328 SIO_SET(VR_MIICMD_CLK); 329 DELAY(1); 330 331 /* Turn off xmit. */ 332 SIO_CLR(VR_MIICMD_DIR); 333 334 /* Check for ack */ 335 SIO_CLR(VR_MIICMD_CLK); 336 DELAY(1); 337 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 338 SIO_SET(VR_MIICMD_CLK); 339 DELAY(1); 340 341 /* 342 * Now try reading data bits. If the ack failed, we still 343 * need to clock through 16 cycles to keep the PHY(s) in sync. 344 */ 345 if (ack) { 346 for(i = 0; i < 16; i++) { 347 SIO_CLR(VR_MIICMD_CLK); 348 DELAY(1); 349 SIO_SET(VR_MIICMD_CLK); 350 DELAY(1); 351 } 352 goto fail; 353 } 354 355 for (i = 0x8000; i; i >>= 1) { 356 SIO_CLR(VR_MIICMD_CLK); 357 DELAY(1); 358 if (!ack) { 359 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 360 frame->mii_data |= i; 361 DELAY(1); 362 } 363 SIO_SET(VR_MIICMD_CLK); 364 DELAY(1); 365 } 366 367 fail: 368 369 SIO_CLR(VR_MIICMD_CLK); 370 DELAY(1); 371 SIO_SET(VR_MIICMD_CLK); 372 DELAY(1); 373 374 splx(s); 375 376 if (ack) 377 return(1); 378 return(0); 379 } 380 #else 381 { 382 int s, i; 383 384 s = splimp(); 385 386 /* Set the PHY-adress */ 387 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 388 frame->mii_phyaddr); 389 390 /* Set the register-adress */ 391 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 392 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 393 394 for (i = 0; i < 10000; i++) { 395 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 396 break; 397 DELAY(1); 398 } 399 400 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 401 402 (void)splx(s); 403 404 return(0); 405 } 406 #endif 407 408 409 /* 410 * Write to a PHY register through the MII. 411 */ 412 static int vr_mii_writereg(sc, frame) 413 struct vr_softc *sc; 414 struct vr_mii_frame *frame; 415 416 #ifdef VR_USESWSHIFT 417 { 418 int s; 419 420 s = splimp(); 421 422 CSR_WRITE_1(sc, VR_MIICMD, 0); 423 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 424 425 /* 426 * Set up frame for TX. 427 */ 428 429 frame->mii_stdelim = VR_MII_STARTDELIM; 430 frame->mii_opcode = VR_MII_WRITEOP; 431 frame->mii_turnaround = VR_MII_TURNAROUND; 432 433 /* 434 * Turn on data output. 435 */ 436 SIO_SET(VR_MIICMD_DIR); 437 438 vr_mii_sync(sc); 439 440 vr_mii_send(sc, frame->mii_stdelim, 2); 441 vr_mii_send(sc, frame->mii_opcode, 2); 442 vr_mii_send(sc, frame->mii_phyaddr, 5); 443 vr_mii_send(sc, frame->mii_regaddr, 5); 444 vr_mii_send(sc, frame->mii_turnaround, 2); 445 vr_mii_send(sc, frame->mii_data, 16); 446 447 /* Idle bit. */ 448 SIO_SET(VR_MIICMD_CLK); 449 DELAY(1); 450 SIO_CLR(VR_MIICMD_CLK); 451 DELAY(1); 452 453 /* 454 * Turn off xmit. 455 */ 456 SIO_CLR(VR_MIICMD_DIR); 457 458 splx(s); 459 460 return(0); 461 } 462 #else 463 { 464 int s, i; 465 466 s = splimp(); 467 468 /* Set the PHY-adress */ 469 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 470 frame->mii_phyaddr); 471 472 /* Set the register-adress and data to write */ 473 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 474 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 475 476 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 477 478 for (i = 0; i < 10000; i++) { 479 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 480 break; 481 DELAY(1); 482 } 483 484 (void)splx(s); 485 486 return(0); 487 } 488 #endif 489 490 static int vr_miibus_readreg(dev, phy, reg) 491 device_t dev; 492 int phy, reg; 493 { 494 struct vr_softc *sc; 495 struct vr_mii_frame frame; 496 497 sc = device_get_softc(dev); 498 499 switch (sc->vr_revid) { 500 case REV_ID_VT6102_APOLLO: 501 if (phy != 1) 502 return 0; 503 default: 504 break; 505 } 506 507 bzero((char *)&frame, sizeof(frame)); 508 509 frame.mii_phyaddr = phy; 510 frame.mii_regaddr = reg; 511 vr_mii_readreg(sc, &frame); 512 513 return(frame.mii_data); 514 } 515 516 static int vr_miibus_writereg(dev, phy, reg, data) 517 device_t dev; 518 u_int16_t phy, reg, data; 519 { 520 struct vr_softc *sc; 521 struct vr_mii_frame frame; 522 523 sc = device_get_softc(dev); 524 525 switch (sc->vr_revid) { 526 case REV_ID_VT6102_APOLLO: 527 if (phy != 1) 528 return 0; 529 default: 530 break; 531 } 532 533 bzero((char *)&frame, sizeof(frame)); 534 535 frame.mii_phyaddr = phy; 536 frame.mii_regaddr = reg; 537 frame.mii_data = data; 538 539 vr_mii_writereg(sc, &frame); 540 541 return(0); 542 } 543 544 static void vr_miibus_statchg(dev) 545 device_t dev; 546 { 547 struct vr_softc *sc; 548 struct mii_data *mii; 549 550 sc = device_get_softc(dev); 551 mii = device_get_softc(sc->vr_miibus); 552 vr_setcfg(sc, mii->mii_media_active); 553 554 return; 555 } 556 557 /* 558 * Calculate CRC of a multicast group address, return the lower 6 bits. 559 */ 560 static u_int8_t vr_calchash(addr) 561 u_int8_t *addr; 562 { 563 u_int32_t crc, carry; 564 int i, j; 565 u_int8_t c; 566 567 /* Compute CRC for the address value. */ 568 crc = 0xFFFFFFFF; /* initial value */ 569 570 for (i = 0; i < 6; i++) { 571 c = *(addr + i); 572 for (j = 0; j < 8; j++) { 573 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 574 crc <<= 1; 575 c >>= 1; 576 if (carry) 577 crc = (crc ^ 0x04c11db6) | carry; 578 } 579 } 580 581 /* return the filter bit position */ 582 return((crc >> 26) & 0x0000003F); 583 } 584 585 /* 586 * Program the 64-bit multicast hash filter. 587 */ 588 static void vr_setmulti(sc) 589 struct vr_softc *sc; 590 { 591 struct ifnet *ifp; 592 int h = 0; 593 u_int32_t hashes[2] = { 0, 0 }; 594 struct ifmultiaddr *ifma; 595 u_int8_t rxfilt; 596 int mcnt = 0; 597 598 ifp = &sc->arpcom.ac_if; 599 600 rxfilt = CSR_READ_1(sc, VR_RXCFG); 601 602 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 603 rxfilt |= VR_RXCFG_RX_MULTI; 604 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 605 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 606 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 607 return; 608 } 609 610 /* first, zot all the existing hash bits */ 611 CSR_WRITE_4(sc, VR_MAR0, 0); 612 CSR_WRITE_4(sc, VR_MAR1, 0); 613 614 /* now program new ones */ 615 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 616 ifma = ifma->ifma_link.le_next) { 617 if (ifma->ifma_addr->sa_family != AF_LINK) 618 continue; 619 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 620 if (h < 32) 621 hashes[0] |= (1 << h); 622 else 623 hashes[1] |= (1 << (h - 32)); 624 mcnt++; 625 } 626 627 if (mcnt) 628 rxfilt |= VR_RXCFG_RX_MULTI; 629 else 630 rxfilt &= ~VR_RXCFG_RX_MULTI; 631 632 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 633 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 634 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 635 636 return; 637 } 638 639 /* 640 * In order to fiddle with the 641 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 642 * first have to put the transmit and/or receive logic in the idle state. 643 */ 644 static void vr_setcfg(sc, media) 645 struct vr_softc *sc; 646 int media; 647 { 648 int restart = 0; 649 650 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 651 restart = 1; 652 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 653 } 654 655 if ((media & IFM_GMASK) == IFM_FDX) 656 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 657 else 658 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 659 660 if (restart) 661 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 662 663 return; 664 } 665 666 static void vr_reset(sc) 667 struct vr_softc *sc; 668 { 669 int i; 670 671 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 672 673 for (i = 0; i < VR_TIMEOUT; i++) { 674 DELAY(10); 675 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 676 break; 677 } 678 if (i == VR_TIMEOUT) { 679 if (sc->vr_revid < REV_ID_VT3065_A) 680 printf("vr%d: reset never completed!\n", sc->vr_unit); 681 else { 682 /* Use newer force reset command */ 683 printf("vr%d: Using force reset command.\n", sc->vr_unit); 684 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 685 } 686 } 687 688 /* Wait a little while for the chip to get its brains in order. */ 689 DELAY(1000); 690 691 return; 692 } 693 694 /* 695 * Probe for a VIA Rhine chip. Check the PCI vendor and device 696 * IDs against our list and return a device name if we find a match. 697 */ 698 static int vr_probe(dev) 699 device_t dev; 700 { 701 struct vr_type *t; 702 703 t = vr_devs; 704 705 while(t->vr_name != NULL) { 706 if ((pci_get_vendor(dev) == t->vr_vid) && 707 (pci_get_device(dev) == t->vr_did)) { 708 device_set_desc(dev, t->vr_name); 709 return(0); 710 } 711 t++; 712 } 713 714 return(ENXIO); 715 } 716 717 /* 718 * Attach the interface. Allocate softc structures, do ifmedia 719 * setup and ethernet/BPF attach. 720 */ 721 static int vr_attach(dev) 722 device_t dev; 723 { 724 int i, s; 725 u_char eaddr[ETHER_ADDR_LEN]; 726 u_int32_t command; 727 struct vr_softc *sc; 728 struct ifnet *ifp; 729 int unit, error = 0, rid; 730 731 s = splimp(); 732 733 sc = device_get_softc(dev); 734 unit = device_get_unit(dev); 735 bzero(sc, sizeof(struct vr_softc *)); 736 737 /* 738 * Handle power management nonsense. 739 */ 740 741 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF; 742 if (command == 0x01) { 743 744 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4); 745 if (command & VR_PSTATE_MASK) { 746 u_int32_t iobase, membase, irq; 747 748 /* Save important PCI config data. */ 749 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 750 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 751 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 752 753 /* Reset the power state. */ 754 printf("vr%d: chip is in D%d power mode " 755 "-- setting to D0\n", unit, command & VR_PSTATE_MASK); 756 command &= 0xFFFFFFFC; 757 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4); 758 759 /* Restore PCI config data. */ 760 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 761 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 762 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 763 } 764 } 765 766 /* 767 * Map control/status registers. 768 */ 769 command = pci_read_config(dev, PCIR_COMMAND, 4); 770 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 771 pci_write_config(dev, PCIR_COMMAND, command, 4); 772 command = pci_read_config(dev, PCIR_COMMAND, 4); 773 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 774 775 #ifdef VR_USEIOSPACE 776 if (!(command & PCIM_CMD_PORTEN)) { 777 printf("vr%d: failed to enable I/O ports!\n", unit); 778 free(sc, M_DEVBUF); 779 goto fail; 780 } 781 #else 782 if (!(command & PCIM_CMD_MEMEN)) { 783 printf("vr%d: failed to enable memory mapping!\n", unit); 784 goto fail; 785 } 786 #endif 787 788 rid = VR_RID; 789 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 790 0, ~0, 1, RF_ACTIVE); 791 792 if (sc->vr_res == NULL) { 793 printf("vr%d: couldn't map ports/memory\n", unit); 794 error = ENXIO; 795 goto fail; 796 } 797 798 sc->vr_btag = rman_get_bustag(sc->vr_res); 799 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 800 801 /* Allocate interrupt */ 802 rid = 0; 803 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 804 RF_SHAREABLE | RF_ACTIVE); 805 806 if (sc->vr_irq == NULL) { 807 printf("vr%d: couldn't map interrupt\n", unit); 808 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 809 error = ENXIO; 810 goto fail; 811 } 812 813 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 814 vr_intr, sc, &sc->vr_intrhand); 815 816 if (error) { 817 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 818 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 819 printf("vr%d: couldn't set up irq\n", unit); 820 goto fail; 821 } 822 823 /* 824 * Windows may put the chip in suspend mode when it 825 * shuts down. Be sure to kick it in the head to wake it 826 * up again. 827 */ 828 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 829 830 /* Reset the adapter. */ 831 vr_reset(sc); 832 833 /* 834 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 835 * initialization and disable AUTOPOLL. 836 */ 837 pci_write_config(dev, VR_PCI_MODE, 838 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 839 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 840 841 /* 842 * Get station address. The way the Rhine chips work, 843 * you're not allowed to directly access the EEPROM once 844 * they've been programmed a special way. Consequently, 845 * we need to read the node address from the PAR0 and PAR1 846 * registers. 847 */ 848 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 849 DELAY(200); 850 for (i = 0; i < ETHER_ADDR_LEN; i++) 851 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 852 853 /* 854 * A Rhine chip was detected. Inform the world. 855 */ 856 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 857 858 sc->vr_unit = unit; 859 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 860 861 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 862 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 863 864 if (sc->vr_ldata == NULL) { 865 printf("vr%d: no memory for list buffers!\n", unit); 866 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 867 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 868 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 869 error = ENXIO; 870 goto fail; 871 } 872 873 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 874 875 ifp = &sc->arpcom.ac_if; 876 ifp->if_softc = sc; 877 ifp->if_unit = unit; 878 ifp->if_name = "vr"; 879 ifp->if_mtu = ETHERMTU; 880 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 881 ifp->if_ioctl = vr_ioctl; 882 ifp->if_output = ether_output; 883 ifp->if_start = vr_start; 884 ifp->if_watchdog = vr_watchdog; 885 ifp->if_init = vr_init; 886 ifp->if_baudrate = 10000000; 887 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 888 889 /* 890 * Do MII setup. 891 */ 892 if (mii_phy_probe(dev, &sc->vr_miibus, 893 vr_ifmedia_upd, vr_ifmedia_sts)) { 894 printf("vr%d: MII without any phy!\n", sc->vr_unit); 895 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 896 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 897 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 898 contigfree(sc->vr_ldata, 899 sizeof(struct vr_list_data), M_DEVBUF); 900 error = ENXIO; 901 goto fail; 902 } 903 904 callout_handle_init(&sc->vr_stat_ch); 905 906 /* 907 * Call MI attach routine. 908 */ 909 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 910 911 fail: 912 splx(s); 913 return(error); 914 } 915 916 static int vr_detach(dev) 917 device_t dev; 918 { 919 struct vr_softc *sc; 920 struct ifnet *ifp; 921 int s; 922 923 s = splimp(); 924 925 sc = device_get_softc(dev); 926 ifp = &sc->arpcom.ac_if; 927 928 vr_stop(sc); 929 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 930 931 bus_generic_detach(dev); 932 device_delete_child(dev, sc->vr_miibus); 933 934 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 935 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 936 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 937 938 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 939 940 splx(s); 941 942 return(0); 943 } 944 945 /* 946 * Initialize the transmit descriptors. 947 */ 948 static int vr_list_tx_init(sc) 949 struct vr_softc *sc; 950 { 951 struct vr_chain_data *cd; 952 struct vr_list_data *ld; 953 int i; 954 955 cd = &sc->vr_cdata; 956 ld = sc->vr_ldata; 957 for (i = 0; i < VR_TX_LIST_CNT; i++) { 958 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 959 if (i == (VR_TX_LIST_CNT - 1)) 960 cd->vr_tx_chain[i].vr_nextdesc = 961 &cd->vr_tx_chain[0]; 962 else 963 cd->vr_tx_chain[i].vr_nextdesc = 964 &cd->vr_tx_chain[i + 1]; 965 } 966 967 cd->vr_tx_free = &cd->vr_tx_chain[0]; 968 cd->vr_tx_tail = cd->vr_tx_head = NULL; 969 970 return(0); 971 } 972 973 974 /* 975 * Initialize the RX descriptors and allocate mbufs for them. Note that 976 * we arrange the descriptors in a closed ring, so that the last descriptor 977 * points back to the first. 978 */ 979 static int vr_list_rx_init(sc) 980 struct vr_softc *sc; 981 { 982 struct vr_chain_data *cd; 983 struct vr_list_data *ld; 984 int i; 985 986 cd = &sc->vr_cdata; 987 ld = sc->vr_ldata; 988 989 for (i = 0; i < VR_RX_LIST_CNT; i++) { 990 cd->vr_rx_chain[i].vr_ptr = 991 (struct vr_desc *)&ld->vr_rx_list[i]; 992 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 993 return(ENOBUFS); 994 if (i == (VR_RX_LIST_CNT - 1)) { 995 cd->vr_rx_chain[i].vr_nextdesc = 996 &cd->vr_rx_chain[0]; 997 ld->vr_rx_list[i].vr_next = 998 vtophys(&ld->vr_rx_list[0]); 999 } else { 1000 cd->vr_rx_chain[i].vr_nextdesc = 1001 &cd->vr_rx_chain[i + 1]; 1002 ld->vr_rx_list[i].vr_next = 1003 vtophys(&ld->vr_rx_list[i + 1]); 1004 } 1005 } 1006 1007 cd->vr_rx_head = &cd->vr_rx_chain[0]; 1008 1009 return(0); 1010 } 1011 1012 /* 1013 * Initialize an RX descriptor and attach an MBUF cluster. 1014 * Note: the length fields are only 11 bits wide, which means the 1015 * largest size we can specify is 2047. This is important because 1016 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1017 * overflow the field and make a mess. 1018 */ 1019 static int vr_newbuf(sc, c, m) 1020 struct vr_softc *sc; 1021 struct vr_chain_onefrag *c; 1022 struct mbuf *m; 1023 { 1024 struct mbuf *m_new = NULL; 1025 1026 if (m == NULL) { 1027 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1028 if (m_new == NULL) 1029 return(ENOBUFS); 1030 1031 MCLGET(m_new, M_DONTWAIT); 1032 if (!(m_new->m_flags & M_EXT)) { 1033 m_freem(m_new); 1034 return(ENOBUFS); 1035 } 1036 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1037 } else { 1038 m_new = m; 1039 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1040 m_new->m_data = m_new->m_ext.ext_buf; 1041 } 1042 1043 m_adj(m_new, sizeof(u_int64_t)); 1044 1045 c->vr_mbuf = m_new; 1046 c->vr_ptr->vr_status = VR_RXSTAT; 1047 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 1048 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 1049 1050 return(0); 1051 } 1052 1053 /* 1054 * A frame has been uploaded: pass the resulting mbuf chain up to 1055 * the higher level protocols. 1056 */ 1057 static void vr_rxeof(sc) 1058 struct vr_softc *sc; 1059 { 1060 struct ether_header *eh; 1061 struct mbuf *m; 1062 struct ifnet *ifp; 1063 struct vr_chain_onefrag *cur_rx; 1064 int total_len = 0; 1065 u_int32_t rxstat; 1066 1067 ifp = &sc->arpcom.ac_if; 1068 1069 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1070 VR_RXSTAT_OWN)) { 1071 struct mbuf *m0 = NULL; 1072 1073 cur_rx = sc->vr_cdata.vr_rx_head; 1074 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1075 m = cur_rx->vr_mbuf; 1076 1077 /* 1078 * If an error occurs, update stats, clear the 1079 * status word and leave the mbuf cluster in place: 1080 * it should simply get re-used next time this descriptor 1081 * comes up in the ring. 1082 */ 1083 if (rxstat & VR_RXSTAT_RXERR) { 1084 ifp->if_ierrors++; 1085 printf("vr%d: rx error (%02x):", 1086 sc->vr_unit, rxstat & 0x000000ff); 1087 if (rxstat & VR_RXSTAT_CRCERR) 1088 printf(" crc error"); 1089 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1090 printf(" frame alignment error\n"); 1091 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1092 printf(" FIFO overflow"); 1093 if (rxstat & VR_RXSTAT_GIANT) 1094 printf(" received giant packet"); 1095 if (rxstat & VR_RXSTAT_RUNT) 1096 printf(" received runt packet"); 1097 if (rxstat & VR_RXSTAT_BUSERR) 1098 printf(" system bus error"); 1099 if (rxstat & VR_RXSTAT_BUFFERR) 1100 printf("rx buffer error"); 1101 printf("\n"); 1102 vr_newbuf(sc, cur_rx, m); 1103 continue; 1104 } 1105 1106 /* No errors; receive the packet. */ 1107 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1108 1109 /* 1110 * XXX The VIA Rhine chip includes the CRC with every 1111 * received frame, and there's no way to turn this 1112 * behavior off (at least, I can't find anything in 1113 * the manual that explains how to do it) so we have 1114 * to trim off the CRC manually. 1115 */ 1116 total_len -= ETHER_CRC_LEN; 1117 1118 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1119 total_len + ETHER_ALIGN, 0, ifp, NULL); 1120 vr_newbuf(sc, cur_rx, m); 1121 if (m0 == NULL) { 1122 ifp->if_ierrors++; 1123 continue; 1124 } 1125 m_adj(m0, ETHER_ALIGN); 1126 m = m0; 1127 1128 ifp->if_ipackets++; 1129 eh = mtod(m, struct ether_header *); 1130 1131 /* Remove header from mbuf and pass it on. */ 1132 m_adj(m, sizeof(struct ether_header)); 1133 ether_input(ifp, eh, m); 1134 } 1135 1136 return; 1137 } 1138 1139 void vr_rxeoc(sc) 1140 struct vr_softc *sc; 1141 { 1142 struct ifnet *ifp; 1143 int i; 1144 1145 ifp = &sc->arpcom.ac_if; 1146 1147 ifp->if_ierrors++; 1148 1149 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1150 DELAY(10000); 1151 1152 for (i = 0x400; 1153 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1154 i--) 1155 ; /* Wait for receiver to stop */ 1156 1157 if (!i) { 1158 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1159 sc->vr_flags |= VR_F_RESTART; 1160 return; 1161 } 1162 1163 vr_rxeof(sc); 1164 1165 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1166 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1167 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1168 1169 return; 1170 } 1171 1172 /* 1173 * A frame was downloaded to the chip. It's safe for us to clean up 1174 * the list buffers. 1175 */ 1176 1177 static void vr_txeof(sc) 1178 struct vr_softc *sc; 1179 { 1180 struct vr_chain *cur_tx; 1181 struct ifnet *ifp; 1182 1183 ifp = &sc->arpcom.ac_if; 1184 1185 /* Reset the timeout timer; if_txeoc will clear it. */ 1186 ifp->if_timer = 5; 1187 1188 /* Sanity check. */ 1189 if (sc->vr_cdata.vr_tx_head == NULL) 1190 return; 1191 1192 /* 1193 * Go through our tx list and free mbufs for those 1194 * frames that have been transmitted. 1195 */ 1196 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1197 u_int32_t txstat; 1198 int i; 1199 1200 cur_tx = sc->vr_cdata.vr_tx_head; 1201 txstat = cur_tx->vr_ptr->vr_status; 1202 1203 if ((txstat & VR_TXSTAT_ABRT) || 1204 (txstat & VR_TXSTAT_UDF)) { 1205 for (i = 0x400; 1206 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1207 i--) 1208 ; /* Wait for chip to shutdown */ 1209 if (!i) { 1210 printf("vr%d: tx shutdown timeout\n", sc->vr_unit); 1211 sc->vr_flags |= VR_F_RESTART; 1212 break; 1213 } 1214 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1215 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1216 break; 1217 } 1218 1219 if (txstat & VR_TXSTAT_OWN) 1220 break; 1221 1222 if (txstat & VR_TXSTAT_ERRSUM) { 1223 ifp->if_oerrors++; 1224 if (txstat & VR_TXSTAT_DEFER) 1225 ifp->if_collisions++; 1226 if (txstat & VR_TXSTAT_LATECOLL) 1227 ifp->if_collisions++; 1228 } 1229 1230 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1231 1232 ifp->if_opackets++; 1233 if (cur_tx->vr_mbuf != NULL) { 1234 m_freem(cur_tx->vr_mbuf); 1235 cur_tx->vr_mbuf = NULL; 1236 } 1237 1238 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1239 sc->vr_cdata.vr_tx_head = NULL; 1240 sc->vr_cdata.vr_tx_tail = NULL; 1241 break; 1242 } 1243 1244 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1245 } 1246 1247 return; 1248 } 1249 1250 /* 1251 * TX 'end of channel' interrupt handler. 1252 */ 1253 static void vr_txeoc(sc) 1254 struct vr_softc *sc; 1255 { 1256 struct ifnet *ifp; 1257 1258 ifp = &sc->arpcom.ac_if; 1259 1260 if (sc->vr_cdata.vr_tx_head == NULL) { 1261 ifp->if_flags &= ~IFF_OACTIVE; 1262 sc->vr_cdata.vr_tx_tail = NULL; 1263 ifp->if_timer = 0; 1264 } 1265 1266 return; 1267 } 1268 1269 static void vr_tick(xsc) 1270 void *xsc; 1271 { 1272 struct vr_softc *sc; 1273 struct mii_data *mii; 1274 int s; 1275 1276 s = splimp(); 1277 1278 sc = xsc; 1279 if (sc->vr_flags & VR_F_RESTART) { 1280 printf("vr%d: restarting\n", sc->vr_unit); 1281 vr_stop(sc); 1282 vr_reset(sc); 1283 vr_init(sc); 1284 sc->vr_flags &= ~VR_F_RESTART; 1285 } 1286 1287 mii = device_get_softc(sc->vr_miibus); 1288 mii_tick(mii); 1289 1290 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1291 1292 splx(s); 1293 1294 return; 1295 } 1296 1297 static void vr_intr(arg) 1298 void *arg; 1299 { 1300 struct vr_softc *sc; 1301 struct ifnet *ifp; 1302 u_int16_t status; 1303 1304 sc = arg; 1305 ifp = &sc->arpcom.ac_if; 1306 1307 /* Supress unwanted interrupts. */ 1308 if (!(ifp->if_flags & IFF_UP)) { 1309 vr_stop(sc); 1310 return; 1311 } 1312 1313 /* Disable interrupts. */ 1314 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1315 1316 for (;;) { 1317 1318 status = CSR_READ_2(sc, VR_ISR); 1319 if (status) 1320 CSR_WRITE_2(sc, VR_ISR, status); 1321 1322 if ((status & VR_INTRS) == 0) 1323 break; 1324 1325 if (status & VR_ISR_RX_OK) 1326 vr_rxeof(sc); 1327 1328 if (status & VR_ISR_RX_DROPPED) { 1329 printf("vr%d: rx packet lost\n", sc->vr_unit); 1330 ifp->if_ierrors++; 1331 } 1332 1333 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1334 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1335 printf("vr%d: receive error (%04x)", 1336 sc->vr_unit, status); 1337 if (status & VR_ISR_RX_NOBUF) 1338 printf(" no buffers"); 1339 if (status & VR_ISR_RX_OFLOW) 1340 printf(" overflow"); 1341 if (status & VR_ISR_RX_DROPPED) 1342 printf(" packet lost"); 1343 printf("\n"); 1344 vr_rxeoc(sc); 1345 } 1346 1347 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1348 vr_reset(sc); 1349 vr_init(sc); 1350 break; 1351 } 1352 1353 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1354 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1355 vr_txeof(sc); 1356 if ((status & VR_ISR_UDFI) || 1357 (status & VR_ISR_TX_ABRT2) || 1358 (status & VR_ISR_TX_ABRT)) { 1359 ifp->if_oerrors++; 1360 if (sc->vr_cdata.vr_tx_head != NULL) { 1361 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1362 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1363 } 1364 } else 1365 vr_txeoc(sc); 1366 } 1367 1368 } 1369 1370 /* Re-enable interrupts. */ 1371 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1372 1373 if (ifp->if_snd.ifq_head != NULL) { 1374 vr_start(ifp); 1375 } 1376 1377 return; 1378 } 1379 1380 /* 1381 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1382 * pointers to the fragment pointers. 1383 */ 1384 static int vr_encap(sc, c, m_head) 1385 struct vr_softc *sc; 1386 struct vr_chain *c; 1387 struct mbuf *m_head; 1388 { 1389 int frag = 0; 1390 struct vr_desc *f = NULL; 1391 int total_len; 1392 struct mbuf *m; 1393 1394 m = m_head; 1395 total_len = 0; 1396 1397 /* 1398 * The VIA Rhine wants packet buffers to be longword 1399 * aligned, but very often our mbufs aren't. Rather than 1400 * waste time trying to decide when to copy and when not 1401 * to copy, just do it all the time. 1402 */ 1403 if (m != NULL) { 1404 struct mbuf *m_new = NULL; 1405 1406 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1407 if (m_new == NULL) { 1408 printf("vr%d: no memory for tx list\n", sc->vr_unit); 1409 return(1); 1410 } 1411 if (m_head->m_pkthdr.len > MHLEN) { 1412 MCLGET(m_new, M_DONTWAIT); 1413 if (!(m_new->m_flags & M_EXT)) { 1414 m_freem(m_new); 1415 printf("vr%d: no memory for tx list\n", 1416 sc->vr_unit); 1417 return(1); 1418 } 1419 } 1420 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1421 mtod(m_new, caddr_t)); 1422 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1423 m_freem(m_head); 1424 m_head = m_new; 1425 /* 1426 * The Rhine chip doesn't auto-pad, so we have to make 1427 * sure to pad short frames out to the minimum frame length 1428 * ourselves. 1429 */ 1430 if (m_head->m_len < VR_MIN_FRAMELEN) { 1431 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1432 m_new->m_len = m_new->m_pkthdr.len; 1433 } 1434 f = c->vr_ptr; 1435 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1436 f->vr_ctl = total_len = m_new->m_len; 1437 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1438 f->vr_status = 0; 1439 frag = 1; 1440 } 1441 1442 c->vr_mbuf = m_head; 1443 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1444 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1445 1446 return(0); 1447 } 1448 1449 /* 1450 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1451 * to the mbuf data regions directly in the transmit lists. We also save a 1452 * copy of the pointers since the transmit list fragment pointers are 1453 * physical addresses. 1454 */ 1455 1456 static void vr_start(ifp) 1457 struct ifnet *ifp; 1458 { 1459 struct vr_softc *sc; 1460 struct mbuf *m_head = NULL; 1461 struct vr_chain *cur_tx = NULL, *start_tx; 1462 1463 sc = ifp->if_softc; 1464 1465 if (ifp->if_flags & IFF_OACTIVE) 1466 return; 1467 1468 /* 1469 * Check for an available queue slot. If there are none, 1470 * punt. 1471 */ 1472 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1473 ifp->if_flags |= IFF_OACTIVE; 1474 return; 1475 } 1476 1477 start_tx = sc->vr_cdata.vr_tx_free; 1478 1479 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1480 IF_DEQUEUE(&ifp->if_snd, m_head); 1481 if (m_head == NULL) 1482 break; 1483 1484 /* Pick a descriptor off the free list. */ 1485 cur_tx = sc->vr_cdata.vr_tx_free; 1486 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1487 1488 /* Pack the data into the descriptor. */ 1489 if (vr_encap(sc, cur_tx, m_head)) { 1490 IF_PREPEND(&ifp->if_snd, m_head); 1491 ifp->if_flags |= IFF_OACTIVE; 1492 cur_tx = NULL; 1493 break; 1494 } 1495 1496 if (cur_tx != start_tx) 1497 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1498 1499 /* 1500 * If there's a BPF listener, bounce a copy of this frame 1501 * to him. 1502 */ 1503 if (ifp->if_bpf) 1504 bpf_mtap(ifp, cur_tx->vr_mbuf); 1505 1506 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1507 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1508 } 1509 1510 /* 1511 * If there are no frames queued, bail. 1512 */ 1513 if (cur_tx == NULL) 1514 return; 1515 1516 sc->vr_cdata.vr_tx_tail = cur_tx; 1517 1518 if (sc->vr_cdata.vr_tx_head == NULL) 1519 sc->vr_cdata.vr_tx_head = start_tx; 1520 1521 /* 1522 * Set a timeout in case the chip goes out to lunch. 1523 */ 1524 ifp->if_timer = 5; 1525 1526 return; 1527 } 1528 1529 static void vr_init(xsc) 1530 void *xsc; 1531 { 1532 struct vr_softc *sc = xsc; 1533 struct ifnet *ifp = &sc->arpcom.ac_if; 1534 struct mii_data *mii; 1535 int s, i; 1536 1537 s = splimp(); 1538 1539 mii = device_get_softc(sc->vr_miibus); 1540 1541 /* 1542 * Cancel pending I/O and free all RX/TX buffers. 1543 */ 1544 vr_stop(sc); 1545 vr_reset(sc); 1546 1547 /* 1548 * Set our station address. 1549 */ 1550 for (i = 0; i < ETHER_ADDR_LEN; i++) 1551 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1552 1553 /* Set DMA size */ 1554 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1555 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1556 1557 /* 1558 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1559 * so we must set both. 1560 */ 1561 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1562 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1563 1564 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1565 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1566 1567 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1568 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1569 1570 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1571 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1572 1573 /* Init circular RX list. */ 1574 if (vr_list_rx_init(sc) == ENOBUFS) { 1575 printf("vr%d: initialization failed: no " 1576 "memory for rx buffers\n", sc->vr_unit); 1577 vr_stop(sc); 1578 (void)splx(s); 1579 return; 1580 } 1581 1582 /* 1583 * Init tx descriptors. 1584 */ 1585 vr_list_tx_init(sc); 1586 1587 /* If we want promiscuous mode, set the allframes bit. */ 1588 if (ifp->if_flags & IFF_PROMISC) 1589 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1590 else 1591 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1592 1593 /* Set capture broadcast bit to capture broadcast frames. */ 1594 if (ifp->if_flags & IFF_BROADCAST) 1595 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1596 else 1597 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1598 1599 /* 1600 * Program the multicast filter, if necessary. 1601 */ 1602 vr_setmulti(sc); 1603 1604 /* 1605 * Load the address of the RX list. 1606 */ 1607 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1608 1609 /* Enable receiver and transmitter. */ 1610 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1611 VR_CMD_TX_ON|VR_CMD_RX_ON| 1612 VR_CMD_RX_GO); 1613 1614 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1615 1616 /* 1617 * Enable interrupts. 1618 */ 1619 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1620 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1621 1622 mii_mediachg(mii); 1623 1624 ifp->if_flags |= IFF_RUNNING; 1625 ifp->if_flags &= ~IFF_OACTIVE; 1626 1627 (void)splx(s); 1628 1629 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1630 1631 return; 1632 } 1633 1634 /* 1635 * Set media options. 1636 */ 1637 static int vr_ifmedia_upd(ifp) 1638 struct ifnet *ifp; 1639 { 1640 struct vr_softc *sc; 1641 1642 sc = ifp->if_softc; 1643 1644 if (ifp->if_flags & IFF_UP) 1645 vr_init(sc); 1646 1647 return(0); 1648 } 1649 1650 /* 1651 * Report current media status. 1652 */ 1653 static void vr_ifmedia_sts(ifp, ifmr) 1654 struct ifnet *ifp; 1655 struct ifmediareq *ifmr; 1656 { 1657 struct vr_softc *sc; 1658 struct mii_data *mii; 1659 1660 sc = ifp->if_softc; 1661 mii = device_get_softc(sc->vr_miibus); 1662 mii_pollstat(mii); 1663 ifmr->ifm_active = mii->mii_media_active; 1664 ifmr->ifm_status = mii->mii_media_status; 1665 1666 return; 1667 } 1668 1669 static int vr_ioctl(ifp, command, data) 1670 struct ifnet *ifp; 1671 u_long command; 1672 caddr_t data; 1673 { 1674 struct vr_softc *sc = ifp->if_softc; 1675 struct ifreq *ifr = (struct ifreq *) data; 1676 struct mii_data *mii; 1677 int s, error = 0; 1678 1679 s = splimp(); 1680 1681 switch(command) { 1682 case SIOCSIFADDR: 1683 case SIOCGIFADDR: 1684 case SIOCSIFMTU: 1685 error = ether_ioctl(ifp, command, data); 1686 break; 1687 case SIOCSIFFLAGS: 1688 if (ifp->if_flags & IFF_UP) { 1689 vr_init(sc); 1690 } else { 1691 if (ifp->if_flags & IFF_RUNNING) 1692 vr_stop(sc); 1693 } 1694 error = 0; 1695 break; 1696 case SIOCADDMULTI: 1697 case SIOCDELMULTI: 1698 vr_setmulti(sc); 1699 error = 0; 1700 break; 1701 case SIOCGIFMEDIA: 1702 case SIOCSIFMEDIA: 1703 mii = device_get_softc(sc->vr_miibus); 1704 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1705 break; 1706 default: 1707 error = EINVAL; 1708 break; 1709 } 1710 1711 (void)splx(s); 1712 1713 return(error); 1714 } 1715 1716 static void vr_watchdog(ifp) 1717 struct ifnet *ifp; 1718 { 1719 struct vr_softc *sc; 1720 1721 sc = ifp->if_softc; 1722 1723 ifp->if_oerrors++; 1724 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1725 1726 vr_stop(sc); 1727 vr_reset(sc); 1728 vr_init(sc); 1729 1730 if (ifp->if_snd.ifq_head != NULL) 1731 vr_start(ifp); 1732 1733 return; 1734 } 1735 1736 /* 1737 * Stop the adapter and free any mbufs allocated to the 1738 * RX and TX lists. 1739 */ 1740 static void vr_stop(sc) 1741 struct vr_softc *sc; 1742 { 1743 int i; 1744 struct ifnet *ifp; 1745 1746 ifp = &sc->arpcom.ac_if; 1747 ifp->if_timer = 0; 1748 1749 untimeout(vr_tick, sc, sc->vr_stat_ch); 1750 1751 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1752 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1753 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1754 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1755 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1756 1757 /* 1758 * Free data in the RX lists. 1759 */ 1760 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1761 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1762 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1763 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1764 } 1765 } 1766 bzero((char *)&sc->vr_ldata->vr_rx_list, 1767 sizeof(sc->vr_ldata->vr_rx_list)); 1768 1769 /* 1770 * Free the TX list buffers. 1771 */ 1772 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1773 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1774 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1775 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1776 } 1777 } 1778 1779 bzero((char *)&sc->vr_ldata->vr_tx_list, 1780 sizeof(sc->vr_ldata->vr_tx_list)); 1781 1782 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1783 1784 return; 1785 } 1786 1787 /* 1788 * Stop all chip I/O so that the kernel's probe routines don't 1789 * get confused by errant DMAs when rebooting. 1790 */ 1791 static void vr_shutdown(dev) 1792 device_t dev; 1793 { 1794 struct vr_softc *sc; 1795 1796 sc = device_get_softc(dev); 1797 1798 vr_stop(sc); 1799 1800 return; 1801 } 1802