1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $ 33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.33 2005/06/21 12:35:14 joerg Exp $ 34 */ 35 36 /* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The VIA Rhine controllers are similar in some respects to the 50 * the DEC tulip chips, except less complicated. The controller 51 * uses an MII bus and an external physical layer interface. The 52 * receiver has a one entry perfect filter and a 64-bit hash table 53 * multicast filter. Transmit and receive descriptors are similar 54 * to the tulip. 55 * 56 * The Rhine has a serious flaw in its transmit DMA mechanism: 57 * transmit buffers must be longword aligned. Unfortunately, 58 * FreeBSD doesn't guarantee that mbufs will be filled in starting 59 * at longword boundaries, so we have to do a buffer copy before 60 * transmission. 61 */ 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/sockio.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/thread2.h> 71 72 #include <net/if.h> 73 #include <net/ifq_var.h> 74 #include <net/if_arp.h> 75 #include <net/ethernet.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 79 #include <net/bpf.h> 80 81 #include <vm/vm.h> /* for vtophys */ 82 #include <vm/pmap.h> /* for vtophys */ 83 #include <machine/bus_pio.h> 84 #include <machine/bus_memio.h> 85 #include <machine/bus.h> 86 #include <machine/resource.h> 87 #include <sys/bus.h> 88 #include <sys/rman.h> 89 90 #include <dev/netif/mii_layer/mii.h> 91 #include <dev/netif/mii_layer/miivar.h> 92 93 #include <bus/pci/pcireg.h> 94 #include <bus/pci/pcivar.h> 95 96 #define VR_USEIOSPACE 97 98 #include <dev/netif/vr/if_vrreg.h> 99 100 /* "controller miibus0" required. See GENERIC if you get errors here. */ 101 #include "miibus_if.h" 102 103 #undef VR_USESWSHIFT 104 105 /* 106 * Various supported device vendors/types and their names. 107 */ 108 static struct vr_type vr_devs[] = { 109 { VIA_VENDORID, VIA_DEVICEID_RHINE, 110 "VIA VT3043 Rhine I 10/100BaseTX" }, 111 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 112 "VIA VT86C100A Rhine II 10/100BaseTX" }, 113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 114 "VIA VT6102 Rhine II 10/100BaseTX" }, 115 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 116 "VIA VT6105 Rhine III 10/100BaseTX" }, 117 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 118 "VIA VT6105M Rhine III 10/100BaseTX" }, 119 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 120 "Delta Electronics Rhine II 10/100BaseTX" }, 121 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 122 "Addtron Technology Rhine II 10/100BaseTX" }, 123 { 0, 0, NULL } 124 }; 125 126 static int vr_probe(device_t); 127 static int vr_attach(device_t); 128 static int vr_detach(device_t); 129 130 static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *, 131 struct mbuf *); 132 static int vr_encap(struct vr_softc *, struct vr_chain *, struct mbuf * ); 133 134 static void vr_rxeof(struct vr_softc *); 135 static void vr_rxeoc(struct vr_softc *); 136 static void vr_txeof(struct vr_softc *); 137 static void vr_txeoc(struct vr_softc *); 138 static void vr_tick(void *); 139 static void vr_intr(void *); 140 static void vr_start(struct ifnet *); 141 static int vr_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 142 static void vr_init(void *); 143 static void vr_stop(struct vr_softc *); 144 static void vr_watchdog(struct ifnet *); 145 static void vr_shutdown(device_t); 146 static int vr_ifmedia_upd(struct ifnet *); 147 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 148 149 #ifdef VR_USESWSHIFT 150 static void vr_mii_sync(struct vr_softc *); 151 static void vr_mii_send(struct vr_softc *, uint32_t, int); 152 #endif 153 static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *); 154 static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *); 155 static int vr_miibus_readreg(device_t, int, int); 156 static int vr_miibus_writereg(device_t, int, int, int); 157 static void vr_miibus_statchg(device_t); 158 159 static void vr_setcfg(struct vr_softc *, int); 160 static void vr_setmulti(struct vr_softc *); 161 static void vr_reset(struct vr_softc *); 162 static int vr_list_rx_init(struct vr_softc *); 163 static int vr_list_tx_init(struct vr_softc *); 164 #ifdef DEVICE_POLLING 165 static void vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 166 #endif 167 168 #ifdef VR_USEIOSPACE 169 #define VR_RES SYS_RES_IOPORT 170 #define VR_RID VR_PCI_LOIO 171 #else 172 #define VR_RES SYS_RES_MEMORY 173 #define VR_RID VR_PCI_LOMEM 174 #endif 175 176 static device_method_t vr_methods[] = { 177 /* Device interface */ 178 DEVMETHOD(device_probe, vr_probe), 179 DEVMETHOD(device_attach, vr_attach), 180 DEVMETHOD(device_detach, vr_detach), 181 DEVMETHOD(device_shutdown, vr_shutdown), 182 183 /* bus interface */ 184 DEVMETHOD(bus_print_child, bus_generic_print_child), 185 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 186 187 /* MII interface */ 188 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 189 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 190 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 191 192 { 0, 0 } 193 }; 194 195 static driver_t vr_driver = { 196 "vr", 197 vr_methods, 198 sizeof(struct vr_softc) 199 }; 200 201 static devclass_t vr_devclass; 202 203 DECLARE_DUMMY_MODULE(if_vr); 204 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 205 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 206 207 #define VR_SETBIT(sc, reg, x) \ 208 CSR_WRITE_1(sc, reg, \ 209 CSR_READ_1(sc, reg) | (x)) 210 211 #define VR_CLRBIT(sc, reg, x) \ 212 CSR_WRITE_1(sc, reg, \ 213 CSR_READ_1(sc, reg) & ~(x)) 214 215 #define VR_SETBIT16(sc, reg, x) \ 216 CSR_WRITE_2(sc, reg, \ 217 CSR_READ_2(sc, reg) | (x)) 218 219 #define VR_CLRBIT16(sc, reg, x) \ 220 CSR_WRITE_2(sc, reg, \ 221 CSR_READ_2(sc, reg) & ~(x)) 222 223 #define VR_SETBIT32(sc, reg, x) \ 224 CSR_WRITE_4(sc, reg, \ 225 CSR_READ_4(sc, reg) | (x)) 226 227 #define VR_CLRBIT32(sc, reg, x) \ 228 CSR_WRITE_4(sc, reg, \ 229 CSR_READ_4(sc, reg) & ~(x)) 230 231 #define SIO_SET(x) \ 232 CSR_WRITE_1(sc, VR_MIICMD, \ 233 CSR_READ_1(sc, VR_MIICMD) | (x)) 234 235 #define SIO_CLR(x) \ 236 CSR_WRITE_1(sc, VR_MIICMD, \ 237 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 238 239 #ifdef VR_USESWSHIFT 240 /* 241 * Sync the PHYs by setting data bit and strobing the clock 32 times. 242 */ 243 static void 244 vr_mii_sync(struct vr_softc *sc) 245 { 246 int i; 247 248 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 249 250 for (i = 0; i < 32; i++) { 251 SIO_SET(VR_MIICMD_CLK); 252 DELAY(1); 253 SIO_CLR(VR_MIICMD_CLK); 254 DELAY(1); 255 } 256 } 257 258 /* 259 * Clock a series of bits through the MII. 260 */ 261 static void 262 vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt) 263 { 264 int i; 265 266 SIO_CLR(VR_MIICMD_CLK); 267 268 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 269 if (bits & i) 270 SIO_SET(VR_MIICMD_DATAIN); 271 else 272 SIO_CLR(VR_MIICMD_DATAIN); 273 DELAY(1); 274 SIO_CLR(VR_MIICMD_CLK); 275 DELAY(1); 276 SIO_SET(VR_MIICMD_CLK); 277 } 278 } 279 #endif 280 281 /* 282 * Read an PHY register through the MII. 283 */ 284 static int 285 vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame) 286 #ifdef VR_USESWSHIFT 287 { 288 int i, ack; 289 290 crit_enter(); 291 292 /* Set up frame for RX. */ 293 frame->mii_stdelim = VR_MII_STARTDELIM; 294 frame->mii_opcode = VR_MII_READOP; 295 frame->mii_turnaround = 0; 296 frame->mii_data = 0; 297 298 CSR_WRITE_1(sc, VR_MIICMD, 0); 299 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 300 301 /* Turn on data xmit. */ 302 SIO_SET(VR_MIICMD_DIR); 303 304 vr_mii_sync(sc); 305 306 /* Send command/address info. */ 307 vr_mii_send(sc, frame->mii_stdelim, 2); 308 vr_mii_send(sc, frame->mii_opcode, 2); 309 vr_mii_send(sc, frame->mii_phyaddr, 5); 310 vr_mii_send(sc, frame->mii_regaddr, 5); 311 312 /* Idle bit. */ 313 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 314 DELAY(1); 315 SIO_SET(VR_MIICMD_CLK); 316 DELAY(1); 317 318 /* Turn off xmit. */ 319 SIO_CLR(VR_MIICMD_DIR); 320 321 /* Check for ack */ 322 SIO_CLR(VR_MIICMD_CLK); 323 DELAY(1); 324 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 325 SIO_SET(VR_MIICMD_CLK); 326 DELAY(1); 327 328 /* 329 * Now try reading data bits. If the ack failed, we still 330 * need to clock through 16 cycles to keep the PHY(s) in sync. 331 */ 332 if (ack) { 333 for(i = 0; i < 16; i++) { 334 SIO_CLR(VR_MIICMD_CLK); 335 DELAY(1); 336 SIO_SET(VR_MIICMD_CLK); 337 DELAY(1); 338 } 339 goto fail; 340 } 341 342 for (i = 0x8000; i; i >>= 1) { 343 SIO_CLR(VR_MIICMD_CLK); 344 DELAY(1); 345 if (!ack) { 346 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 347 frame->mii_data |= i; 348 DELAY(1); 349 } 350 SIO_SET(VR_MIICMD_CLK); 351 DELAY(1); 352 } 353 354 fail: 355 SIO_CLR(VR_MIICMD_CLK); 356 DELAY(1); 357 SIO_SET(VR_MIICMD_CLK); 358 DELAY(1); 359 360 crit_exit(); 361 362 if (ack) 363 return(1); 364 return(0); 365 } 366 #else 367 { 368 int i; 369 370 crit_enter(); 371 372 /* Set the PHY address. */ 373 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 374 frame->mii_phyaddr); 375 376 /* Set the register address. */ 377 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 378 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 379 380 for (i = 0; i < 10000; i++) { 381 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 382 break; 383 DELAY(1); 384 } 385 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 386 387 crit_exit(); 388 389 return(0); 390 } 391 #endif 392 393 394 /* 395 * Write to a PHY register through the MII. 396 */ 397 static int 398 vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame) 399 #ifdef VR_USESWSHIFT 400 { 401 402 crit_enter(); 403 404 CSR_WRITE_1(sc, VR_MIICMD, 0); 405 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 406 407 /* Set up frame for TX. */ 408 frame->mii_stdelim = VR_MII_STARTDELIM; 409 frame->mii_opcode = VR_MII_WRITEOP; 410 frame->mii_turnaround = VR_MII_TURNAROUND; 411 412 /* Turn on data output. */ 413 SIO_SET(VR_MIICMD_DIR); 414 415 vr_mii_sync(sc); 416 417 vr_mii_send(sc, frame->mii_stdelim, 2); 418 vr_mii_send(sc, frame->mii_opcode, 2); 419 vr_mii_send(sc, frame->mii_phyaddr, 5); 420 vr_mii_send(sc, frame->mii_regaddr, 5); 421 vr_mii_send(sc, frame->mii_turnaround, 2); 422 vr_mii_send(sc, frame->mii_data, 16); 423 424 /* Idle bit. */ 425 SIO_SET(VR_MIICMD_CLK); 426 DELAY(1); 427 SIO_CLR(VR_MIICMD_CLK); 428 DELAY(1); 429 430 /* Turn off xmit. */ 431 SIO_CLR(VR_MIICMD_DIR); 432 433 crit_exit(); 434 435 return(0); 436 } 437 #else 438 { 439 int i; 440 441 crit_enter(); 442 443 /* Set the PHY-adress */ 444 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 445 frame->mii_phyaddr); 446 447 /* Set the register address and data to write. */ 448 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 449 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 450 451 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 452 453 for (i = 0; i < 10000; i++) { 454 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 455 break; 456 DELAY(1); 457 } 458 459 crit_exit(); 460 461 return(0); 462 } 463 #endif 464 465 static int 466 vr_miibus_readreg(device_t dev, int phy, int reg) 467 { 468 struct vr_mii_frame frame; 469 struct vr_softc *sc; 470 471 sc = device_get_softc(dev); 472 473 switch (sc->vr_revid) { 474 case REV_ID_VT6102_APOLLO: 475 if (phy != 1) 476 return(0); 477 break; 478 default: 479 break; 480 } 481 482 bzero(&frame, sizeof(frame)); 483 484 frame.mii_phyaddr = phy; 485 frame.mii_regaddr = reg; 486 vr_mii_readreg(sc, &frame); 487 488 return(frame.mii_data); 489 } 490 491 static int 492 vr_miibus_writereg(device_t dev, int phy, int reg, int data) 493 { 494 struct vr_mii_frame frame; 495 struct vr_softc *sc; 496 497 sc = device_get_softc(dev); 498 499 switch (sc->vr_revid) { 500 case REV_ID_VT6102_APOLLO: 501 if (phy != 1) 502 return 0; 503 break; 504 default: 505 break; 506 } 507 508 bzero(&frame, sizeof(frame)); 509 510 frame.mii_phyaddr = phy; 511 frame.mii_regaddr = reg; 512 frame.mii_data = data; 513 514 vr_mii_writereg(sc, &frame); 515 516 return(0); 517 } 518 519 static void 520 vr_miibus_statchg(device_t dev) 521 { 522 struct mii_data *mii; 523 struct vr_softc *sc; 524 525 sc = device_get_softc(dev); 526 mii = device_get_softc(sc->vr_miibus); 527 vr_setcfg(sc, mii->mii_media_active); 528 } 529 530 /* 531 * Program the 64-bit multicast hash filter. 532 */ 533 static void 534 vr_setmulti(struct vr_softc *sc) 535 { 536 struct ifnet *ifp; 537 uint32_t hashes[2] = { 0, 0 }; 538 struct ifmultiaddr *ifma; 539 uint8_t rxfilt; 540 int mcnt = 0; 541 542 ifp = &sc->arpcom.ac_if; 543 544 rxfilt = CSR_READ_1(sc, VR_RXCFG); 545 546 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 547 rxfilt |= VR_RXCFG_RX_MULTI; 548 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 549 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 550 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 551 return; 552 } 553 554 /* First, zero out all the existing hash bits. */ 555 CSR_WRITE_4(sc, VR_MAR0, 0); 556 CSR_WRITE_4(sc, VR_MAR1, 0); 557 558 /* Now program new ones. */ 559 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 560 int h; 561 562 if (ifma->ifma_addr->sa_family != AF_LINK) 563 continue; 564 565 /* use the lower 6 bits */ 566 h = (ether_crc32_be( 567 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 568 ETHER_ADDR_LEN) >> 26) & 0x0000003F; 569 if (h < 32) 570 hashes[0] |= (1 << h); 571 else 572 hashes[1] |= (1 << (h - 32)); 573 mcnt++; 574 } 575 576 if (mcnt) 577 rxfilt |= VR_RXCFG_RX_MULTI; 578 else 579 rxfilt &= ~VR_RXCFG_RX_MULTI; 580 581 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 582 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 583 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 584 } 585 586 /* 587 * In order to fiddle with the 588 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 589 * first have to put the transmit and/or receive logic in the idle state. 590 */ 591 static void 592 vr_setcfg(struct vr_softc *sc, int media) 593 { 594 int restart = 0; 595 596 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 597 restart = 1; 598 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 599 } 600 601 if ((media & IFM_GMASK) == IFM_FDX) 602 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 603 else 604 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 605 606 if (restart) 607 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 608 } 609 610 static void 611 vr_reset(struct vr_softc *sc) 612 { 613 int i; 614 615 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 616 617 for (i = 0; i < VR_TIMEOUT; i++) { 618 DELAY(10); 619 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 620 break; 621 } 622 if (i == VR_TIMEOUT) { 623 struct ifnet *ifp = &sc->arpcom.ac_if; 624 625 if (sc->vr_revid < REV_ID_VT3065_A) { 626 if_printf(ifp, "reset never completed!\n"); 627 } else { 628 /* Use newer force reset command */ 629 if_printf(ifp, "Using force reset command.\n"); 630 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 631 } 632 } 633 634 /* Wait a little while for the chip to get its brains in order. */ 635 DELAY(1000); 636 } 637 638 /* 639 * Probe for a VIA Rhine chip. Check the PCI vendor and device 640 * IDs against our list and return a device name if we find a match. 641 */ 642 static int 643 vr_probe(device_t dev) 644 { 645 struct vr_type *t; 646 uint16_t vid, did; 647 648 vid = pci_get_vendor(dev); 649 did = pci_get_device(dev); 650 651 for (t = vr_devs; t->vr_name != NULL; ++t) { 652 if (vid == t->vr_vid && did == t->vr_did) { 653 device_set_desc(dev, t->vr_name); 654 return(0); 655 } 656 } 657 658 return(ENXIO); 659 } 660 661 /* 662 * Attach the interface. Allocate softc structures, do ifmedia 663 * setup and ethernet/BPF attach. 664 */ 665 static int 666 vr_attach(device_t dev) 667 { 668 int i; 669 uint8_t eaddr[ETHER_ADDR_LEN]; 670 struct vr_softc *sc; 671 struct ifnet *ifp; 672 int error = 0, rid; 673 674 sc = device_get_softc(dev); 675 callout_init(&sc->vr_stat_timer); 676 677 /* 678 * Handle power management nonsense. 679 */ 680 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 681 uint32_t iobase, membase, irq; 682 683 /* Save important PCI config data. */ 684 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 685 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 686 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 687 688 /* Reset the power state. */ 689 device_printf(dev, "chip is in D%d power mode " 690 "-- setting to D0\n", pci_get_powerstate(dev)); 691 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 692 693 /* Restore PCI config data. */ 694 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 695 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 696 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 697 } 698 699 pci_enable_busmaster(dev); 700 701 sc->vr_revid = pci_get_revid(dev); 702 703 rid = VR_RID; 704 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 705 706 if (sc->vr_res == NULL) { 707 device_printf(dev, "couldn't map ports/memory\n"); 708 return ENXIO; 709 } 710 711 sc->vr_btag = rman_get_bustag(sc->vr_res); 712 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 713 714 /* Allocate interrupt */ 715 rid = 0; 716 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 717 RF_SHAREABLE | RF_ACTIVE); 718 719 if (sc->vr_irq == NULL) { 720 device_printf(dev, "couldn't map interrupt\n"); 721 error = ENXIO; 722 goto fail; 723 } 724 725 /* 726 * Windows may put the chip in suspend mode when it 727 * shuts down. Be sure to kick it in the head to wake it 728 * up again. 729 */ 730 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 731 732 ifp = &sc->arpcom.ac_if; 733 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 734 735 /* Reset the adapter. */ 736 vr_reset(sc); 737 738 /* 739 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 740 * initialization and disable AUTOPOLL. 741 */ 742 pci_write_config(dev, VR_PCI_MODE, 743 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 744 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 745 746 /* 747 * Get station address. The way the Rhine chips work, 748 * you're not allowed to directly access the EEPROM once 749 * they've been programmed a special way. Consequently, 750 * we need to read the node address from the PAR0 and PAR1 751 * registers. 752 */ 753 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 754 DELAY(200); 755 for (i = 0; i < ETHER_ADDR_LEN; i++) 756 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 757 758 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 759 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 760 761 if (sc->vr_ldata == NULL) { 762 device_printf(dev, "no memory for list buffers!\n"); 763 error = ENXIO; 764 goto fail; 765 } 766 767 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 768 769 ifp->if_softc = sc; 770 ifp->if_mtu = ETHERMTU; 771 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 772 ifp->if_ioctl = vr_ioctl; 773 ifp->if_start = vr_start; 774 #ifdef DEVICE_POLLING 775 ifp->if_poll = vr_poll; 776 #endif 777 ifp->if_watchdog = vr_watchdog; 778 ifp->if_init = vr_init; 779 ifp->if_baudrate = 10000000; 780 ifq_set_maxlen(&ifp->if_snd, VR_TX_LIST_CNT - 1); 781 ifq_set_ready(&ifp->if_snd); 782 783 /* 784 * Do MII setup. 785 */ 786 crit_enter(); 787 if (mii_phy_probe(dev, &sc->vr_miibus, 788 vr_ifmedia_upd, vr_ifmedia_sts)) { 789 if_printf(ifp, "MII without any phy!\n"); 790 error = ENXIO; 791 goto fail; 792 } 793 crit_exit(); 794 795 /* Call MI attach routine. */ 796 ether_ifattach(ifp, eaddr); 797 798 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 799 vr_intr, sc, &sc->vr_intrhand, NULL); 800 801 if (error) { 802 device_printf(dev, "couldn't set up irq\n"); 803 ether_ifdetach(ifp); 804 goto fail; 805 } 806 return 0; 807 808 fail: 809 vr_detach(dev); 810 return(error); 811 } 812 813 static int 814 vr_detach(device_t dev) 815 { 816 struct vr_softc *sc = device_get_softc(dev); 817 struct ifnet *ifp = &sc->arpcom.ac_if; 818 819 crit_enter(); 820 821 if (device_is_attached(dev)) { 822 vr_stop(sc); 823 ether_ifdetach(ifp); 824 } 825 if (sc->vr_miibus != NULL) 826 device_delete_child(dev, sc->vr_miibus); 827 bus_generic_detach(dev); 828 829 if (sc->vr_intrhand != NULL) 830 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 831 832 crit_exit(); 833 834 if (sc->vr_irq != NULL) 835 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 836 if (sc->vr_res != NULL) 837 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 838 if (sc->vr_ldata != NULL) 839 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 840 841 return(0); 842 } 843 844 /* 845 * Initialize the transmit descriptors. 846 */ 847 static int 848 vr_list_tx_init(struct vr_softc *sc) 849 { 850 struct vr_chain_data *cd; 851 struct vr_list_data *ld; 852 int i, nexti; 853 854 cd = &sc->vr_cdata; 855 ld = sc->vr_ldata; 856 for (i = 0; i < VR_TX_LIST_CNT; i++) { 857 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 858 if (i == (VR_TX_LIST_CNT - 1)) 859 nexti = 0; 860 else 861 nexti = i + 1; 862 cd->vr_tx_chain[i].vr_nextdesc = &cd->vr_tx_chain[nexti]; 863 } 864 865 cd->vr_tx_free = &cd->vr_tx_chain[0]; 866 cd->vr_tx_tail = cd->vr_tx_head = NULL; 867 868 return(0); 869 } 870 871 872 /* 873 * Initialize the RX descriptors and allocate mbufs for them. Note that 874 * we arrange the descriptors in a closed ring, so that the last descriptor 875 * points back to the first. 876 */ 877 static int 878 vr_list_rx_init(struct vr_softc *sc) 879 { 880 struct vr_chain_data *cd; 881 struct vr_list_data *ld; 882 int i, nexti; 883 884 cd = &sc->vr_cdata; 885 ld = sc->vr_ldata; 886 887 for (i = 0; i < VR_RX_LIST_CNT; i++) { 888 cd->vr_rx_chain[i].vr_ptr = (struct vr_desc *)&ld->vr_rx_list[i]; 889 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 890 return(ENOBUFS); 891 if (i == (VR_RX_LIST_CNT - 1)) 892 nexti = 0; 893 else 894 nexti = i + 1; 895 cd->vr_rx_chain[i].vr_nextdesc = &cd->vr_rx_chain[nexti]; 896 ld->vr_rx_list[i].vr_next = vtophys(&ld->vr_rx_list[nexti]); 897 } 898 899 cd->vr_rx_head = &cd->vr_rx_chain[0]; 900 901 return(0); 902 } 903 904 /* 905 * Initialize an RX descriptor and attach an MBUF cluster. 906 * Note: the length fields are only 11 bits wide, which means the 907 * largest size we can specify is 2047. This is important because 908 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 909 * overflow the field and make a mess. 910 */ 911 static int 912 vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m) 913 { 914 struct mbuf *m_new = NULL; 915 916 if (m == NULL) { 917 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 918 if (m_new == NULL) 919 return (ENOBUFS); 920 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 921 } else { 922 m_new = m; 923 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 924 m_new->m_data = m_new->m_ext.ext_buf; 925 } 926 927 m_adj(m_new, sizeof(uint64_t)); 928 929 c->vr_mbuf = m_new; 930 c->vr_ptr->vr_status = VR_RXSTAT; 931 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 932 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 933 934 return(0); 935 } 936 937 /* 938 * A frame has been uploaded: pass the resulting mbuf chain up to 939 * the higher level protocols. 940 */ 941 static void 942 vr_rxeof(struct vr_softc *sc) 943 { 944 struct mbuf *m; 945 struct ifnet *ifp; 946 struct vr_chain_onefrag *cur_rx; 947 int total_len = 0; 948 uint32_t rxstat; 949 950 ifp = &sc->arpcom.ac_if; 951 952 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 953 VR_RXSTAT_OWN)) { 954 struct mbuf *m0 = NULL; 955 956 cur_rx = sc->vr_cdata.vr_rx_head; 957 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 958 m = cur_rx->vr_mbuf; 959 960 /* 961 * If an error occurs, update stats, clear the 962 * status word and leave the mbuf cluster in place: 963 * it should simply get re-used next time this descriptor 964 * comes up in the ring. 965 */ 966 if (rxstat & VR_RXSTAT_RXERR) { 967 ifp->if_ierrors++; 968 if_printf(ifp, "rx error (%02x):", rxstat & 0x000000ff); 969 if (rxstat & VR_RXSTAT_CRCERR) 970 printf(" crc error"); 971 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 972 printf(" frame alignment error\n"); 973 if (rxstat & VR_RXSTAT_FIFOOFLOW) 974 printf(" FIFO overflow"); 975 if (rxstat & VR_RXSTAT_GIANT) 976 printf(" received giant packet"); 977 if (rxstat & VR_RXSTAT_RUNT) 978 printf(" received runt packet"); 979 if (rxstat & VR_RXSTAT_BUSERR) 980 printf(" system bus error"); 981 if (rxstat & VR_RXSTAT_BUFFERR) 982 printf("rx buffer error"); 983 printf("\n"); 984 vr_newbuf(sc, cur_rx, m); 985 continue; 986 } 987 988 /* No errors; receive the packet. */ 989 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 990 991 /* 992 * XXX The VIA Rhine chip includes the CRC with every 993 * received frame, and there's no way to turn this 994 * behavior off (at least, I can't find anything in 995 * the manual that explains how to do it) so we have 996 * to trim off the CRC manually. 997 */ 998 total_len -= ETHER_CRC_LEN; 999 1000 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1001 total_len + ETHER_ALIGN, 0, ifp, NULL); 1002 vr_newbuf(sc, cur_rx, m); 1003 if (m0 == NULL) { 1004 ifp->if_ierrors++; 1005 continue; 1006 } 1007 m_adj(m0, ETHER_ALIGN); 1008 m = m0; 1009 1010 ifp->if_ipackets++; 1011 (*ifp->if_input)(ifp, m); 1012 } 1013 } 1014 1015 static void 1016 vr_rxeoc(struct vr_softc *sc) 1017 { 1018 struct ifnet *ifp; 1019 int i; 1020 1021 ifp = &sc->arpcom.ac_if; 1022 1023 ifp->if_ierrors++; 1024 1025 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1026 DELAY(10000); 1027 1028 /* Wait for receiver to stop */ 1029 for (i = 0x400; 1030 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1031 i--) 1032 ; /* Wait for receiver to stop */ 1033 1034 if (i == 0) { 1035 if_printf(ifp, "rx shutdown error!\n"); 1036 sc->vr_flags |= VR_F_RESTART; 1037 return; 1038 } 1039 1040 vr_rxeof(sc); 1041 1042 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1043 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1044 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1045 } 1046 1047 /* 1048 * A frame was downloaded to the chip. It's safe for us to clean up 1049 * the list buffers. 1050 */ 1051 static void 1052 vr_txeof(struct vr_softc *sc) 1053 { 1054 struct vr_chain *cur_tx; 1055 struct ifnet *ifp; 1056 1057 ifp = &sc->arpcom.ac_if; 1058 1059 /* Reset the timeout timer; if_txeoc will clear it. */ 1060 ifp->if_timer = 5; 1061 1062 /* Sanity check. */ 1063 if (sc->vr_cdata.vr_tx_head == NULL) 1064 return; 1065 1066 /* 1067 * Go through our tx list and free mbufs for those 1068 * frames that have been transmitted. 1069 */ 1070 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1071 uint32_t txstat; 1072 int i; 1073 1074 cur_tx = sc->vr_cdata.vr_tx_head; 1075 txstat = cur_tx->vr_ptr->vr_status; 1076 1077 if ((txstat & VR_TXSTAT_ABRT) || 1078 (txstat & VR_TXSTAT_UDF)) { 1079 for (i = 0x400; 1080 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1081 i--) 1082 ; /* Wait for chip to shutdown */ 1083 if (i == 0) { 1084 if_printf(ifp, "tx shutdown timeout\n"); 1085 sc->vr_flags |= VR_F_RESTART; 1086 break; 1087 } 1088 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1089 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1090 break; 1091 } 1092 1093 if (txstat & VR_TXSTAT_OWN) 1094 break; 1095 1096 if (txstat & VR_TXSTAT_ERRSUM) { 1097 ifp->if_oerrors++; 1098 if (txstat & VR_TXSTAT_DEFER) 1099 ifp->if_collisions++; 1100 if (txstat & VR_TXSTAT_LATECOLL) 1101 ifp->if_collisions++; 1102 } 1103 1104 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1105 1106 ifp->if_opackets++; 1107 if (cur_tx->vr_mbuf != NULL) { 1108 m_freem(cur_tx->vr_mbuf); 1109 cur_tx->vr_mbuf = NULL; 1110 } 1111 1112 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1113 sc->vr_cdata.vr_tx_head = NULL; 1114 sc->vr_cdata.vr_tx_tail = NULL; 1115 break; 1116 } 1117 1118 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1119 } 1120 } 1121 1122 /* 1123 * TX 'end of channel' interrupt handler. 1124 */ 1125 static void 1126 vr_txeoc(struct vr_softc *sc) 1127 { 1128 struct ifnet *ifp; 1129 1130 ifp = &sc->arpcom.ac_if; 1131 1132 if (sc->vr_cdata.vr_tx_head == NULL) { 1133 ifp->if_flags &= ~IFF_OACTIVE; 1134 sc->vr_cdata.vr_tx_tail = NULL; 1135 ifp->if_timer = 0; 1136 } 1137 } 1138 1139 static void 1140 vr_tick(void *xsc) 1141 { 1142 struct vr_softc *sc = xsc; 1143 struct mii_data *mii; 1144 1145 crit_enter(); 1146 1147 if (sc->vr_flags & VR_F_RESTART) { 1148 if_printf(&sc->arpcom.ac_if, "restarting\n"); 1149 vr_stop(sc); 1150 vr_reset(sc); 1151 vr_init(sc); 1152 sc->vr_flags &= ~VR_F_RESTART; 1153 } 1154 1155 mii = device_get_softc(sc->vr_miibus); 1156 mii_tick(mii); 1157 1158 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc); 1159 1160 crit_exit(); 1161 } 1162 1163 static void 1164 vr_intr(void *arg) 1165 { 1166 struct vr_softc *sc; 1167 struct ifnet *ifp; 1168 uint16_t status; 1169 1170 sc = arg; 1171 ifp = &sc->arpcom.ac_if; 1172 1173 /* Supress unwanted interrupts. */ 1174 if (!(ifp->if_flags & IFF_UP)) { 1175 vr_stop(sc); 1176 return; 1177 } 1178 1179 /* Disable interrupts. */ 1180 if ((ifp->if_flags & IFF_POLLING) == 0) 1181 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1182 1183 for (;;) { 1184 status = CSR_READ_2(sc, VR_ISR); 1185 if (status) 1186 CSR_WRITE_2(sc, VR_ISR, status); 1187 1188 if ((status & VR_INTRS) == 0) 1189 break; 1190 1191 if (status & VR_ISR_RX_OK) 1192 vr_rxeof(sc); 1193 1194 if (status & VR_ISR_RX_DROPPED) { 1195 if_printf(ifp, "rx packet lost\n"); 1196 ifp->if_ierrors++; 1197 } 1198 1199 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1200 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1201 if_printf(ifp, "receive error (%04x)", status); 1202 if (status & VR_ISR_RX_NOBUF) 1203 printf(" no buffers"); 1204 if (status & VR_ISR_RX_OFLOW) 1205 printf(" overflow"); 1206 if (status & VR_ISR_RX_DROPPED) 1207 printf(" packet lost"); 1208 printf("\n"); 1209 vr_rxeoc(sc); 1210 } 1211 1212 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1213 vr_reset(sc); 1214 vr_init(sc); 1215 break; 1216 } 1217 1218 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1219 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1220 vr_txeof(sc); 1221 if ((status & VR_ISR_UDFI) || 1222 (status & VR_ISR_TX_ABRT2) || 1223 (status & VR_ISR_TX_ABRT)) { 1224 ifp->if_oerrors++; 1225 if (sc->vr_cdata.vr_tx_head != NULL) { 1226 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1227 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1228 } 1229 } else { 1230 vr_txeoc(sc); 1231 } 1232 } 1233 1234 } 1235 1236 /* Re-enable interrupts. */ 1237 if ((ifp->if_flags & IFF_POLLING) == 0) 1238 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1239 1240 if (!ifq_is_empty(&ifp->if_snd)) 1241 vr_start(ifp); 1242 } 1243 1244 /* 1245 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1246 * pointers to the fragment pointers. 1247 */ 1248 static int 1249 vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head) 1250 { 1251 int frag = 0; 1252 struct vr_desc *f = NULL; 1253 int total_len; 1254 struct mbuf *m_new; 1255 1256 total_len = 0; 1257 1258 /* 1259 * The VIA Rhine wants packet buffers to be longword 1260 * aligned, but very often our mbufs aren't. Rather than 1261 * waste time trying to decide when to copy and when not 1262 * to copy, just do it all the time. 1263 */ 1264 m_new = m_getl(m_head->m_pkthdr.len, MB_DONTWAIT, MT_DATA, M_PKTHDR, 1265 NULL); 1266 if (m_new == NULL) { 1267 if_printf(&sc->arpcom.ac_if, "no memory for tx list\n"); 1268 return (1); 1269 } 1270 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1271 mtod(m_new, caddr_t)); 1272 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1273 /* 1274 * The Rhine chip doesn't auto-pad, so we have to make 1275 * sure to pad short frames out to the minimum frame length 1276 * ourselves. 1277 */ 1278 if (m_new->m_len < VR_MIN_FRAMELEN) { 1279 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1280 m_new->m_len = m_new->m_pkthdr.len; 1281 } 1282 f = c->vr_ptr; 1283 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1284 f->vr_ctl = total_len = m_new->m_len; 1285 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1286 f->vr_status = 0; 1287 frag = 1; 1288 1289 c->vr_mbuf = m_new; 1290 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1291 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1292 1293 return(0); 1294 } 1295 1296 /* 1297 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1298 * to the mbuf data regions directly in the transmit lists. We also save a 1299 * copy of the pointers since the transmit list fragment pointers are 1300 * physical addresses. 1301 */ 1302 static void 1303 vr_start(struct ifnet *ifp) 1304 { 1305 struct vr_softc *sc; 1306 struct mbuf *m_head = NULL; 1307 struct vr_chain *cur_tx = NULL, *start_tx; 1308 1309 sc = ifp->if_softc; 1310 1311 if (ifp->if_flags & IFF_OACTIVE) 1312 return; 1313 1314 /* Check for an available queue slot. If there are none, punt. */ 1315 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1316 ifp->if_flags |= IFF_OACTIVE; 1317 return; 1318 } 1319 1320 start_tx = sc->vr_cdata.vr_tx_free; 1321 1322 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1323 m_head = ifq_poll(&ifp->if_snd); 1324 if (m_head == NULL) 1325 break; 1326 1327 /* Pick a descriptor off the free list. */ 1328 cur_tx = sc->vr_cdata.vr_tx_free; 1329 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1330 1331 /* Pack the data into the descriptor. */ 1332 if (vr_encap(sc, cur_tx, m_head)) { 1333 ifp->if_flags |= IFF_OACTIVE; 1334 cur_tx = NULL; 1335 break; 1336 } 1337 1338 m_head = ifq_dequeue(&ifp->if_snd); 1339 if (cur_tx != start_tx) 1340 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1341 1342 BPF_MTAP(ifp, m_head); 1343 m_freem(m_head); 1344 1345 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1346 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1347 } 1348 1349 /* If there are no frames queued, bail. */ 1350 if (cur_tx == NULL) 1351 return; 1352 1353 sc->vr_cdata.vr_tx_tail = cur_tx; 1354 1355 if (sc->vr_cdata.vr_tx_head == NULL) 1356 sc->vr_cdata.vr_tx_head = start_tx; 1357 1358 /* 1359 * Set a timeout in case the chip goes out to lunch. 1360 */ 1361 ifp->if_timer = 5; 1362 } 1363 1364 static void 1365 vr_init(void *xsc) 1366 { 1367 struct vr_softc *sc = xsc; 1368 struct ifnet *ifp = &sc->arpcom.ac_if; 1369 struct mii_data *mii; 1370 int i; 1371 1372 mii = device_get_softc(sc->vr_miibus); 1373 1374 crit_enter(); 1375 1376 /* Cancel pending I/O and free all RX/TX buffers. */ 1377 vr_stop(sc); 1378 vr_reset(sc); 1379 1380 /* Set our station address. */ 1381 for (i = 0; i < ETHER_ADDR_LEN; i++) 1382 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1383 1384 /* Set DMA size. */ 1385 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1386 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1387 1388 /* 1389 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1390 * so we must set both. 1391 */ 1392 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1393 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1394 1395 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1396 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1397 1398 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1399 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1400 1401 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1402 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1403 1404 /* Init circular RX list. */ 1405 if (vr_list_rx_init(sc) == ENOBUFS) { 1406 vr_stop(sc); 1407 crit_exit(); 1408 if_printf(ifp, "initialization failed: no memory for rx buffers\n"); 1409 return; 1410 } 1411 1412 /* Init tx descriptors. */ 1413 vr_list_tx_init(sc); 1414 1415 /* If we want promiscuous mode, set the allframes bit. */ 1416 if (ifp->if_flags & IFF_PROMISC) 1417 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1418 else 1419 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1420 1421 /* Set capture broadcast bit to capture broadcast frames. */ 1422 if (ifp->if_flags & IFF_BROADCAST) 1423 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1424 else 1425 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1426 1427 /* 1428 * Program the multicast filter, if necessary. 1429 */ 1430 vr_setmulti(sc); 1431 1432 /* 1433 * Load the address of the RX list. 1434 */ 1435 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1436 1437 /* Enable receiver and transmitter. */ 1438 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1439 VR_CMD_TX_ON|VR_CMD_RX_ON| 1440 VR_CMD_RX_GO); 1441 1442 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1443 1444 /* 1445 * Enable interrupts, unless we are polling. 1446 */ 1447 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1448 if ((ifp->if_flags & IFF_POLLING) == 0) 1449 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1450 1451 mii_mediachg(mii); 1452 1453 ifp->if_flags |= IFF_RUNNING; 1454 ifp->if_flags &= ~IFF_OACTIVE; 1455 1456 crit_exit(); 1457 1458 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc); 1459 } 1460 1461 /* 1462 * Set media options. 1463 */ 1464 static int 1465 vr_ifmedia_upd(struct ifnet *ifp) 1466 { 1467 struct vr_softc *sc; 1468 1469 sc = ifp->if_softc; 1470 1471 if (ifp->if_flags & IFF_UP) 1472 vr_init(sc); 1473 1474 return(0); 1475 } 1476 1477 /* 1478 * Report current media status. 1479 */ 1480 static void 1481 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1482 { 1483 struct vr_softc *sc; 1484 struct mii_data *mii; 1485 1486 sc = ifp->if_softc; 1487 mii = device_get_softc(sc->vr_miibus); 1488 mii_pollstat(mii); 1489 ifmr->ifm_active = mii->mii_media_active; 1490 ifmr->ifm_status = mii->mii_media_status; 1491 } 1492 1493 static int 1494 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1495 { 1496 struct vr_softc *sc = ifp->if_softc; 1497 struct ifreq *ifr = (struct ifreq *) data; 1498 struct mii_data *mii; 1499 int error = 0; 1500 1501 crit_enter(); 1502 1503 switch(command) { 1504 case SIOCSIFFLAGS: 1505 if (ifp->if_flags & IFF_UP) { 1506 vr_init(sc); 1507 } else { 1508 if (ifp->if_flags & IFF_RUNNING) 1509 vr_stop(sc); 1510 } 1511 error = 0; 1512 break; 1513 case SIOCADDMULTI: 1514 case SIOCDELMULTI: 1515 vr_setmulti(sc); 1516 error = 0; 1517 break; 1518 case SIOCGIFMEDIA: 1519 case SIOCSIFMEDIA: 1520 mii = device_get_softc(sc->vr_miibus); 1521 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1522 break; 1523 default: 1524 error = ether_ioctl(ifp, command, data); 1525 break; 1526 } 1527 1528 crit_exit(); 1529 1530 return(error); 1531 } 1532 1533 #ifdef DEVICE_POLLING 1534 1535 static void 1536 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1537 { 1538 struct vr_softc *sc = ifp->if_softc; 1539 1540 switch(cmd) { 1541 case POLL_REGISTER: 1542 /* disable interrupts */ 1543 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1544 break; 1545 case POLL_DEREGISTER: 1546 /* enable interrupts */ 1547 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1548 break; 1549 default: 1550 vr_intr(sc); 1551 break; 1552 } 1553 } 1554 #endif 1555 1556 static void 1557 vr_watchdog(struct ifnet *ifp) 1558 { 1559 struct vr_softc *sc; 1560 1561 sc = ifp->if_softc; 1562 1563 ifp->if_oerrors++; 1564 if_printf(ifp, "watchdog timeout\n"); 1565 1566 #ifdef DEVICE_POLLING 1567 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) { 1568 if_printf(ifp, "ints don't seem to be working, " 1569 "emergency switch to polling\n"); 1570 emergency_poll_enable("if_vr"); 1571 ether_poll_register(ifp); /* XXX illegal */ 1572 } else 1573 #endif 1574 { 1575 vr_stop(sc); 1576 vr_reset(sc); 1577 vr_init(sc); 1578 } 1579 1580 if (!ifq_is_empty(&ifp->if_snd)) 1581 vr_start(ifp); 1582 } 1583 1584 /* 1585 * Stop the adapter and free any mbufs allocated to the 1586 * RX and TX lists. 1587 */ 1588 static void 1589 vr_stop(struct vr_softc *sc) 1590 { 1591 int i; 1592 struct ifnet *ifp; 1593 1594 ifp = &sc->arpcom.ac_if; 1595 ifp->if_timer = 0; 1596 1597 callout_stop(&sc->vr_stat_timer); 1598 1599 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1600 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1601 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1602 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1603 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1604 1605 /* 1606 * Free data in the RX lists. 1607 */ 1608 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1609 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1610 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1611 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1612 } 1613 } 1614 bzero((char *)&sc->vr_ldata->vr_rx_list, 1615 sizeof(sc->vr_ldata->vr_rx_list)); 1616 1617 /* 1618 * Free the TX list buffers. 1619 */ 1620 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1621 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1622 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1623 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1624 } 1625 } 1626 1627 bzero((char *)&sc->vr_ldata->vr_tx_list, 1628 sizeof(sc->vr_ldata->vr_tx_list)); 1629 1630 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1631 } 1632 1633 /* 1634 * Stop all chip I/O so that the kernel's probe routines don't 1635 * get confused by errant DMAs when rebooting. 1636 */ 1637 static void 1638 vr_shutdown(device_t dev) 1639 { 1640 struct vr_softc *sc; 1641 1642 sc = device_get_softc(dev); 1643 1644 vr_stop(sc); 1645 } 1646