1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $ 33 */ 34 35 /* 36 * Winbond fast ethernet PCI NIC driver 37 * 38 * Supports various cheap network adapters based on the Winbond W89C840F 39 * fast ethernet controller chip. This includes adapters manufactured by 40 * Winbond itself and some made by Linksys. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/sockio.h> 89 #include <sys/mbuf.h> 90 #include <sys/malloc.h> 91 #include <sys/kernel.h> 92 #include <sys/socket.h> 93 #include <sys/queue.h> 94 #include <sys/serialize.h> 95 #include <sys/bus.h> 96 #include <sys/rman.h> 97 #include <sys/thread2.h> 98 #include <sys/interrupt.h> 99 100 #include <net/if.h> 101 #include <net/ifq_var.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 107 #include <net/bpf.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 112 #include <bus/pci/pcidevs.h> 113 #include <bus/pci/pcireg.h> 114 #include <bus/pci/pcivar.h> 115 116 #include <dev/netif/mii_layer/mii.h> 117 #include <dev/netif/mii_layer/miivar.h> 118 119 /* "controller miibus0" required. See GENERIC if you get errors here. */ 120 #include "miibus_if.h" 121 122 #define WB_USEIOSPACE 123 124 #include "if_wbreg.h" 125 126 /* 127 * Various supported device vendors/types and their names. 128 */ 129 static struct wb_type wb_devs[] = { 130 { PCI_VENDOR_WINBOND, PCI_PRODUCT_WINBOND_W89C840F, 131 "Winbond W89C840F 10/100BaseTX" }, 132 { PCI_VENDOR_COMPEX, PCI_PRODUCT_COMPEX_RL100ATX, 133 "Compex RL100-ATX 10/100baseTX" }, 134 { 0, 0, NULL } 135 }; 136 137 static int wb_probe(device_t); 138 static int wb_attach(device_t); 139 static int wb_detach(device_t); 140 141 static void wb_bfree(void *); 142 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 143 struct mbuf *); 144 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 145 146 static void wb_rxeof(struct wb_softc *); 147 static void wb_rxeoc(struct wb_softc *); 148 static void wb_txeof(struct wb_softc *); 149 static void wb_txeoc(struct wb_softc *); 150 static void wb_intr(void *); 151 static void wb_tick(void *); 152 static void wb_start(struct ifnet *); 153 static int wb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 154 static void wb_init(void *); 155 static void wb_stop(struct wb_softc *); 156 static void wb_watchdog(struct ifnet *); 157 static void wb_shutdown(device_t); 158 static int wb_ifmedia_upd(struct ifnet *); 159 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 160 161 static void wb_eeprom_putbyte(struct wb_softc *, int); 162 static void wb_eeprom_getword(struct wb_softc *, int, uint16_t *); 163 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int); 164 static void wb_mii_sync(struct wb_softc *); 165 static void wb_mii_send(struct wb_softc *, uint32_t, int); 166 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 167 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 168 169 static void wb_setcfg(struct wb_softc *, uint32_t); 170 static void wb_setmulti(struct wb_softc *); 171 static void wb_reset(struct wb_softc *); 172 static void wb_fixmedia(struct wb_softc *); 173 static int wb_list_rx_init(struct wb_softc *); 174 static int wb_list_tx_init(struct wb_softc *); 175 176 static int wb_miibus_readreg(device_t, int, int); 177 static int wb_miibus_writereg(device_t, int, int, int); 178 static void wb_miibus_statchg(device_t); 179 180 #ifdef WB_USEIOSPACE 181 #define WB_RES SYS_RES_IOPORT 182 #define WB_RID WB_PCI_LOIO 183 #else 184 #define WB_RES SYS_RES_MEMORY 185 #define WB_RID WB_PCI_LOMEM 186 #endif 187 188 static device_method_t wb_methods[] = { 189 /* Device interface */ 190 DEVMETHOD(device_probe, wb_probe), 191 DEVMETHOD(device_attach, wb_attach), 192 DEVMETHOD(device_detach, wb_detach), 193 DEVMETHOD(device_shutdown, wb_shutdown), 194 195 /* bus interface, for miibus */ 196 DEVMETHOD(bus_print_child, bus_generic_print_child), 197 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 198 199 /* MII interface */ 200 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 201 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 202 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 203 { 0, 0 } 204 }; 205 206 static DEFINE_CLASS_0(wb, wb_driver, wb_methods, sizeof(struct wb_softc)); 207 static devclass_t wb_devclass; 208 209 DECLARE_DUMMY_MODULE(if_wb); 210 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, NULL, NULL); 211 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, NULL, NULL); 212 213 #define WB_SETBIT(sc, reg, x) \ 214 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 215 216 #define WB_CLRBIT(sc, reg, x) \ 217 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 218 219 #define SIO_SET(x) \ 220 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) | (x)) 221 222 #define SIO_CLR(x) \ 223 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) & ~(x)) 224 225 /* 226 * Send a read command and address to the EEPROM, check for ACK. 227 */ 228 static void 229 wb_eeprom_putbyte(struct wb_softc *sc, int addr) 230 { 231 int d, i; 232 233 d = addr | WB_EECMD_READ; 234 235 /* 236 * Feed in each bit and stobe the clock. 237 */ 238 for (i = 0x400; i; i >>= 1) { 239 if (d & i) 240 SIO_SET(WB_SIO_EE_DATAIN); 241 else 242 SIO_CLR(WB_SIO_EE_DATAIN); 243 DELAY(100); 244 SIO_SET(WB_SIO_EE_CLK); 245 DELAY(150); 246 SIO_CLR(WB_SIO_EE_CLK); 247 DELAY(100); 248 } 249 } 250 251 /* 252 * Read a word of data stored in the EEPROM at address 'addr.' 253 */ 254 static void 255 wb_eeprom_getword(struct wb_softc *sc, int addr, uint16_t *dest) 256 { 257 int i; 258 uint16_t word = 0; 259 260 /* Enter EEPROM access mode. */ 261 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 262 263 /* 264 * Send address of word we want to read. 265 */ 266 wb_eeprom_putbyte(sc, addr); 267 268 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 269 270 /* 271 * Start reading bits from EEPROM. 272 */ 273 for (i = 0x8000; i; i >>= 1) { 274 SIO_SET(WB_SIO_EE_CLK); 275 DELAY(100); 276 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 277 word |= i; 278 SIO_CLR(WB_SIO_EE_CLK); 279 DELAY(100); 280 } 281 282 /* Turn off EEPROM access mode. */ 283 CSR_WRITE_4(sc, WB_SIO, 0); 284 285 *dest = word; 286 } 287 288 /* 289 * Read a sequence of words from the EEPROM. 290 */ 291 static void 292 wb_read_eeprom(struct wb_softc *sc, caddr_t dest, int off, int cnt) 293 { 294 int i; 295 uint16_t word = 0, *ptr; 296 297 for (i = 0; i < cnt; i++) { 298 wb_eeprom_getword(sc, off + i, &word); 299 ptr = (uint16_t *)(dest + (i * 2)); 300 *ptr = word; 301 } 302 } 303 304 /* 305 * Sync the PHYs by setting data bit and strobing the clock 32 times. 306 */ 307 static void 308 wb_mii_sync(struct wb_softc *sc) 309 { 310 int i; 311 312 SIO_SET(WB_SIO_MII_DIR | WB_SIO_MII_DATAIN); 313 314 for (i = 0; i < 32; i++) { 315 SIO_SET(WB_SIO_MII_CLK); 316 DELAY(1); 317 SIO_CLR(WB_SIO_MII_CLK); 318 DELAY(1); 319 } 320 } 321 322 /* 323 * Clock a series of bits through the MII. 324 */ 325 static void 326 wb_mii_send(struct wb_softc *sc, uint32_t bits, int cnt) 327 { 328 int i; 329 330 SIO_CLR(WB_SIO_MII_CLK); 331 332 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 333 if (bits & i) 334 SIO_SET(WB_SIO_MII_DATAIN); 335 else 336 SIO_CLR(WB_SIO_MII_DATAIN); 337 DELAY(1); 338 SIO_CLR(WB_SIO_MII_CLK); 339 DELAY(1); 340 SIO_SET(WB_SIO_MII_CLK); 341 } 342 } 343 344 /* 345 * Read an PHY register through the MII. 346 */ 347 static int 348 wb_mii_readreg(struct wb_softc *sc, struct wb_mii_frame *frame) 349 { 350 int ack, i; 351 352 crit_enter(); 353 354 /* 355 * Set up frame for RX. 356 */ 357 frame->mii_stdelim = WB_MII_STARTDELIM; 358 frame->mii_opcode = WB_MII_READOP; 359 frame->mii_turnaround = 0; 360 frame->mii_data = 0; 361 362 CSR_WRITE_4(sc, WB_SIO, 0); 363 364 /* 365 * Turn on data xmit. 366 */ 367 SIO_SET(WB_SIO_MII_DIR); 368 369 wb_mii_sync(sc); 370 371 /* 372 * Send command/address info. 373 */ 374 wb_mii_send(sc, frame->mii_stdelim, 2); 375 wb_mii_send(sc, frame->mii_opcode, 2); 376 wb_mii_send(sc, frame->mii_phyaddr, 5); 377 wb_mii_send(sc, frame->mii_regaddr, 5); 378 379 /* Idle bit */ 380 SIO_CLR((WB_SIO_MII_CLK | WB_SIO_MII_DATAIN)); 381 DELAY(1); 382 SIO_SET(WB_SIO_MII_CLK); 383 DELAY(1); 384 385 /* Turn off xmit. */ 386 SIO_CLR(WB_SIO_MII_DIR); 387 /* Check for ack */ 388 SIO_CLR(WB_SIO_MII_CLK); 389 DELAY(1); 390 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 391 SIO_SET(WB_SIO_MII_CLK); 392 DELAY(1); 393 SIO_CLR(WB_SIO_MII_CLK); 394 DELAY(1); 395 SIO_SET(WB_SIO_MII_CLK); 396 DELAY(1); 397 398 /* 399 * Now try reading data bits. If the ack failed, we still 400 * need to clock through 16 cycles to keep the PHY(s) in sync. 401 */ 402 if (ack) { 403 for(i = 0; i < 16; i++) { 404 SIO_CLR(WB_SIO_MII_CLK); 405 DELAY(1); 406 SIO_SET(WB_SIO_MII_CLK); 407 DELAY(1); 408 } 409 goto fail; 410 } 411 412 for (i = 0x8000; i; i >>= 1) { 413 SIO_CLR(WB_SIO_MII_CLK); 414 DELAY(1); 415 if (!ack) { 416 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 417 frame->mii_data |= i; 418 DELAY(1); 419 } 420 SIO_SET(WB_SIO_MII_CLK); 421 DELAY(1); 422 } 423 424 fail: 425 426 SIO_CLR(WB_SIO_MII_CLK); 427 DELAY(1); 428 SIO_SET(WB_SIO_MII_CLK); 429 DELAY(1); 430 431 crit_exit(); 432 433 if (ack) 434 return(1); 435 return(0); 436 } 437 438 /* 439 * Write to a PHY register through the MII. 440 */ 441 static int 442 wb_mii_writereg(struct wb_softc *sc, struct wb_mii_frame *frame) 443 { 444 445 crit_enter(); 446 /* 447 * Set up frame for TX. 448 */ 449 450 frame->mii_stdelim = WB_MII_STARTDELIM; 451 frame->mii_opcode = WB_MII_WRITEOP; 452 frame->mii_turnaround = WB_MII_TURNAROUND; 453 454 /* 455 * Turn on data output. 456 */ 457 SIO_SET(WB_SIO_MII_DIR); 458 459 wb_mii_sync(sc); 460 461 wb_mii_send(sc, frame->mii_stdelim, 2); 462 wb_mii_send(sc, frame->mii_opcode, 2); 463 wb_mii_send(sc, frame->mii_phyaddr, 5); 464 wb_mii_send(sc, frame->mii_regaddr, 5); 465 wb_mii_send(sc, frame->mii_turnaround, 2); 466 wb_mii_send(sc, frame->mii_data, 16); 467 468 /* Idle bit. */ 469 SIO_SET(WB_SIO_MII_CLK); 470 DELAY(1); 471 SIO_CLR(WB_SIO_MII_CLK); 472 DELAY(1); 473 474 /* 475 * Turn off xmit. 476 */ 477 SIO_CLR(WB_SIO_MII_DIR); 478 479 crit_exit(); 480 481 return(0); 482 } 483 484 static int 485 wb_miibus_readreg(device_t dev, int phy, int reg) 486 { 487 struct wb_softc *sc = device_get_softc(dev); 488 struct wb_mii_frame frame; 489 490 bzero(&frame, sizeof(frame)); 491 492 frame.mii_phyaddr = phy; 493 frame.mii_regaddr = reg; 494 wb_mii_readreg(sc, &frame); 495 496 return(frame.mii_data); 497 } 498 499 static int 500 wb_miibus_writereg(device_t dev, int phy, int reg, int data) 501 { 502 struct wb_softc *sc = device_get_softc(dev); 503 struct wb_mii_frame frame; 504 505 bzero(&frame, sizeof(frame)); 506 507 frame.mii_phyaddr = phy; 508 frame.mii_regaddr = reg; 509 frame.mii_data = data; 510 511 wb_mii_writereg(sc, &frame); 512 513 return(0); 514 } 515 516 static void 517 wb_miibus_statchg(device_t dev) 518 { 519 struct wb_softc *sc = device_get_softc(dev); 520 struct mii_data *mii; 521 522 mii = device_get_softc(sc->wb_miibus); 523 wb_setcfg(sc, mii->mii_media_active); 524 } 525 526 /* 527 * Program the 64-bit multicast hash filter. 528 */ 529 static void 530 wb_setmulti(struct wb_softc *sc) 531 { 532 struct ifnet *ifp = &sc->arpcom.ac_if; 533 int h = 0, mcnt = 0; 534 uint32_t hashes[2] = { 0, 0 }; 535 struct ifmultiaddr *ifma; 536 uint32_t rxfilt; 537 538 rxfilt = CSR_READ_4(sc, WB_NETCFG); 539 540 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 541 rxfilt |= WB_NETCFG_RX_MULTI; 542 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 543 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 544 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 545 return; 546 } 547 548 /* first, zot all the existing hash bits */ 549 CSR_WRITE_4(sc, WB_MAR0, 0); 550 CSR_WRITE_4(sc, WB_MAR1, 0); 551 552 /* now program new ones */ 553 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 554 if (ifma->ifma_addr->sa_family != AF_LINK) 555 continue; 556 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 557 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 558 if (h < 32) 559 hashes[0] |= (1 << h); 560 else 561 hashes[1] |= (1 << (h - 32)); 562 mcnt++; 563 } 564 565 if (mcnt) 566 rxfilt |= WB_NETCFG_RX_MULTI; 567 else 568 rxfilt &= ~WB_NETCFG_RX_MULTI; 569 570 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 571 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 572 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 573 } 574 575 /* 576 * The Winbond manual states that in order to fiddle with the 577 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 578 * first have to put the transmit and/or receive logic in the idle state. 579 */ 580 static void 581 wb_setcfg(struct wb_softc *sc, uint32_t media) 582 { 583 int i, restart = 0; 584 585 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)) { 586 restart = 1; 587 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)); 588 589 for (i = 0; i < WB_TIMEOUT; i++) { 590 DELAY(10); 591 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 592 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 593 break; 594 } 595 596 if (i == WB_TIMEOUT) { 597 if_printf(&sc->arpcom.ac_if, "failed to force tx and " 598 "rx to idle state\n"); 599 } 600 } 601 602 if (IFM_SUBTYPE(media) == IFM_10_T) 603 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 604 else 605 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 606 607 if ((media & IFM_GMASK) == IFM_FDX) 608 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 609 else 610 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 611 612 if (restart) 613 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON | WB_NETCFG_RX_ON); 614 } 615 616 static void 617 wb_reset(struct wb_softc *sc) 618 { 619 int i; 620 struct mii_data *mii; 621 622 CSR_WRITE_4(sc, WB_NETCFG, 0); 623 CSR_WRITE_4(sc, WB_BUSCTL, 0); 624 CSR_WRITE_4(sc, WB_TXADDR, 0); 625 CSR_WRITE_4(sc, WB_RXADDR, 0); 626 627 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 628 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 629 630 for (i = 0; i < WB_TIMEOUT; i++) { 631 DELAY(10); 632 if ((CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET) == 0) 633 break; 634 } 635 if (i == WB_TIMEOUT) 636 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 637 638 /* Wait a little while for the chip to get its brains in order. */ 639 DELAY(1000); 640 641 if (sc->wb_miibus == NULL) 642 return; 643 644 mii = device_get_softc(sc->wb_miibus); 645 if (mii == NULL) 646 return; 647 648 if (mii->mii_instance) { 649 struct mii_softc *miisc; 650 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 651 mii_phy_reset(miisc); 652 } 653 } 654 655 static void 656 wb_fixmedia(struct wb_softc *sc) 657 { 658 struct mii_data *mii; 659 uint32_t media; 660 661 if (sc->wb_miibus == NULL) 662 return; 663 664 mii = device_get_softc(sc->wb_miibus); 665 666 mii_pollstat(mii); 667 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 668 media = mii->mii_media_active & ~IFM_10_T; 669 media |= IFM_100_TX; 670 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 671 media = mii->mii_media_active & ~IFM_100_TX; 672 media |= IFM_10_T; 673 } else 674 return; 675 676 ifmedia_set(&mii->mii_media, media); 677 } 678 679 /* 680 * Probe for a Winbond chip. Check the PCI vendor and device 681 * IDs against our list and return a device name if we find a match. 682 */ 683 static int 684 wb_probe(device_t dev) 685 { 686 struct wb_type *t; 687 uint16_t vendor, product; 688 689 vendor = pci_get_vendor(dev); 690 product = pci_get_device(dev); 691 692 for (t = wb_devs; t->wb_name != NULL; t++) { 693 if (vendor == t->wb_vid && product == t->wb_did) { 694 device_set_desc(dev, t->wb_name); 695 return(0); 696 } 697 } 698 699 return(ENXIO); 700 } 701 702 /* 703 * Attach the interface. Allocate softc structures, do ifmedia 704 * setup and ethernet/BPF attach. 705 */ 706 static int 707 wb_attach(device_t dev) 708 { 709 u_char eaddr[ETHER_ADDR_LEN]; 710 struct wb_softc *sc; 711 struct ifnet *ifp; 712 int error = 0, rid; 713 714 sc = device_get_softc(dev); 715 callout_init(&sc->wb_stat_timer); 716 717 /* 718 * Handle power management nonsense. 719 */ 720 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 721 uint32_t iobase, membase, irq; 722 723 /* Save important PCI config data. */ 724 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 725 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 726 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 727 728 /* Reset the power state. */ 729 device_printf(dev, "chip is in D%d power mode " 730 "-- setting to D0\n", pci_get_powerstate(dev)); 731 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 732 733 /* Restore PCI config data. */ 734 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 735 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 736 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 737 } 738 739 pci_enable_busmaster(dev); 740 741 rid = WB_RID; 742 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 743 744 if (sc->wb_res == NULL) { 745 device_printf(dev, "couldn't map ports/memory\n"); 746 error = ENXIO; 747 goto fail; 748 } 749 750 sc->wb_btag = rman_get_bustag(sc->wb_res); 751 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 752 753 /* Allocate interrupt */ 754 rid = 0; 755 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 756 RF_SHAREABLE | RF_ACTIVE); 757 758 if (sc->wb_irq == NULL) { 759 device_printf(dev, "couldn't map interrupt\n"); 760 error = ENXIO; 761 goto fail; 762 } 763 764 /* Save the cache line size. */ 765 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 766 767 ifp = &sc->arpcom.ac_if; 768 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 769 770 /* Reset the adapter. */ 771 wb_reset(sc); 772 773 /* 774 * Get station address from the EEPROM. 775 */ 776 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3); 777 778 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 779 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 780 781 if (sc->wb_ldata == NULL) { 782 device_printf(dev, "no memory for list buffers!\n"); 783 error = ENXIO; 784 goto fail; 785 } 786 787 ifp->if_softc = sc; 788 ifp->if_mtu = ETHERMTU; 789 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 790 ifp->if_ioctl = wb_ioctl; 791 ifp->if_start = wb_start; 792 ifp->if_watchdog = wb_watchdog; 793 ifp->if_init = wb_init; 794 ifp->if_baudrate = 10000000; 795 ifq_set_maxlen(&ifp->if_snd, WB_TX_LIST_CNT - 1); 796 ifq_set_ready(&ifp->if_snd); 797 798 /* 799 * Do MII setup. 800 */ 801 if (mii_phy_probe(dev, &sc->wb_miibus, 802 wb_ifmedia_upd, wb_ifmedia_sts)) { 803 error = ENXIO; 804 goto fail; 805 } 806 807 /* 808 * Call MI attach routine. 809 */ 810 ether_ifattach(ifp, eaddr, NULL); 811 812 error = bus_setup_intr(dev, sc->wb_irq, INTR_MPSAFE, 813 wb_intr, sc, &sc->wb_intrhand, 814 ifp->if_serializer); 815 816 if (error) { 817 device_printf(dev, "couldn't set up irq\n"); 818 ether_ifdetach(ifp); 819 goto fail; 820 } 821 822 ifp->if_cpuid = rman_get_cpuid(sc->wb_irq); 823 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 824 825 return(0); 826 827 fail: 828 wb_detach(dev); 829 return(error); 830 } 831 832 static int 833 wb_detach(device_t dev) 834 { 835 struct wb_softc *sc = device_get_softc(dev); 836 struct ifnet *ifp = &sc->arpcom.ac_if; 837 838 839 if (device_is_attached(dev)) { 840 lwkt_serialize_enter(ifp->if_serializer); 841 wb_stop(sc); 842 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 843 lwkt_serialize_exit(ifp->if_serializer); 844 845 ether_ifdetach(ifp); 846 } 847 848 if (sc->wb_miibus) 849 device_delete_child(dev, sc->wb_miibus); 850 bus_generic_detach(dev); 851 852 if (sc->wb_irq) 853 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 854 if (sc->wb_res) 855 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 856 if (sc->wb_ldata_ptr) { 857 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8, 858 M_DEVBUF); 859 } 860 861 return(0); 862 } 863 864 /* 865 * Initialize the transmit descriptors. 866 */ 867 static int 868 wb_list_tx_init(struct wb_softc *sc) 869 { 870 struct wb_chain_data *cd; 871 struct wb_list_data *ld; 872 int i, nexti; 873 874 cd = &sc->wb_cdata; 875 ld = sc->wb_ldata; 876 877 for (i = 0; i < WB_TX_LIST_CNT; i++) { 878 nexti = (i == WB_TX_LIST_CNT - 1) ? 0 : i + 1; 879 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 880 cd->wb_tx_chain[i].wb_nextdesc = &cd->wb_tx_chain[nexti]; 881 } 882 883 cd->wb_tx_free = &cd->wb_tx_chain[0]; 884 cd->wb_tx_tail = cd->wb_tx_head = NULL; 885 886 return(0); 887 } 888 889 /* 890 * Initialize the RX descriptors and allocate mbufs for them. Note that 891 * we arrange the descriptors in a closed ring, so that the last descriptor 892 * points back to the first. 893 */ 894 static int 895 wb_list_rx_init(struct wb_softc *sc) 896 { 897 struct wb_chain_data *cd; 898 struct wb_list_data *ld; 899 int i, nexti; 900 901 cd = &sc->wb_cdata; 902 ld = sc->wb_ldata; 903 904 for (i = 0; i < WB_RX_LIST_CNT; i++) { 905 cd->wb_rx_chain[i].wb_ptr = &ld->wb_rx_list[i]; 906 cd->wb_rx_chain[i].wb_buf = &ld->wb_rxbufs[i]; 907 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 908 return(ENOBUFS); 909 nexti = (WB_RX_LIST_CNT - 1) ? 0 : i + 1; 910 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[nexti]; 911 ld->wb_rx_list[i].wb_next = vtophys(&ld->wb_rx_list[nexti]); 912 } 913 914 cd->wb_rx_head = &cd->wb_rx_chain[0]; 915 916 return(0); 917 } 918 919 static void 920 wb_bfree(void *arg) 921 { 922 } 923 924 /* 925 * Initialize an RX descriptor and attach an MBUF cluster. 926 */ 927 static int 928 wb_newbuf(struct wb_softc *sc, struct wb_chain_onefrag *c, struct mbuf *m) 929 { 930 struct mbuf *m_new = NULL; 931 932 if (m == NULL) { 933 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 934 if (m_new == NULL) 935 return(ENOBUFS); 936 937 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 938 m_new->m_flags |= M_EXT; 939 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 940 m_new->m_len = WB_BUFBYTES; 941 m_new->m_ext.ext_free = wb_bfree; 942 m_new->m_ext.ext_ref = wb_bfree; 943 } else { 944 m_new = m; 945 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 946 m_new->m_data = m_new->m_ext.ext_buf; 947 } 948 949 m_adj(m_new, sizeof(uint64_t)); 950 951 c->wb_mbuf = m_new; 952 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 953 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 954 c->wb_ptr->wb_status = WB_RXSTAT; 955 956 return(0); 957 } 958 959 /* 960 * A frame has been uploaded: pass the resulting mbuf chain up to 961 * the higher level protocols. 962 */ 963 static void 964 wb_rxeof(struct wb_softc *sc) 965 { 966 struct ifnet *ifp = &sc->arpcom.ac_if; 967 struct mbuf *m, *m0; 968 struct wb_chain_onefrag *cur_rx; 969 int total_len = 0; 970 uint32_t rxstat; 971 972 for (;;) { 973 rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status; 974 if ((rxstat & WB_RXSTAT_OWN) == 0) 975 break; 976 977 cur_rx = sc->wb_cdata.wb_rx_head; 978 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 979 980 m = cur_rx->wb_mbuf; 981 982 if ((rxstat & WB_RXSTAT_MIIERR) || 983 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 984 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 985 (rxstat & WB_RXSTAT_LASTFRAG) == 0|| 986 (rxstat & WB_RXSTAT_RXCMP) == 0) { 987 ifp->if_ierrors++; 988 wb_newbuf(sc, cur_rx, m); 989 if_printf(ifp, "receiver babbling: possible chip " 990 "bug, forcing reset\n"); 991 wb_fixmedia(sc); 992 wb_reset(sc); 993 wb_init(sc); 994 return; 995 } 996 997 if (rxstat & WB_RXSTAT_RXERR) { 998 ifp->if_ierrors++; 999 wb_newbuf(sc, cur_rx, m); 1000 break; 1001 } 1002 1003 /* No errors; receive the packet. */ 1004 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1005 1006 /* 1007 * XXX The Winbond chip includes the CRC with every 1008 * received frame, and there's no way to turn this 1009 * behavior off (at least, I can't find anything in 1010 * the manual that explains how to do it) so we have 1011 * to trim off the CRC manually. 1012 */ 1013 total_len -= ETHER_CRC_LEN; 1014 1015 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1016 total_len + ETHER_ALIGN, 0, ifp, NULL); 1017 wb_newbuf(sc, cur_rx, m); 1018 if (m0 == NULL) { 1019 ifp->if_ierrors++; 1020 break; 1021 } 1022 m_adj(m0, ETHER_ALIGN); 1023 m = m0; 1024 1025 ifp->if_ipackets++; 1026 ifp->if_input(ifp, m); 1027 } 1028 } 1029 1030 static void 1031 wb_rxeoc(struct wb_softc *sc) 1032 { 1033 wb_rxeof(sc); 1034 1035 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1036 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1037 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1038 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1039 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1040 } 1041 1042 /* 1043 * A frame was downloaded to the chip. It's safe for us to clean up 1044 * the list buffers. 1045 */ 1046 static void 1047 wb_txeof(struct wb_softc *sc) 1048 { 1049 struct ifnet *ifp = &sc->arpcom.ac_if; 1050 struct wb_chain *cur_tx; 1051 1052 /* Clear the timeout timer. */ 1053 ifp->if_timer = 0; 1054 1055 if (sc->wb_cdata.wb_tx_head == NULL) 1056 return; 1057 1058 /* 1059 * Go through our tx list and free mbufs for those 1060 * frames that have been transmitted. 1061 */ 1062 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1063 uint32_t txstat; 1064 1065 cur_tx = sc->wb_cdata.wb_tx_head; 1066 txstat = WB_TXSTATUS(cur_tx); 1067 1068 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1069 break; 1070 1071 if (txstat & WB_TXSTAT_TXERR) { 1072 ifp->if_oerrors++; 1073 if (txstat & WB_TXSTAT_ABORT) 1074 ifp->if_collisions++; 1075 if (txstat & WB_TXSTAT_LATECOLL) 1076 ifp->if_collisions++; 1077 } 1078 1079 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1080 1081 ifp->if_opackets++; 1082 m_freem(cur_tx->wb_mbuf); 1083 cur_tx->wb_mbuf = NULL; 1084 1085 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1086 sc->wb_cdata.wb_tx_head = NULL; 1087 sc->wb_cdata.wb_tx_tail = NULL; 1088 break; 1089 } 1090 1091 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1092 } 1093 } 1094 1095 /* 1096 * TX 'end of channel' interrupt handler. 1097 */ 1098 static void 1099 wb_txeoc(struct wb_softc *sc) 1100 { 1101 struct ifnet *ifp = &sc->arpcom.ac_if; 1102 1103 ifp->if_timer = 0; 1104 1105 if (sc->wb_cdata.wb_tx_head == NULL) { 1106 ifp->if_flags &= ~IFF_OACTIVE; 1107 sc->wb_cdata.wb_tx_tail = NULL; 1108 } else if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1109 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1110 ifp->if_timer = 5; 1111 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1112 } 1113 } 1114 1115 static void 1116 wb_intr(void *arg) 1117 { 1118 struct wb_softc *sc = arg; 1119 struct ifnet *ifp = &sc->arpcom.ac_if; 1120 uint32_t status; 1121 1122 if ((ifp->if_flags & IFF_UP) == 0) 1123 return; 1124 1125 /* Disable interrupts. */ 1126 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1127 1128 for (;;) { 1129 status = CSR_READ_4(sc, WB_ISR); 1130 if (status) 1131 CSR_WRITE_4(sc, WB_ISR, status); 1132 1133 if ((status & WB_INTRS) == 0) 1134 break; 1135 1136 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1137 ifp->if_ierrors++; 1138 wb_reset(sc); 1139 if (status & WB_ISR_RX_ERR) 1140 wb_fixmedia(sc); 1141 wb_init(sc); 1142 continue; 1143 } 1144 1145 if (status & WB_ISR_RX_OK) 1146 wb_rxeof(sc); 1147 1148 if (status & WB_ISR_RX_IDLE) 1149 wb_rxeoc(sc); 1150 1151 if (status & WB_ISR_TX_OK) 1152 wb_txeof(sc); 1153 1154 if (status & WB_ISR_TX_NOBUF) 1155 wb_txeoc(sc); 1156 1157 if (status & WB_ISR_TX_IDLE) { 1158 wb_txeof(sc); 1159 if (sc->wb_cdata.wb_tx_head != NULL) { 1160 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1161 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1162 } 1163 } 1164 1165 if (status & WB_ISR_TX_UNDERRUN) { 1166 ifp->if_oerrors++; 1167 wb_txeof(sc); 1168 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1169 /* Jack up TX threshold */ 1170 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1171 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1172 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1173 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1174 } 1175 1176 if (status & WB_ISR_BUS_ERR) { 1177 wb_reset(sc); 1178 wb_init(sc); 1179 } 1180 } 1181 1182 /* Re-enable interrupts. */ 1183 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1184 1185 if (!ifq_is_empty(&ifp->if_snd)) 1186 if_devstart(ifp); 1187 } 1188 1189 static void 1190 wb_tick(void *xsc) 1191 { 1192 struct wb_softc *sc = xsc; 1193 struct ifnet *ifp = &sc->arpcom.ac_if; 1194 struct mii_data *mii = device_get_softc(sc->wb_miibus); 1195 1196 lwkt_serialize_enter(ifp->if_serializer); 1197 mii_tick(mii); 1198 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc); 1199 lwkt_serialize_exit(ifp->if_serializer); 1200 } 1201 1202 /* 1203 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1204 * pointers to the fragment pointers. 1205 */ 1206 static int 1207 wb_encap(struct wb_softc *sc, struct wb_chain *c, struct mbuf *m_head) 1208 { 1209 struct wb_desc *f = NULL; 1210 struct mbuf *m; 1211 int frag, total_len; 1212 1213 /* 1214 * Start packing the mbufs in this chain into 1215 * the fragment pointers. Stop when we run out 1216 * of fragments or hit the end of the mbuf chain. 1217 */ 1218 total_len = 0; 1219 1220 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1221 if (m->m_len != 0) { 1222 if (frag == WB_MAXFRAGS) 1223 break; 1224 total_len += m->m_len; 1225 f = &c->wb_ptr->wb_frag[frag]; 1226 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1227 if (frag == 0) { 1228 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1229 f->wb_status = 0; 1230 } else { 1231 f->wb_status = WB_TXSTAT_OWN; 1232 } 1233 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1234 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1235 frag++; 1236 } 1237 } 1238 1239 /* 1240 * Handle special case: we used up all 16 fragments, 1241 * but we have more mbufs left in the chain. Copy the 1242 * data into an mbuf cluster. Note that we don't 1243 * bother clearing the values in the other fragment 1244 * pointers/counters; it wouldn't gain us anything, 1245 * and would waste cycles. 1246 */ 1247 if (m != NULL) { 1248 struct mbuf *m_new = NULL; 1249 1250 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1251 if (m_new == NULL) 1252 return(1); 1253 if (m_head->m_pkthdr.len > MHLEN) { 1254 MCLGET(m_new, MB_DONTWAIT); 1255 if ((m_new->m_flags & M_EXT) == 0) { 1256 m_freem(m_new); 1257 return(1); 1258 } 1259 } 1260 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1261 mtod(m_new, caddr_t)); 1262 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1263 m_freem(m_head); 1264 m_head = m_new; 1265 f = &c->wb_ptr->wb_frag[0]; 1266 f->wb_status = 0; 1267 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1268 f->wb_ctl = total_len = m_new->m_len; 1269 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1270 frag = 1; 1271 } 1272 1273 if (total_len < WB_MIN_FRAMELEN) { 1274 f = &c->wb_ptr->wb_frag[frag]; 1275 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1276 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1277 f->wb_ctl |= WB_TXCTL_TLINK; 1278 f->wb_status = WB_TXSTAT_OWN; 1279 frag++; 1280 } 1281 1282 c->wb_mbuf = m_head; 1283 c->wb_lastdesc = frag - 1; 1284 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1285 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1286 1287 return(0); 1288 } 1289 1290 /* 1291 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1292 * to the mbuf data regions directly in the transmit lists. We also save a 1293 * copy of the pointers since the transmit list fragment pointers are 1294 * physical addresses. 1295 */ 1296 static void 1297 wb_start(struct ifnet *ifp) 1298 { 1299 struct wb_softc *sc = ifp->if_softc; 1300 struct mbuf *m_head = NULL; 1301 struct wb_chain *cur_tx = NULL, *start_tx; 1302 1303 /* 1304 * Check for an available queue slot. If there are none, 1305 * punt. 1306 */ 1307 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1308 ifp->if_flags |= IFF_OACTIVE; 1309 return; 1310 } 1311 1312 start_tx = sc->wb_cdata.wb_tx_free; 1313 1314 while (sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1315 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1316 if (m_head == NULL) 1317 break; 1318 1319 /* Pick a descriptor off the free list. */ 1320 cur_tx = sc->wb_cdata.wb_tx_free; 1321 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1322 1323 /* Pack the data into the descriptor. */ 1324 wb_encap(sc, cur_tx, m_head); 1325 1326 if (cur_tx != start_tx) 1327 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1328 1329 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1330 } 1331 1332 /* 1333 * If there are no packets queued, bail. 1334 */ 1335 if (cur_tx == NULL) 1336 return; 1337 1338 /* 1339 * Place the request for the upload interrupt 1340 * in the last descriptor in the chain. This way, if 1341 * we're chaining several packets at once, we'll only 1342 * get an interupt once for the whole chain rather than 1343 * once for each packet. 1344 */ 1345 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1346 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1347 sc->wb_cdata.wb_tx_tail = cur_tx; 1348 1349 if (sc->wb_cdata.wb_tx_head == NULL) { 1350 sc->wb_cdata.wb_tx_head = start_tx; 1351 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1352 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1353 } else { 1354 /* 1355 * We need to distinguish between the case where 1356 * the own bit is clear because the chip cleared it 1357 * and where the own bit is clear because we haven't 1358 * set it yet. The magic value WB_UNSET is just some 1359 * ramdomly chosen number which doesn't have the own 1360 * bit set. When we actually transmit the frame, the 1361 * status word will have _only_ the own bit set, so 1362 * the txeoc handler will be able to tell if it needs 1363 * to initiate another transmission to flush out pending 1364 * frames. 1365 */ 1366 WB_TXOWN(start_tx) = WB_UNSENT; 1367 } 1368 1369 /* 1370 * Set a timeout in case the chip goes out to lunch. 1371 */ 1372 ifp->if_timer = 5; 1373 } 1374 1375 static void 1376 wb_init(void *xsc) 1377 { 1378 struct wb_softc *sc = xsc; 1379 struct ifnet *ifp = &sc->arpcom.ac_if; 1380 int i; 1381 struct mii_data *mii; 1382 1383 crit_enter(); 1384 1385 mii = device_get_softc(sc->wb_miibus); 1386 1387 /* 1388 * Cancel pending I/O and free all RX/TX buffers. 1389 */ 1390 wb_stop(sc); 1391 wb_reset(sc); 1392 1393 sc->wb_txthresh = WB_TXTHRESH_INIT; 1394 1395 /* 1396 * Set cache alignment and burst length. 1397 */ 1398 #ifdef foo 1399 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1400 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1401 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1402 #endif 1403 1404 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE | WB_BUSCTL_ARBITRATION); 1405 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1406 switch(sc->wb_cachesize) { 1407 case 32: 1408 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1409 break; 1410 case 16: 1411 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1412 break; 1413 case 8: 1414 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1415 break; 1416 case 0: 1417 default: 1418 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1419 break; 1420 } 1421 1422 /* This doesn't tend to work too well at 100Mbps. */ 1423 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1424 1425 /* Init our MAC address */ 1426 for (i = 0; i < ETHER_ADDR_LEN; i++) 1427 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1428 1429 /* Init circular RX list. */ 1430 if (wb_list_rx_init(sc) == ENOBUFS) { 1431 if_printf(ifp, "initialization failed: no " 1432 "memory for rx buffers\n"); 1433 wb_stop(sc); 1434 crit_exit(); 1435 return; 1436 } 1437 1438 /* Init TX descriptors. */ 1439 wb_list_tx_init(sc); 1440 1441 /* If we want promiscuous mode, set the allframes bit. */ 1442 if (ifp->if_flags & IFF_PROMISC) 1443 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1444 else 1445 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1446 1447 /* 1448 * Set capture broadcast bit to capture broadcast frames. 1449 */ 1450 if (ifp->if_flags & IFF_BROADCAST) 1451 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1452 else 1453 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1454 1455 /* 1456 * Program the multicast filter, if necessary. 1457 */ 1458 wb_setmulti(sc); 1459 1460 /* 1461 * Load the address of the RX list. 1462 */ 1463 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1464 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1465 1466 /* 1467 * Enable interrupts. 1468 */ 1469 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1470 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1471 1472 /* Enable receiver and transmitter. */ 1473 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1474 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1475 1476 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1477 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1478 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1479 1480 mii_mediachg(mii); 1481 1482 ifp->if_flags |= IFF_RUNNING; 1483 ifp->if_flags &= ~IFF_OACTIVE; 1484 1485 crit_exit(); 1486 1487 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc); 1488 } 1489 1490 /* 1491 * Set media options. 1492 */ 1493 static int 1494 wb_ifmedia_upd(struct ifnet *ifp) 1495 { 1496 struct wb_softc *sc = ifp->if_softc; 1497 1498 if (ifp->if_flags & IFF_UP) 1499 wb_init(sc); 1500 1501 return(0); 1502 } 1503 1504 /* 1505 * Report current media status. 1506 */ 1507 static void 1508 wb_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1509 { 1510 struct wb_softc *sc = ifp->if_softc; 1511 struct mii_data *mii = device_get_softc(sc->wb_miibus); 1512 1513 mii_pollstat(mii); 1514 ifmr->ifm_active = mii->mii_media_active; 1515 ifmr->ifm_status = mii->mii_media_status; 1516 } 1517 1518 static int 1519 wb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1520 { 1521 struct wb_softc *sc = ifp->if_softc; 1522 struct mii_data *mii; 1523 struct ifreq *ifr = (struct ifreq *) data; 1524 int error = 0; 1525 1526 crit_enter(); 1527 1528 switch(command) { 1529 case SIOCSIFFLAGS: 1530 if (ifp->if_flags & IFF_UP) 1531 wb_init(sc); 1532 else if (ifp->if_flags & IFF_RUNNING) 1533 wb_stop(sc); 1534 error = 0; 1535 break; 1536 case SIOCADDMULTI: 1537 case SIOCDELMULTI: 1538 wb_setmulti(sc); 1539 error = 0; 1540 break; 1541 case SIOCGIFMEDIA: 1542 case SIOCSIFMEDIA: 1543 mii = device_get_softc(sc->wb_miibus); 1544 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1545 break; 1546 default: 1547 error = ether_ioctl(ifp, command, data); 1548 break; 1549 } 1550 1551 crit_exit(); 1552 1553 return(error); 1554 } 1555 1556 static void 1557 wb_watchdog(struct ifnet *ifp) 1558 { 1559 struct wb_softc *sc = ifp->if_softc; 1560 1561 ifp->if_oerrors++; 1562 if_printf(ifp, "watchdog timeout\n"); 1563 #ifdef foo 1564 if ((wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) == 0) 1565 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 1566 #endif 1567 wb_stop(sc); 1568 wb_reset(sc); 1569 wb_init(sc); 1570 1571 if (!ifq_is_empty(&ifp->if_snd)) 1572 if_devstart(ifp); 1573 } 1574 1575 /* 1576 * Stop the adapter and free any mbufs allocated to the 1577 * RX and TX lists. 1578 */ 1579 static void 1580 wb_stop(struct wb_softc *sc) 1581 { 1582 struct ifnet *ifp = &sc->arpcom.ac_if; 1583 int i; 1584 1585 ifp->if_timer = 0; 1586 1587 callout_stop(&sc->wb_stat_timer); 1588 1589 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON | WB_NETCFG_TX_ON)); 1590 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1591 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1592 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1593 1594 /* 1595 * Free data in the RX lists. 1596 */ 1597 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1598 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1599 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1600 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1601 } 1602 } 1603 bzero(&sc->wb_ldata->wb_rx_list, sizeof(sc->wb_ldata->wb_rx_list)); 1604 1605 /* 1606 * Free the TX list buffers. 1607 */ 1608 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1609 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1610 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1611 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1612 } 1613 } 1614 1615 bzero(&sc->wb_ldata->wb_tx_list, sizeof(sc->wb_ldata->wb_tx_list)); 1616 1617 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1618 } 1619 1620 /* 1621 * Stop all chip I/O so that the kernel's probe routines don't 1622 * get confused by errant DMAs when rebooting. 1623 */ 1624 static void 1625 wb_shutdown(device_t dev) 1626 { 1627 struct wb_softc *sc = device_get_softc(dev); 1628 struct ifnet *ifp = &sc->arpcom.ac_if; 1629 1630 lwkt_serialize_enter(ifp->if_serializer); 1631 wb_stop(sc); 1632 lwkt_serialize_exit(ifp->if_serializer); 1633 } 1634 1635