1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $ 33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.8 2004/01/24 06:40:34 dillon Exp $ 34 */ 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 78 /* 79 * The 3c90x series chips use a bus-master DMA interface for transfering 80 * packets to and from the controller chip. Some of the "vortex" cards 81 * (3c59x) also supported a bus master mode, however for those chips 82 * you could only DMA packets to/from a contiguous memory buffer. For 83 * transmission this would mean copying the contents of the queued mbuf 84 * chain into an mbuf cluster and then DMAing the cluster. This extra 85 * copy would sort of defeat the purpose of the bus master support for 86 * any packet that doesn't fit into a single mbuf. 87 * 88 * By contrast, the 3c90x cards support a fragment-based bus master 89 * mode where mbuf chains can be encapsulated using TX descriptors. 90 * This is similar to other PCI chips such as the Texas Instruments 91 * ThunderLAN and the Intel 82557/82558. 92 * 93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 94 * bus master chips because they maintain the old PIO interface for 95 * backwards compatibility, but starting with the 3c905B and the 96 * "cyclone" chips, the compatibility interface has been dropped. 97 * Since using bus master DMA is a big win, we use this driver to 98 * support the PCI "boomerang" chips even though they work with the 99 * "vortex" driver in order to obtain better performance. 100 * 101 * This driver is in the /sys/pci directory because it only supports 102 * PCI-based NICs. 103 */ 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/sockio.h> 108 #include <sys/endian.h> 109 #include <sys/mbuf.h> 110 #include <sys/kernel.h> 111 #include <sys/socket.h> 112 113 #include <net/if.h> 114 #include <net/if_arp.h> 115 #include <net/ethernet.h> 116 #include <net/if_dl.h> 117 #include <net/if_media.h> 118 #include <net/vlan/if_vlan_var.h> 119 120 #include <net/bpf.h> 121 122 #include <machine/bus_memio.h> 123 #include <machine/bus_pio.h> 124 #include <machine/bus.h> 125 #include <machine/clock.h> /* for DELAY */ 126 #include <machine/resource.h> 127 #include <sys/bus.h> 128 #include <sys/rman.h> 129 130 #include "../mii_layer/mii.h" 131 #include "../mii_layer/miivar.h" 132 133 #include <bus/pci/pcireg.h> 134 #include <bus/pci/pcivar.h> 135 136 /* "controller miibus0" required. See GENERIC if you get errors here. */ 137 #include "miibus_if.h" 138 139 #include "if_xlreg.h" 140 141 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 142 143 /* 144 * Various supported device vendors/types and their names. 145 */ 146 static struct xl_type xl_devs[] = { 147 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 148 "3Com 3c900-TPO Etherlink XL" }, 149 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 150 "3Com 3c900-COMBO Etherlink XL" }, 151 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 152 "3Com 3c905-TX Fast Etherlink XL" }, 153 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 154 "3Com 3c905-T4 Fast Etherlink XL" }, 155 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 156 "3Com 3c900B-TPO Etherlink XL" }, 157 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 158 "3Com 3c900B-COMBO Etherlink XL" }, 159 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 160 "3Com 3c900B-TPC Etherlink XL" }, 161 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 162 "3Com 3c900B-FL Etherlink XL" }, 163 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 164 "3Com 3c905B-TX Fast Etherlink XL" }, 165 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 166 "3Com 3c905B-T4 Fast Etherlink XL" }, 167 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 168 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 169 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 170 "3Com 3c905B-COMBO Fast Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 172 "3Com 3c905C-TX Fast Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 174 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 176 "3Com 3c980 Fast Etherlink XL" }, 177 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 178 "3Com 3c980C Fast Etherlink XL" }, 179 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 180 "3Com 3cSOHO100-TX OfficeConnect" }, 181 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 182 "3Com 3c450-TX HomeConnect" }, 183 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 184 "3Com 3c555 Fast Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 186 "3Com 3c556 Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 188 "3Com 3c556B Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 190 "3Com 3c575TX Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 192 "3Com 3c575B Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 194 "3Com 3c575C Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 196 "3Com 3c656 Fast Etherlink XL" }, 197 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 198 "3Com 3c656B Fast Etherlink XL" }, 199 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 200 "3Com 3c656C Fast Etherlink XL" }, 201 { 0, 0, NULL } 202 }; 203 204 static int xl_probe (device_t); 205 static int xl_attach (device_t); 206 static int xl_detach (device_t); 207 208 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *); 209 static void xl_stats_update (void *); 210 static int xl_encap (struct xl_softc *, struct xl_chain *, 211 struct mbuf *); 212 static void xl_rxeof (struct xl_softc *); 213 static int xl_rx_resync (struct xl_softc *); 214 static void xl_txeof (struct xl_softc *); 215 static void xl_txeof_90xB (struct xl_softc *); 216 static void xl_txeoc (struct xl_softc *); 217 static void xl_intr (void *); 218 static void xl_start (struct ifnet *); 219 static void xl_start_90xB (struct ifnet *); 220 static int xl_ioctl (struct ifnet *, u_long, caddr_t); 221 static void xl_init (void *); 222 static void xl_stop (struct xl_softc *); 223 static void xl_watchdog (struct ifnet *); 224 static void xl_shutdown (device_t); 225 static int xl_suspend (device_t); 226 static int xl_resume (device_t); 227 228 static int xl_ifmedia_upd (struct ifnet *); 229 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 230 231 static int xl_eeprom_wait (struct xl_softc *); 232 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 233 static void xl_mii_sync (struct xl_softc *); 234 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 235 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 236 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 237 238 static void xl_setcfg (struct xl_softc *); 239 static void xl_setmode (struct xl_softc *, int); 240 static u_int8_t xl_calchash (caddr_t); 241 static void xl_setmulti (struct xl_softc *); 242 static void xl_setmulti_hash (struct xl_softc *); 243 static void xl_reset (struct xl_softc *); 244 static int xl_list_rx_init (struct xl_softc *); 245 static int xl_list_tx_init (struct xl_softc *); 246 static int xl_list_tx_init_90xB (struct xl_softc *); 247 static void xl_wait (struct xl_softc *); 248 static void xl_mediacheck (struct xl_softc *); 249 static void xl_choose_xcvr (struct xl_softc *, int); 250 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int); 251 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 252 int); 253 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 254 int); 255 #ifdef notdef 256 static void xl_testpacket (struct xl_softc *); 257 #endif 258 259 static int xl_miibus_readreg (device_t, int, int); 260 static int xl_miibus_writereg (device_t, int, int, int); 261 static void xl_miibus_statchg (device_t); 262 static void xl_miibus_mediainit (device_t); 263 264 static device_method_t xl_methods[] = { 265 /* Device interface */ 266 DEVMETHOD(device_probe, xl_probe), 267 DEVMETHOD(device_attach, xl_attach), 268 DEVMETHOD(device_detach, xl_detach), 269 DEVMETHOD(device_shutdown, xl_shutdown), 270 DEVMETHOD(device_suspend, xl_suspend), 271 DEVMETHOD(device_resume, xl_resume), 272 273 /* bus interface */ 274 DEVMETHOD(bus_print_child, bus_generic_print_child), 275 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 276 277 /* MII interface */ 278 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 279 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 280 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 281 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 282 283 { 0, 0 } 284 }; 285 286 static driver_t xl_driver = { 287 "xl", 288 xl_methods, 289 sizeof(struct xl_softc) 290 }; 291 292 static devclass_t xl_devclass; 293 294 DECLARE_DUMMY_MODULE(if_xl); 295 MODULE_DEPEND(if_xl, miibus, 1, 1, 1); 296 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 297 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 298 299 static void 300 xl_dma_map_addr(arg, segs, nseg, error) 301 void *arg; 302 bus_dma_segment_t *segs; 303 int nseg, error; 304 { 305 u_int32_t *paddr; 306 307 paddr = arg; 308 *paddr = segs->ds_addr; 309 } 310 311 static void 312 xl_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 313 void *arg; 314 bus_dma_segment_t *segs; 315 int nseg; 316 bus_size_t mapsize; 317 int error; 318 { 319 u_int32_t *paddr; 320 321 if (error) 322 return; 323 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments")); 324 paddr = arg; 325 *paddr = segs->ds_addr; 326 } 327 328 static void 329 xl_dma_map_txbuf(arg, segs, nseg, mapsize, error) 330 void *arg; 331 bus_dma_segment_t *segs; 332 int nseg; 333 bus_size_t mapsize; 334 int error; 335 { 336 struct xl_list *l; 337 int i, total_len; 338 339 if (error) 340 return; 341 342 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); 343 344 total_len = 0; 345 l = arg; 346 for (i = 0; i < nseg; i++) { 347 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 348 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 349 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 350 total_len += segs[i].ds_len; 351 } 352 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len | 353 XL_LAST_FRAG); 354 l->xl_status = htole32(total_len); 355 l->xl_next = 0; 356 } 357 358 /* 359 * Murphy's law says that it's possible the chip can wedge and 360 * the 'command in progress' bit may never clear. Hence, we wait 361 * only a finite amount of time to avoid getting caught in an 362 * infinite loop. Normally this delay routine would be a macro, 363 * but it isn't called during normal operation so we can afford 364 * to make it a function. 365 */ 366 static void 367 xl_wait(sc) 368 struct xl_softc *sc; 369 { 370 int i; 371 372 for (i = 0; i < XL_TIMEOUT; i++) { 373 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 374 break; 375 } 376 377 if (i == XL_TIMEOUT) 378 printf("xl%d: command never completed!\n", sc->xl_unit); 379 380 return; 381 } 382 383 /* 384 * MII access routines are provided for adapters with external 385 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 386 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 387 * Note: if you don't perform the MDIO operations just right, 388 * it's possible to end up with code that works correctly with 389 * some chips/CPUs/processor speeds/bus speeds/etc but not 390 * with others. 391 */ 392 #define MII_SET(x) \ 393 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 394 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 395 396 #define MII_CLR(x) \ 397 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 398 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 399 400 /* 401 * Sync the PHYs by setting data bit and strobing the clock 32 times. 402 */ 403 static void 404 xl_mii_sync(sc) 405 struct xl_softc *sc; 406 { 407 int i; 408 409 XL_SEL_WIN(4); 410 MII_SET(XL_MII_DIR|XL_MII_DATA); 411 412 for (i = 0; i < 32; i++) { 413 MII_SET(XL_MII_CLK); 414 MII_SET(XL_MII_DATA); 415 MII_SET(XL_MII_DATA); 416 MII_CLR(XL_MII_CLK); 417 MII_SET(XL_MII_DATA); 418 MII_SET(XL_MII_DATA); 419 } 420 421 return; 422 } 423 424 /* 425 * Clock a series of bits through the MII. 426 */ 427 static void 428 xl_mii_send(sc, bits, cnt) 429 struct xl_softc *sc; 430 u_int32_t bits; 431 int cnt; 432 { 433 int i; 434 435 XL_SEL_WIN(4); 436 MII_CLR(XL_MII_CLK); 437 438 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 439 if (bits & i) { 440 MII_SET(XL_MII_DATA); 441 } else { 442 MII_CLR(XL_MII_DATA); 443 } 444 MII_CLR(XL_MII_CLK); 445 MII_SET(XL_MII_CLK); 446 } 447 } 448 449 /* 450 * Read an PHY register through the MII. 451 */ 452 static int 453 xl_mii_readreg(sc, frame) 454 struct xl_softc *sc; 455 struct xl_mii_frame *frame; 456 457 { 458 int i, ack, s; 459 460 s = splimp(); 461 462 /* 463 * Set up frame for RX. 464 */ 465 frame->mii_stdelim = XL_MII_STARTDELIM; 466 frame->mii_opcode = XL_MII_READOP; 467 frame->mii_turnaround = 0; 468 frame->mii_data = 0; 469 470 /* 471 * Select register window 4. 472 */ 473 474 XL_SEL_WIN(4); 475 476 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 477 /* 478 * Turn on data xmit. 479 */ 480 MII_SET(XL_MII_DIR); 481 482 xl_mii_sync(sc); 483 484 /* 485 * Send command/address info. 486 */ 487 xl_mii_send(sc, frame->mii_stdelim, 2); 488 xl_mii_send(sc, frame->mii_opcode, 2); 489 xl_mii_send(sc, frame->mii_phyaddr, 5); 490 xl_mii_send(sc, frame->mii_regaddr, 5); 491 492 /* Idle bit */ 493 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 494 MII_SET(XL_MII_CLK); 495 496 /* Turn off xmit. */ 497 MII_CLR(XL_MII_DIR); 498 499 /* Check for ack */ 500 MII_CLR(XL_MII_CLK); 501 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 502 MII_SET(XL_MII_CLK); 503 504 /* 505 * Now try reading data bits. If the ack failed, we still 506 * need to clock through 16 cycles to keep the PHY(s) in sync. 507 */ 508 if (ack) { 509 for(i = 0; i < 16; i++) { 510 MII_CLR(XL_MII_CLK); 511 MII_SET(XL_MII_CLK); 512 } 513 goto fail; 514 } 515 516 for (i = 0x8000; i; i >>= 1) { 517 MII_CLR(XL_MII_CLK); 518 if (!ack) { 519 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 520 frame->mii_data |= i; 521 } 522 MII_SET(XL_MII_CLK); 523 } 524 525 fail: 526 527 MII_CLR(XL_MII_CLK); 528 MII_SET(XL_MII_CLK); 529 530 splx(s); 531 532 if (ack) 533 return(1); 534 return(0); 535 } 536 537 /* 538 * Write to a PHY register through the MII. 539 */ 540 static int 541 xl_mii_writereg(sc, frame) 542 struct xl_softc *sc; 543 struct xl_mii_frame *frame; 544 545 { 546 int s; 547 548 s = splimp(); 549 550 /* 551 * Set up frame for TX. 552 */ 553 554 frame->mii_stdelim = XL_MII_STARTDELIM; 555 frame->mii_opcode = XL_MII_WRITEOP; 556 frame->mii_turnaround = XL_MII_TURNAROUND; 557 558 /* 559 * Select the window 4. 560 */ 561 XL_SEL_WIN(4); 562 563 /* 564 * Turn on data output. 565 */ 566 MII_SET(XL_MII_DIR); 567 568 xl_mii_sync(sc); 569 570 xl_mii_send(sc, frame->mii_stdelim, 2); 571 xl_mii_send(sc, frame->mii_opcode, 2); 572 xl_mii_send(sc, frame->mii_phyaddr, 5); 573 xl_mii_send(sc, frame->mii_regaddr, 5); 574 xl_mii_send(sc, frame->mii_turnaround, 2); 575 xl_mii_send(sc, frame->mii_data, 16); 576 577 /* Idle bit. */ 578 MII_SET(XL_MII_CLK); 579 MII_CLR(XL_MII_CLK); 580 581 /* 582 * Turn off xmit. 583 */ 584 MII_CLR(XL_MII_DIR); 585 586 splx(s); 587 588 return(0); 589 } 590 591 static int 592 xl_miibus_readreg(dev, phy, reg) 593 device_t dev; 594 int phy, reg; 595 { 596 struct xl_softc *sc; 597 struct xl_mii_frame frame; 598 599 sc = device_get_softc(dev); 600 601 /* 602 * Pretend that PHYs are only available at MII address 24. 603 * This is to guard against problems with certain 3Com ASIC 604 * revisions that incorrectly map the internal transceiver 605 * control registers at all MII addresses. This can cause 606 * the miibus code to attach the same PHY several times over. 607 */ 608 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 609 return(0); 610 611 bzero((char *)&frame, sizeof(frame)); 612 613 frame.mii_phyaddr = phy; 614 frame.mii_regaddr = reg; 615 xl_mii_readreg(sc, &frame); 616 617 return(frame.mii_data); 618 } 619 620 static int 621 xl_miibus_writereg(dev, phy, reg, data) 622 device_t dev; 623 int phy, reg, data; 624 { 625 struct xl_softc *sc; 626 struct xl_mii_frame frame; 627 628 sc = device_get_softc(dev); 629 630 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 631 return(0); 632 633 bzero((char *)&frame, sizeof(frame)); 634 635 frame.mii_phyaddr = phy; 636 frame.mii_regaddr = reg; 637 frame.mii_data = data; 638 639 xl_mii_writereg(sc, &frame); 640 641 return(0); 642 } 643 644 static void 645 xl_miibus_statchg(dev) 646 device_t dev; 647 { 648 struct xl_softc *sc; 649 struct mii_data *mii; 650 651 652 sc = device_get_softc(dev); 653 mii = device_get_softc(sc->xl_miibus); 654 655 xl_setcfg(sc); 656 657 /* Set ASIC's duplex mode to match the PHY. */ 658 XL_SEL_WIN(3); 659 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 660 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 661 else 662 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 663 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 664 665 return; 666 } 667 668 /* 669 * Special support for the 3c905B-COMBO. This card has 10/100 support 670 * plus BNC and AUI ports. This means we will have both an miibus attached 671 * plus some non-MII media settings. In order to allow this, we have to 672 * add the extra media to the miibus's ifmedia struct, but we can't do 673 * that during xl_attach() because the miibus hasn't been attached yet. 674 * So instead, we wait until the miibus probe/attach is done, at which 675 * point we will get a callback telling is that it's safe to add our 676 * extra media. 677 */ 678 static void 679 xl_miibus_mediainit(dev) 680 device_t dev; 681 { 682 struct xl_softc *sc; 683 struct mii_data *mii; 684 struct ifmedia *ifm; 685 686 sc = device_get_softc(dev); 687 mii = device_get_softc(sc->xl_miibus); 688 ifm = &mii->mii_media; 689 690 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 691 /* 692 * Check for a 10baseFL board in disguise. 693 */ 694 if (sc->xl_type == XL_TYPE_905B && 695 sc->xl_media == XL_MEDIAOPT_10FL) { 696 if (bootverbose) 697 printf("xl%d: found 10baseFL\n", sc->xl_unit); 698 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 699 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 700 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 701 ifmedia_add(ifm, 702 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 703 } else { 704 if (bootverbose) 705 printf("xl%d: found AUI\n", sc->xl_unit); 706 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 707 } 708 } 709 710 if (sc->xl_media & XL_MEDIAOPT_BNC) { 711 if (bootverbose) 712 printf("xl%d: found BNC\n", sc->xl_unit); 713 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 714 } 715 716 return; 717 } 718 719 /* 720 * The EEPROM is slow: give it time to come ready after issuing 721 * it a command. 722 */ 723 static int 724 xl_eeprom_wait(sc) 725 struct xl_softc *sc; 726 { 727 int i; 728 729 for (i = 0; i < 100; i++) { 730 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 731 DELAY(162); 732 else 733 break; 734 } 735 736 if (i == 100) { 737 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit); 738 return(1); 739 } 740 741 return(0); 742 } 743 744 /* 745 * Read a sequence of words from the EEPROM. Note that ethernet address 746 * data is stored in the EEPROM in network byte order. 747 */ 748 static int 749 xl_read_eeprom(sc, dest, off, cnt, swap) 750 struct xl_softc *sc; 751 caddr_t dest; 752 int off; 753 int cnt; 754 int swap; 755 { 756 int err = 0, i; 757 u_int16_t word = 0, *ptr; 758 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 759 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 760 /* WARNING! DANGER! 761 * It's easy to accidentally overwrite the rom content! 762 * Note: the 3c575 uses 8bit EEPROM offsets. 763 */ 764 XL_SEL_WIN(0); 765 766 if (xl_eeprom_wait(sc)) 767 return(1); 768 769 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 770 off += 0x30; 771 772 for (i = 0; i < cnt; i++) { 773 if (sc->xl_flags & XL_FLAG_8BITROM) 774 CSR_WRITE_2(sc, XL_W0_EE_CMD, 775 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 776 else 777 CSR_WRITE_2(sc, XL_W0_EE_CMD, 778 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 779 err = xl_eeprom_wait(sc); 780 if (err) 781 break; 782 word = CSR_READ_2(sc, XL_W0_EE_DATA); 783 ptr = (u_int16_t *)(dest + (i * 2)); 784 if (swap) 785 *ptr = ntohs(word); 786 else 787 *ptr = word; 788 } 789 790 return(err ? 1 : 0); 791 } 792 793 /* 794 * This routine is taken from the 3Com Etherlink XL manual, 795 * page 10-7. It calculates a CRC of the supplied multicast 796 * group address and returns the lower 8 bits, which are used 797 * as the multicast filter position. 798 * Note: the 3c905B currently only supports a 64-bit hash table, 799 * which means we really only need 6 bits, but the manual indicates 800 * that future chip revisions will have a 256-bit hash table, 801 * hence the routine is set up to calculate 8 bits of position 802 * info in case we need it some day. 803 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a 804 * 256 bit hash table. This means we have to use all 8 bits regardless. 805 * On older cards, the upper 2 bits will be ignored. Grrrr.... 806 */ 807 static u_int8_t xl_calchash(addr) 808 caddr_t addr; 809 { 810 u_int32_t crc, carry; 811 int i, j; 812 u_int8_t c; 813 814 /* Compute CRC for the address value. */ 815 crc = 0xFFFFFFFF; /* initial value */ 816 817 for (i = 0; i < 6; i++) { 818 c = *(addr + i); 819 for (j = 0; j < 8; j++) { 820 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 821 crc <<= 1; 822 c >>= 1; 823 if (carry) 824 crc = (crc ^ 0x04c11db6) | carry; 825 } 826 } 827 828 /* return the filter bit position */ 829 return(crc & 0x000000FF); 830 } 831 832 /* 833 * NICs older than the 3c905B have only one multicast option, which 834 * is to enable reception of all multicast frames. 835 */ 836 static void 837 xl_setmulti(sc) 838 struct xl_softc *sc; 839 { 840 struct ifnet *ifp; 841 struct ifmultiaddr *ifma; 842 u_int8_t rxfilt; 843 int mcnt = 0; 844 845 ifp = &sc->arpcom.ac_if; 846 847 XL_SEL_WIN(5); 848 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 849 850 if (ifp->if_flags & IFF_ALLMULTI) { 851 rxfilt |= XL_RXFILTER_ALLMULTI; 852 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 853 return; 854 } 855 856 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 857 ifma = ifma->ifma_link.le_next) 858 mcnt++; 859 860 if (mcnt) 861 rxfilt |= XL_RXFILTER_ALLMULTI; 862 else 863 rxfilt &= ~XL_RXFILTER_ALLMULTI; 864 865 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 866 867 return; 868 } 869 870 /* 871 * 3c905B adapters have a hash filter that we can program. 872 */ 873 static void 874 xl_setmulti_hash(sc) 875 struct xl_softc *sc; 876 { 877 struct ifnet *ifp; 878 int h = 0, i; 879 struct ifmultiaddr *ifma; 880 u_int8_t rxfilt; 881 int mcnt = 0; 882 883 ifp = &sc->arpcom.ac_if; 884 885 XL_SEL_WIN(5); 886 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 887 888 if (ifp->if_flags & IFF_ALLMULTI) { 889 rxfilt |= XL_RXFILTER_ALLMULTI; 890 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 891 return; 892 } else 893 rxfilt &= ~XL_RXFILTER_ALLMULTI; 894 895 896 /* first, zot all the existing hash bits */ 897 for (i = 0; i < XL_HASHFILT_SIZE; i++) 898 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 899 900 /* now program new ones */ 901 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 902 ifma = ifma->ifma_link.le_next) { 903 if (ifma->ifma_addr->sa_family != AF_LINK) 904 continue; 905 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 906 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 907 mcnt++; 908 } 909 910 if (mcnt) 911 rxfilt |= XL_RXFILTER_MULTIHASH; 912 else 913 rxfilt &= ~XL_RXFILTER_MULTIHASH; 914 915 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 916 917 return; 918 } 919 920 #ifdef notdef 921 static void 922 xl_testpacket(sc) 923 struct xl_softc *sc; 924 { 925 struct mbuf *m; 926 struct ifnet *ifp; 927 928 ifp = &sc->arpcom.ac_if; 929 930 MGETHDR(m, M_DONTWAIT, MT_DATA); 931 932 if (m == NULL) 933 return; 934 935 bcopy(&sc->arpcom.ac_enaddr, 936 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 937 bcopy(&sc->arpcom.ac_enaddr, 938 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 939 mtod(m, struct ether_header *)->ether_type = htons(3); 940 mtod(m, unsigned char *)[14] = 0; 941 mtod(m, unsigned char *)[15] = 0; 942 mtod(m, unsigned char *)[16] = 0xE3; 943 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 944 IF_ENQUEUE(&ifp->if_snd, m); 945 xl_start(ifp); 946 947 return; 948 } 949 #endif 950 951 static void 952 xl_setcfg(sc) 953 struct xl_softc *sc; 954 { 955 u_int32_t icfg; 956 957 XL_SEL_WIN(3); 958 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 959 icfg &= ~XL_ICFG_CONNECTOR_MASK; 960 if (sc->xl_media & XL_MEDIAOPT_MII || 961 sc->xl_media & XL_MEDIAOPT_BT4) 962 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 963 if (sc->xl_media & XL_MEDIAOPT_BTX) 964 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 965 966 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 967 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 968 969 return; 970 } 971 972 static void 973 xl_setmode(sc, media) 974 struct xl_softc *sc; 975 int media; 976 { 977 u_int32_t icfg; 978 u_int16_t mediastat; 979 980 printf("xl%d: selecting ", sc->xl_unit); 981 982 XL_SEL_WIN(4); 983 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 984 XL_SEL_WIN(3); 985 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 986 987 if (sc->xl_media & XL_MEDIAOPT_BT) { 988 if (IFM_SUBTYPE(media) == IFM_10_T) { 989 printf("10baseT transceiver, "); 990 sc->xl_xcvr = XL_XCVR_10BT; 991 icfg &= ~XL_ICFG_CONNECTOR_MASK; 992 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 993 mediastat |= XL_MEDIASTAT_LINKBEAT| 994 XL_MEDIASTAT_JABGUARD; 995 mediastat &= ~XL_MEDIASTAT_SQEENB; 996 } 997 } 998 999 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1000 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1001 printf("100baseFX port, "); 1002 sc->xl_xcvr = XL_XCVR_100BFX; 1003 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1004 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 1005 mediastat |= XL_MEDIASTAT_LINKBEAT; 1006 mediastat &= ~XL_MEDIASTAT_SQEENB; 1007 } 1008 } 1009 1010 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1011 if (IFM_SUBTYPE(media) == IFM_10_5) { 1012 printf("AUI port, "); 1013 sc->xl_xcvr = XL_XCVR_AUI; 1014 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1015 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 1016 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1017 XL_MEDIASTAT_JABGUARD); 1018 mediastat |= ~XL_MEDIASTAT_SQEENB; 1019 } 1020 if (IFM_SUBTYPE(media) == IFM_10_FL) { 1021 printf("10baseFL transceiver, "); 1022 sc->xl_xcvr = XL_XCVR_AUI; 1023 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1024 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 1025 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1026 XL_MEDIASTAT_JABGUARD); 1027 mediastat |= ~XL_MEDIASTAT_SQEENB; 1028 } 1029 } 1030 1031 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1032 if (IFM_SUBTYPE(media) == IFM_10_2) { 1033 printf("BNC port, "); 1034 sc->xl_xcvr = XL_XCVR_COAX; 1035 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1036 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 1037 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1038 XL_MEDIASTAT_JABGUARD| 1039 XL_MEDIASTAT_SQEENB); 1040 } 1041 } 1042 1043 if ((media & IFM_GMASK) == IFM_FDX || 1044 IFM_SUBTYPE(media) == IFM_100_FX) { 1045 printf("full duplex\n"); 1046 XL_SEL_WIN(3); 1047 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 1048 } else { 1049 printf("half duplex\n"); 1050 XL_SEL_WIN(3); 1051 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 1052 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 1053 } 1054 1055 if (IFM_SUBTYPE(media) == IFM_10_2) 1056 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 1057 else 1058 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 1059 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 1060 XL_SEL_WIN(4); 1061 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 1062 DELAY(800); 1063 XL_SEL_WIN(7); 1064 1065 return; 1066 } 1067 1068 static void 1069 xl_reset(sc) 1070 struct xl_softc *sc; 1071 { 1072 int i; 1073 1074 XL_SEL_WIN(0); 1075 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 1076 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1077 XL_RESETOPT_DISADVFD:0)); 1078 1079 /* 1080 * If we're using memory mapped register mode, pause briefly 1081 * after issuing the reset command before trying to access any 1082 * other registers. With my 3c575C cardbus card, failing to do 1083 * this results in the system locking up while trying to poll 1084 * the command busy bit in the status register. 1085 */ 1086 if (sc->xl_flags & XL_FLAG_USE_MMIO) 1087 DELAY(100000); 1088 1089 for (i = 0; i < XL_TIMEOUT; i++) { 1090 DELAY(10); 1091 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1092 break; 1093 } 1094 1095 if (i == XL_TIMEOUT) 1096 printf("xl%d: reset didn't complete\n", sc->xl_unit); 1097 1098 /* Reset TX and RX. */ 1099 /* Note: the RX reset takes an absurd amount of time 1100 * on newer versions of the Tornado chips such as those 1101 * on the 3c905CX and newer 3c908C cards. We wait an 1102 * extra amount of time so that xl_wait() doesn't complain 1103 * and annoy the users. 1104 */ 1105 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1106 DELAY(100000); 1107 xl_wait(sc); 1108 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1109 xl_wait(sc); 1110 1111 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1112 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1113 XL_SEL_WIN(2); 1114 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1115 XL_W2_RESET_OPTIONS) 1116 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1117 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1118 ); 1119 } 1120 1121 /* Wait a little while for the chip to get its brains in order. */ 1122 DELAY(100000); 1123 return; 1124 } 1125 1126 /* 1127 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1128 * IDs against our list and return a device name if we find a match. 1129 */ 1130 static int 1131 xl_probe(dev) 1132 device_t dev; 1133 { 1134 struct xl_type *t; 1135 1136 t = xl_devs; 1137 1138 while(t->xl_name != NULL) { 1139 if ((pci_get_vendor(dev) == t->xl_vid) && 1140 (pci_get_device(dev) == t->xl_did)) { 1141 device_set_desc(dev, t->xl_name); 1142 return(0); 1143 } 1144 t++; 1145 } 1146 1147 return(ENXIO); 1148 } 1149 1150 /* 1151 * This routine is a kludge to work around possible hardware faults 1152 * or manufacturing defects that can cause the media options register 1153 * (or reset options register, as it's called for the first generation 1154 * 3c90x adapters) to return an incorrect result. I have encountered 1155 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1156 * which doesn't have any of the 'mediaopt' bits set. This screws up 1157 * the attach routine pretty badly because it doesn't know what media 1158 * to look for. If we find ourselves in this predicament, this routine 1159 * will try to guess the media options values and warn the user of a 1160 * possible manufacturing defect with his adapter/system/whatever. 1161 */ 1162 static void 1163 xl_mediacheck(sc) 1164 struct xl_softc *sc; 1165 { 1166 1167 /* 1168 * If some of the media options bits are set, assume they are 1169 * correct. If not, try to figure it out down below. 1170 * XXX I should check for 10baseFL, but I don't have an adapter 1171 * to test with. 1172 */ 1173 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1174 /* 1175 * Check the XCVR value. If it's not in the normal range 1176 * of values, we need to fake it up here. 1177 */ 1178 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1179 return; 1180 else { 1181 printf("xl%d: bogus xcvr value " 1182 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr); 1183 printf("xl%d: choosing new default based " 1184 "on card type\n", sc->xl_unit); 1185 } 1186 } else { 1187 if (sc->xl_type == XL_TYPE_905B && 1188 sc->xl_media & XL_MEDIAOPT_10FL) 1189 return; 1190 printf("xl%d: WARNING: no media options bits set in " 1191 "the media options register!!\n", sc->xl_unit); 1192 printf("xl%d: this could be a manufacturing defect in " 1193 "your adapter or system\n", sc->xl_unit); 1194 printf("xl%d: attempting to guess media type; you " 1195 "should probably consult your vendor\n", sc->xl_unit); 1196 } 1197 1198 xl_choose_xcvr(sc, 1); 1199 1200 return; 1201 } 1202 1203 static void 1204 xl_choose_xcvr(sc, verbose) 1205 struct xl_softc *sc; 1206 int verbose; 1207 { 1208 u_int16_t devid; 1209 1210 /* 1211 * Read the device ID from the EEPROM. 1212 * This is what's loaded into the PCI device ID register, so it has 1213 * to be correct otherwise we wouldn't have gotten this far. 1214 */ 1215 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1216 1217 switch(devid) { 1218 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1219 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1220 sc->xl_media = XL_MEDIAOPT_BT; 1221 sc->xl_xcvr = XL_XCVR_10BT; 1222 if (verbose) 1223 printf("xl%d: guessing 10BaseT " 1224 "transceiver\n", sc->xl_unit); 1225 break; 1226 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1227 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1228 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1229 sc->xl_xcvr = XL_XCVR_10BT; 1230 if (verbose) 1231 printf("xl%d: guessing COMBO " 1232 "(AUI/BNC/TP)\n", sc->xl_unit); 1233 break; 1234 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1235 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1236 sc->xl_xcvr = XL_XCVR_10BT; 1237 if (verbose) 1238 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit); 1239 break; 1240 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1241 sc->xl_media = XL_MEDIAOPT_10FL; 1242 sc->xl_xcvr = XL_XCVR_AUI; 1243 if (verbose) 1244 printf("xl%d: guessing 10baseFL\n", sc->xl_unit); 1245 break; 1246 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1247 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1248 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1249 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1250 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1251 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1252 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1253 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1254 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1255 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1256 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1257 sc->xl_media = XL_MEDIAOPT_MII; 1258 sc->xl_xcvr = XL_XCVR_MII; 1259 if (verbose) 1260 printf("xl%d: guessing MII\n", sc->xl_unit); 1261 break; 1262 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1263 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1264 sc->xl_media = XL_MEDIAOPT_BT4; 1265 sc->xl_xcvr = XL_XCVR_MII; 1266 if (verbose) 1267 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit); 1268 break; 1269 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1270 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1271 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1272 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1273 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1274 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1275 sc->xl_media = XL_MEDIAOPT_BTX; 1276 sc->xl_xcvr = XL_XCVR_AUTO; 1277 if (verbose) 1278 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit); 1279 break; 1280 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1281 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1282 sc->xl_xcvr = XL_XCVR_AUTO; 1283 if (verbose) 1284 printf("xl%d: guessing 10/100 " 1285 "plus BNC/AUI\n", sc->xl_unit); 1286 break; 1287 default: 1288 printf("xl%d: unknown device ID: %x -- " 1289 "defaulting to 10baseT\n", sc->xl_unit, devid); 1290 sc->xl_media = XL_MEDIAOPT_BT; 1291 break; 1292 } 1293 1294 return; 1295 } 1296 1297 /* 1298 * Attach the interface. Allocate softc structures, do ifmedia 1299 * setup and ethernet/BPF attach. 1300 */ 1301 static int 1302 xl_attach(dev) 1303 device_t dev; 1304 { 1305 int s; 1306 u_char eaddr[ETHER_ADDR_LEN]; 1307 u_int16_t xcvr[2]; 1308 u_int32_t command; 1309 struct xl_softc *sc; 1310 struct ifnet *ifp; 1311 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1312 int unit, error = 0, rid, res; 1313 1314 s = splimp(); 1315 1316 sc = device_get_softc(dev); 1317 unit = device_get_unit(dev); 1318 1319 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1320 1321 sc->xl_flags = 0; 1322 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555) 1323 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1324 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 || 1325 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1326 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1327 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1328 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1329 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 || 1330 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556) 1331 sc->xl_flags |= XL_FLAG_8BITROM; 1332 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1333 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1334 1335 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A || 1336 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B || 1337 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C || 1338 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B || 1339 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1340 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1341 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM; 1342 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656) 1343 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1344 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B) 1345 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1346 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C) 1347 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1348 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1349 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1350 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 || 1351 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B) 1352 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1353 XL_FLAG_INVERT_LED_PWR; 1354 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B) 1355 sc->xl_flags |= XL_FLAG_PHYOK; 1356 #ifndef BURN_BRIDGES 1357 /* 1358 * If this is a 3c905B, we have to check one extra thing. 1359 * The 905B supports power management and may be placed in 1360 * a low-power mode (D3 mode), typically by certain operating 1361 * systems which shall not be named. The PCI BIOS is supposed 1362 * to reset the NIC and bring it out of low-power mode, but 1363 * some do not. Consequently, we have to see if this chip 1364 * supports power management, and if so, make sure it's not 1365 * in low-power mode. If power management is available, the 1366 * capid byte will be 0x01. 1367 * 1368 * I _think_ that what actually happens is that the chip 1369 * loses its PCI configuration during the transition from 1370 * D3 back to D0; this means that it should be possible for 1371 * us to save the PCI iobase, membase and IRQ, put the chip 1372 * back in the D0 state, then restore the PCI config ourselves. 1373 */ 1374 1375 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1376 u_int32_t iobase, membase, irq; 1377 1378 /* Save important PCI config data. */ 1379 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1380 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1381 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1382 1383 /* Reset the power state. */ 1384 printf("xl%d: chip is in D%d power mode " 1385 "-- setting to D0\n", unit, 1386 pci_get_powerstate(dev)); 1387 1388 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1389 1390 /* Restore PCI config data. */ 1391 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1392 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1393 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1394 } 1395 #endif 1396 /* 1397 * Map control/status registers. 1398 */ 1399 pci_enable_busmaster(dev); 1400 pci_enable_io(dev, SYS_RES_IOPORT); 1401 pci_enable_io(dev, SYS_RES_MEMORY); 1402 command = pci_read_config(dev, PCIR_COMMAND, 4); 1403 1404 if (!(command & PCIM_CMD_PORTEN) && !(command & PCIM_CMD_MEMEN)) { 1405 printf("xl%d: failed to enable I/O ports and memory mappings!\n", unit); 1406 error = ENXIO; 1407 goto fail; 1408 } 1409 1410 rid = XL_PCI_LOMEM; 1411 res = SYS_RES_MEMORY; 1412 1413 #if 0 1414 sc->xl_res = bus_alloc_resource(dev, res, &rid, 1415 0, ~0, 1, RF_ACTIVE); 1416 #endif 1417 1418 if (sc->xl_res != NULL) { 1419 sc->xl_flags |= XL_FLAG_USE_MMIO; 1420 if (bootverbose) 1421 printf("xl%d: using memory mapped I/O\n", unit); 1422 } else { 1423 rid = XL_PCI_LOIO; 1424 res = SYS_RES_IOPORT; 1425 sc->xl_res = bus_alloc_resource(dev, res, &rid, 1426 0, ~0, 1, RF_ACTIVE); 1427 if (sc->xl_res == NULL) { 1428 printf ("xl%d: couldn't map ports/memory\n", unit); 1429 error = ENXIO; 1430 goto fail; 1431 } 1432 if (bootverbose) 1433 printf("xl%d: using port I/O\n", unit); 1434 } 1435 1436 sc->xl_btag = rman_get_bustag(sc->xl_res); 1437 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1438 1439 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1440 rid = XL_PCI_FUNCMEM; 1441 sc->xl_fres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1442 0, ~0, 1, RF_ACTIVE); 1443 1444 if (sc->xl_fres == NULL) { 1445 printf ("xl%d: couldn't map ports/memory\n", unit); 1446 error = ENXIO; 1447 goto fail; 1448 } 1449 1450 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1451 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1452 } 1453 1454 /* Allocate interrupt */ 1455 rid = 0; 1456 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1457 RF_SHAREABLE | RF_ACTIVE); 1458 if (sc->xl_irq == NULL) { 1459 printf("xl%d: couldn't map interrupt\n", unit); 1460 error = ENXIO; 1461 goto fail; 1462 } 1463 1464 /* Reset the adapter. */ 1465 xl_reset(sc); 1466 1467 /* 1468 * Get station address from the EEPROM. 1469 */ 1470 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1471 printf("xl%d: failed to read station address\n", sc->xl_unit); 1472 error = ENXIO; 1473 goto fail; 1474 } 1475 1476 /* 1477 * A 3Com chip was detected. Inform the world. 1478 */ 1479 printf("xl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1480 1481 sc->xl_unit = unit; 1482 callout_handle_init(&sc->xl_stat_ch); 1483 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1484 1485 /* 1486 * Now allocate a tag for the DMA descriptor lists and a chunk 1487 * of DMA-able memory based on the tag. Also obtain the DMA 1488 * addresses of the RX and TX ring, which we'll need later. 1489 * All of our lists are allocated as a contiguous block 1490 * of memory. 1491 */ 1492 error = bus_dma_tag_create(NULL, 8, 0, 1493 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1494 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, 1495 &sc->xl_ldata.xl_rx_tag); 1496 if (error) { 1497 printf("xl%d: failed to allocate rx dma tag\n", unit); 1498 goto fail; 1499 } 1500 1501 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1502 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT, 1503 &sc->xl_ldata.xl_rx_dmamap); 1504 if (error) { 1505 printf("xl%d: no memory for rx list buffers!\n", unit); 1506 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1507 sc->xl_ldata.xl_rx_tag = NULL; 1508 goto fail; 1509 } 1510 1511 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1512 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1513 XL_RX_LIST_SZ, xl_dma_map_addr, 1514 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1515 if (error) { 1516 printf("xl%d: cannot get dma address of the rx ring!\n", unit); 1517 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1518 sc->xl_ldata.xl_rx_dmamap); 1519 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1520 sc->xl_ldata.xl_rx_tag = NULL; 1521 goto fail; 1522 } 1523 1524 error = bus_dma_tag_create(NULL, 8, 0, 1525 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1526 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, 1527 &sc->xl_ldata.xl_tx_tag); 1528 if (error) { 1529 printf("xl%d: failed to allocate tx dma tag\n", unit); 1530 goto fail; 1531 } 1532 1533 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1534 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT, 1535 &sc->xl_ldata.xl_tx_dmamap); 1536 if (error) { 1537 printf("xl%d: no memory for list buffers!\n", unit); 1538 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1539 sc->xl_ldata.xl_tx_tag = NULL; 1540 goto fail; 1541 } 1542 1543 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1544 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1545 XL_TX_LIST_SZ, xl_dma_map_addr, 1546 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1547 if (error) { 1548 printf("xl%d: cannot get dma address of the tx ring!\n", unit); 1549 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1550 sc->xl_ldata.xl_tx_dmamap); 1551 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1552 sc->xl_ldata.xl_tx_tag = NULL; 1553 goto fail; 1554 } 1555 1556 /* 1557 * Allocate a DMA tag for the mapping of mbufs. 1558 */ 1559 error = bus_dma_tag_create(NULL, 1, 0, 1560 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1561 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, 1562 &sc->xl_mtag); 1563 if (error) { 1564 printf("xl%d: failed to allocate mbuf dma tag\n", unit); 1565 goto fail; 1566 } 1567 1568 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 1569 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 1570 1571 /* We need a spare DMA map for the RX ring. */ 1572 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1573 if (error) 1574 goto fail; 1575 1576 /* 1577 * Figure out the card type. 3c905B adapters have the 1578 * 'supportsNoTxLength' bit set in the capabilities 1579 * word in the EEPROM. 1580 * Note: my 3c575C cardbus card lies. It returns a value 1581 * of 0x1578 for its capabilities word, which is somewhat 1582 * nonsensical. Another way to distinguish a 3c90x chip 1583 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1584 * bit. This will only be set for 3c90x boomerage chips. 1585 */ 1586 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1587 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1588 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1589 sc->xl_type = XL_TYPE_905B; 1590 else 1591 sc->xl_type = XL_TYPE_90X; 1592 1593 ifp = &sc->arpcom.ac_if; 1594 ifp->if_softc = sc; 1595 if_initname(ifp, "xl", unit); 1596 ifp->if_mtu = ETHERMTU; 1597 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1598 ifp->if_ioctl = xl_ioctl; 1599 ifp->if_output = ether_output; 1600 ifp->if_capabilities = 0; 1601 if (sc->xl_type == XL_TYPE_905B) { 1602 ifp->if_start = xl_start_90xB; 1603 ifp->if_capabilities |= IFCAP_HWCSUM; 1604 } else { 1605 ifp->if_start = xl_start; 1606 } 1607 ifp->if_watchdog = xl_watchdog; 1608 ifp->if_init = xl_init; 1609 ifp->if_baudrate = 10000000; 1610 ifp->if_snd.ifq_maxlen = XL_TX_LIST_CNT - 1; 1611 /* 1612 * NOTE: features disabled by default. This seems to corrupt 1613 * tx packet data one out of a million packets or so and then 1614 * generates a good checksum so the receiver doesn't 1615 * know the packet is bad 1616 */ 1617 ifp->if_capenable = 0; /*ifp->if_capabilities;*/ 1618 if (ifp->if_capenable & IFCAP_TXCSUM) 1619 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1620 1621 /* 1622 * Now we have to see what sort of media we have. 1623 * This includes probing for an MII interace and a 1624 * possible PHY. 1625 */ 1626 XL_SEL_WIN(3); 1627 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1628 if (bootverbose) 1629 printf("xl%d: media options word: %x\n", sc->xl_unit, 1630 sc->xl_media); 1631 1632 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1633 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1634 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1635 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1636 1637 xl_mediacheck(sc); 1638 1639 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1640 || sc->xl_media & XL_MEDIAOPT_BT4) { 1641 if (bootverbose) 1642 printf("xl%d: found MII/AUTO\n", sc->xl_unit); 1643 xl_setcfg(sc); 1644 if (mii_phy_probe(dev, &sc->xl_miibus, 1645 xl_ifmedia_upd, xl_ifmedia_sts)) { 1646 printf("xl%d: no PHY found!\n", sc->xl_unit); 1647 error = ENXIO; 1648 goto fail; 1649 } 1650 1651 goto done; 1652 } 1653 1654 /* 1655 * Sanity check. If the user has selected "auto" and this isn't 1656 * a 10/100 card of some kind, we need to force the transceiver 1657 * type to something sane. 1658 */ 1659 if (sc->xl_xcvr == XL_XCVR_AUTO) 1660 xl_choose_xcvr(sc, bootverbose); 1661 1662 /* 1663 * Do ifmedia setup. 1664 */ 1665 if (sc->xl_media & XL_MEDIAOPT_BT) { 1666 if (bootverbose) 1667 printf("xl%d: found 10baseT\n", sc->xl_unit); 1668 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1669 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1670 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1671 ifmedia_add(&sc->ifmedia, 1672 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1673 } 1674 1675 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1676 /* 1677 * Check for a 10baseFL board in disguise. 1678 */ 1679 if (sc->xl_type == XL_TYPE_905B && 1680 sc->xl_media == XL_MEDIAOPT_10FL) { 1681 if (bootverbose) 1682 printf("xl%d: found 10baseFL\n", sc->xl_unit); 1683 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1684 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1685 0, NULL); 1686 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1687 ifmedia_add(&sc->ifmedia, 1688 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1689 } else { 1690 if (bootverbose) 1691 printf("xl%d: found AUI\n", sc->xl_unit); 1692 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1693 } 1694 } 1695 1696 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1697 if (bootverbose) 1698 printf("xl%d: found BNC\n", sc->xl_unit); 1699 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1700 } 1701 1702 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1703 if (bootverbose) 1704 printf("xl%d: found 100baseFX\n", sc->xl_unit); 1705 ifp->if_baudrate = 100000000; 1706 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1707 } 1708 1709 /* Choose a default media. */ 1710 switch(sc->xl_xcvr) { 1711 case XL_XCVR_10BT: 1712 media = IFM_ETHER|IFM_10_T; 1713 xl_setmode(sc, media); 1714 break; 1715 case XL_XCVR_AUI: 1716 if (sc->xl_type == XL_TYPE_905B && 1717 sc->xl_media == XL_MEDIAOPT_10FL) { 1718 media = IFM_ETHER|IFM_10_FL; 1719 xl_setmode(sc, media); 1720 } else { 1721 media = IFM_ETHER|IFM_10_5; 1722 xl_setmode(sc, media); 1723 } 1724 break; 1725 case XL_XCVR_COAX: 1726 media = IFM_ETHER|IFM_10_2; 1727 xl_setmode(sc, media); 1728 break; 1729 case XL_XCVR_AUTO: 1730 case XL_XCVR_100BTX: 1731 case XL_XCVR_MII: 1732 /* Chosen by miibus */ 1733 break; 1734 case XL_XCVR_100BFX: 1735 media = IFM_ETHER|IFM_100_FX; 1736 break; 1737 default: 1738 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, 1739 sc->xl_xcvr); 1740 /* 1741 * This will probably be wrong, but it prevents 1742 * the ifmedia code from panicking. 1743 */ 1744 media = IFM_ETHER|IFM_10_T; 1745 break; 1746 } 1747 1748 if (sc->xl_miibus == NULL) 1749 ifmedia_set(&sc->ifmedia, media); 1750 1751 done: 1752 1753 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1754 XL_SEL_WIN(0); 1755 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1756 } 1757 1758 /* 1759 * Call MI attach routine. 1760 */ 1761 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1762 1763 /* 1764 * Tell the upper layer(s) we support long frames. 1765 */ 1766 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1767 1768 /* Hook interrupt last to avoid having to lock softc */ 1769 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET, 1770 xl_intr, sc, &sc->xl_intrhand); 1771 if (error) { 1772 printf("xl%d: couldn't set up irq\n", unit); 1773 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1774 goto fail; 1775 } 1776 1777 fail: 1778 if (error) 1779 xl_detach(dev); 1780 1781 splx(s); 1782 1783 return(error); 1784 } 1785 1786 /* 1787 * Shutdown hardware and free up resources. This can be called any 1788 * time after the mutex has been initialized. It is called in both 1789 * the error case in attach and the normal detach case so it needs 1790 * to be careful about only freeing resources that have actually been 1791 * allocated. 1792 */ 1793 static int 1794 xl_detach(dev) 1795 device_t dev; 1796 { 1797 struct xl_softc *sc; 1798 struct ifnet *ifp; 1799 int rid, res; 1800 int s; 1801 1802 s = splimp(); 1803 1804 sc = device_get_softc(dev); 1805 ifp = &sc->arpcom.ac_if; 1806 1807 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1808 rid = XL_PCI_LOMEM; 1809 res = SYS_RES_MEMORY; 1810 } else { 1811 rid = XL_PCI_LOIO; 1812 res = SYS_RES_IOPORT; 1813 } 1814 1815 xl_reset(sc); 1816 xl_stop(sc); 1817 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1818 1819 if (sc->xl_miibus) 1820 device_delete_child(dev, sc->xl_miibus); 1821 bus_generic_detach(dev); 1822 ifmedia_removeall(&sc->ifmedia); 1823 1824 if (sc->xl_intrhand) 1825 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1826 if (sc->xl_irq) 1827 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1828 if (sc->xl_fres != NULL) 1829 bus_release_resource(dev, SYS_RES_MEMORY, 1830 XL_PCI_FUNCMEM, sc->xl_fres); 1831 if (sc->xl_res) 1832 bus_release_resource(dev, res, rid, sc->xl_res); 1833 1834 if (sc->xl_mtag) { 1835 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1836 bus_dma_tag_destroy(sc->xl_mtag); 1837 } 1838 if (sc->xl_ldata.xl_rx_tag) { 1839 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1840 sc->xl_ldata.xl_rx_dmamap); 1841 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1842 sc->xl_ldata.xl_rx_dmamap); 1843 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1844 } 1845 if (sc->xl_ldata.xl_tx_tag) { 1846 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1847 sc->xl_ldata.xl_tx_dmamap); 1848 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1849 sc->xl_ldata.xl_tx_dmamap); 1850 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1851 } 1852 1853 splx(s); 1854 1855 return(0); 1856 } 1857 1858 /* 1859 * Initialize the transmit descriptors. 1860 */ 1861 static int 1862 xl_list_tx_init(sc) 1863 struct xl_softc *sc; 1864 { 1865 struct xl_chain_data *cd; 1866 struct xl_list_data *ld; 1867 int error, i; 1868 1869 cd = &sc->xl_cdata; 1870 ld = &sc->xl_ldata; 1871 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1872 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1873 error = bus_dmamap_create(sc->xl_mtag, 0, 1874 &cd->xl_tx_chain[i].xl_map); 1875 if (error) 1876 return(error); 1877 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1878 i * sizeof(struct xl_list); 1879 if (i == (XL_TX_LIST_CNT - 1)) 1880 cd->xl_tx_chain[i].xl_next = NULL; 1881 else 1882 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1883 } 1884 1885 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1886 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1887 1888 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1889 return(0); 1890 } 1891 1892 /* 1893 * Initialize the transmit descriptors. 1894 */ 1895 static int 1896 xl_list_tx_init_90xB(sc) 1897 struct xl_softc *sc; 1898 { 1899 struct xl_chain_data *cd; 1900 struct xl_list_data *ld; 1901 int error, i; 1902 1903 cd = &sc->xl_cdata; 1904 ld = &sc->xl_ldata; 1905 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1906 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1907 error = bus_dmamap_create(sc->xl_mtag, 0, 1908 &cd->xl_tx_chain[i].xl_map); 1909 if (error) 1910 return(error); 1911 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1912 i * sizeof(struct xl_list); 1913 if (i == (XL_TX_LIST_CNT - 1)) 1914 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1915 else 1916 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1917 if (i == 0) 1918 cd->xl_tx_chain[i].xl_prev = 1919 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1920 else 1921 cd->xl_tx_chain[i].xl_prev = 1922 &cd->xl_tx_chain[i - 1]; 1923 } 1924 1925 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1926 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1927 1928 cd->xl_tx_prod = 1; 1929 cd->xl_tx_cons = 1; 1930 cd->xl_tx_cnt = 0; 1931 1932 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1933 return(0); 1934 } 1935 1936 /* 1937 * Initialize the RX descriptors and allocate mbufs for them. Note that 1938 * we arrange the descriptors in a closed ring, so that the last descriptor 1939 * points back to the first. 1940 */ 1941 static int 1942 xl_list_rx_init(sc) 1943 struct xl_softc *sc; 1944 { 1945 struct xl_chain_data *cd; 1946 struct xl_list_data *ld; 1947 int error, i, next; 1948 u_int32_t nextptr; 1949 1950 cd = &sc->xl_cdata; 1951 ld = &sc->xl_ldata; 1952 1953 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1954 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1955 error = bus_dmamap_create(sc->xl_mtag, 0, 1956 &cd->xl_rx_chain[i].xl_map); 1957 if (error) 1958 return(error); 1959 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1960 if (error) 1961 return(error); 1962 if (i == (XL_RX_LIST_CNT - 1)) 1963 next = 0; 1964 else 1965 next = i + 1; 1966 nextptr = ld->xl_rx_dmaaddr + 1967 next * sizeof(struct xl_list_onefrag); 1968 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1969 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1970 } 1971 1972 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1973 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1974 1975 return(0); 1976 } 1977 1978 /* 1979 * Initialize an RX descriptor and attach an MBUF cluster. 1980 * If we fail to do so, we need to leave the old mbuf and 1981 * the old DMA map untouched so that it can be reused. 1982 */ 1983 static int 1984 xl_newbuf(sc, c) 1985 struct xl_softc *sc; 1986 struct xl_chain_onefrag *c; 1987 { 1988 struct mbuf *m_new = NULL; 1989 bus_dmamap_t map; 1990 int error; 1991 u_int32_t baddr; 1992 1993 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1994 if (m_new == NULL) 1995 return(ENOBUFS); 1996 1997 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1998 1999 /* Force longword alignment for packet payload. */ 2000 m_adj(m_new, ETHER_ALIGN); 2001 2002 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new, 2003 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT); 2004 if (error) { 2005 m_freem(m_new); 2006 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error); 2007 return(error); 2008 } 2009 2010 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 2011 map = c->xl_map; 2012 c->xl_map = sc->xl_tmpmap; 2013 sc->xl_tmpmap = map; 2014 c->xl_mbuf = m_new; 2015 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 2016 c->xl_ptr->xl_status = 0; 2017 c->xl_ptr->xl_frag.xl_addr = htole32(baddr); 2018 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 2019 return(0); 2020 } 2021 2022 static int 2023 xl_rx_resync(sc) 2024 struct xl_softc *sc; 2025 { 2026 struct xl_chain_onefrag *pos; 2027 int i; 2028 2029 pos = sc->xl_cdata.xl_rx_head; 2030 2031 for (i = 0; i < XL_RX_LIST_CNT; i++) { 2032 if (pos->xl_ptr->xl_status) 2033 break; 2034 pos = pos->xl_next; 2035 } 2036 2037 if (i == XL_RX_LIST_CNT) 2038 return(0); 2039 2040 sc->xl_cdata.xl_rx_head = pos; 2041 2042 return(EAGAIN); 2043 } 2044 2045 /* 2046 * A frame has been uploaded: pass the resulting mbuf chain up to 2047 * the higher level protocols. 2048 */ 2049 static void 2050 xl_rxeof(sc) 2051 struct xl_softc *sc; 2052 { 2053 struct ether_header *eh; 2054 struct mbuf *m; 2055 struct ifnet *ifp; 2056 struct xl_chain_onefrag *cur_rx; 2057 int total_len = 0; 2058 u_int32_t rxstat; 2059 2060 ifp = &sc->arpcom.ac_if; 2061 2062 again: 2063 2064 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 2065 BUS_DMASYNC_POSTREAD); 2066 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 2067 cur_rx = sc->xl_cdata.xl_rx_head; 2068 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 2069 total_len = rxstat & XL_RXSTAT_LENMASK; 2070 2071 /* 2072 * Since we have told the chip to allow large frames, 2073 * we need to trap giant frame errors in software. We allow 2074 * a little more than the normal frame size to account for 2075 * frames with VLAN tags. 2076 */ 2077 if (total_len > XL_MAX_FRAMELEN) 2078 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 2079 2080 /* 2081 * If an error occurs, update stats, clear the 2082 * status word and leave the mbuf cluster in place: 2083 * it should simply get re-used next time this descriptor 2084 * comes up in the ring. 2085 */ 2086 if (rxstat & XL_RXSTAT_UP_ERROR) { 2087 ifp->if_ierrors++; 2088 cur_rx->xl_ptr->xl_status = 0; 2089 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2090 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2091 continue; 2092 } 2093 2094 /* 2095 * If the error bit was not set, the upload complete 2096 * bit should be set which means we have a valid packet. 2097 * If not, something truly strange has happened. 2098 */ 2099 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2100 printf("xl%d: bad receive status -- " 2101 "packet dropped\n", sc->xl_unit); 2102 ifp->if_ierrors++; 2103 cur_rx->xl_ptr->xl_status = 0; 2104 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2105 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2106 continue; 2107 } 2108 2109 /* No errors; receive the packet. */ 2110 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2111 BUS_DMASYNC_POSTREAD); 2112 m = cur_rx->xl_mbuf; 2113 2114 /* 2115 * Try to conjure up a new mbuf cluster. If that 2116 * fails, it means we have an out of memory condition and 2117 * should leave the buffer in place and continue. This will 2118 * result in a lost packet, but there's little else we 2119 * can do in this situation. 2120 */ 2121 if (xl_newbuf(sc, cur_rx)) { 2122 ifp->if_ierrors++; 2123 cur_rx->xl_ptr->xl_status = 0; 2124 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2125 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2126 continue; 2127 } 2128 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2129 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2130 2131 ifp->if_ipackets++; 2132 eh = mtod(m, struct ether_header *); 2133 m->m_pkthdr.rcvif = ifp; 2134 m->m_pkthdr.len = m->m_len = total_len; 2135 2136 /* Remove header from mbuf and pass it on. */ 2137 m_adj(m, sizeof(struct ether_header)); 2138 2139 if (ifp->if_capenable & IFCAP_RXCSUM) { 2140 /* Do IP checksum checking. */ 2141 if (rxstat & XL_RXSTAT_IPCKOK) 2142 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2143 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2144 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2145 if ((rxstat & XL_RXSTAT_TCPCOK && 2146 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2147 (rxstat & XL_RXSTAT_UDPCKOK && 2148 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2149 m->m_pkthdr.csum_flags |= 2150 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2151 m->m_pkthdr.csum_data = 0xffff; 2152 } 2153 } 2154 2155 ether_input(ifp, eh, m); 2156 } 2157 2158 /* 2159 * Handle the 'end of channel' condition. When the upload 2160 * engine hits the end of the RX ring, it will stall. This 2161 * is our cue to flush the RX ring, reload the uplist pointer 2162 * register and unstall the engine. 2163 * XXX This is actually a little goofy. With the ThunderLAN 2164 * chip, you get an interrupt when the receiver hits the end 2165 * of the receive ring, which tells you exactly when you 2166 * you need to reload the ring pointer. Here we have to 2167 * fake it. I'm mad at myself for not being clever enough 2168 * to avoid the use of a goto here. 2169 */ 2170 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2171 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2172 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2173 xl_wait(sc); 2174 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2175 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2176 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2177 goto again; 2178 } 2179 2180 return; 2181 } 2182 2183 /* 2184 * A frame was downloaded to the chip. It's safe for us to clean up 2185 * the list buffers. 2186 */ 2187 static void 2188 xl_txeof(sc) 2189 struct xl_softc *sc; 2190 { 2191 struct xl_chain *cur_tx; 2192 struct ifnet *ifp; 2193 2194 ifp = &sc->arpcom.ac_if; 2195 2196 /* Clear the timeout timer. */ 2197 ifp->if_timer = 0; 2198 2199 /* 2200 * Go through our tx list and free mbufs for those 2201 * frames that have been uploaded. Note: the 3c905B 2202 * sets a special bit in the status word to let us 2203 * know that a frame has been downloaded, but the 2204 * original 3c900/3c905 adapters don't do that. 2205 * Consequently, we have to use a different test if 2206 * xl_type != XL_TYPE_905B. 2207 */ 2208 while(sc->xl_cdata.xl_tx_head != NULL) { 2209 cur_tx = sc->xl_cdata.xl_tx_head; 2210 2211 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2212 break; 2213 2214 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2215 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2216 BUS_DMASYNC_POSTWRITE); 2217 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2218 m_freem(cur_tx->xl_mbuf); 2219 cur_tx->xl_mbuf = NULL; 2220 ifp->if_opackets++; 2221 2222 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2223 sc->xl_cdata.xl_tx_free = cur_tx; 2224 } 2225 2226 if (sc->xl_cdata.xl_tx_head == NULL) { 2227 ifp->if_flags &= ~IFF_OACTIVE; 2228 sc->xl_cdata.xl_tx_tail = NULL; 2229 } else { 2230 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2231 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2232 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2233 sc->xl_cdata.xl_tx_head->xl_phys); 2234 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2235 } 2236 } 2237 2238 return; 2239 } 2240 2241 static void 2242 xl_txeof_90xB(sc) 2243 struct xl_softc *sc; 2244 { 2245 struct xl_chain *cur_tx = NULL; 2246 struct ifnet *ifp; 2247 int idx; 2248 2249 ifp = &sc->arpcom.ac_if; 2250 2251 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2252 BUS_DMASYNC_POSTREAD); 2253 idx = sc->xl_cdata.xl_tx_cons; 2254 while(idx != sc->xl_cdata.xl_tx_prod) { 2255 2256 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2257 2258 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2259 XL_TXSTAT_DL_COMPLETE)) 2260 break; 2261 2262 if (cur_tx->xl_mbuf != NULL) { 2263 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2264 BUS_DMASYNC_POSTWRITE); 2265 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2266 m_freem(cur_tx->xl_mbuf); 2267 cur_tx->xl_mbuf = NULL; 2268 } 2269 2270 ifp->if_opackets++; 2271 2272 sc->xl_cdata.xl_tx_cnt--; 2273 XL_INC(idx, XL_TX_LIST_CNT); 2274 ifp->if_timer = 0; 2275 } 2276 2277 sc->xl_cdata.xl_tx_cons = idx; 2278 2279 if (cur_tx != NULL) 2280 ifp->if_flags &= ~IFF_OACTIVE; 2281 2282 return; 2283 } 2284 2285 /* 2286 * TX 'end of channel' interrupt handler. Actually, we should 2287 * only get a 'TX complete' interrupt if there's a transmit error, 2288 * so this is really TX error handler. 2289 */ 2290 static void 2291 xl_txeoc(sc) 2292 struct xl_softc *sc; 2293 { 2294 u_int8_t txstat; 2295 2296 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2297 if (txstat & XL_TXSTATUS_UNDERRUN || 2298 txstat & XL_TXSTATUS_JABBER || 2299 txstat & XL_TXSTATUS_RECLAIM) { 2300 printf("xl%d: transmission error: %x\n", 2301 sc->xl_unit, txstat); 2302 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2303 xl_wait(sc); 2304 if (sc->xl_type == XL_TYPE_905B) { 2305 if (sc->xl_cdata.xl_tx_cnt) { 2306 int i; 2307 struct xl_chain *c; 2308 i = sc->xl_cdata.xl_tx_cons; 2309 c = &sc->xl_cdata.xl_tx_chain[i]; 2310 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2311 c->xl_phys); 2312 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2313 } 2314 } else { 2315 if (sc->xl_cdata.xl_tx_head != NULL) 2316 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2317 sc->xl_cdata.xl_tx_head->xl_phys); 2318 } 2319 /* 2320 * Remember to set this for the 2321 * first generation 3c90X chips. 2322 */ 2323 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2324 if (txstat & XL_TXSTATUS_UNDERRUN && 2325 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2326 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2327 printf("xl%d: tx underrun, increasing tx start" 2328 " threshold to %d bytes\n", sc->xl_unit, 2329 sc->xl_tx_thresh); 2330 } 2331 CSR_WRITE_2(sc, XL_COMMAND, 2332 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2333 if (sc->xl_type == XL_TYPE_905B) { 2334 CSR_WRITE_2(sc, XL_COMMAND, 2335 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2336 } 2337 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2338 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2339 } else { 2340 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2341 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2342 } 2343 /* 2344 * Write an arbitrary byte to the TX_STATUS register 2345 * to clear this interrupt/error and advance to the next. 2346 */ 2347 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2348 } 2349 2350 return; 2351 } 2352 2353 static void 2354 xl_intr(arg) 2355 void *arg; 2356 { 2357 struct xl_softc *sc; 2358 struct ifnet *ifp; 2359 u_int16_t status; 2360 2361 sc = arg; 2362 ifp = &sc->arpcom.ac_if; 2363 2364 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) { 2365 2366 CSR_WRITE_2(sc, XL_COMMAND, 2367 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2368 2369 if (status & XL_STAT_UP_COMPLETE) { 2370 int curpkts; 2371 2372 curpkts = ifp->if_ipackets; 2373 xl_rxeof(sc); 2374 if (curpkts == ifp->if_ipackets) { 2375 while (xl_rx_resync(sc)) 2376 xl_rxeof(sc); 2377 } 2378 } 2379 2380 if (status & XL_STAT_DOWN_COMPLETE) { 2381 if (sc->xl_type == XL_TYPE_905B) 2382 xl_txeof_90xB(sc); 2383 else 2384 xl_txeof(sc); 2385 } 2386 2387 if (status & XL_STAT_TX_COMPLETE) { 2388 ifp->if_oerrors++; 2389 xl_txeoc(sc); 2390 } 2391 2392 if (status & XL_STAT_ADFAIL) { 2393 xl_reset(sc); 2394 xl_init(sc); 2395 } 2396 2397 if (status & XL_STAT_STATSOFLOW) { 2398 sc->xl_stats_no_timeout = 1; 2399 xl_stats_update(sc); 2400 sc->xl_stats_no_timeout = 0; 2401 } 2402 } 2403 2404 if (ifp->if_snd.ifq_head != NULL) 2405 (*ifp->if_start)(ifp); 2406 2407 return; 2408 } 2409 2410 static void 2411 xl_stats_update(xsc) 2412 void *xsc; 2413 { 2414 struct xl_softc *sc; 2415 struct ifnet *ifp; 2416 struct xl_stats xl_stats; 2417 u_int8_t *p; 2418 int i; 2419 struct mii_data *mii = NULL; 2420 2421 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2422 2423 sc = xsc; 2424 ifp = &sc->arpcom.ac_if; 2425 if (sc->xl_miibus != NULL) 2426 mii = device_get_softc(sc->xl_miibus); 2427 2428 p = (u_int8_t *)&xl_stats; 2429 2430 /* Read all the stats registers. */ 2431 XL_SEL_WIN(6); 2432 2433 for (i = 0; i < 16; i++) 2434 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2435 2436 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2437 2438 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2439 xl_stats.xl_tx_single_collision + 2440 xl_stats.xl_tx_late_collision; 2441 2442 /* 2443 * Boomerang and cyclone chips have an extra stats counter 2444 * in window 4 (BadSSD). We have to read this too in order 2445 * to clear out all the stats registers and avoid a statsoflow 2446 * interrupt. 2447 */ 2448 XL_SEL_WIN(4); 2449 CSR_READ_1(sc, XL_W4_BADSSD); 2450 2451 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2452 mii_tick(mii); 2453 2454 XL_SEL_WIN(7); 2455 2456 if (!sc->xl_stats_no_timeout) 2457 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 2458 2459 return; 2460 } 2461 2462 /* 2463 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2464 * pointers to the fragment pointers. 2465 */ 2466 static int 2467 xl_encap(sc, c, m_head) 2468 struct xl_softc *sc; 2469 struct xl_chain *c; 2470 struct mbuf *m_head; 2471 { 2472 int error; 2473 u_int32_t status; 2474 struct ifnet *ifp; 2475 2476 ifp = &sc->arpcom.ac_if; 2477 2478 /* 2479 * Start packing the mbufs in this chain into 2480 * the fragment pointers. Stop when we run out 2481 * of fragments or hit the end of the mbuf chain. 2482 */ 2483 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, 2484 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2485 2486 if (error && error != EFBIG) { 2487 m_freem(m_head); 2488 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error); 2489 return(1); 2490 } 2491 2492 /* 2493 * Handle special case: we used up all 63 fragments, 2494 * but we have more mbufs left in the chain. Copy the 2495 * data into an mbuf cluster. Note that we don't 2496 * bother clearing the values in the other fragment 2497 * pointers/counters; it wouldn't gain us anything, 2498 * and would waste cycles. 2499 */ 2500 if (error) { 2501 struct mbuf *m_new; 2502 2503 m_new = m_defrag(m_head, M_DONTWAIT); 2504 if (m_new == NULL) { 2505 m_freem(m_head); 2506 return(1); 2507 } else { 2508 m_head = m_new; 2509 } 2510 2511 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, 2512 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2513 if (error) { 2514 m_freem(m_head); 2515 printf("xl%d: can't map mbuf (error %d)\n", 2516 sc->xl_unit, error); 2517 return(1); 2518 } 2519 } 2520 2521 if (sc->xl_type == XL_TYPE_905B) { 2522 status = XL_TXSTAT_RND_DEFEAT; 2523 2524 if (m_head->m_pkthdr.csum_flags) { 2525 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2526 status |= XL_TXSTAT_IPCKSUM; 2527 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2528 status |= XL_TXSTAT_TCPCKSUM; 2529 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2530 status |= XL_TXSTAT_UDPCKSUM; 2531 } 2532 c->xl_ptr->xl_status = htole32(status); 2533 } 2534 2535 c->xl_mbuf = m_head; 2536 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2537 return(0); 2538 } 2539 2540 /* 2541 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2542 * to the mbuf data regions directly in the transmit lists. We also save a 2543 * copy of the pointers since the transmit list fragment pointers are 2544 * physical addresses. 2545 */ 2546 static void 2547 xl_start(ifp) 2548 struct ifnet *ifp; 2549 { 2550 struct xl_softc *sc; 2551 struct mbuf *m_head = NULL; 2552 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2553 struct xl_chain *prev_tx; 2554 u_int32_t status; 2555 int error; 2556 2557 sc = ifp->if_softc; 2558 /* 2559 * Check for an available queue slot. If there are none, 2560 * punt. 2561 */ 2562 if (sc->xl_cdata.xl_tx_free == NULL) { 2563 xl_txeoc(sc); 2564 xl_txeof(sc); 2565 if (sc->xl_cdata.xl_tx_free == NULL) { 2566 ifp->if_flags |= IFF_OACTIVE; 2567 return; 2568 } 2569 } 2570 2571 start_tx = sc->xl_cdata.xl_tx_free; 2572 2573 while(sc->xl_cdata.xl_tx_free != NULL) { 2574 IF_DEQUEUE(&ifp->if_snd, m_head); 2575 if (m_head == NULL) 2576 break; 2577 2578 /* Pick a descriptor off the free list. */ 2579 prev_tx = cur_tx; 2580 cur_tx = sc->xl_cdata.xl_tx_free; 2581 2582 /* Pack the data into the descriptor. */ 2583 error = xl_encap(sc, cur_tx, m_head); 2584 if (error) { 2585 cur_tx = prev_tx; 2586 continue; 2587 } 2588 2589 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2590 cur_tx->xl_next = NULL; 2591 2592 /* Chain it together. */ 2593 if (prev != NULL) { 2594 prev->xl_next = cur_tx; 2595 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2596 } 2597 prev = cur_tx; 2598 2599 /* 2600 * If there's a BPF listener, bounce a copy of this frame 2601 * to him. 2602 */ 2603 if (ifp->if_bpf) 2604 bpf_mtap(ifp, cur_tx->xl_mbuf); 2605 } 2606 2607 /* 2608 * If there are no packets queued, bail. 2609 */ 2610 if (cur_tx == NULL) { 2611 return; 2612 } 2613 2614 /* 2615 * Place the request for the upload interrupt 2616 * in the last descriptor in the chain. This way, if 2617 * we're chaining several packets at once, we'll only 2618 * get an interupt once for the whole chain rather than 2619 * once for each packet. 2620 */ 2621 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2622 XL_TXSTAT_DL_INTR); 2623 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2624 BUS_DMASYNC_PREWRITE); 2625 2626 /* 2627 * Queue the packets. If the TX channel is clear, update 2628 * the downlist pointer register. 2629 */ 2630 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2631 xl_wait(sc); 2632 2633 if (sc->xl_cdata.xl_tx_head != NULL) { 2634 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2635 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2636 htole32(start_tx->xl_phys); 2637 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2638 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2639 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2640 sc->xl_cdata.xl_tx_tail = cur_tx; 2641 } else { 2642 sc->xl_cdata.xl_tx_head = start_tx; 2643 sc->xl_cdata.xl_tx_tail = cur_tx; 2644 } 2645 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2646 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2647 2648 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2649 2650 XL_SEL_WIN(7); 2651 2652 /* 2653 * Set a timeout in case the chip goes out to lunch. 2654 */ 2655 ifp->if_timer = 5; 2656 2657 /* 2658 * XXX Under certain conditions, usually on slower machines 2659 * where interrupts may be dropped, it's possible for the 2660 * adapter to chew up all the buffers in the receive ring 2661 * and stall, without us being able to do anything about it. 2662 * To guard against this, we need to make a pass over the 2663 * RX queue to make sure there aren't any packets pending. 2664 * Doing it here means we can flush the receive ring at the 2665 * same time the chip is DMAing the transmit descriptors we 2666 * just gave it. 2667 * 2668 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2669 * nature of their chips in all their marketing literature; 2670 * we may as well take advantage of it. :) 2671 */ 2672 xl_rxeof(sc); 2673 2674 return; 2675 } 2676 2677 static void 2678 xl_start_90xB(ifp) 2679 struct ifnet *ifp; 2680 { 2681 struct xl_softc *sc; 2682 struct mbuf *m_head = NULL; 2683 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2684 struct xl_chain *prev_tx; 2685 int error, idx; 2686 2687 sc = ifp->if_softc; 2688 2689 if (ifp->if_flags & IFF_OACTIVE) { 2690 return; 2691 } 2692 2693 idx = sc->xl_cdata.xl_tx_prod; 2694 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2695 2696 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2697 2698 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2699 ifp->if_flags |= IFF_OACTIVE; 2700 break; 2701 } 2702 2703 IF_DEQUEUE(&ifp->if_snd, m_head); 2704 if (m_head == NULL) 2705 break; 2706 2707 prev_tx = cur_tx; 2708 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2709 2710 /* Pack the data into the descriptor. */ 2711 error = xl_encap(sc, cur_tx, m_head); 2712 if (error) { 2713 cur_tx = prev_tx; 2714 continue; 2715 } 2716 2717 /* Chain it together. */ 2718 if (prev != NULL) 2719 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2720 prev = cur_tx; 2721 2722 /* 2723 * If there's a BPF listener, bounce a copy of this frame 2724 * to him. 2725 */ 2726 if (ifp->if_bpf) 2727 bpf_mtap(ifp, cur_tx->xl_mbuf); 2728 2729 XL_INC(idx, XL_TX_LIST_CNT); 2730 sc->xl_cdata.xl_tx_cnt++; 2731 } 2732 2733 /* 2734 * If there are no packets queued, bail. 2735 */ 2736 if (cur_tx == NULL) { 2737 return; 2738 } 2739 2740 /* 2741 * Place the request for the upload interrupt 2742 * in the last descriptor in the chain. This way, if 2743 * we're chaining several packets at once, we'll only 2744 * get an interupt once for the whole chain rather than 2745 * once for each packet. 2746 */ 2747 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2748 XL_TXSTAT_DL_INTR); 2749 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2750 BUS_DMASYNC_PREWRITE); 2751 2752 /* Start transmission */ 2753 sc->xl_cdata.xl_tx_prod = idx; 2754 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2755 2756 /* 2757 * Set a timeout in case the chip goes out to lunch. 2758 */ 2759 ifp->if_timer = 5; 2760 2761 return; 2762 } 2763 2764 static void 2765 xl_init(xsc) 2766 void *xsc; 2767 { 2768 struct xl_softc *sc = xsc; 2769 struct ifnet *ifp = &sc->arpcom.ac_if; 2770 int error, i; 2771 u_int16_t rxfilt = 0; 2772 struct mii_data *mii = NULL; 2773 int s; 2774 2775 s = splimp(); 2776 2777 /* 2778 * Cancel pending I/O and free all RX/TX buffers. 2779 */ 2780 xl_stop(sc); 2781 2782 if (sc->xl_miibus == NULL) { 2783 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2784 xl_wait(sc); 2785 } 2786 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2787 xl_wait(sc); 2788 DELAY(10000); 2789 2790 if (sc->xl_miibus != NULL) 2791 mii = device_get_softc(sc->xl_miibus); 2792 2793 /* Init our MAC address */ 2794 XL_SEL_WIN(2); 2795 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2796 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2797 sc->arpcom.ac_enaddr[i]); 2798 } 2799 2800 /* Clear the station mask. */ 2801 for (i = 0; i < 3; i++) 2802 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2803 #ifdef notdef 2804 /* Reset TX and RX. */ 2805 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2806 xl_wait(sc); 2807 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2808 xl_wait(sc); 2809 #endif 2810 /* Init circular RX list. */ 2811 error = xl_list_rx_init(sc); 2812 if (error) { 2813 printf("xl%d: initialization of the rx ring failed (%d)\n", 2814 sc->xl_unit, error); 2815 xl_stop(sc); 2816 splx(s); 2817 return; 2818 } 2819 2820 /* Init TX descriptors. */ 2821 if (sc->xl_type == XL_TYPE_905B) 2822 error = xl_list_tx_init_90xB(sc); 2823 else 2824 error = xl_list_tx_init(sc); 2825 if (error) { 2826 printf("xl%d: initialization of the tx ring failed (%d)\n", 2827 sc->xl_unit, error); 2828 xl_stop(sc); 2829 splx(s); 2830 } 2831 2832 /* 2833 * Set the TX freethresh value. 2834 * Note that this has no effect on 3c905B "cyclone" 2835 * cards but is required for 3c900/3c905 "boomerang" 2836 * cards in order to enable the download engine. 2837 */ 2838 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2839 2840 /* Set the TX start threshold for best performance. */ 2841 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2842 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2843 2844 /* 2845 * If this is a 3c905B, also set the tx reclaim threshold. 2846 * This helps cut down on the number of tx reclaim errors 2847 * that could happen on a busy network. The chip multiplies 2848 * the register value by 16 to obtain the actual threshold 2849 * in bytes, so we divide by 16 when setting the value here. 2850 * The existing threshold value can be examined by reading 2851 * the register at offset 9 in window 5. 2852 */ 2853 if (sc->xl_type == XL_TYPE_905B) { 2854 CSR_WRITE_2(sc, XL_COMMAND, 2855 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2856 } 2857 2858 /* Set RX filter bits. */ 2859 XL_SEL_WIN(5); 2860 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2861 2862 /* Set the individual bit to receive frames for this host only. */ 2863 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2864 2865 /* If we want promiscuous mode, set the allframes bit. */ 2866 if (ifp->if_flags & IFF_PROMISC) { 2867 rxfilt |= XL_RXFILTER_ALLFRAMES; 2868 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2869 } else { 2870 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2871 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2872 } 2873 2874 /* 2875 * Set capture broadcast bit to capture broadcast frames. 2876 */ 2877 if (ifp->if_flags & IFF_BROADCAST) { 2878 rxfilt |= XL_RXFILTER_BROADCAST; 2879 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2880 } else { 2881 rxfilt &= ~XL_RXFILTER_BROADCAST; 2882 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2883 } 2884 2885 /* 2886 * Program the multicast filter, if necessary. 2887 */ 2888 if (sc->xl_type == XL_TYPE_905B) 2889 xl_setmulti_hash(sc); 2890 else 2891 xl_setmulti(sc); 2892 2893 /* 2894 * Load the address of the RX list. We have to 2895 * stall the upload engine before we can manipulate 2896 * the uplist pointer register, then unstall it when 2897 * we're finished. We also have to wait for the 2898 * stall command to complete before proceeding. 2899 * Note that we have to do this after any RX resets 2900 * have completed since the uplist register is cleared 2901 * by a reset. 2902 */ 2903 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2904 xl_wait(sc); 2905 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2906 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2907 xl_wait(sc); 2908 2909 2910 if (sc->xl_type == XL_TYPE_905B) { 2911 /* Set polling interval */ 2912 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2913 /* Load the address of the TX list */ 2914 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2915 xl_wait(sc); 2916 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2917 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2918 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2919 xl_wait(sc); 2920 } 2921 2922 /* 2923 * If the coax transceiver is on, make sure to enable 2924 * the DC-DC converter. 2925 */ 2926 XL_SEL_WIN(3); 2927 if (sc->xl_xcvr == XL_XCVR_COAX) 2928 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2929 else 2930 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2931 2932 /* 2933 * increase packet size to allow reception of 802.1q or ISL packets. 2934 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2935 * control register. For 3c90xB/C chips, use the RX packet size 2936 * register. 2937 */ 2938 2939 if (sc->xl_type == XL_TYPE_905B) 2940 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2941 else { 2942 u_int8_t macctl; 2943 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2944 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2945 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2946 } 2947 2948 /* Clear out the stats counters. */ 2949 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2950 sc->xl_stats_no_timeout = 1; 2951 xl_stats_update(sc); 2952 sc->xl_stats_no_timeout = 0; 2953 XL_SEL_WIN(4); 2954 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2955 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2956 2957 /* 2958 * Enable interrupts. 2959 */ 2960 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2961 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2962 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2963 if (sc->xl_flags & XL_FLAG_FUNCREG) 2964 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2965 2966 /* Set the RX early threshold */ 2967 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2968 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2969 2970 /* Enable receiver and transmitter. */ 2971 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2972 xl_wait(sc); 2973 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2974 xl_wait(sc); 2975 2976 if (mii != NULL) 2977 mii_mediachg(mii); 2978 2979 /* Select window 7 for normal operations. */ 2980 XL_SEL_WIN(7); 2981 2982 ifp->if_flags |= IFF_RUNNING; 2983 ifp->if_flags &= ~IFF_OACTIVE; 2984 2985 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 2986 2987 splx(s); 2988 2989 return; 2990 } 2991 2992 /* 2993 * Set media options. 2994 */ 2995 static int 2996 xl_ifmedia_upd(ifp) 2997 struct ifnet *ifp; 2998 { 2999 struct xl_softc *sc; 3000 struct ifmedia *ifm = NULL; 3001 struct mii_data *mii = NULL; 3002 3003 sc = ifp->if_softc; 3004 if (sc->xl_miibus != NULL) 3005 mii = device_get_softc(sc->xl_miibus); 3006 if (mii == NULL) 3007 ifm = &sc->ifmedia; 3008 else 3009 ifm = &mii->mii_media; 3010 3011 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3012 case IFM_100_FX: 3013 case IFM_10_FL: 3014 case IFM_10_2: 3015 case IFM_10_5: 3016 xl_setmode(sc, ifm->ifm_media); 3017 return(0); 3018 break; 3019 default: 3020 break; 3021 } 3022 3023 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 3024 || sc->xl_media & XL_MEDIAOPT_BT4) { 3025 xl_init(sc); 3026 } else { 3027 xl_setmode(sc, ifm->ifm_media); 3028 } 3029 3030 return(0); 3031 } 3032 3033 /* 3034 * Report current media status. 3035 */ 3036 static void 3037 xl_ifmedia_sts(ifp, ifmr) 3038 struct ifnet *ifp; 3039 struct ifmediareq *ifmr; 3040 { 3041 struct xl_softc *sc; 3042 u_int32_t icfg; 3043 struct mii_data *mii = NULL; 3044 3045 sc = ifp->if_softc; 3046 if (sc->xl_miibus != NULL) 3047 mii = device_get_softc(sc->xl_miibus); 3048 3049 XL_SEL_WIN(3); 3050 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3051 icfg >>= XL_ICFG_CONNECTOR_BITS; 3052 3053 ifmr->ifm_active = IFM_ETHER; 3054 3055 switch(icfg) { 3056 case XL_XCVR_10BT: 3057 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3058 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3059 ifmr->ifm_active |= IFM_FDX; 3060 else 3061 ifmr->ifm_active |= IFM_HDX; 3062 break; 3063 case XL_XCVR_AUI: 3064 if (sc->xl_type == XL_TYPE_905B && 3065 sc->xl_media == XL_MEDIAOPT_10FL) { 3066 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3067 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3068 ifmr->ifm_active |= IFM_FDX; 3069 else 3070 ifmr->ifm_active |= IFM_HDX; 3071 } else 3072 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3073 break; 3074 case XL_XCVR_COAX: 3075 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3076 break; 3077 /* 3078 * XXX MII and BTX/AUTO should be separate cases. 3079 */ 3080 3081 case XL_XCVR_100BTX: 3082 case XL_XCVR_AUTO: 3083 case XL_XCVR_MII: 3084 if (mii != NULL) { 3085 mii_pollstat(mii); 3086 ifmr->ifm_active = mii->mii_media_active; 3087 ifmr->ifm_status = mii->mii_media_status; 3088 } 3089 break; 3090 case XL_XCVR_100BFX: 3091 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3092 break; 3093 default: 3094 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg); 3095 break; 3096 } 3097 3098 return; 3099 } 3100 3101 static int 3102 xl_ioctl(ifp, command, data) 3103 struct ifnet *ifp; 3104 u_long command; 3105 caddr_t data; 3106 { 3107 struct xl_softc *sc = ifp->if_softc; 3108 struct ifreq *ifr = (struct ifreq *) data; 3109 int error = 0; 3110 struct mii_data *mii = NULL; 3111 u_int8_t rxfilt; 3112 int s; 3113 3114 s = splimp(); 3115 3116 switch(command) { 3117 case SIOCSIFADDR: 3118 case SIOCGIFADDR: 3119 case SIOCSIFMTU: 3120 error = ether_ioctl(ifp, command, data); 3121 break; 3122 case SIOCSIFFLAGS: 3123 XL_SEL_WIN(5); 3124 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3125 if (ifp->if_flags & IFF_UP) { 3126 if (ifp->if_flags & IFF_RUNNING && 3127 ifp->if_flags & IFF_PROMISC && 3128 !(sc->xl_if_flags & IFF_PROMISC)) { 3129 rxfilt |= XL_RXFILTER_ALLFRAMES; 3130 CSR_WRITE_2(sc, XL_COMMAND, 3131 XL_CMD_RX_SET_FILT|rxfilt); 3132 XL_SEL_WIN(7); 3133 } else if (ifp->if_flags & IFF_RUNNING && 3134 !(ifp->if_flags & IFF_PROMISC) && 3135 sc->xl_if_flags & IFF_PROMISC) { 3136 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3137 CSR_WRITE_2(sc, XL_COMMAND, 3138 XL_CMD_RX_SET_FILT|rxfilt); 3139 XL_SEL_WIN(7); 3140 } else 3141 xl_init(sc); 3142 } else { 3143 if (ifp->if_flags & IFF_RUNNING) 3144 xl_stop(sc); 3145 } 3146 sc->xl_if_flags = ifp->if_flags; 3147 error = 0; 3148 break; 3149 case SIOCADDMULTI: 3150 case SIOCDELMULTI: 3151 if (sc->xl_type == XL_TYPE_905B) 3152 xl_setmulti_hash(sc); 3153 else 3154 xl_setmulti(sc); 3155 error = 0; 3156 break; 3157 case SIOCGIFMEDIA: 3158 case SIOCSIFMEDIA: 3159 if (sc->xl_miibus != NULL) 3160 mii = device_get_softc(sc->xl_miibus); 3161 if (mii == NULL) 3162 error = ifmedia_ioctl(ifp, ifr, 3163 &sc->ifmedia, command); 3164 else 3165 error = ifmedia_ioctl(ifp, ifr, 3166 &mii->mii_media, command); 3167 break; 3168 case SIOCSIFCAP: 3169 ifp->if_capenable = ifr->ifr_reqcap; 3170 if (ifp->if_capenable & IFCAP_TXCSUM) 3171 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3172 else 3173 ifp->if_hwassist = 0; 3174 break; 3175 default: 3176 error = EINVAL; 3177 break; 3178 } 3179 3180 splx(s); 3181 return(error); 3182 } 3183 3184 static void 3185 xl_watchdog(ifp) 3186 struct ifnet *ifp; 3187 { 3188 struct xl_softc *sc; 3189 u_int16_t status = 0; 3190 3191 sc = ifp->if_softc; 3192 3193 ifp->if_oerrors++; 3194 XL_SEL_WIN(4); 3195 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3196 printf("xl%d: watchdog timeout\n", sc->xl_unit); 3197 3198 if (status & XL_MEDIASTAT_CARRIER) 3199 printf("xl%d: no carrier - transceiver cable problem?\n", 3200 sc->xl_unit); 3201 xl_txeoc(sc); 3202 xl_txeof(sc); 3203 xl_rxeof(sc); 3204 xl_reset(sc); 3205 xl_init(sc); 3206 3207 if (ifp->if_snd.ifq_head != NULL) 3208 (*ifp->if_start)(ifp); 3209 3210 return; 3211 } 3212 3213 /* 3214 * Stop the adapter and free any mbufs allocated to the 3215 * RX and TX lists. 3216 */ 3217 static void 3218 xl_stop(sc) 3219 struct xl_softc *sc; 3220 { 3221 int i; 3222 struct ifnet *ifp; 3223 3224 ifp = &sc->arpcom.ac_if; 3225 ifp->if_timer = 0; 3226 3227 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3228 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3229 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3230 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3231 xl_wait(sc); 3232 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3233 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3234 DELAY(800); 3235 3236 #ifdef foo 3237 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3238 xl_wait(sc); 3239 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3240 xl_wait(sc); 3241 #endif 3242 3243 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3244 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3245 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3246 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3247 3248 /* Stop the stats updater. */ 3249 untimeout(xl_stats_update, sc, sc->xl_stat_ch); 3250 3251 /* 3252 * Free data in the RX lists. 3253 */ 3254 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3255 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3256 bus_dmamap_unload(sc->xl_mtag, 3257 sc->xl_cdata.xl_rx_chain[i].xl_map); 3258 bus_dmamap_destroy(sc->xl_mtag, 3259 sc->xl_cdata.xl_rx_chain[i].xl_map); 3260 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3261 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3262 } 3263 } 3264 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3265 /* 3266 * Free the TX list buffers. 3267 */ 3268 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3269 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3270 bus_dmamap_unload(sc->xl_mtag, 3271 sc->xl_cdata.xl_tx_chain[i].xl_map); 3272 bus_dmamap_destroy(sc->xl_mtag, 3273 sc->xl_cdata.xl_tx_chain[i].xl_map); 3274 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3275 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3276 } 3277 } 3278 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3279 3280 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3281 3282 return; 3283 } 3284 3285 /* 3286 * Stop all chip I/O so that the kernel's probe routines don't 3287 * get confused by errant DMAs when rebooting. 3288 */ 3289 static void 3290 xl_shutdown(dev) 3291 device_t dev; 3292 { 3293 struct xl_softc *sc; 3294 3295 sc = device_get_softc(dev); 3296 3297 xl_reset(sc); 3298 xl_stop(sc); 3299 3300 return; 3301 } 3302 3303 static int 3304 xl_suspend(dev) 3305 device_t dev; 3306 { 3307 struct xl_softc *sc; 3308 int s; 3309 3310 s = splimp(); 3311 3312 sc = device_get_softc(dev); 3313 3314 xl_stop(sc); 3315 3316 splx(s); 3317 3318 return(0); 3319 } 3320 3321 static int 3322 xl_resume(dev) 3323 device_t dev; 3324 { 3325 struct xl_softc *sc; 3326 struct ifnet *ifp; 3327 int s; 3328 3329 s = splimp(); 3330 3331 sc = device_get_softc(dev); 3332 ifp = &sc->arpcom.ac_if; 3333 3334 xl_reset(sc); 3335 if (ifp->if_flags & IFF_UP) 3336 xl_init(sc); 3337 3338 splx(s); 3339 return(0); 3340 } 3341