1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $ 33 */ 34 35 /* 36 * 3Com 3c90x Etherlink XL PCI NIC driver 37 * 38 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 39 * bus-master chips (3c90x cards and embedded controllers) including 40 * the following: 41 * 42 * 3Com 3c900-TPO 10Mbps/RJ-45 43 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 44 * 3Com 3c905-TX 10/100Mbps/RJ-45 45 * 3Com 3c905-T4 10/100Mbps/RJ-45 46 * 3Com 3c900B-TPO 10Mbps/RJ-45 47 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 48 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 49 * 3Com 3c900B-FL 10Mbps/Fiber-optic 50 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 51 * 3Com 3c905B-TX 10/100Mbps/RJ-45 52 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 53 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 54 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 55 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 56 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 57 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 58 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 59 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 60 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 62 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 67 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 68 * Dell on-board 3c920 10/100Mbps/RJ-45 69 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 70 * Dell Latitude laptop docking station embedded 3c905-TX 71 * 72 * Written by Bill Paul <wpaul@ctr.columbia.edu> 73 * Electrical Engineering Department 74 * Columbia University, New York City 75 */ 76 77 /* 78 * The 3c90x series chips use a bus-master DMA interface for transfering 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 */ 100 101 #include "opt_polling.h" 102 103 #include <sys/param.h> 104 #include <sys/systm.h> 105 #include <sys/sockio.h> 106 #include <sys/endian.h> 107 #include <sys/mbuf.h> 108 #include <sys/kernel.h> 109 #include <sys/socket.h> 110 #include <sys/serialize.h> 111 #include <sys/bus.h> 112 #include <sys/rman.h> 113 #include <sys/thread2.h> 114 #include <sys/interrupt.h> 115 116 #include <net/if.h> 117 #include <net/ifq_var.h> 118 #include <net/if_arp.h> 119 #include <net/ethernet.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 #include <net/vlan/if_vlan_var.h> 123 124 #include <net/bpf.h> 125 126 #include "../mii_layer/mii.h" 127 #include "../mii_layer/miivar.h" 128 129 #include <bus/pci/pcireg.h> 130 #include <bus/pci/pcivar.h> 131 132 /* "controller miibus0" required. See GENERIC if you get errors here. */ 133 #include "miibus_if.h" 134 135 #include "if_xlreg.h" 136 137 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 138 139 /* 140 * Various supported device vendors/types and their names. 141 */ 142 static struct xl_type xl_devs[] = { 143 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 144 "3Com 3c900-TPO Etherlink XL" }, 145 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 146 "3Com 3c900-COMBO Etherlink XL" }, 147 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 148 "3Com 3c905-TX Fast Etherlink XL" }, 149 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 150 "3Com 3c905-T4 Fast Etherlink XL" }, 151 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 152 "3Com 3c900B-TPO Etherlink XL" }, 153 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 154 "3Com 3c900B-COMBO Etherlink XL" }, 155 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 156 "3Com 3c900B-TPC Etherlink XL" }, 157 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 158 "3Com 3c900B-FL Etherlink XL" }, 159 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 160 "3Com 3c905B-TX Fast Etherlink XL" }, 161 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 162 "3Com 3c905B-T4 Fast Etherlink XL" }, 163 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 164 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 165 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 166 "3Com 3c905B-COMBO Fast Etherlink XL" }, 167 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 168 "3Com 3c905C-TX Fast Etherlink XL" }, 169 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 170 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 172 "3Com 3c980 Fast Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 174 "3Com 3c980C Fast Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 176 "3Com 3cSOHO100-TX OfficeConnect" }, 177 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 178 "3Com 3c450-TX HomeConnect" }, 179 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 180 "3Com 3c555 Fast Etherlink XL" }, 181 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 182 "3Com 3c556 Fast Etherlink XL" }, 183 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 184 "3Com 3c556B Fast Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 186 "3Com 3c575TX Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 188 "3Com 3c575B Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 190 "3Com 3c575C Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 192 "3Com 3c656 Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 194 "3Com 3c656B Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 196 "3Com 3c656C Fast Etherlink XL" }, 197 { 0, 0, NULL } 198 }; 199 200 static int xl_probe (device_t); 201 static int xl_attach (device_t); 202 static int xl_detach (device_t); 203 static void xl_shutdown (device_t); 204 static int xl_suspend (device_t); 205 static int xl_resume (device_t); 206 207 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *, 208 int); 209 static void xl_stats_update (void *); 210 static void xl_stats_update_serialized(void *); 211 static int xl_encap (struct xl_softc *, struct xl_chain *, 212 struct mbuf *); 213 static void xl_rxeof (struct xl_softc *, int); 214 static int xl_rx_resync (struct xl_softc *); 215 static void xl_txeof (struct xl_softc *); 216 static void xl_txeof_90xB (struct xl_softc *); 217 static void xl_txeoc (struct xl_softc *); 218 static void xl_intr (void *); 219 static void xl_start_body (struct ifnet *, int); 220 static void xl_start (struct ifnet *); 221 static void xl_start_90xB (struct ifnet *); 222 static int xl_ioctl (struct ifnet *, u_long, caddr_t, 223 struct ucred *); 224 static void xl_init (void *); 225 static void xl_stop (struct xl_softc *); 226 static void xl_watchdog (struct ifnet *); 227 #ifdef DEVICE_POLLING 228 static void xl_start_poll (struct ifnet *); 229 static void xl_poll (struct ifnet *, enum poll_cmd, int); 230 #endif 231 static void xl_enable_intrs (struct xl_softc *, uint16_t); 232 233 static int xl_ifmedia_upd (struct ifnet *); 234 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 235 236 static int xl_eeprom_wait (struct xl_softc *); 237 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 238 static void xl_mii_sync (struct xl_softc *); 239 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 240 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 241 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 242 243 static void xl_setcfg (struct xl_softc *); 244 static void xl_setmode (struct xl_softc *, int); 245 static void xl_setmulti (struct xl_softc *); 246 static void xl_setmulti_hash (struct xl_softc *); 247 static void xl_reset (struct xl_softc *); 248 static int xl_list_rx_init (struct xl_softc *); 249 static void xl_list_tx_init (struct xl_softc *); 250 static void xl_list_tx_init_90xB(struct xl_softc *); 251 static void xl_wait (struct xl_softc *); 252 static void xl_mediacheck (struct xl_softc *); 253 static void xl_choose_xcvr (struct xl_softc *, int); 254 255 static int xl_dma_alloc (device_t); 256 static void xl_dma_free (device_t); 257 258 #ifdef notdef 259 static void xl_testpacket (struct xl_softc *); 260 #endif 261 262 static int xl_miibus_readreg (device_t, int, int); 263 static int xl_miibus_writereg (device_t, int, int, int); 264 static void xl_miibus_statchg (device_t); 265 static void xl_miibus_mediainit (device_t); 266 267 static device_method_t xl_methods[] = { 268 /* Device interface */ 269 DEVMETHOD(device_probe, xl_probe), 270 DEVMETHOD(device_attach, xl_attach), 271 DEVMETHOD(device_detach, xl_detach), 272 DEVMETHOD(device_shutdown, xl_shutdown), 273 DEVMETHOD(device_suspend, xl_suspend), 274 DEVMETHOD(device_resume, xl_resume), 275 276 /* bus interface */ 277 DEVMETHOD(bus_print_child, bus_generic_print_child), 278 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 279 280 /* MII interface */ 281 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 282 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 283 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 284 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 285 286 { 0, 0 } 287 }; 288 289 static driver_t xl_driver = { 290 "xl", 291 xl_methods, 292 sizeof(struct xl_softc) 293 }; 294 295 static devclass_t xl_devclass; 296 297 DECLARE_DUMMY_MODULE(if_xl); 298 MODULE_DEPEND(if_xl, miibus, 1, 1, 1); 299 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, NULL, NULL); 300 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, NULL, NULL); 301 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, NULL, NULL); 302 303 static void 304 xl_enable_intrs(struct xl_softc *sc, uint16_t intrs) 305 { 306 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | 0xFF); 307 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB | intrs); 308 if (sc->xl_flags & XL_FLAG_FUNCREG) 309 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 310 } 311 312 /* 313 * Murphy's law says that it's possible the chip can wedge and 314 * the 'command in progress' bit may never clear. Hence, we wait 315 * only a finite amount of time to avoid getting caught in an 316 * infinite loop. Normally this delay routine would be a macro, 317 * but it isn't called during normal operation so we can afford 318 * to make it a function. 319 */ 320 static void 321 xl_wait(struct xl_softc *sc) 322 { 323 int i; 324 325 for (i = 0; i < XL_TIMEOUT; i++) { 326 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 327 break; 328 } 329 330 if (i == XL_TIMEOUT) 331 if_printf(&sc->arpcom.ac_if, "command never completed!"); 332 333 return; 334 } 335 336 /* 337 * MII access routines are provided for adapters with external 338 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 339 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 340 * Note: if you don't perform the MDIO operations just right, 341 * it's possible to end up with code that works correctly with 342 * some chips/CPUs/processor speeds/bus speeds/etc but not 343 * with others. 344 */ 345 #define MII_SET(x) \ 346 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 347 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 348 349 #define MII_CLR(x) \ 350 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 351 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 352 353 /* 354 * Sync the PHYs by setting data bit and strobing the clock 32 times. 355 */ 356 static void 357 xl_mii_sync(struct xl_softc *sc) 358 { 359 int i; 360 361 XL_SEL_WIN(4); 362 MII_SET(XL_MII_DIR|XL_MII_DATA); 363 364 for (i = 0; i < 32; i++) { 365 MII_SET(XL_MII_CLK); 366 MII_SET(XL_MII_DATA); 367 MII_SET(XL_MII_DATA); 368 MII_CLR(XL_MII_CLK); 369 MII_SET(XL_MII_DATA); 370 MII_SET(XL_MII_DATA); 371 } 372 373 return; 374 } 375 376 /* 377 * Clock a series of bits through the MII. 378 */ 379 static void 380 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 381 { 382 int i; 383 384 XL_SEL_WIN(4); 385 MII_CLR(XL_MII_CLK); 386 387 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 388 if (bits & i) { 389 MII_SET(XL_MII_DATA); 390 } else { 391 MII_CLR(XL_MII_DATA); 392 } 393 MII_CLR(XL_MII_CLK); 394 MII_SET(XL_MII_CLK); 395 } 396 } 397 398 /* 399 * Read an PHY register through the MII. 400 */ 401 static int 402 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 403 { 404 int i, ack; 405 406 /* 407 * Set up frame for RX. 408 */ 409 frame->mii_stdelim = XL_MII_STARTDELIM; 410 frame->mii_opcode = XL_MII_READOP; 411 frame->mii_turnaround = 0; 412 frame->mii_data = 0; 413 414 /* 415 * Select register window 4. 416 */ 417 418 XL_SEL_WIN(4); 419 420 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 421 /* 422 * Turn on data xmit. 423 */ 424 MII_SET(XL_MII_DIR); 425 426 xl_mii_sync(sc); 427 428 /* 429 * Send command/address info. 430 */ 431 xl_mii_send(sc, frame->mii_stdelim, 2); 432 xl_mii_send(sc, frame->mii_opcode, 2); 433 xl_mii_send(sc, frame->mii_phyaddr, 5); 434 xl_mii_send(sc, frame->mii_regaddr, 5); 435 436 /* Idle bit */ 437 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 438 MII_SET(XL_MII_CLK); 439 440 /* Turn off xmit. */ 441 MII_CLR(XL_MII_DIR); 442 443 /* Check for ack */ 444 MII_CLR(XL_MII_CLK); 445 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 446 MII_SET(XL_MII_CLK); 447 448 /* 449 * Now try reading data bits. If the ack failed, we still 450 * need to clock through 16 cycles to keep the PHY(s) in sync. 451 */ 452 if (ack) { 453 for(i = 0; i < 16; i++) { 454 MII_CLR(XL_MII_CLK); 455 MII_SET(XL_MII_CLK); 456 } 457 goto fail; 458 } 459 460 for (i = 0x8000; i; i >>= 1) { 461 MII_CLR(XL_MII_CLK); 462 if (!ack) { 463 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 464 frame->mii_data |= i; 465 } 466 MII_SET(XL_MII_CLK); 467 } 468 469 fail: 470 471 MII_CLR(XL_MII_CLK); 472 MII_SET(XL_MII_CLK); 473 474 if (ack) 475 return(1); 476 return(0); 477 } 478 479 /* 480 * Write to a PHY register through the MII. 481 */ 482 static int 483 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 484 { 485 /* 486 * Set up frame for TX. 487 */ 488 489 frame->mii_stdelim = XL_MII_STARTDELIM; 490 frame->mii_opcode = XL_MII_WRITEOP; 491 frame->mii_turnaround = XL_MII_TURNAROUND; 492 493 /* 494 * Select the window 4. 495 */ 496 XL_SEL_WIN(4); 497 498 /* 499 * Turn on data output. 500 */ 501 MII_SET(XL_MII_DIR); 502 503 xl_mii_sync(sc); 504 505 xl_mii_send(sc, frame->mii_stdelim, 2); 506 xl_mii_send(sc, frame->mii_opcode, 2); 507 xl_mii_send(sc, frame->mii_phyaddr, 5); 508 xl_mii_send(sc, frame->mii_regaddr, 5); 509 xl_mii_send(sc, frame->mii_turnaround, 2); 510 xl_mii_send(sc, frame->mii_data, 16); 511 512 /* Idle bit. */ 513 MII_SET(XL_MII_CLK); 514 MII_CLR(XL_MII_CLK); 515 516 /* 517 * Turn off xmit. 518 */ 519 MII_CLR(XL_MII_DIR); 520 521 return(0); 522 } 523 524 static int 525 xl_miibus_readreg(device_t dev, int phy, int reg) 526 { 527 struct xl_softc *sc; 528 struct xl_mii_frame frame; 529 530 sc = device_get_softc(dev); 531 532 /* 533 * Pretend that PHYs are only available at MII address 24. 534 * This is to guard against problems with certain 3Com ASIC 535 * revisions that incorrectly map the internal transceiver 536 * control registers at all MII addresses. This can cause 537 * the miibus code to attach the same PHY several times over. 538 */ 539 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 540 return(0); 541 542 bzero((char *)&frame, sizeof(frame)); 543 544 frame.mii_phyaddr = phy; 545 frame.mii_regaddr = reg; 546 xl_mii_readreg(sc, &frame); 547 548 return(frame.mii_data); 549 } 550 551 static int 552 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 553 { 554 struct xl_softc *sc; 555 struct xl_mii_frame frame; 556 557 sc = device_get_softc(dev); 558 559 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 560 return(0); 561 562 bzero((char *)&frame, sizeof(frame)); 563 564 frame.mii_phyaddr = phy; 565 frame.mii_regaddr = reg; 566 frame.mii_data = data; 567 568 xl_mii_writereg(sc, &frame); 569 570 return(0); 571 } 572 573 static void 574 xl_miibus_statchg(device_t dev) 575 { 576 struct xl_softc *sc; 577 struct mii_data *mii; 578 579 sc = device_get_softc(dev); 580 mii = device_get_softc(sc->xl_miibus); 581 582 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer); 583 584 xl_setcfg(sc); 585 586 /* Set ASIC's duplex mode to match the PHY. */ 587 XL_SEL_WIN(3); 588 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 589 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 590 else 591 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 592 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 593 } 594 595 /* 596 * Special support for the 3c905B-COMBO. This card has 10/100 support 597 * plus BNC and AUI ports. This means we will have both an miibus attached 598 * plus some non-MII media settings. In order to allow this, we have to 599 * add the extra media to the miibus's ifmedia struct, but we can't do 600 * that during xl_attach() because the miibus hasn't been attached yet. 601 * So instead, we wait until the miibus probe/attach is done, at which 602 * point we will get a callback telling is that it's safe to add our 603 * extra media. 604 */ 605 static void 606 xl_miibus_mediainit(device_t dev) 607 { 608 struct xl_softc *sc; 609 struct mii_data *mii; 610 struct ifmedia *ifm; 611 612 sc = device_get_softc(dev); 613 mii = device_get_softc(sc->xl_miibus); 614 ifm = &mii->mii_media; 615 616 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 617 /* 618 * Check for a 10baseFL board in disguise. 619 */ 620 if (sc->xl_type == XL_TYPE_905B && 621 sc->xl_media == XL_MEDIAOPT_10FL) { 622 if (bootverbose) 623 device_printf(dev, "found 10baseFL\n"); 624 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 625 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 626 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 627 ifmedia_add(ifm, 628 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 629 } else { 630 if (bootverbose) 631 device_printf(dev, "found AUI\n"); 632 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 633 } 634 } 635 636 if (sc->xl_media & XL_MEDIAOPT_BNC) { 637 if (bootverbose) 638 device_printf(dev, "found BNC\n"); 639 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 640 } 641 642 return; 643 } 644 645 /* 646 * The EEPROM is slow: give it time to come ready after issuing 647 * it a command. 648 */ 649 static int 650 xl_eeprom_wait(struct xl_softc *sc) 651 { 652 int i; 653 654 for (i = 0; i < 100; i++) { 655 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 656 DELAY(162); 657 else 658 break; 659 } 660 661 if (i == 100) { 662 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 663 return(1); 664 } 665 666 return(0); 667 } 668 669 /* 670 * Read a sequence of words from the EEPROM. Note that ethernet address 671 * data is stored in the EEPROM in network byte order. 672 */ 673 static int 674 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 675 { 676 int err = 0, i; 677 u_int16_t word = 0, *ptr; 678 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 679 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 680 /* WARNING! DANGER! 681 * It's easy to accidentally overwrite the rom content! 682 * Note: the 3c575 uses 8bit EEPROM offsets. 683 */ 684 XL_SEL_WIN(0); 685 686 if (xl_eeprom_wait(sc)) 687 return(1); 688 689 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 690 off += 0x30; 691 692 for (i = 0; i < cnt; i++) { 693 if (sc->xl_flags & XL_FLAG_8BITROM) 694 CSR_WRITE_2(sc, XL_W0_EE_CMD, 695 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 696 else 697 CSR_WRITE_2(sc, XL_W0_EE_CMD, 698 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 699 err = xl_eeprom_wait(sc); 700 if (err) 701 break; 702 word = CSR_READ_2(sc, XL_W0_EE_DATA); 703 ptr = (u_int16_t *)(dest + (i * 2)); 704 if (swap) 705 *ptr = ntohs(word); 706 else 707 *ptr = word; 708 } 709 710 return(err ? 1 : 0); 711 } 712 713 /* 714 * NICs older than the 3c905B have only one multicast option, which 715 * is to enable reception of all multicast frames. 716 */ 717 static void 718 xl_setmulti(struct xl_softc *sc) 719 { 720 struct ifnet *ifp; 721 struct ifmultiaddr *ifma; 722 u_int8_t rxfilt; 723 int mcnt = 0; 724 725 ifp = &sc->arpcom.ac_if; 726 727 XL_SEL_WIN(5); 728 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 729 730 if (ifp->if_flags & IFF_ALLMULTI) { 731 rxfilt |= XL_RXFILTER_ALLMULTI; 732 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 733 return; 734 } 735 736 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 737 mcnt++; 738 739 if (mcnt) 740 rxfilt |= XL_RXFILTER_ALLMULTI; 741 else 742 rxfilt &= ~XL_RXFILTER_ALLMULTI; 743 744 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 745 746 return; 747 } 748 749 /* 750 * 3c905B adapters have a hash filter that we can program. 751 */ 752 static void 753 xl_setmulti_hash(struct xl_softc *sc) 754 { 755 struct ifnet *ifp; 756 int h = 0, i; 757 struct ifmultiaddr *ifma; 758 u_int8_t rxfilt; 759 int mcnt = 0; 760 761 ifp = &sc->arpcom.ac_if; 762 763 XL_SEL_WIN(5); 764 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 765 766 if (ifp->if_flags & IFF_ALLMULTI) { 767 rxfilt |= XL_RXFILTER_ALLMULTI; 768 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 769 return; 770 } else 771 rxfilt &= ~XL_RXFILTER_ALLMULTI; 772 773 774 /* first, zot all the existing hash bits */ 775 for (i = 0; i < XL_HASHFILT_SIZE; i++) 776 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 777 778 /* now program new ones */ 779 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 780 if (ifma->ifma_addr->sa_family != AF_LINK) 781 continue; 782 783 /* 784 * Note: the 3c905B currently only supports a 64-bit 785 * hash table, which means we really only need 6 bits, 786 * but the manual indicates that future chip revisions 787 * will have a 256-bit hash table, hence the routine is 788 * set up to calculate 8 bits of position info in case 789 * we need it some day. 790 * Note II, The Sequel: _CURRENT_ versions of the 3c905B 791 * have a 256 bit hash table. This means we have to use 792 * all 8 bits regardless. On older cards, the upper 2 793 * bits will be ignored. Grrrr.... 794 */ 795 h = ether_crc32_be( 796 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 797 ETHER_ADDR_LEN) & 0xff; 798 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 799 mcnt++; 800 } 801 802 if (mcnt) 803 rxfilt |= XL_RXFILTER_MULTIHASH; 804 else 805 rxfilt &= ~XL_RXFILTER_MULTIHASH; 806 807 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 808 809 return; 810 } 811 812 #ifdef notdef 813 static void 814 xl_testpacket(struct xl_softc *sc) 815 { 816 struct mbuf *m; 817 struct ifnet *ifp; 818 819 ifp = &sc->arpcom.ac_if; 820 821 MGETHDR(m, MB_DONTWAIT, MT_DATA); 822 823 if (m == NULL) 824 return; 825 826 bcopy(&sc->arpcom.ac_enaddr, 827 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 828 bcopy(&sc->arpcom.ac_enaddr, 829 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 830 mtod(m, struct ether_header *)->ether_type = htons(3); 831 mtod(m, unsigned char *)[14] = 0; 832 mtod(m, unsigned char *)[15] = 0; 833 mtod(m, unsigned char *)[16] = 0xE3; 834 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 835 IF_ENQUEUE(&ifp->if_snd, m); 836 xl_start(ifp); 837 838 return; 839 } 840 #endif 841 842 static void 843 xl_setcfg(struct xl_softc *sc) 844 { 845 u_int32_t icfg; 846 847 XL_SEL_WIN(3); 848 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 849 icfg &= ~XL_ICFG_CONNECTOR_MASK; 850 if (sc->xl_media & XL_MEDIAOPT_MII || 851 sc->xl_media & XL_MEDIAOPT_BT4) 852 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 853 if (sc->xl_media & XL_MEDIAOPT_BTX) 854 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 855 856 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 857 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 858 859 return; 860 } 861 862 static void 863 xl_setmode(struct xl_softc *sc, int media) 864 { 865 struct ifnet *ifp = &sc->arpcom.ac_if; 866 u_int32_t icfg; 867 u_int16_t mediastat; 868 869 if_printf(ifp, "selecting "); 870 871 XL_SEL_WIN(4); 872 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 873 XL_SEL_WIN(3); 874 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 875 876 if (sc->xl_media & XL_MEDIAOPT_BT) { 877 if (IFM_SUBTYPE(media) == IFM_10_T) { 878 kprintf("10baseT transceiver, "); 879 sc->xl_xcvr = XL_XCVR_10BT; 880 icfg &= ~XL_ICFG_CONNECTOR_MASK; 881 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 882 mediastat |= XL_MEDIASTAT_LINKBEAT| 883 XL_MEDIASTAT_JABGUARD; 884 mediastat &= ~XL_MEDIASTAT_SQEENB; 885 } 886 } 887 888 if (sc->xl_media & XL_MEDIAOPT_BFX) { 889 if (IFM_SUBTYPE(media) == IFM_100_FX) { 890 kprintf("100baseFX port, "); 891 sc->xl_xcvr = XL_XCVR_100BFX; 892 icfg &= ~XL_ICFG_CONNECTOR_MASK; 893 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 894 mediastat |= XL_MEDIASTAT_LINKBEAT; 895 mediastat &= ~XL_MEDIASTAT_SQEENB; 896 } 897 } 898 899 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 900 if (IFM_SUBTYPE(media) == IFM_10_5) { 901 kprintf("AUI port, "); 902 sc->xl_xcvr = XL_XCVR_AUI; 903 icfg &= ~XL_ICFG_CONNECTOR_MASK; 904 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 905 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 906 XL_MEDIASTAT_JABGUARD); 907 mediastat |= ~XL_MEDIASTAT_SQEENB; 908 } 909 if (IFM_SUBTYPE(media) == IFM_10_FL) { 910 kprintf("10baseFL transceiver, "); 911 sc->xl_xcvr = XL_XCVR_AUI; 912 icfg &= ~XL_ICFG_CONNECTOR_MASK; 913 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 914 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 915 XL_MEDIASTAT_JABGUARD); 916 mediastat |= ~XL_MEDIASTAT_SQEENB; 917 } 918 } 919 920 if (sc->xl_media & XL_MEDIAOPT_BNC) { 921 if (IFM_SUBTYPE(media) == IFM_10_2) { 922 kprintf("BNC port, "); 923 sc->xl_xcvr = XL_XCVR_COAX; 924 icfg &= ~XL_ICFG_CONNECTOR_MASK; 925 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 926 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 927 XL_MEDIASTAT_JABGUARD| 928 XL_MEDIASTAT_SQEENB); 929 } 930 } 931 932 if ((media & IFM_GMASK) == IFM_FDX || 933 IFM_SUBTYPE(media) == IFM_100_FX) { 934 kprintf("full duplex\n"); 935 XL_SEL_WIN(3); 936 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 937 } else { 938 kprintf("half duplex\n"); 939 XL_SEL_WIN(3); 940 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 941 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 942 } 943 944 if (IFM_SUBTYPE(media) == IFM_10_2) 945 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 946 else 947 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 948 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 949 XL_SEL_WIN(4); 950 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 951 DELAY(800); 952 XL_SEL_WIN(7); 953 } 954 955 static void 956 xl_reset(struct xl_softc *sc) 957 { 958 int i; 959 960 XL_SEL_WIN(0); 961 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 962 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 963 XL_RESETOPT_DISADVFD:0)); 964 965 /* 966 * If we're using memory mapped register mode, pause briefly 967 * after issuing the reset command before trying to access any 968 * other registers. With my 3c575C cardbus card, failing to do 969 * this results in the system locking up while trying to poll 970 * the command busy bit in the status register. 971 */ 972 if (sc->xl_flags & XL_FLAG_USE_MMIO) 973 DELAY(100000); 974 975 for (i = 0; i < XL_TIMEOUT; i++) { 976 DELAY(10); 977 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 978 break; 979 } 980 981 if (i == XL_TIMEOUT) 982 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n"); 983 984 /* Reset TX and RX. */ 985 /* Note: the RX reset takes an absurd amount of time 986 * on newer versions of the Tornado chips such as those 987 * on the 3c905CX and newer 3c908C cards. We wait an 988 * extra amount of time so that xl_wait() doesn't complain 989 * and annoy the users. 990 */ 991 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 992 DELAY(100000); 993 xl_wait(sc); 994 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 995 xl_wait(sc); 996 997 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 998 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 999 XL_SEL_WIN(2); 1000 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1001 XL_W2_RESET_OPTIONS) 1002 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1003 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1004 ); 1005 } 1006 1007 /* Wait a little while for the chip to get its brains in order. */ 1008 DELAY(100000); 1009 return; 1010 } 1011 1012 /* 1013 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1014 * IDs against our list and return a device name if we find a match. 1015 */ 1016 static int 1017 xl_probe(device_t dev) 1018 { 1019 struct xl_type *t; 1020 uint16_t vid, did; 1021 1022 vid = pci_get_vendor(dev); 1023 did = pci_get_device(dev); 1024 for (t = xl_devs; t->xl_name != NULL; t++) { 1025 if (vid == t->xl_vid && did == t->xl_did) { 1026 device_set_desc(dev, t->xl_name); 1027 return(0); 1028 } 1029 } 1030 return(ENXIO); 1031 } 1032 1033 /* 1034 * This routine is a kludge to work around possible hardware faults 1035 * or manufacturing defects that can cause the media options register 1036 * (or reset options register, as it's called for the first generation 1037 * 3c90x adapters) to return an incorrect result. I have encountered 1038 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1039 * which doesn't have any of the 'mediaopt' bits set. This screws up 1040 * the attach routine pretty badly because it doesn't know what media 1041 * to look for. If we find ourselves in this predicament, this routine 1042 * will try to guess the media options values and warn the user of a 1043 * possible manufacturing defect with his adapter/system/whatever. 1044 */ 1045 static void 1046 xl_mediacheck(struct xl_softc *sc) 1047 { 1048 struct ifnet *ifp = &sc->arpcom.ac_if; 1049 1050 /* 1051 * If some of the media options bits are set, assume they are 1052 * correct. If not, try to figure it out down below. 1053 * XXX I should check for 10baseFL, but I don't have an adapter 1054 * to test with. 1055 */ 1056 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1057 /* 1058 * Check the XCVR value. If it's not in the normal range 1059 * of values, we need to fake it up here. 1060 */ 1061 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1062 return; 1063 else { 1064 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n", 1065 sc->xl_xcvr); 1066 if_printf(ifp, 1067 "choosing new default based on card type\n"); 1068 } 1069 } else { 1070 if (sc->xl_type == XL_TYPE_905B && 1071 sc->xl_media & XL_MEDIAOPT_10FL) 1072 return; 1073 if_printf(ifp, "WARNING: no media options bits set in " 1074 "the media options register!!\n"); 1075 if_printf(ifp, "this could be a manufacturing defect in " 1076 "your adapter or system\n"); 1077 if_printf(ifp, "attempting to guess media type; you " 1078 "should probably consult your vendor\n"); 1079 } 1080 1081 xl_choose_xcvr(sc, 1); 1082 } 1083 1084 static void 1085 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1086 { 1087 struct ifnet *ifp = &sc->arpcom.ac_if; 1088 u_int16_t devid; 1089 1090 /* 1091 * Read the device ID from the EEPROM. 1092 * This is what's loaded into the PCI device ID register, so it has 1093 * to be correct otherwise we wouldn't have gotten this far. 1094 */ 1095 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1096 1097 switch(devid) { 1098 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1099 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1100 sc->xl_media = XL_MEDIAOPT_BT; 1101 sc->xl_xcvr = XL_XCVR_10BT; 1102 if (verbose) 1103 if_printf(ifp, "guessing 10BaseT transceiver\n"); 1104 break; 1105 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1106 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1107 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1108 sc->xl_xcvr = XL_XCVR_10BT; 1109 if (verbose) 1110 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n"); 1111 break; 1112 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1113 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1114 sc->xl_xcvr = XL_XCVR_10BT; 1115 if (verbose) 1116 if_printf(ifp, "guessing TPC (BNC/TP)\n"); 1117 break; 1118 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1119 sc->xl_media = XL_MEDIAOPT_10FL; 1120 sc->xl_xcvr = XL_XCVR_AUI; 1121 if (verbose) 1122 if_printf(ifp, "guessing 10baseFL\n"); 1123 break; 1124 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1125 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1126 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1127 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1128 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1129 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1130 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1131 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1132 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1133 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1134 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1135 sc->xl_media = XL_MEDIAOPT_MII; 1136 sc->xl_xcvr = XL_XCVR_MII; 1137 if (verbose) 1138 if_printf(ifp, "guessing MII\n"); 1139 break; 1140 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1141 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1142 sc->xl_media = XL_MEDIAOPT_BT4; 1143 sc->xl_xcvr = XL_XCVR_MII; 1144 if (verbose) 1145 if_printf(ifp, "guessing 100BaseT4/MII\n"); 1146 break; 1147 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1148 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1149 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1150 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1151 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1152 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1153 sc->xl_media = XL_MEDIAOPT_BTX; 1154 sc->xl_xcvr = XL_XCVR_AUTO; 1155 if (verbose) 1156 if_printf(ifp, "guessing 10/100 internal\n"); 1157 break; 1158 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1159 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1160 sc->xl_xcvr = XL_XCVR_AUTO; 1161 if (verbose) 1162 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n"); 1163 break; 1164 default: 1165 if_printf(ifp, 1166 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1167 sc->xl_media = XL_MEDIAOPT_BT; 1168 break; 1169 } 1170 1171 return; 1172 } 1173 1174 /* 1175 * Attach the interface. Allocate softc structures, do ifmedia 1176 * setup and ethernet/BPF attach. 1177 */ 1178 static int 1179 xl_attach(device_t dev) 1180 { 1181 u_char eaddr[ETHER_ADDR_LEN]; 1182 u_int16_t xcvr[2]; 1183 struct xl_softc *sc; 1184 struct ifnet *ifp; 1185 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1186 int error = 0, rid, res; 1187 uint16_t did; 1188 1189 sc = device_get_softc(dev); 1190 1191 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1192 1193 did = pci_get_device(dev); 1194 1195 sc->xl_flags = 0; 1196 if (did == TC_DEVICEID_HURRICANE_555) 1197 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1198 if (did == TC_DEVICEID_HURRICANE_556 || 1199 did == TC_DEVICEID_HURRICANE_556B) 1200 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1201 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1202 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1203 if (did == TC_DEVICEID_HURRICANE_555 || 1204 did == TC_DEVICEID_HURRICANE_556) 1205 sc->xl_flags |= XL_FLAG_8BITROM; 1206 if (did == TC_DEVICEID_HURRICANE_556B) 1207 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1208 if (did == TC_DEVICEID_HURRICANE_575B || 1209 did == TC_DEVICEID_HURRICANE_575C || 1210 did == TC_DEVICEID_HURRICANE_656B || 1211 did == TC_DEVICEID_TORNADO_656C) 1212 sc->xl_flags |= XL_FLAG_FUNCREG; 1213 if (did == TC_DEVICEID_HURRICANE_575A || 1214 did == TC_DEVICEID_HURRICANE_575B || 1215 did == TC_DEVICEID_HURRICANE_575C || 1216 did == TC_DEVICEID_HURRICANE_656B || 1217 did == TC_DEVICEID_TORNADO_656C) 1218 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1219 XL_FLAG_8BITROM; 1220 if (did == TC_DEVICEID_HURRICANE_656) 1221 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1222 if (did == TC_DEVICEID_HURRICANE_575B) 1223 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1224 if (did == TC_DEVICEID_HURRICANE_575C) 1225 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1226 if (did == TC_DEVICEID_TORNADO_656C) 1227 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1228 if (did == TC_DEVICEID_HURRICANE_656 || 1229 did == TC_DEVICEID_HURRICANE_656B) 1230 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1231 XL_FLAG_INVERT_LED_PWR; 1232 if (did == TC_DEVICEID_TORNADO_10_100BT_920B) 1233 sc->xl_flags |= XL_FLAG_PHYOK; 1234 #ifndef BURN_BRIDGES 1235 /* 1236 * If this is a 3c905B, we have to check one extra thing. 1237 * The 905B supports power management and may be placed in 1238 * a low-power mode (D3 mode), typically by certain operating 1239 * systems which shall not be named. The PCI BIOS is supposed 1240 * to reset the NIC and bring it out of low-power mode, but 1241 * some do not. Consequently, we have to see if this chip 1242 * supports power management, and if so, make sure it's not 1243 * in low-power mode. If power management is available, the 1244 * capid byte will be 0x01. 1245 * 1246 * I _think_ that what actually happens is that the chip 1247 * loses its PCI configuration during the transition from 1248 * D3 back to D0; this means that it should be possible for 1249 * us to save the PCI iobase, membase and IRQ, put the chip 1250 * back in the D0 state, then restore the PCI config ourselves. 1251 */ 1252 1253 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1254 u_int32_t iobase, membase, irq; 1255 1256 /* Save important PCI config data. */ 1257 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1258 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1259 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1260 1261 /* Reset the power state. */ 1262 device_printf(dev, "chip is in D%d power mode " 1263 "-- setting to D0\n", pci_get_powerstate(dev)); 1264 1265 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1266 1267 /* Restore PCI config data. */ 1268 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1269 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1270 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1271 } 1272 #endif 1273 /* 1274 * Map control/status registers. 1275 */ 1276 pci_enable_busmaster(dev); 1277 1278 rid = XL_PCI_LOMEM; 1279 res = SYS_RES_MEMORY; 1280 1281 #if 0 1282 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1283 #endif 1284 1285 if (sc->xl_res != NULL) { 1286 sc->xl_flags |= XL_FLAG_USE_MMIO; 1287 if (bootverbose) 1288 device_printf(dev, "using memory mapped I/O\n"); 1289 } else { 1290 rid = XL_PCI_LOIO; 1291 res = SYS_RES_IOPORT; 1292 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1293 if (sc->xl_res == NULL) { 1294 device_printf(dev, "couldn't map ports/memory\n"); 1295 error = ENXIO; 1296 goto fail; 1297 } 1298 if (bootverbose) 1299 device_printf(dev, "using port I/O\n"); 1300 } 1301 1302 sc->xl_btag = rman_get_bustag(sc->xl_res); 1303 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1304 1305 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1306 rid = XL_PCI_FUNCMEM; 1307 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1308 RF_ACTIVE); 1309 1310 if (sc->xl_fres == NULL) { 1311 device_printf(dev, "couldn't map funcreg memory\n"); 1312 error = ENXIO; 1313 goto fail; 1314 } 1315 1316 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1317 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1318 } 1319 1320 /* Allocate interrupt */ 1321 rid = 0; 1322 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1323 RF_SHAREABLE | RF_ACTIVE); 1324 if (sc->xl_irq == NULL) { 1325 device_printf(dev, "couldn't map interrupt\n"); 1326 error = ENXIO; 1327 goto fail; 1328 } 1329 1330 ifp = &sc->arpcom.ac_if; 1331 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1332 1333 /* Reset the adapter. */ 1334 xl_reset(sc); 1335 1336 /* 1337 * Get station address from the EEPROM. 1338 */ 1339 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1340 device_printf(dev, "failed to read station address\n"); 1341 error = ENXIO; 1342 goto fail; 1343 } 1344 1345 callout_init(&sc->xl_stat_timer); 1346 1347 error = xl_dma_alloc(dev); 1348 if (error) 1349 goto fail; 1350 1351 /* 1352 * Figure out the card type. 3c905B adapters have the 1353 * 'supportsNoTxLength' bit set in the capabilities 1354 * word in the EEPROM. 1355 * Note: my 3c575C cardbus card lies. It returns a value 1356 * of 0x1578 for its capabilities word, which is somewhat 1357 * nonsensical. Another way to distinguish a 3c90x chip 1358 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1359 * bit. This will only be set for 3c90x boomerage chips. 1360 */ 1361 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1362 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1363 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1364 sc->xl_type = XL_TYPE_905B; 1365 else 1366 sc->xl_type = XL_TYPE_90X; 1367 if (bootverbose) { 1368 device_printf(dev, "type %s\n", 1369 sc->xl_type == XL_TYPE_905B ? "90XB" : "90X"); 1370 } 1371 1372 ifp->if_softc = sc; 1373 ifp->if_mtu = ETHERMTU; 1374 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1375 ifp->if_ioctl = xl_ioctl; 1376 if (sc->xl_type == XL_TYPE_905B) { 1377 ifp->if_start = xl_start_90xB; 1378 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_MTU; 1379 } else { 1380 ifp->if_start = xl_start; 1381 } 1382 ifp->if_watchdog = xl_watchdog; 1383 ifp->if_init = xl_init; 1384 #ifdef DEVICE_POLLING 1385 ifp->if_poll = xl_poll; 1386 #endif 1387 ifp->if_baudrate = 10000000; 1388 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1389 ifq_set_ready(&ifp->if_snd); 1390 /* 1391 * NOTE: Hardware checksum features disabled by default. 1392 * This seems to corrupt tx packet data one out of a 1393 * million packets or so and then generates a good checksum 1394 * so the receiver doesn't know the packet is bad 1395 */ 1396 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1397 if (ifp->if_capenable & IFCAP_TXCSUM) 1398 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1399 1400 /* 1401 * Now we have to see what sort of media we have. 1402 * This includes probing for an MII interace and a 1403 * possible PHY. 1404 */ 1405 XL_SEL_WIN(3); 1406 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1407 if (bootverbose) 1408 if_printf(ifp, "media options word: %x\n", sc->xl_media); 1409 1410 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1411 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1412 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1413 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1414 1415 xl_mediacheck(sc); 1416 1417 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1418 || sc->xl_media & XL_MEDIAOPT_BT4) { 1419 if (bootverbose) 1420 if_printf(ifp, "found MII/AUTO\n"); 1421 xl_setcfg(sc); 1422 1423 error = mii_phy_probe(dev, &sc->xl_miibus, 1424 xl_ifmedia_upd, xl_ifmedia_sts); 1425 if (error) { 1426 if_printf(ifp, "no PHY found!\n"); 1427 goto fail; 1428 } 1429 1430 goto done; 1431 } 1432 1433 /* 1434 * Sanity check. If the user has selected "auto" and this isn't 1435 * a 10/100 card of some kind, we need to force the transceiver 1436 * type to something sane. 1437 */ 1438 if (sc->xl_xcvr == XL_XCVR_AUTO) 1439 xl_choose_xcvr(sc, bootverbose); 1440 1441 /* 1442 * Do ifmedia setup. 1443 */ 1444 if (sc->xl_media & XL_MEDIAOPT_BT) { 1445 if (bootverbose) 1446 if_printf(ifp, "found 10baseT\n"); 1447 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1448 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1449 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1450 ifmedia_add(&sc->ifmedia, 1451 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1452 } 1453 1454 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1455 /* 1456 * Check for a 10baseFL board in disguise. 1457 */ 1458 if (sc->xl_type == XL_TYPE_905B && 1459 sc->xl_media == XL_MEDIAOPT_10FL) { 1460 if (bootverbose) 1461 if_printf(ifp, "found 10baseFL\n"); 1462 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1463 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1464 0, NULL); 1465 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1466 ifmedia_add(&sc->ifmedia, 1467 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1468 } else { 1469 if (bootverbose) 1470 if_printf(ifp, "found AUI\n"); 1471 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1472 } 1473 } 1474 1475 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1476 if (bootverbose) 1477 if_printf(ifp, "found BNC\n"); 1478 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1479 } 1480 1481 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1482 if (bootverbose) 1483 if_printf(ifp, "found 100baseFX\n"); 1484 ifp->if_baudrate = 100000000; 1485 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1486 } 1487 1488 /* Choose a default media. */ 1489 switch(sc->xl_xcvr) { 1490 case XL_XCVR_10BT: 1491 media = IFM_ETHER|IFM_10_T; 1492 xl_setmode(sc, media); 1493 break; 1494 case XL_XCVR_AUI: 1495 if (sc->xl_type == XL_TYPE_905B && 1496 sc->xl_media == XL_MEDIAOPT_10FL) { 1497 media = IFM_ETHER|IFM_10_FL; 1498 xl_setmode(sc, media); 1499 } else { 1500 media = IFM_ETHER|IFM_10_5; 1501 xl_setmode(sc, media); 1502 } 1503 break; 1504 case XL_XCVR_COAX: 1505 media = IFM_ETHER|IFM_10_2; 1506 xl_setmode(sc, media); 1507 break; 1508 case XL_XCVR_AUTO: 1509 case XL_XCVR_100BTX: 1510 case XL_XCVR_MII: 1511 /* Chosen by miibus */ 1512 break; 1513 case XL_XCVR_100BFX: 1514 media = IFM_ETHER|IFM_100_FX; 1515 break; 1516 default: 1517 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr); 1518 /* 1519 * This will probably be wrong, but it prevents 1520 * the ifmedia code from panicking. 1521 */ 1522 media = IFM_ETHER|IFM_10_T; 1523 break; 1524 } 1525 1526 if (sc->xl_miibus == NULL) 1527 ifmedia_set(&sc->ifmedia, media); 1528 1529 done: 1530 1531 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1532 XL_SEL_WIN(0); 1533 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1534 } 1535 1536 /* 1537 * Call MI attach routine. 1538 */ 1539 ether_ifattach(ifp, eaddr, NULL); 1540 1541 /* 1542 * Tell the upper layer(s) we support long frames. 1543 */ 1544 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1545 1546 /* Hook interrupt last to avoid having to lock softc */ 1547 error = bus_setup_intr(dev, sc->xl_irq, INTR_MPSAFE, 1548 xl_intr, sc, &sc->xl_intrhand, 1549 ifp->if_serializer); 1550 if (error) { 1551 if_printf(ifp, "couldn't set up irq\n"); 1552 ether_ifdetach(ifp); 1553 goto fail; 1554 } 1555 1556 ifp->if_cpuid = rman_get_cpuid(sc->xl_irq); 1557 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 1558 1559 return 0; 1560 1561 fail: 1562 xl_detach(dev); 1563 return error; 1564 } 1565 1566 /* 1567 * Shutdown hardware and free up resources. This can be called any 1568 * time after the mutex has been initialized. It is called in both 1569 * the error case in attach and the normal detach case so it needs 1570 * to be careful about only freeing resources that have actually been 1571 * allocated. 1572 */ 1573 static int 1574 xl_detach(device_t dev) 1575 { 1576 struct xl_softc *sc; 1577 struct ifnet *ifp; 1578 int rid, res; 1579 1580 sc = device_get_softc(dev); 1581 ifp = &sc->arpcom.ac_if; 1582 1583 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1584 rid = XL_PCI_LOMEM; 1585 res = SYS_RES_MEMORY; 1586 } else { 1587 rid = XL_PCI_LOIO; 1588 res = SYS_RES_IOPORT; 1589 } 1590 1591 if (device_is_attached(dev)) { 1592 lwkt_serialize_enter(ifp->if_serializer); 1593 xl_reset(sc); 1594 xl_stop(sc); 1595 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1596 lwkt_serialize_exit(ifp->if_serializer); 1597 1598 ether_ifdetach(ifp); 1599 } 1600 1601 if (sc->xl_miibus) 1602 device_delete_child(dev, sc->xl_miibus); 1603 bus_generic_detach(dev); 1604 ifmedia_removeall(&sc->ifmedia); 1605 1606 if (sc->xl_irq) 1607 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1608 if (sc->xl_fres != NULL) 1609 bus_release_resource(dev, SYS_RES_MEMORY, 1610 XL_PCI_FUNCMEM, sc->xl_fres); 1611 if (sc->xl_res) 1612 bus_release_resource(dev, res, rid, sc->xl_res); 1613 1614 xl_dma_free(dev); 1615 1616 return(0); 1617 } 1618 1619 static int 1620 xl_dma_alloc(device_t dev) 1621 { 1622 struct xl_softc *sc; 1623 struct xl_chain_data *cd; 1624 struct xl_list_data *ld; 1625 bus_dmamem_t dmem; 1626 int i, error; 1627 1628 sc = device_get_softc(dev); 1629 cd = &sc->xl_cdata; 1630 ld = &sc->xl_ldata; 1631 1632 /* 1633 * Allocate the parent bus DMA tag appropriate for PCI. 1634 */ 1635 error = bus_dma_tag_create(NULL, 1, 0, 1636 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1637 NULL, NULL, 1638 BUS_SPACE_MAXSIZE_32BIT, 0, 1639 BUS_SPACE_MAXSIZE_32BIT, 1640 0, &sc->xl_parent_tag); 1641 if (error) { 1642 device_printf(dev, "could not allocate parent dma tag\n"); 1643 return error; 1644 } 1645 1646 /* 1647 * Now allocate a tag for the DMA descriptor lists and a chunk 1648 * of DMA-able memory based on the tag. Also obtain the DMA 1649 * addresses of the RX and TX ring, which we'll need later. 1650 * All of our lists are allocated as a contiguous block 1651 * of memory. 1652 */ 1653 error = bus_dmamem_coherent(sc->xl_parent_tag, XL_LIST_ALIGN, 0, 1654 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1655 XL_RX_LIST_SZ, BUS_DMA_WAITOK, &dmem); 1656 if (error) { 1657 device_printf(dev, "failed to allocate rx list\n"); 1658 return error; 1659 } 1660 ld->xl_rx_tag = dmem.dmem_tag; 1661 ld->xl_rx_dmamap = dmem.dmem_map; 1662 ld->xl_rx_list = dmem.dmem_addr; 1663 ld->xl_rx_dmaaddr = dmem.dmem_busaddr; 1664 1665 error = bus_dmamem_coherent(sc->xl_parent_tag, XL_LIST_ALIGN, 0, 1666 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1667 XL_TX_LIST_SZ, BUS_DMA_WAITOK, &dmem); 1668 if (error) { 1669 device_printf(dev, "failed to allocate tx list\n"); 1670 return error; 1671 } 1672 ld->xl_tx_tag = dmem.dmem_tag; 1673 ld->xl_tx_dmamap = dmem.dmem_map; 1674 ld->xl_tx_list = dmem.dmem_addr; 1675 ld->xl_tx_dmaaddr = dmem.dmem_busaddr; 1676 1677 /* 1678 * Allocate a DMA tag for the mapping of mbufs. 1679 */ 1680 error = bus_dma_tag_create(sc->xl_parent_tag, 1, 0, 1681 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1682 NULL, NULL, 1683 MCLBYTES, 1, MCLBYTES, 1684 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1685 &sc->xl_rx_mtag); 1686 if (error) { 1687 device_printf(dev, "failed to allocate RX mbuf dma tag\n"); 1688 return error; 1689 } 1690 1691 /* 1692 * Allocate a spare DMA map for the RX ring. 1693 */ 1694 error = bus_dmamap_create(sc->xl_rx_mtag, BUS_DMA_WAITOK, 1695 &sc->xl_tmpmap); 1696 if (error) { 1697 device_printf(dev, "failed to create RX mbuf tmp dma map\n"); 1698 bus_dma_tag_destroy(sc->xl_rx_mtag); 1699 sc->xl_rx_mtag = NULL; 1700 return error; 1701 } 1702 1703 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1704 error = bus_dmamap_create(sc->xl_rx_mtag, BUS_DMA_WAITOK, 1705 &cd->xl_rx_chain[i].xl_map); 1706 if (error) { 1707 device_printf(dev, "failed to create %dth " 1708 "rx descriptor dma map!\n", i); 1709 return error; 1710 } 1711 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1712 } 1713 1714 error = bus_dma_tag_create(sc->xl_parent_tag, 1, 0, 1715 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1716 NULL, NULL, 1717 MCLBYTES, XL_MAXFRAGS, MCLBYTES, 1718 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 1719 &sc->xl_tx_mtag); 1720 if (error) { 1721 device_printf(dev, "failed to allocate TX mbuf dma tag\n"); 1722 return error; 1723 } 1724 1725 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1726 error = bus_dmamap_create(sc->xl_tx_mtag, BUS_DMA_WAITOK, 1727 &cd->xl_tx_chain[i].xl_map); 1728 if (error) { 1729 device_printf(dev, "failed to create %dth " 1730 "tx descriptor dma map!\n", i); 1731 return error; 1732 } 1733 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1734 } 1735 return 0; 1736 } 1737 1738 static void 1739 xl_dma_free(device_t dev) 1740 { 1741 struct xl_softc *sc; 1742 struct xl_chain_data *cd; 1743 struct xl_list_data *ld; 1744 int i; 1745 1746 sc = device_get_softc(dev); 1747 cd = &sc->xl_cdata; 1748 ld = &sc->xl_ldata; 1749 1750 for (i = 0; i < XL_RX_LIST_CNT; ++i) { 1751 if (cd->xl_rx_chain[i].xl_ptr != NULL) { 1752 if (cd->xl_rx_chain[i].xl_mbuf != NULL) { 1753 bus_dmamap_unload(sc->xl_rx_mtag, 1754 cd->xl_rx_chain[i].xl_map); 1755 m_freem(cd->xl_rx_chain[i].xl_mbuf); 1756 } 1757 bus_dmamap_destroy(sc->xl_rx_mtag, 1758 cd->xl_rx_chain[i].xl_map); 1759 } 1760 } 1761 1762 for (i = 0; i < XL_TX_LIST_CNT; ++i) { 1763 if (cd->xl_tx_chain[i].xl_ptr != NULL) { 1764 if (cd->xl_tx_chain[i].xl_mbuf != NULL) { 1765 bus_dmamap_unload(sc->xl_tx_mtag, 1766 cd->xl_tx_chain[i].xl_map); 1767 m_freem(cd->xl_tx_chain[i].xl_mbuf); 1768 } 1769 bus_dmamap_destroy(sc->xl_tx_mtag, 1770 cd->xl_tx_chain[i].xl_map); 1771 } 1772 } 1773 1774 if (ld->xl_rx_tag) { 1775 bus_dmamap_unload(ld->xl_rx_tag, ld->xl_rx_dmamap); 1776 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list, 1777 ld->xl_rx_dmamap); 1778 bus_dma_tag_destroy(ld->xl_rx_tag); 1779 } 1780 1781 if (ld->xl_tx_tag) { 1782 bus_dmamap_unload(ld->xl_tx_tag, ld->xl_tx_dmamap); 1783 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list, 1784 ld->xl_tx_dmamap); 1785 bus_dma_tag_destroy(ld->xl_tx_tag); 1786 } 1787 1788 if (sc->xl_rx_mtag) { 1789 bus_dmamap_destroy(sc->xl_rx_mtag, sc->xl_tmpmap); 1790 bus_dma_tag_destroy(sc->xl_rx_mtag); 1791 } 1792 if (sc->xl_tx_mtag) 1793 bus_dma_tag_destroy(sc->xl_tx_mtag); 1794 1795 if (sc->xl_parent_tag) 1796 bus_dma_tag_destroy(sc->xl_parent_tag); 1797 } 1798 1799 /* 1800 * Initialize the transmit descriptors. 1801 */ 1802 static void 1803 xl_list_tx_init(struct xl_softc *sc) 1804 { 1805 struct xl_chain_data *cd; 1806 struct xl_list_data *ld; 1807 int i; 1808 1809 cd = &sc->xl_cdata; 1810 ld = &sc->xl_ldata; 1811 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1812 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1813 i * sizeof(struct xl_list); 1814 if (i == (XL_TX_LIST_CNT - 1)) 1815 cd->xl_tx_chain[i].xl_next = NULL; 1816 else 1817 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1818 } 1819 1820 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1821 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1822 } 1823 1824 /* 1825 * Initialize the transmit descriptors. 1826 */ 1827 static void 1828 xl_list_tx_init_90xB(struct xl_softc *sc) 1829 { 1830 struct xl_chain_data *cd; 1831 struct xl_list_data *ld; 1832 int i; 1833 1834 cd = &sc->xl_cdata; 1835 ld = &sc->xl_ldata; 1836 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1837 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1838 i * sizeof(struct xl_list); 1839 if (i == (XL_TX_LIST_CNT - 1)) 1840 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1841 else 1842 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1843 if (i == 0) { 1844 cd->xl_tx_chain[i].xl_prev = 1845 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1846 } else { 1847 cd->xl_tx_chain[i].xl_prev = 1848 &cd->xl_tx_chain[i - 1]; 1849 } 1850 } 1851 1852 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1853 1854 cd->xl_tx_prod = 1; 1855 cd->xl_tx_cons = 1; 1856 cd->xl_tx_cnt = 0; 1857 } 1858 1859 /* 1860 * Initialize the RX descriptors and allocate mbufs for them. Note that 1861 * we arrange the descriptors in a closed ring, so that the last descriptor 1862 * points back to the first. 1863 */ 1864 static int 1865 xl_list_rx_init(struct xl_softc *sc) 1866 { 1867 struct xl_chain_data *cd; 1868 struct xl_list_data *ld; 1869 int error, i, next; 1870 u_int32_t nextptr; 1871 1872 cd = &sc->xl_cdata; 1873 ld = &sc->xl_ldata; 1874 1875 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1876 error = xl_newbuf(sc, &cd->xl_rx_chain[i], 1); 1877 if (error) 1878 return(error); 1879 if (i == (XL_RX_LIST_CNT - 1)) 1880 next = 0; 1881 else 1882 next = i + 1; 1883 nextptr = ld->xl_rx_dmaaddr + 1884 next * sizeof(struct xl_list_onefrag); 1885 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1886 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1887 } 1888 1889 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1890 1891 return(0); 1892 } 1893 1894 /* 1895 * Initialize an RX descriptor and attach an MBUF cluster. 1896 * If we fail to do so, we need to leave the old mbuf and 1897 * the old DMA map untouched so that it can be reused. 1898 */ 1899 static int 1900 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c, int init) 1901 { 1902 struct mbuf *m_new; 1903 bus_dmamap_t map; 1904 int error, nsegs; 1905 bus_dma_segment_t seg; 1906 1907 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1908 if (m_new == NULL) 1909 return(ENOBUFS); 1910 1911 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1912 1913 /* Force longword alignment for packet payload. */ 1914 m_adj(m_new, ETHER_ALIGN); 1915 1916 error = bus_dmamap_load_mbuf_segment(sc->xl_rx_mtag, sc->xl_tmpmap, 1917 m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT); 1918 if (error) { 1919 m_freem(m_new); 1920 if (init) { 1921 if_printf(&sc->arpcom.ac_if, 1922 "can't map mbuf (error %d)\n", error); 1923 } 1924 return(error); 1925 } 1926 1927 if (c->xl_mbuf != NULL) { 1928 bus_dmamap_sync(sc->xl_rx_mtag, c->xl_map, 1929 BUS_DMASYNC_POSTREAD); 1930 bus_dmamap_unload(sc->xl_rx_mtag, c->xl_map); 1931 } 1932 1933 map = c->xl_map; 1934 c->xl_map = sc->xl_tmpmap; 1935 sc->xl_tmpmap = map; 1936 c->xl_mbuf = m_new; 1937 1938 c->xl_ptr->xl_frag.xl_len = htole32(seg.ds_len | XL_LAST_FRAG); 1939 c->xl_ptr->xl_frag.xl_addr = htole32(seg.ds_addr); 1940 c->xl_ptr->xl_status = 0; 1941 1942 return(0); 1943 } 1944 1945 static int 1946 xl_rx_resync(struct xl_softc *sc) 1947 { 1948 struct xl_chain_onefrag *pos; 1949 int i; 1950 1951 pos = sc->xl_cdata.xl_rx_head; 1952 1953 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1954 if (pos->xl_ptr->xl_status) 1955 break; 1956 pos = pos->xl_next; 1957 } 1958 1959 if (i == XL_RX_LIST_CNT) 1960 return(0); 1961 1962 sc->xl_cdata.xl_rx_head = pos; 1963 1964 return(EAGAIN); 1965 } 1966 1967 /* 1968 * A frame has been uploaded: pass the resulting mbuf chain up to 1969 * the higher level protocols. 1970 */ 1971 static void 1972 xl_rxeof(struct xl_softc *sc, int count) 1973 { 1974 struct mbuf *m; 1975 struct ifnet *ifp; 1976 struct xl_chain_onefrag *cur_rx; 1977 int total_len = 0; 1978 u_int32_t rxstat; 1979 1980 ifp = &sc->arpcom.ac_if; 1981 again: 1982 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1983 #ifdef DEVICE_POLLING 1984 if (count >= 0 && count-- == 0) 1985 break; 1986 #endif 1987 cur_rx = sc->xl_cdata.xl_rx_head; 1988 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1989 total_len = rxstat & XL_RXSTAT_LENMASK; 1990 1991 /* 1992 * Since we have told the chip to allow large frames, 1993 * we need to trap giant frame errors in software. We allow 1994 * a little more than the normal frame size to account for 1995 * frames with VLAN tags. 1996 */ 1997 if (total_len > XL_MAX_FRAMELEN) 1998 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1999 2000 /* 2001 * If an error occurs, update stats, clear the 2002 * status word and leave the mbuf cluster in place: 2003 * it should simply get re-used next time this descriptor 2004 * comes up in the ring. 2005 */ 2006 if (rxstat & XL_RXSTAT_UP_ERROR) { 2007 ifp->if_ierrors++; 2008 cur_rx->xl_ptr->xl_status = 0; 2009 continue; 2010 } 2011 2012 /* 2013 * If the error bit was not set, the upload complete 2014 * bit should be set which means we have a valid packet. 2015 * If not, something truly strange has happened. 2016 */ 2017 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2018 if_printf(ifp, 2019 "bad receive status -- packet dropped\n"); 2020 ifp->if_ierrors++; 2021 cur_rx->xl_ptr->xl_status = 0; 2022 continue; 2023 } 2024 2025 /* No errors; receive the packet. */ 2026 m = cur_rx->xl_mbuf; 2027 2028 /* 2029 * Try to conjure up a new mbuf cluster. If that 2030 * fails, it means we have an out of memory condition and 2031 * should leave the buffer in place and continue. This will 2032 * result in a lost packet, but there's little else we 2033 * can do in this situation. 2034 */ 2035 if (xl_newbuf(sc, cur_rx, 0)) { 2036 ifp->if_ierrors++; 2037 cur_rx->xl_ptr->xl_status = 0; 2038 continue; 2039 } 2040 2041 ifp->if_ipackets++; 2042 m->m_pkthdr.rcvif = ifp; 2043 m->m_pkthdr.len = m->m_len = total_len; 2044 2045 if (ifp->if_capenable & IFCAP_RXCSUM) { 2046 /* Do IP checksum checking. */ 2047 if (rxstat & XL_RXSTAT_IPCKOK) 2048 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2049 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2050 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2051 if ((rxstat & XL_RXSTAT_TCPCOK && 2052 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2053 (rxstat & XL_RXSTAT_UDPCKOK && 2054 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2055 m->m_pkthdr.csum_flags |= 2056 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 2057 CSUM_FRAG_NOT_CHECKED; 2058 m->m_pkthdr.csum_data = 0xffff; 2059 } 2060 } 2061 2062 ifp->if_input(ifp, m); 2063 } 2064 2065 if (sc->xl_type != XL_TYPE_905B) { 2066 /* 2067 * Handle the 'end of channel' condition. When the upload 2068 * engine hits the end of the RX ring, it will stall. This 2069 * is our cue to flush the RX ring, reload the uplist pointer 2070 * register and unstall the engine. 2071 * XXX This is actually a little goofy. With the ThunderLAN 2072 * chip, you get an interrupt when the receiver hits the end 2073 * of the receive ring, which tells you exactly when you 2074 * you need to reload the ring pointer. Here we have to 2075 * fake it. I'm mad at myself for not being clever enough 2076 * to avoid the use of a goto here. 2077 */ 2078 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2079 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2080 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2081 xl_wait(sc); 2082 CSR_WRITE_4(sc, XL_UPLIST_PTR, 2083 sc->xl_ldata.xl_rx_dmaaddr); 2084 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2085 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2086 goto again; 2087 } 2088 } 2089 } 2090 2091 /* 2092 * A frame was downloaded to the chip. It's safe for us to clean up 2093 * the list buffers. 2094 */ 2095 static void 2096 xl_txeof(struct xl_softc *sc) 2097 { 2098 struct xl_chain *cur_tx; 2099 struct ifnet *ifp; 2100 2101 ifp = &sc->arpcom.ac_if; 2102 2103 /* Clear the timeout timer. */ 2104 ifp->if_timer = 0; 2105 2106 /* 2107 * Go through our tx list and free mbufs for those 2108 * frames that have been uploaded. Note: the 3c905B 2109 * sets a special bit in the status word to let us 2110 * know that a frame has been downloaded, but the 2111 * original 3c900/3c905 adapters don't do that. 2112 * Consequently, we have to use a different test if 2113 * xl_type != XL_TYPE_905B. 2114 */ 2115 while(sc->xl_cdata.xl_tx_head != NULL) { 2116 cur_tx = sc->xl_cdata.xl_tx_head; 2117 2118 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2119 break; 2120 2121 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2122 bus_dmamap_unload(sc->xl_tx_mtag, cur_tx->xl_map); 2123 m_freem(cur_tx->xl_mbuf); 2124 cur_tx->xl_mbuf = NULL; 2125 ifp->if_opackets++; 2126 2127 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2128 sc->xl_cdata.xl_tx_free = cur_tx; 2129 } 2130 2131 if (sc->xl_cdata.xl_tx_head == NULL) { 2132 ifp->if_flags &= ~IFF_OACTIVE; 2133 sc->xl_cdata.xl_tx_tail = NULL; 2134 } else { 2135 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2136 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2137 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2138 sc->xl_cdata.xl_tx_head->xl_phys); 2139 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2140 } 2141 } 2142 2143 return; 2144 } 2145 2146 static void 2147 xl_txeof_90xB(struct xl_softc *sc) 2148 { 2149 struct xl_chain *cur_tx = NULL; 2150 struct ifnet *ifp; 2151 int idx; 2152 2153 ifp = &sc->arpcom.ac_if; 2154 2155 idx = sc->xl_cdata.xl_tx_cons; 2156 while(idx != sc->xl_cdata.xl_tx_prod) { 2157 2158 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2159 2160 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2161 XL_TXSTAT_DL_COMPLETE)) 2162 break; 2163 2164 if (cur_tx->xl_mbuf != NULL) { 2165 bus_dmamap_unload(sc->xl_tx_mtag, cur_tx->xl_map); 2166 m_freem(cur_tx->xl_mbuf); 2167 cur_tx->xl_mbuf = NULL; 2168 } 2169 2170 ifp->if_opackets++; 2171 2172 sc->xl_cdata.xl_tx_cnt--; 2173 XL_INC(idx, XL_TX_LIST_CNT); 2174 ifp->if_timer = 0; 2175 } 2176 2177 sc->xl_cdata.xl_tx_cons = idx; 2178 2179 if (cur_tx != NULL) 2180 ifp->if_flags &= ~IFF_OACTIVE; 2181 2182 return; 2183 } 2184 2185 /* 2186 * TX 'end of channel' interrupt handler. Actually, we should 2187 * only get a 'TX complete' interrupt if there's a transmit error, 2188 * so this is really TX error handler. 2189 */ 2190 static void 2191 xl_txeoc(struct xl_softc *sc) 2192 { 2193 struct ifnet *ifp = &sc->arpcom.ac_if; 2194 u_int8_t txstat; 2195 2196 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2197 if (txstat & XL_TXSTATUS_UNDERRUN || 2198 txstat & XL_TXSTATUS_JABBER || 2199 txstat & XL_TXSTATUS_RECLAIM) { 2200 if_printf(ifp, "transmission error: %x\n", txstat); 2201 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2202 xl_wait(sc); 2203 if (sc->xl_type == XL_TYPE_905B) { 2204 if (sc->xl_cdata.xl_tx_cnt) { 2205 int i; 2206 struct xl_chain *c; 2207 i = sc->xl_cdata.xl_tx_cons; 2208 c = &sc->xl_cdata.xl_tx_chain[i]; 2209 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2210 c->xl_phys); 2211 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2212 } 2213 } else { 2214 if (sc->xl_cdata.xl_tx_head != NULL) 2215 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2216 sc->xl_cdata.xl_tx_head->xl_phys); 2217 } 2218 /* 2219 * Remember to set this for the 2220 * first generation 3c90X chips. 2221 */ 2222 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2223 if (txstat & XL_TXSTATUS_UNDERRUN && 2224 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2225 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2226 if_printf(ifp, "tx underrun, increasing tx start" 2227 " threshold to %d bytes\n", 2228 sc->xl_tx_thresh); 2229 } 2230 CSR_WRITE_2(sc, XL_COMMAND, 2231 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2232 if (sc->xl_type == XL_TYPE_905B) { 2233 CSR_WRITE_2(sc, XL_COMMAND, 2234 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2235 } 2236 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2237 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2238 } else { 2239 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2240 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2241 } 2242 /* 2243 * Write an arbitrary byte to the TX_STATUS register 2244 * to clear this interrupt/error and advance to the next. 2245 */ 2246 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2247 } 2248 2249 return; 2250 } 2251 2252 #ifdef DEVICE_POLLING 2253 2254 static void 2255 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2256 { 2257 struct xl_softc *sc = ifp->if_softc; 2258 2259 ASSERT_SERIALIZED(ifp->if_serializer); 2260 2261 switch (cmd) { 2262 case POLL_REGISTER: 2263 xl_enable_intrs(sc, 0); 2264 if (sc->xl_type != XL_TYPE_905B) 2265 ifp->if_start = xl_start_poll; 2266 break; 2267 case POLL_DEREGISTER: 2268 if (sc->xl_type != XL_TYPE_905B) 2269 ifp->if_start = xl_start; 2270 xl_enable_intrs(sc, XL_INTRS); 2271 break; 2272 case POLL_ONLY: 2273 case POLL_AND_CHECK_STATUS: 2274 xl_rxeof(sc, count); 2275 if (sc->xl_type == XL_TYPE_905B) 2276 xl_txeof_90xB(sc); 2277 else 2278 xl_txeof(sc); 2279 2280 if (!ifq_is_empty(&ifp->if_snd)) 2281 if_devstart(ifp); 2282 2283 if (cmd == POLL_AND_CHECK_STATUS) { 2284 uint16_t status; 2285 2286 /* XXX copy & pasted from xl_intr() */ 2287 status = CSR_READ_2(sc, XL_STATUS); 2288 if ((status & XL_INTRS) && status != 0xFFFF) { 2289 CSR_WRITE_2(sc, XL_COMMAND, 2290 XL_CMD_INTR_ACK | (status & XL_INTRS)); 2291 2292 if (status & XL_STAT_TX_COMPLETE) { 2293 ifp->if_oerrors++; 2294 xl_txeoc(sc); 2295 } 2296 2297 if (status & XL_STAT_ADFAIL) { 2298 xl_reset(sc); 2299 xl_init(sc); 2300 } 2301 2302 if (status & XL_STAT_STATSOFLOW) { 2303 sc->xl_stats_no_timeout = 1; 2304 xl_stats_update_serialized(sc); 2305 sc->xl_stats_no_timeout = 0; 2306 } 2307 } 2308 } 2309 break; 2310 } 2311 } 2312 2313 #endif /* DEVICE_POLLING */ 2314 2315 static void 2316 xl_intr(void *arg) 2317 { 2318 struct xl_softc *sc; 2319 struct ifnet *ifp; 2320 u_int16_t status; 2321 2322 sc = arg; 2323 ifp = &sc->arpcom.ac_if; 2324 2325 ASSERT_SERIALIZED(ifp->if_serializer); 2326 2327 while(((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) && 2328 status != 0xFFFF) { 2329 2330 CSR_WRITE_2(sc, XL_COMMAND, 2331 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2332 2333 if (status & XL_STAT_UP_COMPLETE) { 2334 int curpkts; 2335 2336 curpkts = ifp->if_ipackets; 2337 xl_rxeof(sc, -1); 2338 if (curpkts == ifp->if_ipackets) { 2339 while (xl_rx_resync(sc)) 2340 xl_rxeof(sc, -1); 2341 } 2342 } 2343 2344 if (status & XL_STAT_DOWN_COMPLETE) { 2345 if (sc->xl_type == XL_TYPE_905B) 2346 xl_txeof_90xB(sc); 2347 else 2348 xl_txeof(sc); 2349 } 2350 2351 if (status & XL_STAT_TX_COMPLETE) { 2352 ifp->if_oerrors++; 2353 xl_txeoc(sc); 2354 } 2355 2356 if (status & XL_STAT_ADFAIL) { 2357 xl_reset(sc); 2358 xl_init(sc); 2359 } 2360 2361 if (status & XL_STAT_STATSOFLOW) { 2362 sc->xl_stats_no_timeout = 1; 2363 xl_stats_update_serialized(sc); 2364 sc->xl_stats_no_timeout = 0; 2365 } 2366 } 2367 2368 if (!ifq_is_empty(&ifp->if_snd)) 2369 if_devstart(ifp); 2370 } 2371 2372 static void 2373 xl_stats_update(void *xsc) 2374 { 2375 struct xl_softc *sc = xsc; 2376 2377 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2378 xl_stats_update_serialized(xsc); 2379 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2380 } 2381 2382 static void 2383 xl_stats_update_serialized(void *xsc) 2384 { 2385 struct xl_softc *sc; 2386 struct ifnet *ifp; 2387 struct xl_stats xl_stats; 2388 u_int8_t *p; 2389 int i; 2390 struct mii_data *mii = NULL; 2391 2392 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2393 2394 sc = xsc; 2395 ifp = &sc->arpcom.ac_if; 2396 if (sc->xl_miibus != NULL) 2397 mii = device_get_softc(sc->xl_miibus); 2398 2399 p = (u_int8_t *)&xl_stats; 2400 2401 /* Read all the stats registers. */ 2402 XL_SEL_WIN(6); 2403 2404 for (i = 0; i < 16; i++) 2405 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2406 2407 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2408 2409 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2410 xl_stats.xl_tx_single_collision + 2411 xl_stats.xl_tx_late_collision; 2412 2413 /* 2414 * Boomerang and cyclone chips have an extra stats counter 2415 * in window 4 (BadSSD). We have to read this too in order 2416 * to clear out all the stats registers and avoid a statsoflow 2417 * interrupt. 2418 */ 2419 XL_SEL_WIN(4); 2420 CSR_READ_1(sc, XL_W4_BADSSD); 2421 2422 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2423 mii_tick(mii); 2424 2425 XL_SEL_WIN(7); 2426 2427 if (!sc->xl_stats_no_timeout) 2428 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2429 2430 return; 2431 } 2432 2433 /* 2434 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2435 * pointers to the fragment pointers. 2436 */ 2437 static int 2438 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head) 2439 { 2440 int error, nsegs, i; 2441 u_int32_t status; 2442 bus_dma_segment_t segs[XL_MAXFRAGS]; 2443 struct xl_list *l; 2444 2445 error = bus_dmamap_load_mbuf_defrag(sc->xl_tx_mtag, c->xl_map, &m_head, 2446 segs, XL_MAXFRAGS, &nsegs, BUS_DMA_NOWAIT); 2447 if (error) { 2448 m_freem(m_head); 2449 return error; 2450 } 2451 bus_dmamap_sync(sc->xl_tx_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2452 2453 if (sc->xl_type == XL_TYPE_905B) { 2454 status = XL_TXSTAT_RND_DEFEAT; 2455 if (m_head->m_pkthdr.csum_flags) { 2456 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2457 status |= XL_TXSTAT_IPCKSUM; 2458 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2459 status |= XL_TXSTAT_TCPCKSUM; 2460 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2461 status |= XL_TXSTAT_UDPCKSUM; 2462 } 2463 } else { 2464 status = m_head->m_pkthdr.len; 2465 } 2466 2467 l = c->xl_ptr; 2468 for (i = 0; i < nsegs; i++) { 2469 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 2470 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 2471 } 2472 l->xl_frag[nsegs - 1].xl_len = 2473 htole32(segs[nsegs - 1].ds_len | XL_LAST_FRAG); 2474 l->xl_status = htole32(status); 2475 l->xl_next = 0; 2476 2477 c->xl_mbuf = m_head; 2478 2479 return(0); 2480 } 2481 2482 static void 2483 xl_start(struct ifnet *ifp) 2484 { 2485 ASSERT_SERIALIZED(ifp->if_serializer); 2486 xl_start_body(ifp, 1); 2487 } 2488 2489 #ifdef DEVICE_POLLING 2490 static void 2491 xl_start_poll(struct ifnet *ifp) 2492 { 2493 xl_start_body(ifp, 0); 2494 } 2495 #endif 2496 2497 /* 2498 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2499 * to the mbuf data regions directly in the transmit lists. We also save a 2500 * copy of the pointers since the transmit list fragment pointers are 2501 * physical addresses. 2502 */ 2503 static void 2504 xl_start_body(struct ifnet *ifp, int proc_rx) 2505 { 2506 struct xl_softc *sc; 2507 struct mbuf *m_head = NULL; 2508 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2509 struct xl_chain *prev_tx; 2510 u_int32_t status; 2511 int error; 2512 2513 sc = ifp->if_softc; 2514 /* 2515 * Check for an available queue slot. If there are none, 2516 * punt. 2517 */ 2518 if (sc->xl_cdata.xl_tx_free == NULL) { 2519 xl_txeoc(sc); 2520 xl_txeof(sc); 2521 if (sc->xl_cdata.xl_tx_free == NULL) { 2522 ifp->if_flags |= IFF_OACTIVE; 2523 return; 2524 } 2525 } 2526 2527 start_tx = sc->xl_cdata.xl_tx_free; 2528 2529 while(sc->xl_cdata.xl_tx_free != NULL) { 2530 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2531 if (m_head == NULL) 2532 break; 2533 2534 /* Pick a descriptor off the free list. */ 2535 prev_tx = cur_tx; 2536 cur_tx = sc->xl_cdata.xl_tx_free; 2537 2538 /* Pack the data into the descriptor. */ 2539 error = xl_encap(sc, cur_tx, m_head); 2540 if (error) { 2541 cur_tx = prev_tx; 2542 continue; 2543 } 2544 2545 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2546 cur_tx->xl_next = NULL; 2547 2548 /* Chain it together. */ 2549 if (prev != NULL) { 2550 prev->xl_next = cur_tx; 2551 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2552 } 2553 prev = cur_tx; 2554 2555 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2556 } 2557 2558 /* 2559 * If there are no packets queued, bail. 2560 */ 2561 if (cur_tx == NULL) 2562 return; 2563 2564 /* 2565 * Place the request for the upload interrupt 2566 * in the last descriptor in the chain. This way, if 2567 * we're chaining several packets at once, we'll only 2568 * get an interupt once for the whole chain rather than 2569 * once for each packet. 2570 */ 2571 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2572 XL_TXSTAT_DL_INTR); 2573 2574 /* 2575 * Queue the packets. If the TX channel is clear, update 2576 * the downlist pointer register. 2577 */ 2578 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2579 xl_wait(sc); 2580 2581 if (sc->xl_cdata.xl_tx_head != NULL) { 2582 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2583 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2584 htole32(start_tx->xl_phys); 2585 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2586 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2587 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2588 sc->xl_cdata.xl_tx_tail = cur_tx; 2589 } else { 2590 sc->xl_cdata.xl_tx_head = start_tx; 2591 sc->xl_cdata.xl_tx_tail = cur_tx; 2592 } 2593 2594 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2595 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2596 2597 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2598 2599 XL_SEL_WIN(7); 2600 2601 /* 2602 * Set a timeout in case the chip goes out to lunch. 2603 */ 2604 ifp->if_timer = 5; 2605 2606 if (proc_rx) { 2607 /* 2608 * XXX Under certain conditions, usually on slower machines 2609 * where interrupts may be dropped, it's possible for the 2610 * adapter to chew up all the buffers in the receive ring 2611 * and stall, without us being able to do anything about it. 2612 * To guard against this, we need to make a pass over the 2613 * RX queue to make sure there aren't any packets pending. 2614 * Doing it here means we can flush the receive ring at the 2615 * same time the chip is DMAing the transmit descriptors we 2616 * just gave it. 2617 * 2618 * 3Com goes to some lengths to emphasize the Parallel 2619 * Tasking (tm) nature of their chips in all their marketing 2620 * literature; we may as well take advantage of it. :) 2621 */ 2622 xl_rxeof(sc, -1); 2623 } 2624 } 2625 2626 static void 2627 xl_start_90xB(struct ifnet *ifp) 2628 { 2629 struct xl_softc *sc; 2630 struct mbuf *m_head = NULL; 2631 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2632 struct xl_chain *prev_tx; 2633 int error, idx; 2634 2635 ASSERT_SERIALIZED(ifp->if_serializer); 2636 2637 sc = ifp->if_softc; 2638 2639 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 2640 return; 2641 2642 idx = sc->xl_cdata.xl_tx_prod; 2643 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2644 2645 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2646 2647 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2648 ifp->if_flags |= IFF_OACTIVE; 2649 break; 2650 } 2651 2652 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2653 if (m_head == NULL) 2654 break; 2655 2656 prev_tx = cur_tx; 2657 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2658 2659 /* Pack the data into the descriptor. */ 2660 error = xl_encap(sc, cur_tx, m_head); 2661 if (error) { 2662 cur_tx = prev_tx; 2663 continue; 2664 } 2665 2666 /* Chain it together. */ 2667 if (prev != NULL) 2668 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2669 prev = cur_tx; 2670 2671 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2672 2673 XL_INC(idx, XL_TX_LIST_CNT); 2674 sc->xl_cdata.xl_tx_cnt++; 2675 } 2676 2677 /* 2678 * If there are no packets queued, bail. 2679 */ 2680 if (cur_tx == NULL) 2681 return; 2682 2683 /* 2684 * Place the request for the upload interrupt 2685 * in the last descriptor in the chain. This way, if 2686 * we're chaining several packets at once, we'll only 2687 * get an interupt once for the whole chain rather than 2688 * once for each packet. 2689 */ 2690 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2691 XL_TXSTAT_DL_INTR); 2692 2693 /* Start transmission */ 2694 sc->xl_cdata.xl_tx_prod = idx; 2695 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2696 2697 /* 2698 * Set a timeout in case the chip goes out to lunch. 2699 */ 2700 ifp->if_timer = 5; 2701 } 2702 2703 static void 2704 xl_init(void *xsc) 2705 { 2706 struct xl_softc *sc = xsc; 2707 struct ifnet *ifp = &sc->arpcom.ac_if; 2708 int error, i; 2709 u_int16_t rxfilt = 0; 2710 struct mii_data *mii = NULL; 2711 2712 ASSERT_SERIALIZED(ifp->if_serializer); 2713 2714 /* 2715 * Cancel pending I/O and free all RX/TX buffers. 2716 */ 2717 xl_stop(sc); 2718 2719 if (sc->xl_miibus == NULL) { 2720 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2721 xl_wait(sc); 2722 } 2723 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2724 xl_wait(sc); 2725 DELAY(10000); 2726 2727 if (sc->xl_miibus != NULL) 2728 mii = device_get_softc(sc->xl_miibus); 2729 2730 /* Init our MAC address */ 2731 XL_SEL_WIN(2); 2732 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2733 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2734 sc->arpcom.ac_enaddr[i]); 2735 } 2736 2737 /* Clear the station mask. */ 2738 for (i = 0; i < 3; i++) 2739 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2740 #ifdef notdef 2741 /* Reset TX and RX. */ 2742 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2743 xl_wait(sc); 2744 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2745 xl_wait(sc); 2746 #endif 2747 /* Init circular RX list. */ 2748 error = xl_list_rx_init(sc); 2749 if (error) { 2750 if_printf(ifp, "initialization of the rx ring failed (%d)\n", 2751 error); 2752 xl_stop(sc); 2753 return; 2754 } 2755 2756 /* Init TX descriptors. */ 2757 if (sc->xl_type == XL_TYPE_905B) 2758 xl_list_tx_init_90xB(sc); 2759 else 2760 xl_list_tx_init(sc); 2761 2762 /* 2763 * Set the TX freethresh value. 2764 * Note that this has no effect on 3c905B "cyclone" 2765 * cards but is required for 3c900/3c905 "boomerang" 2766 * cards in order to enable the download engine. 2767 */ 2768 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2769 2770 /* Set the TX start threshold for best performance. */ 2771 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2772 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2773 2774 /* 2775 * If this is a 3c905B, also set the tx reclaim threshold. 2776 * This helps cut down on the number of tx reclaim errors 2777 * that could happen on a busy network. The chip multiplies 2778 * the register value by 16 to obtain the actual threshold 2779 * in bytes, so we divide by 16 when setting the value here. 2780 * The existing threshold value can be examined by reading 2781 * the register at offset 9 in window 5. 2782 */ 2783 if (sc->xl_type == XL_TYPE_905B) { 2784 CSR_WRITE_2(sc, XL_COMMAND, 2785 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2786 } 2787 2788 /* Set RX filter bits. */ 2789 XL_SEL_WIN(5); 2790 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2791 2792 /* Set the individual bit to receive frames for this host only. */ 2793 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2794 2795 /* If we want promiscuous mode, set the allframes bit. */ 2796 if (ifp->if_flags & IFF_PROMISC) { 2797 rxfilt |= XL_RXFILTER_ALLFRAMES; 2798 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2799 } else { 2800 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2801 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2802 } 2803 2804 /* 2805 * Set capture broadcast bit to capture broadcast frames. 2806 */ 2807 if (ifp->if_flags & IFF_BROADCAST) { 2808 rxfilt |= XL_RXFILTER_BROADCAST; 2809 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2810 } else { 2811 rxfilt &= ~XL_RXFILTER_BROADCAST; 2812 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2813 } 2814 2815 /* 2816 * Program the multicast filter, if necessary. 2817 */ 2818 if (sc->xl_type == XL_TYPE_905B) 2819 xl_setmulti_hash(sc); 2820 else 2821 xl_setmulti(sc); 2822 2823 if (sc->xl_type == XL_TYPE_905B) { 2824 /* Set UP polling interval */ 2825 CSR_WRITE_1(sc, XL_UP_POLL, 64); 2826 } 2827 2828 /* 2829 * Load the address of the RX list. We have to 2830 * stall the upload engine before we can manipulate 2831 * the uplist pointer register, then unstall it when 2832 * we're finished. We also have to wait for the 2833 * stall command to complete before proceeding. 2834 * Note that we have to do this after any RX resets 2835 * have completed since the uplist register is cleared 2836 * by a reset. 2837 */ 2838 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2839 xl_wait(sc); 2840 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2841 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2842 xl_wait(sc); 2843 2844 if (sc->xl_type == XL_TYPE_905B) { 2845 /* Set DN polling interval */ 2846 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2847 2848 /* Load the address of the TX list */ 2849 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2850 xl_wait(sc); 2851 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2852 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2853 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2854 xl_wait(sc); 2855 } 2856 2857 /* 2858 * If the coax transceiver is on, make sure to enable 2859 * the DC-DC converter. 2860 */ 2861 XL_SEL_WIN(3); 2862 if (sc->xl_xcvr == XL_XCVR_COAX) 2863 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2864 else 2865 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2866 2867 /* 2868 * increase packet size to allow reception of 802.1q or ISL packets. 2869 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2870 * control register. For 3c90xB/C chips, use the RX packet size 2871 * register. 2872 */ 2873 2874 if (sc->xl_type == XL_TYPE_905B) { 2875 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2876 } else { 2877 u_int8_t macctl; 2878 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2879 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2880 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2881 } 2882 2883 /* Clear out the stats counters. */ 2884 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2885 sc->xl_stats_no_timeout = 1; 2886 xl_stats_update_serialized(sc); 2887 sc->xl_stats_no_timeout = 0; 2888 XL_SEL_WIN(4); 2889 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2890 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2891 2892 /* 2893 * Enable interrupts. 2894 */ 2895 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS); 2896 #ifdef DEVICE_POLLING 2897 /* Do not enable interrupt if polling(4) is enabled */ 2898 if ((ifp->if_flags & IFF_POLLING) != 0) 2899 xl_enable_intrs(sc, 0); 2900 else 2901 #endif 2902 xl_enable_intrs(sc, XL_INTRS); 2903 2904 /* Set the RX early threshold */ 2905 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2906 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2907 2908 /* Enable receiver and transmitter. */ 2909 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2910 xl_wait(sc); 2911 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2912 xl_wait(sc); 2913 2914 if (mii != NULL) 2915 mii_mediachg(mii); 2916 2917 /* Select window 7 for normal operations. */ 2918 XL_SEL_WIN(7); 2919 2920 ifp->if_flags |= IFF_RUNNING; 2921 ifp->if_flags &= ~IFF_OACTIVE; 2922 2923 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2924 } 2925 2926 /* 2927 * Set media options. 2928 */ 2929 static int 2930 xl_ifmedia_upd(struct ifnet *ifp) 2931 { 2932 struct xl_softc *sc; 2933 struct ifmedia *ifm = NULL; 2934 struct mii_data *mii = NULL; 2935 2936 ASSERT_SERIALIZED(ifp->if_serializer); 2937 2938 sc = ifp->if_softc; 2939 if (sc->xl_miibus != NULL) 2940 mii = device_get_softc(sc->xl_miibus); 2941 if (mii == NULL) 2942 ifm = &sc->ifmedia; 2943 else 2944 ifm = &mii->mii_media; 2945 2946 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2947 case IFM_100_FX: 2948 case IFM_10_FL: 2949 case IFM_10_2: 2950 case IFM_10_5: 2951 xl_setmode(sc, ifm->ifm_media); 2952 return(0); 2953 break; 2954 default: 2955 break; 2956 } 2957 2958 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 2959 || sc->xl_media & XL_MEDIAOPT_BT4) { 2960 xl_init(sc); 2961 } else { 2962 xl_setmode(sc, ifm->ifm_media); 2963 } 2964 2965 return(0); 2966 } 2967 2968 /* 2969 * Report current media status. 2970 */ 2971 static void 2972 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2973 { 2974 struct xl_softc *sc; 2975 u_int32_t icfg; 2976 struct mii_data *mii = NULL; 2977 2978 ASSERT_SERIALIZED(ifp->if_serializer); 2979 2980 sc = ifp->if_softc; 2981 if (sc->xl_miibus != NULL) 2982 mii = device_get_softc(sc->xl_miibus); 2983 2984 XL_SEL_WIN(3); 2985 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2986 icfg >>= XL_ICFG_CONNECTOR_BITS; 2987 2988 ifmr->ifm_active = IFM_ETHER; 2989 2990 switch(icfg) { 2991 case XL_XCVR_10BT: 2992 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2993 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2994 ifmr->ifm_active |= IFM_FDX; 2995 else 2996 ifmr->ifm_active |= IFM_HDX; 2997 break; 2998 case XL_XCVR_AUI: 2999 if (sc->xl_type == XL_TYPE_905B && 3000 sc->xl_media == XL_MEDIAOPT_10FL) { 3001 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3002 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3003 ifmr->ifm_active |= IFM_FDX; 3004 else 3005 ifmr->ifm_active |= IFM_HDX; 3006 } else 3007 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3008 break; 3009 case XL_XCVR_COAX: 3010 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3011 break; 3012 /* 3013 * XXX MII and BTX/AUTO should be separate cases. 3014 */ 3015 3016 case XL_XCVR_100BTX: 3017 case XL_XCVR_AUTO: 3018 case XL_XCVR_MII: 3019 if (mii != NULL) { 3020 mii_pollstat(mii); 3021 ifmr->ifm_active = mii->mii_media_active; 3022 ifmr->ifm_status = mii->mii_media_status; 3023 } 3024 break; 3025 case XL_XCVR_100BFX: 3026 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3027 break; 3028 default: 3029 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3030 break; 3031 } 3032 3033 return; 3034 } 3035 3036 static int 3037 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3038 { 3039 struct xl_softc *sc = ifp->if_softc; 3040 struct ifreq *ifr = (struct ifreq *) data; 3041 int error = 0; 3042 struct mii_data *mii = NULL; 3043 u_int8_t rxfilt; 3044 3045 ASSERT_SERIALIZED(ifp->if_serializer); 3046 3047 switch(command) { 3048 case SIOCSIFFLAGS: 3049 XL_SEL_WIN(5); 3050 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3051 if (ifp->if_flags & IFF_UP) { 3052 if (ifp->if_flags & IFF_RUNNING && 3053 ifp->if_flags & IFF_PROMISC && 3054 !(sc->xl_if_flags & IFF_PROMISC)) { 3055 rxfilt |= XL_RXFILTER_ALLFRAMES; 3056 CSR_WRITE_2(sc, XL_COMMAND, 3057 XL_CMD_RX_SET_FILT|rxfilt); 3058 XL_SEL_WIN(7); 3059 } else if (ifp->if_flags & IFF_RUNNING && 3060 !(ifp->if_flags & IFF_PROMISC) && 3061 sc->xl_if_flags & IFF_PROMISC) { 3062 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3063 CSR_WRITE_2(sc, XL_COMMAND, 3064 XL_CMD_RX_SET_FILT|rxfilt); 3065 XL_SEL_WIN(7); 3066 } else 3067 xl_init(sc); 3068 } else { 3069 if (ifp->if_flags & IFF_RUNNING) 3070 xl_stop(sc); 3071 } 3072 sc->xl_if_flags = ifp->if_flags; 3073 error = 0; 3074 break; 3075 case SIOCADDMULTI: 3076 case SIOCDELMULTI: 3077 if (sc->xl_type == XL_TYPE_905B) 3078 xl_setmulti_hash(sc); 3079 else 3080 xl_setmulti(sc); 3081 error = 0; 3082 break; 3083 case SIOCGIFMEDIA: 3084 case SIOCSIFMEDIA: 3085 if (sc->xl_miibus != NULL) 3086 mii = device_get_softc(sc->xl_miibus); 3087 if (mii == NULL) 3088 error = ifmedia_ioctl(ifp, ifr, 3089 &sc->ifmedia, command); 3090 else 3091 error = ifmedia_ioctl(ifp, ifr, 3092 &mii->mii_media, command); 3093 break; 3094 case SIOCSIFCAP: 3095 ifp->if_capenable &= ~IFCAP_HWCSUM; 3096 ifp->if_capenable |= (ifr->ifr_reqcap & IFCAP_HWCSUM); 3097 if (ifp->if_capenable & IFCAP_HWCSUM) 3098 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3099 else 3100 ifp->if_hwassist = 0; 3101 break; 3102 default: 3103 error = ether_ioctl(ifp, command, data); 3104 break; 3105 } 3106 return(error); 3107 } 3108 3109 static void 3110 xl_watchdog(struct ifnet *ifp) 3111 { 3112 struct xl_softc *sc; 3113 u_int16_t status = 0; 3114 3115 ASSERT_SERIALIZED(ifp->if_serializer); 3116 3117 sc = ifp->if_softc; 3118 3119 ifp->if_oerrors++; 3120 XL_SEL_WIN(4); 3121 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3122 if_printf(ifp, "watchdog timeout\n"); 3123 3124 if (status & XL_MEDIASTAT_CARRIER) 3125 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 3126 xl_txeoc(sc); 3127 xl_txeof(sc); 3128 xl_rxeof(sc, -1); 3129 xl_reset(sc); 3130 xl_init(sc); 3131 3132 if (!ifq_is_empty(&ifp->if_snd)) 3133 if_devstart(ifp); 3134 } 3135 3136 /* 3137 * Stop the adapter and free any mbufs allocated to the 3138 * RX and TX lists. 3139 */ 3140 static void 3141 xl_stop(struct xl_softc *sc) 3142 { 3143 int i; 3144 struct ifnet *ifp; 3145 3146 ifp = &sc->arpcom.ac_if; 3147 ASSERT_SERIALIZED(ifp->if_serializer); 3148 3149 ifp->if_timer = 0; 3150 3151 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3152 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3153 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3154 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3155 xl_wait(sc); 3156 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3157 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3158 DELAY(800); 3159 3160 #ifdef foo 3161 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3162 xl_wait(sc); 3163 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3164 xl_wait(sc); 3165 #endif 3166 3167 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3168 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3169 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3170 if (sc->xl_flags & XL_FLAG_FUNCREG) 3171 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3172 3173 /* Stop the stats updater. */ 3174 callout_stop(&sc->xl_stat_timer); 3175 3176 /* 3177 * Free data in the RX lists. 3178 */ 3179 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3180 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3181 bus_dmamap_unload(sc->xl_rx_mtag, 3182 sc->xl_cdata.xl_rx_chain[i].xl_map); 3183 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3184 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3185 } 3186 } 3187 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3188 3189 /* 3190 * Free the TX list buffers. 3191 */ 3192 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3193 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3194 bus_dmamap_unload(sc->xl_tx_mtag, 3195 sc->xl_cdata.xl_tx_chain[i].xl_map); 3196 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3197 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3198 } 3199 } 3200 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3201 3202 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3203 } 3204 3205 /* 3206 * Stop all chip I/O so that the kernel's probe routines don't 3207 * get confused by errant DMAs when rebooting. 3208 */ 3209 static void 3210 xl_shutdown(device_t dev) 3211 { 3212 struct xl_softc *sc = device_get_softc(dev); 3213 3214 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 3215 xl_reset(sc); 3216 xl_stop(sc); 3217 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 3218 } 3219 3220 static int 3221 xl_suspend(device_t dev) 3222 { 3223 struct xl_softc *sc = device_get_softc(dev); 3224 3225 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 3226 xl_stop(sc); 3227 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 3228 3229 return(0); 3230 } 3231 3232 static int 3233 xl_resume(device_t dev) 3234 { 3235 struct xl_softc *sc; 3236 struct ifnet *ifp; 3237 3238 sc = device_get_softc(dev); 3239 ifp = &sc->arpcom.ac_if; 3240 3241 lwkt_serialize_enter(ifp->if_serializer); 3242 xl_reset(sc); 3243 if (ifp->if_flags & IFF_UP) 3244 xl_init(sc); 3245 lwkt_serialize_exit(ifp->if_serializer); 3246 3247 return(0); 3248 } 3249