1 /* 2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/coretemp/coretemp.c,v 1.14 2011/05/05 19:15:15 delphij Exp $ 27 */ 28 29 /* 30 * Device driver for Intel's On Die thermal sensor via MSR. 31 * First introduced in Intel's Core line of processors. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/systm.h> 37 #include <sys/types.h> 38 #include <sys/module.h> 39 #include <sys/conf.h> 40 #include <sys/kernel.h> 41 #include <sys/sensors.h> 42 #include <sys/proc.h> /* for curthread */ 43 #include <sys/sched.h> 44 45 #include <machine/specialreg.h> 46 #include <machine/cpufunc.h> 47 #include <machine/cputypes.h> 48 #include <machine/md_var.h> 49 50 struct coretemp_softc { 51 struct ksensordev sc_sensordev; 52 struct ksensor sc_sensor; 53 device_t sc_dev; 54 int sc_tjmax; 55 }; 56 57 /* 58 * Device methods. 59 */ 60 static void coretemp_identify(driver_t *driver, device_t parent); 61 static int coretemp_probe(device_t dev); 62 static int coretemp_attach(device_t dev); 63 static int coretemp_detach(device_t dev); 64 65 static int coretemp_get_temp(device_t dev); 66 static void coretemp_refresh(void *arg); 67 68 static device_method_t coretemp_methods[] = { 69 /* Device interface */ 70 DEVMETHOD(device_identify, coretemp_identify), 71 DEVMETHOD(device_probe, coretemp_probe), 72 DEVMETHOD(device_attach, coretemp_attach), 73 DEVMETHOD(device_detach, coretemp_detach), 74 75 DEVMETHOD_END 76 }; 77 78 static driver_t coretemp_driver = { 79 "coretemp", 80 coretemp_methods, 81 sizeof(struct coretemp_softc), 82 }; 83 84 static devclass_t coretemp_devclass; 85 DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, NULL); 86 87 static void 88 coretemp_identify(driver_t *driver, device_t parent) 89 { 90 device_t child; 91 u_int regs[4]; 92 93 /* Make sure we're not being doubly invoked. */ 94 if (device_find_child(parent, "coretemp", -1) != NULL) 95 return; 96 97 /* Check that CPUID 0x06 is supported and the vendor is Intel.*/ 98 if (cpu_high < 6 || cpu_vendor_id != CPU_VENDOR_INTEL) 99 return; 100 /* 101 * CPUID 0x06 returns 1 if the processor has on-die thermal 102 * sensors. EBX[0:3] contains the number of sensors. 103 */ 104 do_cpuid(0x06, regs); 105 if ((regs[0] & 0x1) != 1) 106 return; 107 108 /* 109 * We add a child for each CPU since settings must be performed 110 * on each CPU in the SMP case. 111 */ 112 child = device_add_child(parent, "coretemp", -1); 113 if (child == NULL) 114 device_printf(parent, "add coretemp child failed\n"); 115 } 116 117 static int 118 coretemp_probe(device_t dev) 119 { 120 if (resource_disabled("coretemp", 0)) 121 return (ENXIO); 122 123 device_set_desc(dev, "CPU On-Die Thermal Sensors"); 124 125 return (BUS_PROBE_GENERIC); 126 } 127 128 static int 129 coretemp_attach(device_t dev) 130 { 131 struct coretemp_softc *sc = device_get_softc(dev); 132 device_t pdev; 133 uint64_t msr; 134 int cpu_model, cpu_stepping; 135 int ret, tjtarget; 136 137 sc->sc_dev = dev; 138 pdev = device_get_parent(dev); 139 cpu_model = CPUID_TO_MODEL(cpu_id); 140 cpu_stepping = cpu_id & CPUID_STEPPING; 141 142 /* 143 * Some CPUs, namely the PIII, don't have thermal sensors, but 144 * report them when the CPUID check is performed in 145 * coretemp_identify(). This leads to a later GPF when the sensor 146 * is queried via a MSR, so we stop here. 147 */ 148 if (cpu_model < 0xe) 149 return (ENXIO); 150 151 #if 0 /* 152 * XXXrpaulo: I have this CPU model and when it returns from C3 153 * coretemp continues to function properly. 154 */ 155 156 /* 157 * Check for errata AE18. 158 * "Processor Digital Thermal Sensor (DTS) Readout stops 159 * updating upon returning from C3/C4 state." 160 * 161 * Adapted from the Linux coretemp driver. 162 */ 163 if (cpu_model == 0xe && cpu_stepping < 0xc) { 164 msr = rdmsr(MSR_BIOS_SIGN); 165 msr = msr >> 32; 166 if (msr < 0x39) { 167 device_printf(dev, "not supported (Intel errata " 168 "AE18), try updating your BIOS\n"); 169 return (ENXIO); 170 } 171 } 172 #endif 173 174 /* 175 * Use 100C as the initial value. 176 */ 177 sc->sc_tjmax = 100; 178 179 if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) { 180 /* 181 * On some Core 2 CPUs, there's an undocumented MSR that 182 * can tell us if Tj(max) is 100 or 85. 183 * 184 * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG was adapted 185 * from the Linux coretemp driver. 186 */ 187 msr = rdmsr(MSR_IA32_EXT_CONFIG); 188 if (msr & (1 << 30)) 189 sc->sc_tjmax = 85; 190 } else if (cpu_model == 0x17) { 191 switch (cpu_stepping) { 192 case 0x6: /* Mobile Core 2 Duo */ 193 sc->sc_tjmax = 105; 194 break; 195 default: /* Unknown stepping */ 196 break; 197 } 198 } else if (cpu_model == 0x1c) { 199 switch (cpu_stepping) { 200 case 0xa: /* 45nm Atom D400, N400 and D500 series */ 201 sc->sc_tjmax = 100; 202 break; 203 default: 204 sc->sc_tjmax = 90; 205 break; 206 } 207 } else { 208 /* 209 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET. 210 * 211 * This method is described in Intel white paper "CPU 212 * Monitoring With DTS/PECI". (#322683) 213 */ 214 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr); 215 if (ret == 0) { 216 tjtarget = (msr >> 16) & 0xff; 217 218 /* 219 * On earlier generation of processors, the value 220 * obtained from IA32_TEMPERATURE_TARGET register is 221 * an offset that needs to be summed with a model 222 * specific base. It is however not clear what 223 * these numbers are, with the publicly available 224 * documents from Intel. 225 * 226 * For now, we consider [70, 100]C range, as 227 * described in #322683, as "reasonable" and accept 228 * these values whenever the MSR is available for 229 * read, regardless the CPU model. 230 */ 231 if (tjtarget >= 70 && tjtarget <= 100) 232 sc->sc_tjmax = tjtarget; 233 else 234 device_printf(dev, "Tj(target) value %d " 235 "does not seem right.\n", tjtarget); 236 } else 237 device_printf(dev, "Can not get Tj(target) " 238 "from your CPU, using 100C.\n"); 239 } 240 241 if (bootverbose) 242 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax); 243 244 /* 245 * Add hw.sensors.cpuN.temp0 MIB. 246 */ 247 strlcpy(sc->sc_sensordev.xname, device_get_nameunit(pdev), 248 sizeof(sc->sc_sensordev.xname)); 249 sc->sc_sensor.type = SENSOR_TEMP; 250 sensor_attach(&sc->sc_sensordev, &sc->sc_sensor); 251 if (sensor_task_register(sc, coretemp_refresh, 2)) { 252 device_printf(dev, "unable to register update task\n"); 253 return (ENXIO); 254 } 255 sensordev_install(&sc->sc_sensordev); 256 257 return (0); 258 } 259 260 static int 261 coretemp_detach(device_t dev) 262 { 263 struct coretemp_softc *sc = device_get_softc(dev); 264 265 sensordev_deinstall(&sc->sc_sensordev); 266 sensor_task_unregister(sc); 267 268 return (0); 269 } 270 271 272 static int 273 coretemp_get_temp(device_t dev) 274 { 275 uint64_t msr; 276 int temp, cpu, origcpu; 277 struct coretemp_softc *sc = device_get_softc(dev); 278 char stemp[16]; 279 280 cpu = device_get_unit(device_get_parent(dev)); 281 282 /* 283 * Bind to specific CPU to read the correct temperature. 284 * If not all CPUs are initialised, then only read from 285 * cpu0, returning -1 on all other CPUs. 286 */ 287 if (ncpus > 1) { 288 origcpu = mycpuid; 289 lwkt_migratecpu(cpu); 290 291 msr = rdmsr(MSR_THERM_STATUS); 292 293 lwkt_migratecpu(origcpu); 294 } else if (cpu != 0) 295 return (-1); 296 else 297 msr = rdmsr(MSR_THERM_STATUS); 298 299 /* 300 * Check for Thermal Status and Thermal Status Log. 301 */ 302 if ((msr & 0x3) == 0x3) 303 device_printf(dev, "PROCHOT asserted\n"); 304 305 /* 306 * Bit 31 contains "Reading valid" 307 */ 308 if (((msr >> 31) & 0x1) == 1) { 309 /* 310 * Starting on bit 16 and ending on bit 22. 311 */ 312 temp = sc->sc_tjmax - ((msr >> 16) & 0x7f); 313 } else 314 temp = -1; 315 316 /* 317 * Check for Critical Temperature Status and Critical 318 * Temperature Log. 319 * It doesn't really matter if the current temperature is 320 * invalid because the "Critical Temperature Log" bit will 321 * tell us if the Critical Temperature has been reached in 322 * past. It's not directly related to the current temperature. 323 * 324 * If we reach a critical level, allow devctl(4) to catch this 325 * and shutdown the system. 326 */ 327 if (((msr >> 4) & 0x3) == 0x3) { 328 device_printf(dev, "critical temperature detected, " 329 "suggest system shutdown\n"); 330 ksnprintf(stemp, sizeof(stemp), "%d", temp); 331 devctl_notify("coretemp", "Thermal", stemp, "notify=0xcc"); 332 } 333 334 return (temp); 335 } 336 337 static void 338 coretemp_refresh(void *arg) 339 { 340 struct coretemp_softc *sc = arg; 341 device_t dev = sc->sc_dev; 342 struct ksensor *s = &sc->sc_sensor; 343 int temp; 344 345 temp = coretemp_get_temp(dev); 346 347 if (temp == -1) { 348 s->flags |= SENSOR_FINVALID; 349 s->value = 0; 350 } else { 351 s->flags &= ~SENSOR_FINVALID; 352 s->value = temp * 1000000 + 273150000; 353 } 354 } 355