1 /*- 2 * Copyright (c) 2000 Matthew N. Dodd <winter@jurai.net> 3 * All rights reserved. 4 * 5 * Copyright (c) 1997 Simon Shapiro 6 * All Rights Reserved 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/dpt/dpt_pci.c,v 1.17.2.2 2000/08/26 22:21:21 peter Exp $ 30 * $DragonFly: src/sys/dev/raid/dpt/dpt_pci.c,v 1.3 2003/08/07 21:17:08 dillon Exp $ 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 39 #include <machine/bus_memio.h> 40 #include <machine/bus_pio.h> 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <sys/rman.h> 44 45 #include <bus/pci/pcireg.h> 46 #include <bus/pci/pcivar.h> 47 48 #include <bus/cam/scsi/scsi_all.h> 49 50 #include "dpt.h" 51 52 #define DPT_VENDOR_ID 0x1044 53 #define DPT_DEVICE_ID 0xa400 54 55 #define DPT_PCI_IOADDR PCIR_MAPS /* I/O Address */ 56 #define DPT_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 57 58 #define ISA_PRIMARY_WD_ADDRESS 0x1f8 59 60 static int dpt_pci_probe (device_t); 61 static int dpt_pci_attach (device_t); 62 63 static int 64 dpt_pci_probe (device_t dev) 65 { 66 if ((pci_get_vendor(dev) == DPT_VENDOR_ID) && 67 (pci_get_device(dev) == DPT_DEVICE_ID)) { 68 device_set_desc(dev, "DPT Caching SCSI RAID Controller"); 69 return (0); 70 } 71 return (ENXIO); 72 } 73 74 static int 75 dpt_pci_attach (device_t dev) 76 { 77 dpt_softc_t * dpt; 78 struct resource *io = 0; 79 struct resource *irq = 0; 80 int s; 81 int rid; 82 void * ih; 83 int error = 0; 84 85 int iotype = 0; 86 u_int32_t command; 87 88 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 89 90 #ifdef DPT_ALLOW_MMIO 91 if ((command & PCIM_CMD_MEMEN) != 0) { 92 rid = DPT_PCI_MEMADDR; 93 iotype = SYS_RES_MEMORY; 94 io = bus_alloc_resource(dev, iotype, &rid, 0, ~0, 1, RF_ACTIVE); 95 } 96 #endif 97 if (io == NULL && (command & PCIM_CMD_PORTEN) != 0) { 98 rid = DPT_PCI_IOADDR; 99 iotype = SYS_RES_IOPORT; 100 io = bus_alloc_resource(dev, iotype, &rid, 0, ~0, 1, RF_ACTIVE); 101 } 102 103 if (io == NULL) { 104 device_printf(dev, "can't allocate register resources\n"); 105 error = ENOMEM; 106 goto bad; 107 } 108 109 rid = 0; 110 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 111 RF_ACTIVE | RF_SHAREABLE); 112 if (!irq) { 113 device_printf(dev, "No irq?!\n"); 114 error = ENOMEM; 115 goto bad; 116 } 117 118 /* Ensure busmastering is enabled */ 119 command |= PCIM_CMD_BUSMASTEREN; 120 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); 121 122 if (rman_get_start(io) == (ISA_PRIMARY_WD_ADDRESS - 0x10)) { 123 #ifdef DPT_DEBUG_WARN 124 device_printf(dev, "Mapped as an IDE controller. " 125 "Disabling SCSI setup\n"); 126 #endif 127 error = ENXIO; 128 goto bad; 129 } 130 131 /* Device registers are offset 0x10 into the register window. FEH */ 132 dpt = dpt_alloc(dev, rman_get_bustag(io), rman_get_bushandle(io) + 0x10); 133 if (dpt == NULL) { 134 error = ENXIO; 135 goto bad; 136 } 137 138 /* Allocate a dmatag representing the capabilities of this attachment */ 139 /* XXX Should be a child of the PCI bus dma tag */ 140 if (bus_dma_tag_create( /* parent */ NULL, 141 /* alignemnt */ 1, 142 /* boundary */ 0, 143 /* lowaddr */ BUS_SPACE_MAXADDR_32BIT, 144 /* highaddr */ BUS_SPACE_MAXADDR, 145 /* filter */ NULL, 146 /* filterarg */ NULL, 147 /* maxsize */ BUS_SPACE_MAXSIZE_32BIT, 148 /* nsegments */ BUS_SPACE_UNRESTRICTED, 149 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT, 150 /* flags */ 0, 151 &dpt->parent_dmat) != 0) { 152 dpt_free(dpt); 153 error = ENXIO; 154 goto bad; 155 } 156 157 s = splcam(); 158 159 if (dpt_init(dpt) != 0) { 160 dpt_free(dpt); 161 error = ENXIO; 162 goto bad; 163 } 164 165 /* Register with the XPT */ 166 dpt_attach(dpt); 167 168 splx(s); 169 170 if (bus_setup_intr(dev, irq, INTR_TYPE_CAM, dpt_intr, dpt, &ih)) { 171 device_printf(dev, "Unable to register interrupt handler\n"); 172 error = ENXIO; 173 goto bad; 174 } 175 176 return (error); 177 178 bad: 179 if (io) 180 bus_release_resource(dev, iotype, 0, io); 181 if (irq) 182 bus_release_resource(dev, SYS_RES_IRQ, 0, irq); 183 184 return (error); 185 } 186 187 static device_method_t dpt_pci_methods[] = { 188 /* Device interface */ 189 DEVMETHOD(device_probe, dpt_pci_probe), 190 DEVMETHOD(device_attach, dpt_pci_attach), 191 192 { 0, 0 } 193 }; 194 195 static driver_t dpt_pci_driver = { 196 "dpt", 197 dpt_pci_methods, 198 sizeof(dpt_softc_t), 199 }; 200 201 static devclass_t dpt_devclass; 202 203 DRIVER_MODULE(dpt, pci, dpt_pci_driver, dpt_devclass, 0, 0); 204