1 /* 2 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <dev/sound/pcm/sound.h> 28 #include <dev/sound/pcm/ac97.h> 29 #include <dev/sound/pci/aureal.h> 30 31 #include <pci/pcireg.h> 32 #include <pci/pcivar.h> 33 34 SND_DECLARE_FILE("$FreeBSD: src/sys/dev/sound/pci/aureal.c,v 1.8.2.7 2002/04/22 15:49:31 cg Exp $"); 35 36 /* PCI IDs of supported chips */ 37 #define AU8820_PCI_ID 0x000112eb 38 39 /* channel interface */ 40 static u_int32_t au_playfmt[] = { 41 AFMT_U8, 42 AFMT_STEREO | AFMT_U8, 43 AFMT_S16_LE, 44 AFMT_STEREO | AFMT_S16_LE, 45 0 46 }; 47 static struct pcmchan_caps au_playcaps = {4000, 48000, au_playfmt, 0}; 48 49 static u_int32_t au_recfmt[] = { 50 AFMT_U8, 51 AFMT_STEREO | AFMT_U8, 52 AFMT_S16_LE, 53 AFMT_STEREO | AFMT_S16_LE, 54 0 55 }; 56 static struct pcmchan_caps au_reccaps = {4000, 48000, au_recfmt, 0}; 57 58 /* -------------------------------------------------------------------- */ 59 60 struct au_info; 61 62 struct au_chinfo { 63 struct au_info *parent; 64 struct pcm_channel *channel; 65 struct snd_dbuf *buffer; 66 int dir; 67 }; 68 69 struct au_info { 70 int unit; 71 72 bus_space_tag_t st[3]; 73 bus_space_handle_t sh[3]; 74 75 bus_dma_tag_t parent_dmat; 76 void *lock; 77 78 u_int32_t x[32], y[128]; 79 char z[128]; 80 u_int32_t routes[4], interrupts; 81 struct au_chinfo pch; 82 }; 83 84 static int au_init(device_t dev, struct au_info *au); 85 static void au_intr(void *); 86 87 /* -------------------------------------------------------------------- */ 88 89 static u_int32_t 90 au_rd(struct au_info *au, int mapno, int regno, int size) 91 { 92 switch(size) { 93 case 1: 94 return bus_space_read_1(au->st[mapno], au->sh[mapno], regno); 95 case 2: 96 return bus_space_read_2(au->st[mapno], au->sh[mapno], regno); 97 case 4: 98 return bus_space_read_4(au->st[mapno], au->sh[mapno], regno); 99 default: 100 return 0xffffffff; 101 } 102 } 103 104 static void 105 au_wr(struct au_info *au, int mapno, int regno, u_int32_t data, int size) 106 { 107 switch(size) { 108 case 1: 109 bus_space_write_1(au->st[mapno], au->sh[mapno], regno, data); 110 break; 111 case 2: 112 bus_space_write_2(au->st[mapno], au->sh[mapno], regno, data); 113 break; 114 case 4: 115 bus_space_write_4(au->st[mapno], au->sh[mapno], regno, data); 116 break; 117 } 118 } 119 120 /* -------------------------------------------------------------------- */ 121 122 static int 123 au_rdcd(kobj_t obj, void *arg, int regno) 124 { 125 struct au_info *au = (struct au_info *)arg; 126 int i=0, j=0; 127 128 regno<<=16; 129 au_wr(au, 0, AU_REG_CODECIO, regno, 4); 130 while (j<50) { 131 i=au_rd(au, 0, AU_REG_CODECIO, 4); 132 if ((i & 0x00ff0000) == (regno | 0x00800000)) break; 133 DELAY(j * 200 + 2000); 134 j++; 135 } 136 if (j==50) printf("pcm%d: codec timeout reading register %x (%x)\n", 137 au->unit, (regno & AU_CDC_REGMASK)>>16, i); 138 return i & AU_CDC_DATAMASK; 139 } 140 141 static int 142 au_wrcd(kobj_t obj, void *arg, int regno, u_int32_t data) 143 { 144 struct au_info *au = (struct au_info *)arg; 145 int i, j, tries; 146 i=j=tries=0; 147 do { 148 while (j<50 && (i & AU_CDC_WROK) == 0) { 149 i=au_rd(au, 0, AU_REG_CODECST, 4); 150 DELAY(2000); 151 j++; 152 } 153 if (j==50) printf("codec timeout during write of register %x, data %x\n", 154 regno, data); 155 au_wr(au, 0, AU_REG_CODECIO, (regno<<16) | AU_CDC_REGSET | data, 4); 156 /* DELAY(20000); 157 i=au_rdcd(au, regno); 158 */ tries++; 159 } while (0); /* (i != data && tries < 3); */ 160 /* 161 if (tries == 3) printf("giving up writing 0x%4x to codec reg %2x\n", data, regno); 162 */ 163 164 return 0; 165 } 166 167 static kobj_method_t au_ac97_methods[] = { 168 KOBJMETHOD(ac97_read, au_rdcd), 169 KOBJMETHOD(ac97_write, au_wrcd), 170 { 0, 0 } 171 }; 172 AC97_DECLARE(au_ac97); 173 174 /* -------------------------------------------------------------------- */ 175 176 static void 177 au_setbit(u_int32_t *p, char bit, u_int32_t value) 178 { 179 p += bit >> 5; 180 bit &= 0x1f; 181 *p &= ~ (1 << bit); 182 *p |= (value << bit); 183 } 184 185 static void 186 au_addroute(struct au_info *au, int a, int b, int route) 187 { 188 int j = 0x1099c+(a<<2); 189 if (au->x[a] != a+0x67) j = AU_REG_RTBASE+(au->x[a]<<2); 190 191 au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xffffffff, 4); 192 au_wr(au, 0, j, route | (b<<7), 4); 193 au->y[route]=au->x[a]; 194 au->x[a]=route; 195 au->z[route]=a & 0x000000ff; 196 au_setbit(au->routes, route, 1); 197 } 198 199 static void 200 au_delroute(struct au_info *au, int route) 201 { 202 int i; 203 int j=au->z[route]; 204 205 au_setbit(au->routes, route, 0); 206 au->z[route]=0x1f; 207 i=au_rd(au, 0, AU_REG_RTBASE+(route<<2), 4); 208 au_wr(au, 0, AU_REG_RTBASE+(au->y[route]<<2), i, 4); 209 au->y[i & 0x7f]=au->y[route]; 210 au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xfffffffe, 4); 211 if (au->x[j] == route) au->x[j]=au->y[route]; 212 au->y[route]=0x7f; 213 } 214 215 static void 216 au_encodec(struct au_info *au, char channel) 217 { 218 au_wr(au, 0, AU_REG_CODECEN, 219 au_rd(au, 0, AU_REG_CODECEN, 4) | (1 << (channel + 8)), 4); 220 } 221 222 static void 223 au_clrfifo(struct au_info *au, u_int32_t c) 224 { 225 u_int32_t i; 226 227 for (i=0; i<32; i++) au_wr(au, 0, AU_REG_FIFOBASE+(c<<7)+(i<<2), 0, 4); 228 } 229 230 static void 231 au_setadb(struct au_info *au, u_int32_t c, u_int32_t enable) 232 { 233 int x; 234 235 x = au_rd(au, 0, AU_REG_ADB, 4); 236 x &= ~(1 << c); 237 x |= (enable << c); 238 au_wr(au, 0, AU_REG_ADB, x, 4); 239 } 240 241 static void 242 au_prepareoutput(struct au_chinfo *ch, u_int32_t format) 243 { 244 struct au_info *au = ch->parent; 245 int i, stereo = (format & AFMT_STEREO)? 1 : 0; 246 u_int32_t baseaddr = vtophys(sndbuf_getbuf(ch->buffer)); 247 248 au_wr(au, 0, 0x1061c, 0, 4); 249 au_wr(au, 0, 0x10620, 0, 4); 250 au_wr(au, 0, 0x10624, 0, 4); 251 switch(format & ~AFMT_STEREO) { 252 case 1: 253 i=0xb000; 254 break; 255 case 2: 256 i=0xf000; 257 break; 258 case 8: 259 i=0x7000; 260 break; 261 case 16: 262 i=0x23000; 263 break; 264 default: 265 i=0x3000; 266 } 267 au_wr(au, 0, 0x10200, baseaddr, 4); 268 au_wr(au, 0, 0x10204, baseaddr+0x1000, 4); 269 au_wr(au, 0, 0x10208, baseaddr+0x2000, 4); 270 au_wr(au, 0, 0x1020c, baseaddr+0x3000, 4); 271 272 au_wr(au, 0, 0x10400, 0xdeffffff, 4); 273 au_wr(au, 0, 0x10404, 0xfcffffff, 4); 274 275 au_wr(au, 0, 0x10580, i, 4); 276 277 au_wr(au, 0, 0x10210, baseaddr, 4); 278 au_wr(au, 0, 0x10214, baseaddr+0x1000, 4); 279 au_wr(au, 0, 0x10218, baseaddr+0x2000, 4); 280 au_wr(au, 0, 0x1021c, baseaddr+0x3000, 4); 281 282 au_wr(au, 0, 0x10408, 0x00fff000 | 0x56000000 | 0x00000fff, 4); 283 au_wr(au, 0, 0x1040c, 0x00fff000 | 0x74000000 | 0x00000fff, 4); 284 285 au_wr(au, 0, 0x10584, i, 4); 286 287 au_wr(au, 0, 0x0f800, stereo? 0x00030032 : 0x00030030, 4); 288 au_wr(au, 0, 0x0f804, stereo? 0x00030032 : 0x00030030, 4); 289 290 au_addroute(au, 0x11, 0, 0x58); 291 au_addroute(au, 0x11, stereo? 0 : 1, 0x59); 292 } 293 294 /* -------------------------------------------------------------------- */ 295 /* channel interface */ 296 static void * 297 auchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 298 { 299 struct au_info *au = devinfo; 300 struct au_chinfo *ch = (dir == PCMDIR_PLAY)? &au->pch : NULL; 301 302 ch->parent = au; 303 ch->channel = c; 304 ch->buffer = b; 305 ch->dir = dir; 306 if (sndbuf_alloc(ch->buffer, au->parent_dmat, AU_BUFFSIZE) == -1) return NULL; 307 return ch; 308 } 309 310 static int 311 auchan_setformat(kobj_t obj, void *data, u_int32_t format) 312 { 313 struct au_chinfo *ch = data; 314 315 if (ch->dir == PCMDIR_PLAY) au_prepareoutput(ch, format); 316 return 0; 317 } 318 319 static int 320 auchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 321 { 322 struct au_chinfo *ch = data; 323 if (ch->dir == PCMDIR_PLAY) { 324 } else { 325 } 326 return speed; 327 } 328 329 static int 330 auchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 331 { 332 return blocksize; 333 } 334 335 static int 336 auchan_trigger(kobj_t obj, void *data, int go) 337 { 338 struct au_chinfo *ch = data; 339 struct au_info *au = ch->parent; 340 341 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD) 342 return 0; 343 344 if (ch->dir == PCMDIR_PLAY) { 345 au_setadb(au, 0x11, (go)? 1 : 0); 346 if (!go) { 347 au_wr(au, 0, 0xf800, 0, 4); 348 au_wr(au, 0, 0xf804, 0, 4); 349 au_delroute(au, 0x58); 350 au_delroute(au, 0x59); 351 } 352 } else { 353 } 354 return 0; 355 } 356 357 static int 358 auchan_getptr(kobj_t obj, void *data) 359 { 360 struct au_chinfo *ch = data; 361 struct au_info *au = ch->parent; 362 if (ch->dir == PCMDIR_PLAY) { 363 return au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1); 364 } else { 365 return 0; 366 } 367 } 368 369 static struct pcmchan_caps * 370 auchan_getcaps(kobj_t obj, void *data) 371 { 372 struct au_chinfo *ch = data; 373 return (ch->dir == PCMDIR_PLAY)? &au_playcaps : &au_reccaps; 374 } 375 376 static kobj_method_t auchan_methods[] = { 377 KOBJMETHOD(channel_init, auchan_init), 378 KOBJMETHOD(channel_setformat, auchan_setformat), 379 KOBJMETHOD(channel_setspeed, auchan_setspeed), 380 KOBJMETHOD(channel_setblocksize, auchan_setblocksize), 381 KOBJMETHOD(channel_trigger, auchan_trigger), 382 KOBJMETHOD(channel_getptr, auchan_getptr), 383 KOBJMETHOD(channel_getcaps, auchan_getcaps), 384 { 0, 0 } 385 }; 386 CHANNEL_DECLARE(auchan); 387 388 /* -------------------------------------------------------------------- */ 389 /* The interrupt handler */ 390 static void 391 au_intr (void *p) 392 { 393 struct au_info *au = p; 394 u_int32_t intsrc, i; 395 396 au->interrupts++; 397 intsrc=au_rd(au, 0, AU_REG_IRQSRC, 4); 398 printf("pcm%d: interrupt with src %x\n", au->unit, intsrc); 399 if (intsrc & AU_IRQ_FATAL) printf("pcm%d: fatal error irq\n", au->unit); 400 if (intsrc & AU_IRQ_PARITY) printf("pcm%d: parity error irq\n", au->unit); 401 if (intsrc & AU_IRQ_UNKNOWN) { 402 (void)au_rd(au, 0, AU_REG_UNK1, 4); 403 au_wr(au, 0, AU_REG_UNK1, 0, 4); 404 au_wr(au, 0, AU_REG_UNK1, 0x10000, 4); 405 } 406 if (intsrc & AU_IRQ_PCMOUT) { 407 i=au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1); 408 chn_intr(au->pch.channel); 409 (void)au_rd(au, 0, AU_REG_UNK3, 4); 410 (void)au_rd(au, 0, AU_REG_UNK4, 4); 411 (void)au_rd(au, 0, AU_REG_UNK5, 4); 412 } 413 /* don't support midi 414 if (intsrc & AU_IRQ_MIDI) { 415 i=au_rd(au, 0, 0x11004, 4); 416 j=10; 417 while (i & 0xff) { 418 if (j-- <= 0) break; 419 i=au_rd(au, 0, 0x11000, 4); 420 if ((au->midi_stat & 1) && (au->midi_out)) 421 au->midi_out(au->midi_devno, i); 422 i=au_rd(au, 0, 0x11004); 423 } 424 } 425 */ 426 au_wr(au, 0, AU_REG_IRQSRC, intsrc & 0x7ff, 4); 427 au_rd(au, 0, AU_REG_IRQSRC, 4); 428 } 429 430 431 /* -------------------------------------------------------------------- */ 432 433 /* Probe and attach the card */ 434 435 static int 436 au_init(device_t dev, struct au_info *au) 437 { 438 u_int32_t i, j; 439 440 au_wr(au, 0, AU_REG_IRQGLOB, 0xffffffff, 4); 441 DELAY(100000); 442 443 /* init codec */ 444 /* cold reset */ 445 for (i=0; i<32; i++) { 446 au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4); 447 DELAY(10000); 448 } 449 if (1) { 450 au_wr(au, 0, AU_REG_CODECST, 0x8068, 4); 451 DELAY(10000); 452 au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4); 453 DELAY(10000); 454 } else { 455 au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4); 456 DELAY(100000); 457 au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4); 458 DELAY(100000); 459 au_wr(au, 0, AU_REG_CODECST, 0x80e8, 4); 460 DELAY(100000); 461 au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4); 462 DELAY(100000); 463 au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4); 464 DELAY(100000); 465 au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4); 466 DELAY(100000); 467 } 468 469 /* init */ 470 for (i=0; i<32; i++) { 471 au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4); 472 DELAY(10000); 473 } 474 au_wr(au, 0, AU_REG_CODECST, 0xe8, 4); 475 DELAY(10000); 476 au_wr(au, 0, AU_REG_CODECEN, 0, 4); 477 478 /* setup codec */ 479 i=j=0; 480 while (j<100 && (i & AU_CDC_READY)==0) { 481 i=au_rd(au, 0, AU_REG_CODECST, 4); 482 DELAY(1000); 483 j++; 484 } 485 if (j==100) device_printf(dev, "codec not ready, status 0x%x\n", i); 486 487 /* init adb */ 488 /*au->x5c=0;*/ 489 for (i=0; i<32; i++) au->x[i]=i+0x67; 490 for (i=0; i<128; i++) au->y[i]=0x7f; 491 for (i=0; i<128; i++) au->z[i]=0x1f; 492 au_wr(au, 0, AU_REG_ADB, 0, 4); 493 for (i=0; i<124; i++) au_wr(au, 0, AU_REG_RTBASE+(i<<2), 0xffffffff, 4); 494 495 /* test */ 496 i=au_rd(au, 0, 0x107c0, 4); 497 if (i!=0xdeadbeef) device_printf(dev, "dma check failed: 0x%x\n", i); 498 499 /* install mixer */ 500 au_wr(au, 0, AU_REG_IRQGLOB, 501 au_rd(au, 0, AU_REG_IRQGLOB, 4) | AU_IRQ_ENABLE, 4); 502 /* braindead but it's what the oss/linux driver does 503 * for (i=0; i<0x80000000; i++) au_wr(au, 0, i<<2, 0, 4); 504 */ 505 au->routes[0]=au->routes[1]=au->routes[2]=au->routes[3]=0; 506 /*au->x1e4=0;*/ 507 508 /* attach channel */ 509 au_addroute(au, 0x11, 0x48, 0x02); 510 au_addroute(au, 0x11, 0x49, 0x03); 511 au_encodec(au, 0); 512 au_encodec(au, 1); 513 514 for (i=0; i<48; i++) au_wr(au, 0, 0xf800+(i<<2), 0x20, 4); 515 for (i=2; i<6; i++) au_wr(au, 0, 0xf800+(i<<2), 0, 4); 516 au_wr(au, 0, 0xf8c0, 0x0843, 4); 517 for (i=0; i<4; i++) au_clrfifo(au, i); 518 519 return (0); 520 } 521 522 static int 523 au_testirq(struct au_info *au) 524 { 525 au_wr(au, 0, AU_REG_UNK1, 0x80001000, 4); 526 au_wr(au, 0, AU_REG_IRQEN, 0x00001030, 4); 527 au_wr(au, 0, AU_REG_IRQSRC, 0x000007ff, 4); 528 DELAY(1000000); 529 if (au->interrupts==0) printf("pcm%d: irq test failed\n", au->unit); 530 /* this apparently generates an irq */ 531 return 0; 532 } 533 534 static int 535 au_pci_probe(device_t dev) 536 { 537 if (pci_get_devid(dev) == AU8820_PCI_ID) { 538 device_set_desc(dev, "Aureal Vortex 8820"); 539 return 0; 540 } 541 542 return ENXIO; 543 } 544 545 static int 546 au_pci_attach(device_t dev) 547 { 548 u_int32_t data; 549 struct au_info *au; 550 int type[10]; 551 int regid[10]; 552 struct resource *reg[10]; 553 int i, j, mapped = 0; 554 int irqid; 555 struct resource *irq = 0; 556 void *ih = 0; 557 struct ac97_info *codec; 558 char status[SND_STATUSLEN]; 559 560 if ((au = malloc(sizeof(*au), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 561 device_printf(dev, "cannot allocate softc\n"); 562 return ENXIO; 563 } 564 565 au->unit = device_get_unit(dev); 566 567 data = pci_read_config(dev, PCIR_COMMAND, 2); 568 data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 569 pci_write_config(dev, PCIR_COMMAND, data, 2); 570 data = pci_read_config(dev, PCIR_COMMAND, 2); 571 572 j=0; 573 /* XXX dfr: is this strictly necessary? */ 574 for (i=0; i<PCI_MAXMAPS_0; i++) { 575 #if 0 576 /* Slapped wrist: config_id and map are private structures */ 577 if (bootverbose) { 578 printf("pcm%d: map %d - allocating ", unit, i+1); 579 printf("0x%x bytes of ", 1<<config_id->map[i].ln2size); 580 printf("%s space ", (config_id->map[i].type & PCI_MAPPORT)? 581 "io" : "memory"); 582 printf("at 0x%x...", config_id->map[i].base); 583 } 584 #endif 585 regid[j] = PCIR_MAPS + i*4; 586 type[j] = SYS_RES_MEMORY; 587 reg[j] = bus_alloc_resource(dev, type[j], ®id[j], 588 0, ~0, 1, RF_ACTIVE); 589 if (!reg[j]) { 590 type[j] = SYS_RES_IOPORT; 591 reg[j] = bus_alloc_resource(dev, type[j], ®id[j], 592 0, ~0, 1, RF_ACTIVE); 593 } 594 if (reg[j]) { 595 au->st[i] = rman_get_bustag(reg[j]); 596 au->sh[i] = rman_get_bushandle(reg[j]); 597 mapped++; 598 } 599 #if 0 600 if (bootverbose) printf("%s\n", mapped? "ok" : "failed"); 601 #endif 602 if (mapped) j++; 603 if (j == 10) { 604 /* XXX */ 605 device_printf(dev, "too many resources"); 606 goto bad; 607 } 608 } 609 610 #if 0 611 if (j < config_id->nummaps) { 612 printf("pcm%d: unable to map a required resource\n", unit); 613 free(au, M_DEVBUF); 614 return; 615 } 616 #endif 617 618 au_wr(au, 0, AU_REG_IRQEN, 0, 4); 619 620 irqid = 0; 621 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &irqid, 622 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 623 if (!irq || snd_setup_intr(dev, irq, 0, au_intr, au, &ih)) { 624 device_printf(dev, "unable to map interrupt\n"); 625 goto bad; 626 } 627 628 if (au_testirq(au)) device_printf(dev, "irq test failed\n"); 629 630 if (au_init(dev, au) == -1) { 631 device_printf(dev, "unable to initialize the card\n"); 632 goto bad; 633 } 634 635 codec = AC97_CREATE(dev, au, au_ac97); 636 if (codec == NULL) goto bad; 637 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad; 638 639 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 640 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 641 /*highaddr*/BUS_SPACE_MAXADDR, 642 /*filter*/NULL, /*filterarg*/NULL, 643 /*maxsize*/AU_BUFFSIZE, /*nsegments*/1, /*maxsegz*/0x3ffff, 644 /*flags*/0, &au->parent_dmat) != 0) { 645 device_printf(dev, "unable to create dma tag\n"); 646 goto bad; 647 } 648 649 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld", 650 (type[0] == SYS_RES_IOPORT)? "io" : "memory", 651 rman_get_start(reg[0]), rman_get_start(irq)); 652 653 if (pcm_register(dev, au, 1, 1)) goto bad; 654 /* pcm_addchan(dev, PCMDIR_REC, &au_chantemplate, au); */ 655 pcm_addchan(dev, PCMDIR_PLAY, &auchan_class, au); 656 pcm_setstatus(dev, status); 657 658 return 0; 659 660 bad: 661 if (au) free(au, M_DEVBUF); 662 for (i = 0; i < j; i++) 663 bus_release_resource(dev, type[i], regid[i], reg[i]); 664 if (ih) bus_teardown_intr(dev, irq, ih); 665 if (irq) bus_release_resource(dev, SYS_RES_IRQ, irqid, irq); 666 return ENXIO; 667 } 668 669 static device_method_t au_methods[] = { 670 /* Device interface */ 671 DEVMETHOD(device_probe, au_pci_probe), 672 DEVMETHOD(device_attach, au_pci_attach), 673 674 { 0, 0 } 675 }; 676 677 static driver_t au_driver = { 678 "pcm", 679 au_methods, 680 PCM_SOFTC_SIZE, 681 }; 682 683 DRIVER_MODULE(snd_aureal, pci, au_driver, pcm_devclass, 0, 0); 684 MODULE_DEPEND(snd_aureal, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 685 MODULE_VERSION(snd_aureal, 1); 686