1 /*- 2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * The order of pokes in the initiation sequence is based on Linux 27 * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom 28 * woller (twoller@crystal.cirrus.com). Shingo Watanabe (nabe@nabechan.org) 29 * contributed towards power management. 30 * 31 * $FreeBSD: src/sys/dev/sound/pci/cs4281.c,v 1.22 2005/03/01 08:58:05 imp Exp $ 32 */ 33 34 #include <dev/sound/pcm/sound.h> 35 #include <dev/sound/pcm/ac97.h> 36 37 #include <bus/pci/pcireg.h> 38 #include <bus/pci/pcivar.h> 39 40 #include <dev/sound/pci/cs4281.h> 41 42 #define CS4281_DEFAULT_BUFSZ 16384 43 44 /* Max fifo size for full duplex is 64 */ 45 #define CS4281_FIFO_SIZE 15 46 47 /* DMA Engine Indices */ 48 #define CS4281_DMA_PLAY 0 49 #define CS4281_DMA_REC 1 50 51 /* Misc */ 52 53 #define inline __inline 54 55 #ifndef DEB 56 #define DEB(x) /* x */ 57 #endif /* DEB */ 58 59 /* ------------------------------------------------------------------------- */ 60 /* Structures */ 61 62 struct sc_info; 63 64 /* channel registers */ 65 struct sc_chinfo { 66 struct sc_info *parent; 67 68 struct snd_dbuf *buffer; 69 struct pcm_channel *channel; 70 71 u_int32_t spd, fmt, bps, blksz; 72 73 int dma_setup, dma_active, dma_chan; 74 }; 75 76 /* device private data */ 77 struct sc_info { 78 device_t dev; 79 u_int32_t type; 80 81 bus_space_tag_t st; 82 bus_space_handle_t sh; 83 bus_dma_tag_t parent_dmat; 84 85 struct resource *reg, *irq, *mem; 86 int regtype, regid, irqid, memid; 87 void *ih; 88 89 int power; 90 unsigned long bufsz; 91 struct sc_chinfo pch; 92 struct sc_chinfo rch; 93 }; 94 95 /* -------------------------------------------------------------------- */ 96 /* prototypes */ 97 98 /* ADC/DAC control */ 99 static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go); 100 static void adcdac_prog(struct sc_chinfo *ch); 101 102 /* power management and interrupt control */ 103 static void cs4281_intr(void *); 104 static int cs4281_power(struct sc_info *, int); 105 static int cs4281_init(struct sc_info *); 106 107 /* talk to the card */ 108 static u_int32_t cs4281_rd(struct sc_info *, int); 109 static void cs4281_wr(struct sc_info *, int, u_int32_t); 110 111 /* misc */ 112 static u_int8_t cs4281_rate_to_rv(u_int32_t); 113 static u_int32_t cs4281_format_to_dmr(u_int32_t); 114 static u_int32_t cs4281_format_to_bps(u_int32_t); 115 116 /* -------------------------------------------------------------------- */ 117 /* formats (do not add formats without editing cs_fmt_tab) */ 118 119 static u_int32_t cs4281_fmts[] = { 120 AFMT_U8, 121 AFMT_U8 | AFMT_STEREO, 122 AFMT_S8, 123 AFMT_S8 | AFMT_STEREO, 124 AFMT_S16_LE, 125 AFMT_S16_LE | AFMT_STEREO, 126 AFMT_U16_LE, 127 AFMT_U16_LE | AFMT_STEREO, 128 AFMT_S16_BE, 129 AFMT_S16_BE | AFMT_STEREO, 130 AFMT_U16_BE, 131 AFMT_U16_BE | AFMT_STEREO, 132 0 133 }; 134 135 static struct pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0}; 136 137 /* -------------------------------------------------------------------- */ 138 /* Hardware */ 139 140 static inline u_int32_t 141 cs4281_rd(struct sc_info *sc, int regno) 142 { 143 return bus_space_read_4(sc->st, sc->sh, regno); 144 } 145 146 static inline void 147 cs4281_wr(struct sc_info *sc, int regno, u_int32_t data) 148 { 149 bus_space_write_4(sc->st, sc->sh, regno, data); 150 DELAY(100); 151 } 152 153 static inline void 154 cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask) 155 { 156 u_int32_t r; 157 r = cs4281_rd(sc, regno); 158 cs4281_wr(sc, regno, r & ~mask); 159 } 160 161 static inline void 162 cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask) 163 { 164 u_int32_t v; 165 v = cs4281_rd(sc, regno); 166 cs4281_wr(sc, regno, v | mask); 167 } 168 169 static int 170 cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries) 171 { 172 u_int32_t v; 173 174 while(tries > 0) { 175 DELAY(100); 176 v = cs4281_rd(sc, regno); 177 if ((v & mask) == mask) break; 178 tries --; 179 } 180 return tries; 181 } 182 183 static int 184 cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries) 185 { 186 u_int32_t v; 187 188 while(tries > 0) { 189 DELAY(100); 190 v = ~ cs4281_rd(sc, regno); 191 if (v & mask) break; 192 tries --; 193 } 194 return tries; 195 } 196 197 /* ------------------------------------------------------------------------- */ 198 /* Register value mapping functions */ 199 200 static u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000}; 201 #define CS4281_NUM_RATES NELEM(cs4281_rates) 202 203 static u_int8_t 204 cs4281_rate_to_rv(u_int32_t rate) 205 { 206 u_int32_t v; 207 208 for (v = 0; v < CS4281_NUM_RATES; v++) { 209 if (rate == cs4281_rates[v]) return v; 210 } 211 212 v = 1536000 / rate; 213 if (v > 255 || v < 32) v = 5; /* default to 8k */ 214 return v; 215 } 216 217 static u_int32_t 218 cs4281_rv_to_rate(u_int8_t rv) 219 { 220 u_int32_t r; 221 222 if (rv < CS4281_NUM_RATES) return cs4281_rates[rv]; 223 r = 1536000 / rv; 224 return r; 225 } 226 227 static inline u_int32_t 228 cs4281_format_to_dmr(u_int32_t format) 229 { 230 u_int32_t dmr = 0; 231 if (AFMT_8BIT & format) dmr |= CS4281PCI_DMR_SIZE8; 232 if (!(AFMT_STEREO & format)) dmr |= CS4281PCI_DMR_MONO; 233 if (AFMT_BIGENDIAN & format) dmr |= CS4281PCI_DMR_BEND; 234 if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN; 235 return dmr; 236 } 237 238 static inline u_int32_t 239 cs4281_format_to_bps(u_int32_t format) 240 { 241 return ((AFMT_8BIT & format) ? 1 : 2) * ((AFMT_STEREO & format) ? 2 : 1); 242 } 243 244 /* -------------------------------------------------------------------- */ 245 /* ac97 codec */ 246 247 static u_int32_t 248 cs4281_rdcd(kobj_t obj, void *devinfo, int regno) 249 { 250 struct sc_info *sc = (struct sc_info *)devinfo; 251 regno &= 0xff; 252 253 /* Remove old state */ 254 cs4281_rd(sc, CS4281PCI_ACSDA); 255 256 /* Fill in AC97 register value request form */ 257 cs4281_wr(sc, CS4281PCI_ACCAD, regno); 258 cs4281_wr(sc, CS4281PCI_ACCDA, 0); 259 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN | 260 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV | 261 CS4281PCI_ACCTL_CRW); 262 263 /* Wait for read to complete */ 264 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) { 265 device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n"); 266 return 0xffffffff; 267 } 268 269 /* Wait for valid status */ 270 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_VSTS, 250) == 0) { 271 device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n"); 272 return 0xffffffff; 273 } 274 275 return cs4281_rd(sc, CS4281PCI_ACSDA); 276 } 277 278 static void 279 cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 280 { 281 struct sc_info *sc = (struct sc_info *)devinfo; 282 regno &= 0xff; 283 284 cs4281_wr(sc, CS4281PCI_ACCAD, regno); 285 cs4281_wr(sc, CS4281PCI_ACCDA, data); 286 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN | 287 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV); 288 289 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) { 290 device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n"); 291 } 292 } 293 294 static kobj_method_t cs4281_ac97_methods[] = { 295 KOBJMETHOD(ac97_read, cs4281_rdcd), 296 KOBJMETHOD(ac97_write, cs4281_wrcd), 297 KOBJMETHOD_END 298 }; 299 AC97_DECLARE(cs4281_ac97); 300 301 /* ------------------------------------------------------------------------- */ 302 /* shared rec/play channel interface */ 303 304 static void * 305 cs4281chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 306 { 307 struct sc_info *sc = devinfo; 308 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 309 310 ch->buffer = b; 311 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) { 312 return NULL; 313 } 314 ch->parent = sc; 315 ch->channel = c; 316 317 ch->fmt = AFMT_U8; 318 ch->spd = DSP_DEFAULT_SPEED; 319 ch->bps = 1; 320 ch->blksz = sndbuf_getsize(ch->buffer); 321 322 ch->dma_chan = (dir == PCMDIR_PLAY) ? CS4281_DMA_PLAY : CS4281_DMA_REC; 323 ch->dma_setup = 0; 324 325 adcdac_go(ch, 0); 326 adcdac_prog(ch); 327 328 return ch; 329 } 330 331 static int 332 cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 333 { 334 struct sc_chinfo *ch = data; 335 struct sc_info *sc = ch->parent; 336 u_int32_t go; 337 338 go = adcdac_go(ch, 0); 339 340 /* 2 interrupts are possible and used in buffer (half-empty,empty), 341 * hence factor of 2. */ 342 ch->blksz = MIN(blocksize, sc->bufsz / 2); 343 sndbuf_resize(ch->buffer, 2, ch->blksz); 344 ch->dma_setup = 0; 345 adcdac_prog(ch); 346 adcdac_go(ch, go); 347 348 DEB(kprintf("cs4281chan_setblocksize: blksz %d Setting %d\n", blocksize, ch->blksz)); 349 350 return ch->blksz; 351 } 352 353 static int 354 cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed) 355 { 356 struct sc_chinfo *ch = data; 357 struct sc_info *sc = ch->parent; 358 u_int32_t go, v, r; 359 360 go = adcdac_go(ch, 0); /* pause */ 361 r = (ch->dma_chan == CS4281_DMA_PLAY) ? CS4281PCI_DACSR : CS4281PCI_ADCSR; 362 v = cs4281_rate_to_rv(speed); 363 cs4281_wr(sc, r, v); 364 adcdac_go(ch, go); /* unpause */ 365 366 ch->spd = cs4281_rv_to_rate(v); 367 return ch->spd; 368 } 369 370 static int 371 cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format) 372 { 373 struct sc_chinfo *ch = data; 374 struct sc_info *sc = ch->parent; 375 u_int32_t v, go; 376 377 go = adcdac_go(ch, 0); /* pause */ 378 379 if (ch->dma_chan == CS4281_DMA_PLAY) 380 v = CS4281PCI_DMR_TR_PLAY; 381 else 382 v = CS4281PCI_DMR_TR_REC; 383 v |= CS4281PCI_DMR_DMA | CS4281PCI_DMR_AUTO; 384 v |= cs4281_format_to_dmr(format); 385 cs4281_wr(sc, CS4281PCI_DMR(ch->dma_chan), v); 386 387 adcdac_go(ch, go); /* unpause */ 388 389 ch->fmt = format; 390 ch->bps = cs4281_format_to_bps(format); 391 ch->dma_setup = 0; 392 393 return 0; 394 } 395 396 static int 397 cs4281chan_getptr(kobj_t obj, void *data) 398 { 399 struct sc_chinfo *ch = data; 400 struct sc_info *sc = ch->parent; 401 u_int32_t dba, dca, ptr; 402 int sz; 403 404 sz = sndbuf_getsize(ch->buffer); 405 dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan)); 406 dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan)); 407 ptr = (dca - dba + sz) % sz; 408 409 return ptr; 410 } 411 412 static int 413 cs4281chan_trigger(kobj_t obj, void *data, int go) 414 { 415 struct sc_chinfo *ch = data; 416 417 switch(go) { 418 case PCMTRIG_START: 419 adcdac_prog(ch); 420 adcdac_go(ch, 1); 421 break; 422 case PCMTRIG_ABORT: 423 adcdac_go(ch, 0); 424 break; 425 default: 426 break; 427 } 428 429 /* return 0 if ok */ 430 return 0; 431 } 432 433 static struct pcmchan_caps * 434 cs4281chan_getcaps(kobj_t obj, void *data) 435 { 436 return &cs4281_caps; 437 } 438 439 static kobj_method_t cs4281chan_methods[] = { 440 KOBJMETHOD(channel_init, cs4281chan_init), 441 KOBJMETHOD(channel_setformat, cs4281chan_setformat), 442 KOBJMETHOD(channel_setspeed, cs4281chan_setspeed), 443 KOBJMETHOD(channel_setblocksize, cs4281chan_setblocksize), 444 KOBJMETHOD(channel_trigger, cs4281chan_trigger), 445 KOBJMETHOD(channel_getptr, cs4281chan_getptr), 446 KOBJMETHOD(channel_getcaps, cs4281chan_getcaps), 447 KOBJMETHOD_END 448 }; 449 CHANNEL_DECLARE(cs4281chan); 450 451 /* -------------------------------------------------------------------- */ 452 /* ADC/DAC control */ 453 454 /* adcdac_go enables/disable DMA channel, returns non-zero if DMA was 455 * active before call */ 456 457 static u_int32_t 458 adcdac_go(struct sc_chinfo *ch, u_int32_t go) 459 { 460 struct sc_info *sc = ch->parent; 461 u_int32_t going; 462 463 going = !(cs4281_rd(sc, CS4281PCI_DCR(ch->dma_chan)) & CS4281PCI_DCR_MSK); 464 465 if (go) 466 cs4281_clr4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK); 467 else 468 cs4281_set4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK); 469 470 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI); 471 472 return going; 473 } 474 475 static void 476 adcdac_prog(struct sc_chinfo *ch) 477 { 478 struct sc_info *sc = ch->parent; 479 u_int32_t go; 480 481 if (!ch->dma_setup) { 482 go = adcdac_go(ch, 0); 483 cs4281_wr(sc, CS4281PCI_DBA(ch->dma_chan), 484 sndbuf_getbufaddr(ch->buffer)); 485 cs4281_wr(sc, CS4281PCI_DBC(ch->dma_chan), 486 sndbuf_getsize(ch->buffer) / ch->bps - 1); 487 ch->dma_setup = 1; 488 adcdac_go(ch, go); 489 } 490 } 491 492 /* -------------------------------------------------------------------- */ 493 /* The interrupt handler */ 494 495 static void 496 cs4281_intr(void *p) 497 { 498 struct sc_info *sc = (struct sc_info *)p; 499 u_int32_t hisr; 500 501 hisr = cs4281_rd(sc, CS4281PCI_HISR); 502 503 if (hisr == 0) return; 504 505 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_PLAY)) { 506 chn_intr(sc->pch.channel); 507 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */ 508 } 509 510 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_REC)) { 511 chn_intr(sc->rch.channel); 512 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */ 513 } 514 515 /* Signal End-of-Interrupt */ 516 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI); 517 } 518 519 /* -------------------------------------------------------------------- */ 520 /* power management related */ 521 522 static int 523 cs4281_power(struct sc_info *sc, int state) 524 { 525 526 switch (state) { 527 case 0: 528 /* Permit r/w access to all BA0 registers */ 529 cs4281_wr(sc, CS4281PCI_CWPR, CS4281PCI_CWPR_MAGIC); 530 /* Power on */ 531 cs4281_clr4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN); 532 break; 533 case 3: 534 /* Power off card and codec */ 535 cs4281_set4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN); 536 cs4281_clr4(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN); 537 break; 538 } 539 540 DEB(kprintf("cs4281_power %d -> %d\n", sc->power, state)); 541 sc->power = state; 542 543 return 0; 544 } 545 546 static int 547 cs4281_init(struct sc_info *sc) 548 { 549 u_int32_t i, v; 550 551 /* (0) Blast clock register and serial port */ 552 cs4281_wr(sc, CS4281PCI_CLKCR1, 0); 553 cs4281_wr(sc, CS4281PCI_SERMC, 0); 554 555 /* (1) Make ESYN 0 to turn sync pulse on AC97 link */ 556 cs4281_wr(sc, CS4281PCI_ACCTL, 0); 557 DELAY(50); 558 559 /* (2) Effect Reset */ 560 cs4281_wr(sc, CS4281PCI_SPMC, 0); 561 DELAY(100); 562 cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN); 563 /* Wait 50ms for ABITCLK to become stable */ 564 DELAY(50000); 565 566 /* (3) Enable Sound System Clocks */ 567 cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP); 568 DELAY(50000); /* Wait for PLL to stabilize */ 569 cs4281_wr(sc, CS4281PCI_CLKCR1, 570 CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE); 571 572 /* (4) Power Up - this combination is essential. */ 573 cs4281_set4(sc, CS4281PCI_SSPM, 574 CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN | 575 CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN); 576 577 /* (5) Wait for clock stabilization */ 578 if (cs4281_waitset(sc, 579 CS4281PCI_CLKCR1, 580 CS4281PCI_CLKCR1_DLLRDY, 581 250) == 0) { 582 device_printf(sc->dev, "Clock stabilization failed\n"); 583 return -1; 584 } 585 586 /* (6) Enable ASYNC generation. */ 587 cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN); 588 589 /* Wait to allow AC97 to start generating clock bit */ 590 DELAY(50000); 591 592 /* Set AC97 timing */ 593 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97); 594 595 /* (7) Wait for AC97 ready signal */ 596 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) { 597 device_printf(sc->dev, "codec did not avail\n"); 598 return -1; 599 } 600 601 /* (8) Assert valid frame signal to begin sending commands to 602 * AC97 codec */ 603 cs4281_wr(sc, 604 CS4281PCI_ACCTL, 605 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN); 606 607 /* (9) Wait for codec calibration */ 608 for(i = 0 ; i < 1000; i++) { 609 DELAY(10000); 610 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 611 if ((v & 0x0f) == 0x0f) { 612 break; 613 } 614 } 615 if (i == 1000) { 616 device_printf(sc->dev, "codec failed to calibrate\n"); 617 return -1; 618 } 619 620 /* (10) Set AC97 timing */ 621 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97); 622 623 /* (11) Wait for valid data to arrive */ 624 if (cs4281_waitset(sc, 625 CS4281PCI_ACISV, 626 CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4), 627 10000) == 0) { 628 device_printf(sc->dev, "cs4281 never got valid data\n"); 629 return -1; 630 } 631 632 /* (12) Start digital data transfer of audio data to codec */ 633 cs4281_wr(sc, 634 CS4281PCI_ACOSV, 635 CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4)); 636 637 /* Set Master and headphone to max */ 638 cs4281_wrcd(0, sc, AC97_MIX_AUXOUT, 0); 639 cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0); 640 641 /* Power on the DAC */ 642 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff; 643 cs4281_wrcd(0, sc, AC97_REG_POWER, v); 644 645 /* Wait until DAC state ready */ 646 for(i = 0; i < 320; i++) { 647 DELAY(100); 648 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 649 if (v & 0x02) break; 650 } 651 652 /* Power on the ADC */ 653 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff; 654 cs4281_wrcd(0, sc, AC97_REG_POWER, v); 655 656 /* Wait until ADC state ready */ 657 for(i = 0; i < 320; i++) { 658 DELAY(100); 659 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 660 if (v & 0x01) break; 661 } 662 663 /* FIFO configuration (driver is DMA orientated, implicit FIFO) */ 664 /* Play FIFO */ 665 666 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_PLAY_SLOT) | 667 CS4281PCI_FCR_LS(CS4281PCI_LPCM_PLAY_SLOT) | 668 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)| 669 CS4281PCI_FCR_OF(0); 670 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v); 671 672 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v | CS4281PCI_FCR_FEN); 673 674 /* Record FIFO */ 675 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_REC_SLOT) | 676 CS4281PCI_FCR_LS(CS4281PCI_LPCM_REC_SLOT) | 677 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)| 678 CS4281PCI_FCR_OF(CS4281_FIFO_SIZE + 1); 679 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_PSH); 680 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_FEN); 681 682 /* Match AC97 slots to FIFOs */ 683 v = CS4281PCI_SRCSA_PLSS(CS4281PCI_LPCM_PLAY_SLOT) | 684 CS4281PCI_SRCSA_PRSS(CS4281PCI_RPCM_PLAY_SLOT) | 685 CS4281PCI_SRCSA_CLSS(CS4281PCI_LPCM_REC_SLOT) | 686 CS4281PCI_SRCSA_CRSS(CS4281PCI_RPCM_REC_SLOT); 687 cs4281_wr(sc, CS4281PCI_SRCSA, v); 688 689 /* Set Auto-Initialize and set directions */ 690 cs4281_wr(sc, 691 CS4281PCI_DMR(CS4281_DMA_PLAY), 692 CS4281PCI_DMR_DMA | 693 CS4281PCI_DMR_AUTO | 694 CS4281PCI_DMR_TR_PLAY); 695 cs4281_wr(sc, 696 CS4281PCI_DMR(CS4281_DMA_REC), 697 CS4281PCI_DMR_DMA | 698 CS4281PCI_DMR_AUTO | 699 CS4281PCI_DMR_TR_REC); 700 701 /* Enable half and empty buffer interrupts keeping DMA paused */ 702 cs4281_wr(sc, 703 CS4281PCI_DCR(CS4281_DMA_PLAY), 704 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK); 705 cs4281_wr(sc, 706 CS4281PCI_DCR(CS4281_DMA_REC), 707 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK); 708 709 /* Enable Interrupts */ 710 cs4281_clr4(sc, 711 CS4281PCI_HIMR, 712 CS4281PCI_HIMR_DMAI | 713 CS4281PCI_HIMR_DMA(CS4281_DMA_PLAY) | 714 CS4281PCI_HIMR_DMA(CS4281_DMA_REC)); 715 716 /* Set playback volume */ 717 cs4281_wr(sc, CS4281PCI_PPLVC, 7); 718 cs4281_wr(sc, CS4281PCI_PPRVC, 7); 719 720 return 0; 721 } 722 723 /* -------------------------------------------------------------------- */ 724 /* Probe and attach the card */ 725 726 static int 727 cs4281_pci_probe(device_t dev) 728 { 729 char *s = NULL; 730 731 switch (pci_get_devid(dev)) { 732 case CS4281_PCI_ID: 733 s = "Crystal Semiconductor CS4281"; 734 break; 735 } 736 737 if (s) 738 device_set_desc(dev, s); 739 return s ? BUS_PROBE_DEFAULT : ENXIO; 740 } 741 742 static int 743 cs4281_pci_attach(device_t dev) 744 { 745 struct sc_info *sc; 746 struct ac97_info *codec = NULL; 747 u_int32_t data; 748 char status[SND_STATUSLEN]; 749 750 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 751 sc->dev = dev; 752 sc->type = pci_get_devid(dev); 753 754 data = pci_read_config(dev, PCIR_COMMAND, 2); 755 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 756 pci_write_config(dev, PCIR_COMMAND, data, 2); 757 758 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 759 /* Reset the power state. */ 760 device_printf(dev, "chip is in D%d power mode " 761 "-- setting to D0\n", pci_get_powerstate(dev)); 762 763 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 764 } 765 766 sc->regid = PCIR_BAR(0); 767 sc->regtype = SYS_RES_MEMORY; 768 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid, 769 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE); 770 if (!sc->reg) { 771 sc->regtype = SYS_RES_IOPORT; 772 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid, 773 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE); 774 if (!sc->reg) { 775 device_printf(dev, "unable to allocate register space\n"); 776 goto bad; 777 } 778 } 779 sc->st = rman_get_bustag(sc->reg); 780 sc->sh = rman_get_bushandle(sc->reg); 781 782 sc->memid = PCIR_BAR(1); 783 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->memid, 0, 784 ~0, CS4281PCI_BA1_SIZE, RF_ACTIVE); 785 if (sc->mem == NULL) { 786 device_printf(dev, "unable to allocate fifo space\n"); 787 goto bad; 788 } 789 790 sc->irqid = 0; 791 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 792 RF_ACTIVE | RF_SHAREABLE); 793 if (!sc->irq) { 794 device_printf(dev, "unable to allocate interrupt\n"); 795 goto bad; 796 } 797 798 if (snd_setup_intr(dev, sc->irq, 0, cs4281_intr, sc, &sc->ih)) { 799 device_printf(dev, "unable to setup interrupt\n"); 800 goto bad; 801 } 802 803 sc->bufsz = pcm_getbuffersize(dev, 4096, CS4281_DEFAULT_BUFSZ, 65536); 804 805 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 806 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 807 /*highaddr*/BUS_SPACE_MAXADDR, 808 /*filter*/NULL, /*filterarg*/NULL, 809 /*maxsize*/sc->bufsz, /*nsegments*/1, 810 /*maxsegz*/0x3ffff, 811 /*flags*/0, 812 &sc->parent_dmat) != 0) { 813 device_printf(dev, "unable to create dma tag\n"); 814 goto bad; 815 } 816 817 /* power up */ 818 cs4281_power(sc, 0); 819 820 /* init chip */ 821 if (cs4281_init(sc) == -1) { 822 device_printf(dev, "unable to initialize the card\n"); 823 goto bad; 824 } 825 826 /* create/init mixer */ 827 codec = AC97_CREATE(dev, sc, cs4281_ac97); 828 if (codec == NULL) 829 goto bad; 830 831 mixer_init(dev, ac97_getmixerclass(), codec); 832 833 if (pcm_register(dev, sc, 1, 1)) 834 goto bad; 835 836 pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc); 837 pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc); 838 839 ksnprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s", 840 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory", 841 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cs4281)); 842 pcm_setstatus(dev, status); 843 844 return 0; 845 846 bad: 847 if (codec) 848 ac97_destroy(codec); 849 if (sc->reg) 850 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 851 if (sc->mem) 852 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem); 853 if (sc->ih) 854 bus_teardown_intr(dev, sc->irq, sc->ih); 855 if (sc->irq) 856 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 857 if (sc->parent_dmat) 858 bus_dma_tag_destroy(sc->parent_dmat); 859 kfree(sc, M_DEVBUF); 860 861 return ENXIO; 862 } 863 864 static int 865 cs4281_pci_detach(device_t dev) 866 { 867 int r; 868 struct sc_info *sc; 869 870 r = pcm_unregister(dev); 871 if (r) 872 return r; 873 874 sc = pcm_getdevinfo(dev); 875 876 /* power off */ 877 cs4281_power(sc, 3); 878 879 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 880 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem); 881 bus_teardown_intr(dev, sc->irq, sc->ih); 882 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 883 bus_dma_tag_destroy(sc->parent_dmat); 884 kfree(sc, M_DEVBUF); 885 886 return 0; 887 } 888 889 static int 890 cs4281_pci_suspend(device_t dev) 891 { 892 struct sc_info *sc; 893 894 sc = pcm_getdevinfo(dev); 895 896 sc->rch.dma_active = adcdac_go(&sc->rch, 0); 897 sc->pch.dma_active = adcdac_go(&sc->pch, 0); 898 899 cs4281_power(sc, 3); 900 901 return 0; 902 } 903 904 static int 905 cs4281_pci_resume(device_t dev) 906 { 907 struct sc_info *sc; 908 909 sc = pcm_getdevinfo(dev); 910 911 /* power up */ 912 cs4281_power(sc, 0); 913 914 /* initialize chip */ 915 if (cs4281_init(sc) == -1) { 916 device_printf(dev, "unable to reinitialize the card\n"); 917 return ENXIO; 918 } 919 920 /* restore mixer state */ 921 if (mixer_reinit(dev) == -1) { 922 device_printf(dev, "unable to reinitialize the mixer\n"); 923 return ENXIO; 924 } 925 926 /* restore chip state */ 927 cs4281chan_setspeed(NULL, &sc->rch, sc->rch.spd); 928 cs4281chan_setblocksize(NULL, &sc->rch, sc->rch.blksz); 929 cs4281chan_setformat(NULL, &sc->rch, sc->rch.fmt); 930 adcdac_go(&sc->rch, sc->rch.dma_active); 931 932 cs4281chan_setspeed(NULL, &sc->pch, sc->pch.spd); 933 cs4281chan_setblocksize(NULL, &sc->pch, sc->pch.blksz); 934 cs4281chan_setformat(NULL, &sc->pch, sc->pch.fmt); 935 adcdac_go(&sc->pch, sc->pch.dma_active); 936 937 return 0; 938 } 939 940 static device_method_t cs4281_methods[] = { 941 /* Device interface */ 942 DEVMETHOD(device_probe, cs4281_pci_probe), 943 DEVMETHOD(device_attach, cs4281_pci_attach), 944 DEVMETHOD(device_detach, cs4281_pci_detach), 945 DEVMETHOD(device_suspend, cs4281_pci_suspend), 946 DEVMETHOD(device_resume, cs4281_pci_resume), 947 DEVMETHOD_END 948 }; 949 950 static driver_t cs4281_driver = { 951 "pcm", 952 cs4281_methods, 953 PCM_SOFTC_SIZE, 954 }; 955 956 DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, pcm_devclass, NULL, NULL); 957 MODULE_DEPEND(snd_cs4281, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 958 MODULE_VERSION(snd_cs4281, 1); 959