1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/sound/pci/hda/hdac.c,v 1.36.2.3 2007/06/21 20:58:44 ariff Exp $ 28 * $DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.9 2007/07/22 18:53:19 dillon Exp $ 29 */ 30 31 /* 32 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 33 * that this driver still in its early stage, and possible of rewrite are 34 * pretty much guaranteed. There are supposedly several distinct parent/child 35 * busses to make this "perfect", but as for now and for the sake of 36 * simplicity, everything is gobble up within single source. 37 * 38 * List of subsys: 39 * 1) HDA Controller support 40 * 2) HDA Codecs support, which may include 41 * - HDA 42 * - Modem 43 * - HDMI 44 * 3) Widget parser - the real magic of why this driver works on so 45 * many hardwares with minimal vendor specific quirk. The original 46 * parser was written using Ruby and can be found at 47 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 48 * ruby parser take the verbose dmesg dump as its input. Refer to 49 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 50 * interesting documents, especially UAA (Universal Audio Architecture). 51 * 4) Possible vendor specific support. 52 * (snd_hda_intel, snd_hda_ati, etc..) 53 * 54 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 55 * Compaq V3000 with Conexant HDA. 56 * 57 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 58 * * * 59 * * This driver is a collaborative effort made by: * 60 * * * 61 * * Stephane E. Potvin <sepotvin@videotron.ca> * 62 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 63 * * Wesley Morgan <morganw@chemikals.org> * 64 * * Daniel Eischen <deischen@FreeBSD.org> * 65 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 66 * * Ariff Abdullah <ariff@FreeBSD.org> * 67 * * * 68 * * ....and various people from freebsd-multimedia@FreeBSD.org * 69 * * * 70 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 71 */ 72 73 #include <sys/ctype.h> 74 75 #include <dev/sound/pcm/sound.h> 76 #include <bus/pci/pcireg.h> 77 #include <bus/pci/pcivar.h> 78 79 #include <dev/sound/pci/hda/hdac_private.h> 80 #include <dev/sound/pci/hda/hdac_reg.h> 81 #include <dev/sound/pci/hda/hda_reg.h> 82 #include <dev/sound/pci/hda/hdac.h> 83 84 #include "mixer_if.h" 85 86 #define HDA_DRV_TEST_REV "20070619_0045" 87 #define HDA_WIDGET_PARSER_REV 1 88 89 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.9 2007/07/22 18:53:19 dillon Exp $"); 90 91 #define HDA_BOOTVERBOSE(stmt) do { \ 92 if (bootverbose != 0) { \ 93 stmt \ 94 } \ 95 } while(0) 96 97 #if 1 98 #undef HDAC_INTR_EXTRA 99 #define HDAC_INTR_EXTRA 1 100 #endif 101 102 #define hdac_lock(sc) snd_mtxlock((sc)->lock) 103 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 104 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 105 #define hdac_lockowned(sc) (1)/* mtx_owned((sc)->lock) */ 106 107 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 108 #include <machine/specialreg.h> 109 #define HDAC_DMA_ATTR(sc, v, s, attr) do { \ 110 vm_offset_t va = (vm_offset_t)(v); \ 111 vm_size_t sz = (vm_size_t)(s); \ 112 if ((sc) != NULL && (sc)->nocache != 0 && va != 0 && sz != 0) \ 113 (void)pmap_change_attr(va, sz, (attr)); \ 114 } while(0) 115 #else 116 #define HDAC_DMA_ATTR(...) 117 #endif 118 119 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 120 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 121 (fl) == 0xffffffff || \ 122 (((fl) & 0xffff0000) == 0xffff0000 && \ 123 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 124 (((fl) & 0x0000ffff) == 0x0000ffff && \ 125 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 126 #define HDA_MATCH_ALL 0xffffffff 127 #define HDAC_INVALID 0xffffffff 128 129 /* Default controller / jack sense poll: 250ms */ 130 #define HDAC_POLL_INTERVAL max(hz >> 2, 1) 131 132 #define HDA_MODEL_CONSTRUCT(vendor, model) \ 133 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 134 135 /* Controller models */ 136 137 /* Intel */ 138 #define INTEL_VENDORID 0x8086 139 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 140 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 141 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 142 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 143 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 144 145 /* Nvidia */ 146 #define NVIDIA_VENDORID 0x10de 147 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 148 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 149 #define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 150 #define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 151 #define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 152 #define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 153 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 154 155 /* ATI */ 156 #define ATI_VENDORID 0x1002 157 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 158 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 159 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 160 161 /* VIA */ 162 #define VIA_VENDORID 0x1106 163 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 164 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 165 166 /* SiS */ 167 #define SIS_VENDORID 0x1039 168 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 169 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 170 171 /* OEM/subvendors */ 172 173 /* Intel */ 174 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 175 176 /* HP/Compaq */ 177 #define HP_VENDORID 0x103c 178 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 179 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 180 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 181 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 182 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 183 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 184 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 185 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 186 /* What is wrong with XN 2563 anyway? (Got the picture ?) */ 187 #define HP_NX6325_SUBVENDORX 0x103c30b0 188 189 /* Dell */ 190 #define DELL_VENDORID 0x1028 191 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 192 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 193 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 194 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 195 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 196 197 /* Clevo */ 198 #define CLEVO_VENDORID 0x1558 199 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 200 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 201 202 /* Acer */ 203 #define ACER_VENDORID 0x1025 204 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 205 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 206 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 207 208 /* Asus */ 209 #define ASUS_VENDORID 0x1043 210 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 211 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 212 #define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 213 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 214 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 215 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 216 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 217 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 218 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 219 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 220 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 221 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 222 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 223 #define ASUS_VMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 224 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 225 226 /* IBM / Lenovo */ 227 #define IBM_VENDORID 0x1014 228 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 229 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 230 231 /* Lenovo */ 232 #define LENOVO_VENDORID 0x17aa 233 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 234 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 235 236 /* Samsung */ 237 #define SAMSUNG_VENDORID 0x144d 238 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 239 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 240 241 /* Medion ? */ 242 #define MEDION_VENDORID 0x161f 243 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 244 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 245 246 /* 247 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 248 * instead of their own, which is beyond my comprehension 249 * (see HDA_CODEC_STAC9221 below). 250 */ 251 #define APPLE_INTEL_MAC 0x76808384 252 253 /* LG Electronics */ 254 #define LG_VENDORID 0x1854 255 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 256 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 257 258 /* Fujitsu Siemens */ 259 #define FS_VENDORID 0x1734 260 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 261 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 262 263 /* Toshiba */ 264 #define TOSHIBA_VENDORID 0x1179 265 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 266 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 267 268 /* Micro-Star International (MSI) */ 269 #define MSI_VENDORID 0x1462 270 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 271 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 272 273 /* Uniwill ? */ 274 #define UNIWILL_VENDORID 0x1584 275 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 276 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 277 278 279 /* Misc constants.. */ 280 #define HDA_AMP_MUTE_DEFAULT (0xffffffff) 281 #define HDA_AMP_MUTE_NONE (0) 282 #define HDA_AMP_MUTE_LEFT (1 << 0) 283 #define HDA_AMP_MUTE_RIGHT (1 << 1) 284 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 285 286 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 287 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 288 289 #define HDA_DAC_PATH (1 << 0) 290 #define HDA_ADC_PATH (1 << 1) 291 #define HDA_ADC_RECSEL (1 << 2) 292 293 #define HDA_DAC_LOCKED (1 << 3) 294 #define HDA_ADC_LOCKED (1 << 4) 295 296 #define HDA_CTL_OUT (1 << 0) 297 #define HDA_CTL_IN (1 << 1) 298 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 299 300 #define HDA_GPIO_MAX 8 301 /* 0 - 7 = GPIO , 8 = Flush */ 302 #define HDA_QUIRK_GPIO0 (1 << 0) 303 #define HDA_QUIRK_GPIO1 (1 << 1) 304 #define HDA_QUIRK_GPIO2 (1 << 2) 305 #define HDA_QUIRK_GPIO3 (1 << 3) 306 #define HDA_QUIRK_GPIO4 (1 << 4) 307 #define HDA_QUIRK_GPIO5 (1 << 5) 308 #define HDA_QUIRK_GPIO6 (1 << 6) 309 #define HDA_QUIRK_GPIO7 (1 << 7) 310 #define HDA_QUIRK_GPIOFLUSH (1 << 8) 311 312 /* 9 - 25 = anything else */ 313 #define HDA_QUIRK_SOFTPCMVOL (1 << 9) 314 #define HDA_QUIRK_FIXEDRATE (1 << 10) 315 #define HDA_QUIRK_FORCESTEREO (1 << 11) 316 #define HDA_QUIRK_EAPDINV (1 << 12) 317 #define HDA_QUIRK_DMAPOS (1 << 13) 318 319 /* 26 - 31 = vrefs */ 320 #define HDA_QUIRK_IVREF50 (1 << 26) 321 #define HDA_QUIRK_IVREF80 (1 << 27) 322 #define HDA_QUIRK_IVREF100 (1 << 28) 323 #define HDA_QUIRK_OVREF50 (1 << 29) 324 #define HDA_QUIRK_OVREF80 (1 << 30) 325 #define HDA_QUIRK_OVREF100 (1 << 31) 326 327 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 328 HDA_QUIRK_IVREF100) 329 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 330 HDA_QUIRK_OVREF100) 331 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 332 333 #define SOUND_MASK_SKIP (1 << 30) 334 #define SOUND_MASK_DISABLE (1 << 31) 335 336 static const struct { 337 char *key; 338 uint32_t value; 339 } hdac_quirks_tab[] = { 340 { "gpio0", HDA_QUIRK_GPIO0 }, 341 { "gpio1", HDA_QUIRK_GPIO1 }, 342 { "gpio2", HDA_QUIRK_GPIO2 }, 343 { "gpio3", HDA_QUIRK_GPIO3 }, 344 { "gpio4", HDA_QUIRK_GPIO4 }, 345 { "gpio5", HDA_QUIRK_GPIO5 }, 346 { "gpio6", HDA_QUIRK_GPIO6 }, 347 { "gpio7", HDA_QUIRK_GPIO7 }, 348 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 349 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 350 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 351 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 352 { "eapdinv", HDA_QUIRK_EAPDINV }, 353 { "dmapos", HDA_QUIRK_DMAPOS }, 354 { "ivref50", HDA_QUIRK_IVREF50 }, 355 { "ivref80", HDA_QUIRK_IVREF80 }, 356 { "ivref100", HDA_QUIRK_IVREF100 }, 357 { "ovref50", HDA_QUIRK_OVREF50 }, 358 { "ovref80", HDA_QUIRK_OVREF80 }, 359 { "ovref100", HDA_QUIRK_OVREF100 }, 360 { "ivref", HDA_QUIRK_IVREF }, 361 { "ovref", HDA_QUIRK_OVREF }, 362 { "vref", HDA_QUIRK_VREF }, 363 }; 364 #define HDAC_QUIRKS_TAB_LEN \ 365 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 366 367 #define HDA_BDL_MIN 2 368 #define HDA_BDL_MAX 256 369 #define HDA_BDL_DEFAULT HDA_BDL_MIN 370 371 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 372 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 373 374 #define HDA_BUFSZ_MIN 4096 375 #define HDA_BUFSZ_MAX 65536 376 #define HDA_BUFSZ_DEFAULT 16384 377 378 #define HDA_PARSE_MAXDEPTH 10 379 380 #define HDAC_UNSOLTAG_EVENT_HP 0x00 381 #define HDAC_UNSOLTAG_EVENT_TEST 0x01 382 383 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 384 385 enum { 386 HDA_PARSE_MIXER, 387 HDA_PARSE_DIRECT 388 }; 389 390 /* Default */ 391 static uint32_t hdac_fmt[] = { 392 AFMT_STEREO | AFMT_S16_LE, 393 0 394 }; 395 396 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 397 398 static const struct { 399 uint32_t model; 400 char *desc; 401 } hdac_devices[] = { 402 { HDA_INTEL_82801F, "Intel 82801F" }, 403 { HDA_INTEL_82801G, "Intel 82801G" }, 404 { HDA_INTEL_82801H, "Intel 82801H" }, 405 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 406 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 407 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 408 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 409 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 410 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 411 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 412 { HDA_ATI_SB450, "ATI SB450" }, 413 { HDA_ATI_SB600, "ATI SB600" }, 414 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 415 { HDA_SIS_966, "SiS 966" }, 416 /* Unknown */ 417 { HDA_INTEL_ALL, "Intel (Unknown)" }, 418 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 419 { HDA_ATI_ALL, "ATI (Unknown)" }, 420 { HDA_VIA_ALL, "VIA (Unknown)" }, 421 { HDA_SIS_ALL, "SiS (Unknown)" }, 422 }; 423 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 424 425 static const struct { 426 uint16_t vendor; 427 uint8_t reg; 428 uint8_t mask; 429 uint8_t enable; 430 } hdac_pcie_snoop[] = { 431 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 432 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 433 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 434 }; 435 #define HDAC_PCIESNOOP_LEN \ 436 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 437 438 static const struct { 439 uint32_t rate; 440 int valid; 441 uint16_t base; 442 uint16_t mul; 443 uint16_t div; 444 } hda_rate_tab[] = { 445 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 446 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 447 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 448 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 449 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 450 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 451 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 452 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 453 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 454 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 455 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 456 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 457 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 458 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 459 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 460 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 461 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 462 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 463 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 464 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 465 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 466 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 467 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 468 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 469 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 470 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 471 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 472 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 473 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 474 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 475 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 476 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 477 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 478 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 479 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 480 }; 481 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 482 483 /* All codecs you can eat... */ 484 #define HDA_CODEC_CONSTRUCT(vendor, id) \ 485 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 486 487 /* Realtek */ 488 #define REALTEK_VENDORID 0x10ec 489 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 490 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 491 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 492 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 493 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 494 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 495 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 496 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 497 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 498 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 499 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 500 501 /* Analog Devices */ 502 #define ANALOGDEVICES_VENDORID 0x11d4 503 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 504 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 505 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 506 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 507 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 508 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 509 510 /* CMedia */ 511 #define CMEDIA_VENDORID 0x434d 512 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 513 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 514 515 /* Sigmatel */ 516 #define SIGMATEL_VENDORID 0x8384 517 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 518 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 519 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 520 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 521 #define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 522 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 523 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 524 525 /* 526 * Conexant 527 * 528 * Ok, the truth is, I don't have any idea at all whether 529 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 530 * place that tell me it is "Venice" is from its Windows driver INF. 531 * 532 * Venice - CX????? 533 * Waikiki - CX20551-22 534 */ 535 #define CONEXANT_VENDORID 0x14f1 536 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 537 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 538 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 539 540 /* VIA */ 541 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 542 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 543 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 544 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 545 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 546 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 547 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 548 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 549 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 550 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 551 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 552 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 553 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 554 555 556 /* Codecs */ 557 static const struct { 558 uint32_t id; 559 char *name; 560 } hdac_codecs[] = { 561 { HDA_CODEC_ALC260, "Realtek ALC260" }, 562 { HDA_CODEC_ALC262, "Realtek ALC262" }, 563 { HDA_CODEC_ALC660, "Realtek ALC660" }, 564 { HDA_CODEC_ALC861, "Realtek ALC861" }, 565 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 566 { HDA_CODEC_ALC880, "Realtek ALC880" }, 567 { HDA_CODEC_ALC882, "Realtek ALC882" }, 568 { HDA_CODEC_ALC883, "Realtek ALC883" }, 569 { HDA_CODEC_ALC885, "Realtek ALC885" }, 570 { HDA_CODEC_ALC888, "Realtek ALC888" }, 571 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 572 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 573 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 574 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 575 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 576 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 577 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 578 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 579 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 580 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 581 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 582 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 583 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 584 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 585 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 586 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 587 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 588 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 589 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 590 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 591 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 592 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 593 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 594 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 595 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 596 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 597 /* Unknown codec */ 598 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 599 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 600 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 601 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 602 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 603 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 604 }; 605 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 606 607 enum { 608 HDAC_HP_SWITCH_CTL, 609 HDAC_HP_SWITCH_CTRL, 610 HDAC_HP_SWITCH_DEBUG 611 }; 612 613 static const struct { 614 uint32_t model; 615 uint32_t id; 616 int type; 617 int inverted; 618 int polling; 619 int execsense; 620 nid_t hpnid; 621 nid_t spkrnid[8]; 622 nid_t eapdnid; 623 } hdac_hp_switch[] = { 624 /* Specific OEM models */ 625 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 626 0, 0, -1, 17, { 16, -1 }, 16 }, 627 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 628 0, 0, -1, 21, { 16, 17, -1 }, -1 } */ 629 /*{ HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG, 630 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 },*/ 631 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 632 0, 0, -1, 6, { 5, -1 }, 5 }, 633 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 634 0, 0, -1, 6, { 5, -1 }, 5 }, 635 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 636 0, 0, -1, 6, { 5, -1 }, 5 }, 637 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 638 0, 0, -1, 6, { 5, -1 }, -1 }, 639 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 640 0, 0, -1, 13, { 14, -1 }, -1 }, 641 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 642 0, 0, -1, 13, { 14, -1 }, -1 }, 643 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL, 644 0, 0, -1, 6, { 5, 7, -1 }, -1 }, 645 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 646 0, 0, -1, 10, { 13, -1 }, -1 }, 647 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 648 1, 0, -1, 26, { 27, -1 }, -1 }, 649 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 650 0, 0, -1, 27, { 20, -1 }, -1 }, 651 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 652 0, 0, -1, 20, { 21, -1 }, -1 }, 653 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 654 0, 0, -1, 20, { 21, -1 }, -1 }, 655 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 656 0, 0, -1, 20, { 21, -1 }, -1 }, 657 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 658 0, 0, -1, 20, { 27, -1 }, -1 }, 659 /* 660 * All models that at least come from the same vendor with 661 * simmilar codec. 662 */ 663 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 664 0, 0, -1, 17, { 16, -1 }, 16 }, 665 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 666 0, 0, -1, 6, { 5, -1 }, 5 }, 667 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 668 0, 0, -1, 6, { 5, -1 }, -1 }, 669 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 670 0, 0, -1, 13, { 14, -1 }, -1 }, 671 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 672 1, 0, -1, 26, { 27, -1 }, -1 }, 673 #if 0 674 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 675 0, 0, -1, 20, { 21, -1 }, -1 }, 676 #endif 677 }; 678 #define HDAC_HP_SWITCH_LEN \ 679 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 680 681 static const struct { 682 uint32_t model; 683 uint32_t id; 684 nid_t eapdnid; 685 int hp_switch; 686 } hdac_eapd_switch[] = { 687 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 688 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 689 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 690 }; 691 #define HDAC_EAPD_SWITCH_LEN \ 692 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 693 694 /**************************************************************************** 695 * Function prototypes 696 ****************************************************************************/ 697 static void hdac_intr_handler(void *); 698 static int hdac_reset(struct hdac_softc *); 699 static int hdac_get_capabilities(struct hdac_softc *); 700 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 701 static int hdac_dma_alloc(struct hdac_softc *, 702 struct hdac_dma *, bus_size_t); 703 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 704 static int hdac_mem_alloc(struct hdac_softc *); 705 static void hdac_mem_free(struct hdac_softc *); 706 static int hdac_irq_alloc(struct hdac_softc *); 707 static void hdac_irq_free(struct hdac_softc *); 708 static void hdac_corb_init(struct hdac_softc *); 709 static void hdac_rirb_init(struct hdac_softc *); 710 static void hdac_corb_start(struct hdac_softc *); 711 static void hdac_rirb_start(struct hdac_softc *); 712 static void hdac_scan_codecs(struct hdac_softc *); 713 static int hdac_probe_codec(struct hdac_codec *); 714 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 715 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 716 717 static void hdac_attach2(void *); 718 719 static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 720 uint32_t, int); 721 static void hdac_command_send_internal(struct hdac_softc *, 722 struct hdac_command_list *, int); 723 724 static int hdac_probe(device_t); 725 static int hdac_attach(device_t); 726 static int hdac_detach(device_t); 727 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 728 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 729 uint32_t, int, int); 730 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 731 nid_t, int, int); 732 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 733 nid_t, nid_t, int, int, int, int, int, int); 734 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 735 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 736 737 static int hdac_rirb_flush(struct hdac_softc *sc); 738 static int hdac_unsolq_flush(struct hdac_softc *sc); 739 740 #define hdac_command(a1, a2, a3) \ 741 hdac_command_sendone_internal(a1, a2, a3) 742 743 #define hdac_codec_id(d) \ 744 ((uint32_t)((d == NULL) ? 0x00000000 : \ 745 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 746 ((uint32_t)(d)->device_id & 0x0000ffff)))) 747 748 static char * 749 hdac_codec_name(struct hdac_devinfo *devinfo) 750 { 751 uint32_t id; 752 int i; 753 754 id = hdac_codec_id(devinfo); 755 756 for (i = 0; i < HDAC_CODECS_LEN; i++) { 757 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 758 return (hdac_codecs[i].name); 759 } 760 761 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 762 } 763 764 static char * 765 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 766 { 767 static char *ossname[] = SOUND_DEVICE_NAMES; 768 static char *unknown = "???"; 769 int i; 770 771 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 772 if (devmask & (1 << i)) 773 return (ossname[i]); 774 } 775 return (unknown); 776 } 777 778 static void 779 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 780 { 781 static char *ossname[] = SOUND_DEVICE_NAMES; 782 int i, first = 1; 783 784 bzero(buf, len); 785 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 786 if (mask & (1 << i)) { 787 if (first == 0) 788 strlcat(buf, ", ", len); 789 strlcat(buf, ossname[i], len); 790 first = 0; 791 } 792 } 793 } 794 795 static struct hdac_audio_ctl * 796 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 797 { 798 if (devinfo == NULL || 799 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 800 index == NULL || devinfo->function.audio.ctl == NULL || 801 devinfo->function.audio.ctlcnt < 1 || 802 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 803 return (NULL); 804 return (&devinfo->function.audio.ctl[(*index)++]); 805 } 806 807 static struct hdac_audio_ctl * 808 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 809 int index, int cnt) 810 { 811 struct hdac_audio_ctl *ctl, *retctl = NULL; 812 int i, at, atindex, found = 0; 813 814 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 815 return (NULL); 816 817 at = cnt; 818 if (at == 0) 819 at = 1; 820 else if (at < 0) 821 at = -1; 822 atindex = index; 823 if (atindex < 0) 824 atindex = -1; 825 826 i = 0; 827 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 828 if (ctl->enable == 0 || ctl->widget == NULL) 829 continue; 830 if (!(ctl->widget->nid == nid && (atindex == -1 || 831 ctl->index == atindex))) 832 continue; 833 found++; 834 if (found == cnt) 835 return (ctl); 836 retctl = ctl; 837 } 838 839 return ((at == -1) ? retctl : NULL); 840 } 841 842 static void 843 hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 844 { 845 struct hdac_softc *sc; 846 struct hdac_widget *w; 847 struct hdac_audio_ctl *ctl; 848 uint32_t val, id, res; 849 int i = 0, j, forcemute; 850 nid_t cad; 851 852 if (devinfo == NULL || devinfo->codec == NULL || 853 devinfo->codec->sc == NULL) 854 return; 855 856 sc = devinfo->codec->sc; 857 cad = devinfo->codec->cad; 858 id = hdac_codec_id(devinfo); 859 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 860 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 861 sc->pci_subvendor) && 862 hdac_hp_switch[i].id == id) 863 break; 864 } 865 866 if (i >= HDAC_HP_SWITCH_LEN) 867 return; 868 869 forcemute = 0; 870 if (hdac_hp_switch[i].eapdnid != -1) { 871 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 872 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 873 forcemute = (w->param.eapdbtl & 874 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 875 } 876 877 if (hdac_hp_switch[i].execsense != -1) 878 hdac_command(sc, 879 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 880 hdac_hp_switch[i].execsense), cad); 881 res = hdac_command(sc, 882 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 883 HDA_BOOTVERBOSE( 884 device_printf(sc->dev, 885 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 886 hdac_hp_switch[i].hpnid, res); 887 ); 888 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 889 res ^= hdac_hp_switch[i].inverted; 890 891 switch (hdac_hp_switch[i].type) { 892 case HDAC_HP_SWITCH_CTL: 893 ctl = hdac_audio_ctl_amp_get(devinfo, 894 hdac_hp_switch[i].hpnid, 0, 1); 895 if (ctl != NULL) { 896 val = (res != 0 && forcemute == 0) ? 897 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 898 if (val != ctl->muted) { 899 ctl->muted = val; 900 hdac_audio_ctl_amp_set(ctl, 901 HDA_AMP_MUTE_DEFAULT, ctl->left, 902 ctl->right); 903 } 904 } 905 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 906 ctl = hdac_audio_ctl_amp_get(devinfo, 907 hdac_hp_switch[i].spkrnid[j], 0, 1); 908 if (ctl == NULL) 909 continue; 910 val = (res != 0 || forcemute == 1) ? 911 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 912 if (val == ctl->muted) 913 continue; 914 ctl->muted = val; 915 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 916 ctl->left, ctl->right); 917 } 918 break; 919 case HDAC_HP_SWITCH_CTRL: 920 if (res != 0) { 921 /* HP in */ 922 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 923 if (w != NULL && w->type == 924 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 925 if (forcemute == 0) 926 val = w->wclass.pin.ctrl | 927 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 928 else 929 val = w->wclass.pin.ctrl & 930 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 931 if (val != w->wclass.pin.ctrl) { 932 w->wclass.pin.ctrl = val; 933 hdac_command(sc, 934 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 935 w->nid, w->wclass.pin.ctrl), cad); 936 } 937 } 938 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 939 w = hdac_widget_get(devinfo, 940 hdac_hp_switch[i].spkrnid[j]); 941 if (w == NULL || w->type != 942 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 943 continue; 944 val = w->wclass.pin.ctrl & 945 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 946 if (val == w->wclass.pin.ctrl) 947 continue; 948 w->wclass.pin.ctrl = val; 949 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 950 cad, w->nid, w->wclass.pin.ctrl), cad); 951 } 952 } else { 953 /* HP out */ 954 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 955 if (w != NULL && w->type == 956 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 957 val = w->wclass.pin.ctrl & 958 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 959 if (val != w->wclass.pin.ctrl) { 960 w->wclass.pin.ctrl = val; 961 hdac_command(sc, 962 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 963 w->nid, w->wclass.pin.ctrl), cad); 964 } 965 } 966 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 967 w = hdac_widget_get(devinfo, 968 hdac_hp_switch[i].spkrnid[j]); 969 if (w == NULL || w->type != 970 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 971 continue; 972 if (forcemute == 0) 973 val = w->wclass.pin.ctrl | 974 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 975 else 976 val = w->wclass.pin.ctrl & 977 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 978 if (val == w->wclass.pin.ctrl) 979 continue; 980 w->wclass.pin.ctrl = val; 981 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 982 cad, w->nid, w->wclass.pin.ctrl), cad); 983 } 984 } 985 break; 986 case HDAC_HP_SWITCH_DEBUG: 987 if (hdac_hp_switch[i].execsense != -1) 988 hdac_command(sc, 989 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 990 hdac_hp_switch[i].execsense), cad); 991 res = hdac_command(sc, 992 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 993 device_printf(sc->dev, 994 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 995 hdac_hp_switch[i].hpnid, res); 996 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 997 w = hdac_widget_get(devinfo, 998 hdac_hp_switch[i].spkrnid[j]); 999 if (w == NULL || w->type != 1000 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1001 continue; 1002 if (hdac_hp_switch[i].execsense != -1) 1003 hdac_command(sc, 1004 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 1005 hdac_hp_switch[i].execsense), cad); 1006 res = hdac_command(sc, 1007 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 1008 device_printf(sc->dev, 1009 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1010 j + 1, w->nid, res); 1011 } 1012 break; 1013 default: 1014 break; 1015 } 1016 } 1017 1018 static void 1019 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1020 { 1021 struct hdac_softc *sc; 1022 struct hdac_devinfo *devinfo = NULL; 1023 device_t *devlist = NULL; 1024 int devcount, i; 1025 1026 if (codec == NULL || codec->sc == NULL) 1027 return; 1028 1029 sc = codec->sc; 1030 1031 HDA_BOOTVERBOSE( 1032 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 1033 ); 1034 1035 device_get_children(sc->dev, &devlist, &devcount); 1036 for (i = 0; devlist != NULL && i < devcount; i++) { 1037 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 1038 if (devinfo != NULL && devinfo->node_type == 1039 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 1040 devinfo->codec != NULL && 1041 devinfo->codec->cad == codec->cad) { 1042 break; 1043 } else 1044 devinfo = NULL; 1045 } 1046 if (devlist != NULL) 1047 kfree(devlist, M_TEMP); 1048 1049 if (devinfo == NULL) 1050 return; 1051 1052 switch (tag) { 1053 case HDAC_UNSOLTAG_EVENT_HP: 1054 hdac_hp_switch_handler(devinfo); 1055 break; 1056 case HDAC_UNSOLTAG_EVENT_TEST: 1057 device_printf(sc->dev, "Unsol Test!\n"); 1058 break; 1059 default: 1060 break; 1061 } 1062 } 1063 1064 static int 1065 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1066 { 1067 /* XXX to be removed */ 1068 #ifdef HDAC_INTR_EXTRA 1069 uint32_t res; 1070 #endif 1071 1072 if (ch->blkcnt == 0) 1073 return (0); 1074 1075 /* XXX to be removed */ 1076 #ifdef HDAC_INTR_EXTRA 1077 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1078 #endif 1079 1080 /* XXX to be removed */ 1081 #ifdef HDAC_INTR_EXTRA 1082 HDA_BOOTVERBOSE( 1083 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1084 device_printf(sc->dev, 1085 "PCMDIR_%s intr triggered beyond stream boundary:" 1086 "%08x\n", 1087 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1088 ); 1089 #endif 1090 1091 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1092 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1093 1094 /* XXX to be removed */ 1095 #ifdef HDAC_INTR_EXTRA 1096 if (res & HDAC_SDSTS_BCIS) { 1097 #endif 1098 return (1); 1099 /* XXX to be removed */ 1100 #ifdef HDAC_INTR_EXTRA 1101 } 1102 #endif 1103 1104 return (0); 1105 } 1106 1107 /**************************************************************************** 1108 * void hdac_intr_handler(void *) 1109 * 1110 * Interrupt handler. Processes interrupts received from the hdac. 1111 ****************************************************************************/ 1112 static void 1113 hdac_intr_handler(void *context) 1114 { 1115 struct hdac_softc *sc; 1116 uint32_t intsts; 1117 uint8_t rirbsts; 1118 struct hdac_rirb *rirb_base; 1119 uint32_t trigger = 0; 1120 1121 sc = (struct hdac_softc *)context; 1122 1123 hdac_lock(sc); 1124 if (sc->polling != 0) { 1125 hdac_unlock(sc); 1126 return; 1127 } 1128 /* Do we have anything to do? */ 1129 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1130 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1131 hdac_unlock(sc); 1132 return; 1133 } 1134 1135 /* Was this a controller interrupt? */ 1136 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1137 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1138 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1139 /* Get as many responses that we can */ 1140 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1141 HDAC_WRITE_1(&sc->mem, 1142 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1143 hdac_rirb_flush(sc); 1144 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1145 } 1146 /* XXX to be removed */ 1147 /* Clear interrupt and exit */ 1148 #ifdef HDAC_INTR_EXTRA 1149 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1150 #endif 1151 } 1152 1153 hdac_unsolq_flush(sc); 1154 1155 if (intsts & HDAC_INTSTS_SIS_MASK) { 1156 if ((intsts & (1 << sc->num_iss)) && 1157 hdac_stream_intr(sc, &sc->play) != 0) 1158 trigger |= 1; 1159 if ((intsts & (1 << 0)) && 1160 hdac_stream_intr(sc, &sc->rec) != 0) 1161 trigger |= 2; 1162 /* XXX to be removed */ 1163 #ifdef HDAC_INTR_EXTRA 1164 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1165 HDAC_INTSTS_SIS_MASK); 1166 #endif 1167 } 1168 1169 hdac_unlock(sc); 1170 1171 if (trigger & 1) 1172 chn_intr(sc->play.c); 1173 if (trigger & 2) 1174 chn_intr(sc->rec.c); 1175 } 1176 1177 /**************************************************************************** 1178 * int hdac_reset(hdac_softc *) 1179 * 1180 * Reset the hdac to a quiescent and known state. 1181 ****************************************************************************/ 1182 static int 1183 hdac_reset(struct hdac_softc *sc) 1184 { 1185 uint32_t gctl; 1186 int count, i; 1187 1188 /* 1189 * Stop all Streams DMA engine 1190 */ 1191 for (i = 0; i < sc->num_iss; i++) 1192 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1193 for (i = 0; i < sc->num_oss; i++) 1194 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1195 for (i = 0; i < sc->num_bss; i++) 1196 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1197 1198 /* 1199 * Stop Control DMA engines. 1200 */ 1201 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1202 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1203 1204 /* 1205 * Reset DMA position buffer. 1206 */ 1207 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1208 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1209 1210 /* 1211 * Reset the controller. The reset must remain asserted for 1212 * a minimum of 100us. 1213 */ 1214 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1215 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1216 count = 10000; 1217 do { 1218 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1219 if (!(gctl & HDAC_GCTL_CRST)) 1220 break; 1221 DELAY(10); 1222 } while (--count); 1223 if (gctl & HDAC_GCTL_CRST) { 1224 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1225 return (ENXIO); 1226 } 1227 DELAY(100); 1228 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1229 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1230 count = 10000; 1231 do { 1232 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1233 if (gctl & HDAC_GCTL_CRST) 1234 break; 1235 DELAY(10); 1236 } while (--count); 1237 if (!(gctl & HDAC_GCTL_CRST)) { 1238 device_printf(sc->dev, "Device stuck in reset\n"); 1239 return (ENXIO); 1240 } 1241 1242 /* 1243 * Wait for codecs to finish their own reset sequence. The delay here 1244 * should be of 250us but for some reasons, on it's not enough on my 1245 * computer. Let's use twice as much as necessary to make sure that 1246 * it's reset properly. 1247 */ 1248 DELAY(1000); 1249 1250 return (0); 1251 } 1252 1253 1254 /**************************************************************************** 1255 * int hdac_get_capabilities(struct hdac_softc *); 1256 * 1257 * Retreive the general capabilities of the hdac; 1258 * Number of Input Streams 1259 * Number of Output Streams 1260 * Number of bidirectional Streams 1261 * 64bit ready 1262 * CORB and RIRB sizes 1263 ****************************************************************************/ 1264 static int 1265 hdac_get_capabilities(struct hdac_softc *sc) 1266 { 1267 uint16_t gcap; 1268 uint8_t corbsize, rirbsize; 1269 1270 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1271 sc->num_iss = HDAC_GCAP_ISS(gcap); 1272 sc->num_oss = HDAC_GCAP_OSS(gcap); 1273 sc->num_bss = HDAC_GCAP_BSS(gcap); 1274 1275 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1276 1277 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1278 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1279 HDAC_CORBSIZE_CORBSZCAP_256) 1280 sc->corb_size = 256; 1281 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1282 HDAC_CORBSIZE_CORBSZCAP_16) 1283 sc->corb_size = 16; 1284 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1285 HDAC_CORBSIZE_CORBSZCAP_2) 1286 sc->corb_size = 2; 1287 else { 1288 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1289 __func__, corbsize); 1290 return (ENXIO); 1291 } 1292 1293 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1294 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1295 HDAC_RIRBSIZE_RIRBSZCAP_256) 1296 sc->rirb_size = 256; 1297 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1298 HDAC_RIRBSIZE_RIRBSZCAP_16) 1299 sc->rirb_size = 16; 1300 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1301 HDAC_RIRBSIZE_RIRBSZCAP_2) 1302 sc->rirb_size = 2; 1303 else { 1304 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1305 __func__, rirbsize); 1306 return (ENXIO); 1307 } 1308 1309 return (0); 1310 } 1311 1312 1313 /**************************************************************************** 1314 * void hdac_dma_cb 1315 * 1316 * This function is called by bus_dmamap_load when the mapping has been 1317 * established. We just record the physical address of the mapping into 1318 * the struct hdac_dma passed in. 1319 ****************************************************************************/ 1320 static void 1321 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1322 { 1323 struct hdac_dma *dma; 1324 1325 if (error == 0) { 1326 dma = (struct hdac_dma *)callback_arg; 1327 dma->dma_paddr = segs[0].ds_addr; 1328 } 1329 } 1330 1331 1332 /**************************************************************************** 1333 * int hdac_dma_alloc 1334 * 1335 * This function allocate and setup a dma region (struct hdac_dma). 1336 * It must be freed by a corresponding hdac_dma_free. 1337 ****************************************************************************/ 1338 static int 1339 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1340 { 1341 bus_size_t roundsz; 1342 int result; 1343 int lowaddr; 1344 1345 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1346 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1347 BUS_SPACE_MAXADDR_32BIT; 1348 bzero(dma, sizeof(*dma)); 1349 1350 /* 1351 * Create a DMA tag 1352 */ 1353 result = bus_dma_tag_create(NULL, /* parent */ 1354 HDAC_DMA_ALIGNMENT, /* alignment */ 1355 0, /* boundary */ 1356 lowaddr, /* lowaddr */ 1357 BUS_SPACE_MAXADDR, /* highaddr */ 1358 NULL, /* filtfunc */ 1359 NULL, /* fistfuncarg */ 1360 roundsz, /* maxsize */ 1361 1, /* nsegments */ 1362 roundsz, /* maxsegsz */ 1363 0, /* flags */ 1364 &dma->dma_tag); /* dmat */ 1365 if (result != 0) { 1366 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1367 __func__, result); 1368 goto hdac_dma_alloc_fail; 1369 } 1370 1371 /* 1372 * Allocate DMA memory 1373 */ 1374 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 1375 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1376 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1377 ((sc->nocache != 0) ? BUS_DMA_NOCACHE : 0), &dma->dma_map); 1378 #else 1379 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1380 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->dma_map); 1381 #endif 1382 if (result != 0) { 1383 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1384 __func__, result); 1385 goto hdac_dma_alloc_fail; 1386 } 1387 1388 dma->dma_size = roundsz; 1389 1390 /* 1391 * Map the memory 1392 */ 1393 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1394 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1395 if (result != 0 || dma->dma_paddr == 0) { 1396 if (result == 0) 1397 result = ENOMEM; 1398 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1399 __func__, result); 1400 goto hdac_dma_alloc_fail; 1401 } 1402 1403 HDA_BOOTVERBOSE( 1404 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1405 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1406 ); 1407 1408 return (0); 1409 1410 hdac_dma_alloc_fail: 1411 hdac_dma_free(sc, dma); 1412 1413 return (result); 1414 } 1415 1416 1417 /**************************************************************************** 1418 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1419 * 1420 * Free a struct dhac_dma that has been previously allocated via the 1421 * hdac_dma_alloc function. 1422 ****************************************************************************/ 1423 static void 1424 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1425 { 1426 if (dma->dma_map != NULL) { 1427 #if 0 1428 /* Flush caches */ 1429 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1430 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1431 #endif 1432 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1433 } 1434 if (dma->dma_vaddr != NULL) { 1435 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1436 dma->dma_vaddr = NULL; 1437 } 1438 dma->dma_map = NULL; 1439 if (dma->dma_tag != NULL) { 1440 bus_dma_tag_destroy(dma->dma_tag); 1441 dma->dma_tag = NULL; 1442 } 1443 dma->dma_size = 0; 1444 } 1445 1446 /**************************************************************************** 1447 * int hdac_mem_alloc(struct hdac_softc *) 1448 * 1449 * Allocate all the bus resources necessary to speak with the physical 1450 * controller. 1451 ****************************************************************************/ 1452 static int 1453 hdac_mem_alloc(struct hdac_softc *sc) 1454 { 1455 struct hdac_mem *mem; 1456 1457 mem = &sc->mem; 1458 mem->mem_rid = PCIR_BAR(0); 1459 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1460 &mem->mem_rid, RF_ACTIVE); 1461 if (mem->mem_res == NULL) { 1462 device_printf(sc->dev, 1463 "%s: Unable to allocate memory resource\n", __func__); 1464 return (ENOMEM); 1465 } 1466 mem->mem_tag = rman_get_bustag(mem->mem_res); 1467 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1468 1469 return (0); 1470 } 1471 1472 /**************************************************************************** 1473 * void hdac_mem_free(struct hdac_softc *) 1474 * 1475 * Free up resources previously allocated by hdac_mem_alloc. 1476 ****************************************************************************/ 1477 static void 1478 hdac_mem_free(struct hdac_softc *sc) 1479 { 1480 struct hdac_mem *mem; 1481 1482 mem = &sc->mem; 1483 if (mem->mem_res != NULL) 1484 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1485 mem->mem_res); 1486 mem->mem_res = NULL; 1487 } 1488 1489 /**************************************************************************** 1490 * int hdac_irq_alloc(struct hdac_softc *) 1491 * 1492 * Allocate and setup the resources necessary for interrupt handling. 1493 ****************************************************************************/ 1494 static int 1495 hdac_irq_alloc(struct hdac_softc *sc) 1496 { 1497 struct hdac_irq *irq; 1498 int result; 1499 1500 irq = &sc->irq; 1501 irq->irq_rid = 0x0; 1502 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1503 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1504 if (irq->irq_res == NULL) { 1505 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1506 __func__); 1507 goto hdac_irq_alloc_fail; 1508 } 1509 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1510 hdac_intr_handler, sc, &irq->irq_handle); 1511 if (result != 0) { 1512 device_printf(sc->dev, 1513 "%s: Unable to setup interrupt handler (%x)\n", 1514 __func__, result); 1515 goto hdac_irq_alloc_fail; 1516 } 1517 1518 return (0); 1519 1520 hdac_irq_alloc_fail: 1521 hdac_irq_free(sc); 1522 1523 return (ENXIO); 1524 } 1525 1526 /**************************************************************************** 1527 * void hdac_irq_free(struct hdac_softc *) 1528 * 1529 * Free up resources previously allocated by hdac_irq_alloc. 1530 ****************************************************************************/ 1531 static void 1532 hdac_irq_free(struct hdac_softc *sc) 1533 { 1534 struct hdac_irq *irq; 1535 1536 irq = &sc->irq; 1537 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1538 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1539 if (irq->irq_res != NULL) 1540 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1541 irq->irq_res); 1542 irq->irq_handle = NULL; 1543 irq->irq_res = NULL; 1544 } 1545 1546 /**************************************************************************** 1547 * void hdac_corb_init(struct hdac_softc *) 1548 * 1549 * Initialize the corb registers for operations but do not start it up yet. 1550 * The CORB engine must not be running when this function is called. 1551 ****************************************************************************/ 1552 static void 1553 hdac_corb_init(struct hdac_softc *sc) 1554 { 1555 uint8_t corbsize; 1556 uint64_t corbpaddr; 1557 1558 /* Setup the CORB size. */ 1559 switch (sc->corb_size) { 1560 case 256: 1561 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1562 break; 1563 case 16: 1564 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1565 break; 1566 case 2: 1567 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1568 break; 1569 default: 1570 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1571 } 1572 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1573 1574 /* Setup the CORB Address in the hdac */ 1575 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1576 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1577 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1578 1579 /* Set the WP and RP */ 1580 sc->corb_wp = 0; 1581 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1582 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1583 /* 1584 * The HDA specification indicates that the CORBRPRST bit will always 1585 * read as zero. Unfortunately, it seems that at least the 82801G 1586 * doesn't reset the bit to zero, which stalls the corb engine. 1587 * manually reset the bit to zero before continuing. 1588 */ 1589 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1590 1591 /* Enable CORB error reporting */ 1592 #if 0 1593 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1594 #endif 1595 } 1596 1597 /**************************************************************************** 1598 * void hdac_rirb_init(struct hdac_softc *) 1599 * 1600 * Initialize the rirb registers for operations but do not start it up yet. 1601 * The RIRB engine must not be running when this function is called. 1602 ****************************************************************************/ 1603 static void 1604 hdac_rirb_init(struct hdac_softc *sc) 1605 { 1606 uint8_t rirbsize; 1607 uint64_t rirbpaddr; 1608 1609 /* Setup the RIRB size. */ 1610 switch (sc->rirb_size) { 1611 case 256: 1612 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1613 break; 1614 case 16: 1615 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1616 break; 1617 case 2: 1618 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1619 break; 1620 default: 1621 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1622 } 1623 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1624 1625 /* Setup the RIRB Address in the hdac */ 1626 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1627 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1628 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1629 1630 /* Setup the WP and RP */ 1631 sc->rirb_rp = 0; 1632 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1633 1634 if (sc->polling == 0) { 1635 /* Setup the interrupt threshold */ 1636 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1637 1638 /* Enable Overrun and response received reporting */ 1639 #if 0 1640 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1641 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1642 #else 1643 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1644 #endif 1645 } 1646 1647 #if 0 1648 /* 1649 * Make sure that the Host CPU cache doesn't contain any dirty 1650 * cache lines that falls in the rirb. If I understood correctly, it 1651 * should be sufficient to do this only once as the rirb is purely 1652 * read-only from now on. 1653 */ 1654 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1655 BUS_DMASYNC_PREREAD); 1656 #endif 1657 } 1658 1659 /**************************************************************************** 1660 * void hdac_corb_start(hdac_softc *) 1661 * 1662 * Startup the corb DMA engine 1663 ****************************************************************************/ 1664 static void 1665 hdac_corb_start(struct hdac_softc *sc) 1666 { 1667 uint32_t corbctl; 1668 1669 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1670 corbctl |= HDAC_CORBCTL_CORBRUN; 1671 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1672 } 1673 1674 /**************************************************************************** 1675 * void hdac_rirb_start(hdac_softc *) 1676 * 1677 * Startup the rirb DMA engine 1678 ****************************************************************************/ 1679 static void 1680 hdac_rirb_start(struct hdac_softc *sc) 1681 { 1682 uint32_t rirbctl; 1683 1684 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1685 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1686 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1687 } 1688 1689 1690 /**************************************************************************** 1691 * void hdac_scan_codecs(struct hdac_softc *) 1692 * 1693 * Scan the bus for available codecs. 1694 ****************************************************************************/ 1695 static void 1696 hdac_scan_codecs(struct hdac_softc *sc) 1697 { 1698 struct hdac_codec *codec; 1699 int i; 1700 uint16_t statests; 1701 1702 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1703 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1704 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1705 /* We have found a codec. */ 1706 codec = (struct hdac_codec *)kmalloc(sizeof(*codec), 1707 M_HDAC, M_ZERO | M_NOWAIT); 1708 if (codec == NULL) { 1709 device_printf(sc->dev, 1710 "Unable to allocate memory for codec\n"); 1711 continue; 1712 } 1713 codec->commands = NULL; 1714 codec->responses_received = 0; 1715 codec->verbs_sent = 0; 1716 codec->sc = sc; 1717 codec->cad = i; 1718 sc->codecs[i] = codec; 1719 if (hdac_probe_codec(codec) != 0) 1720 break; 1721 } 1722 } 1723 /* All codecs have been probed, now try to attach drivers to them */ 1724 /* bus_generic_attach(sc->dev); */ 1725 } 1726 1727 /**************************************************************************** 1728 * void hdac_probe_codec(struct hdac_softc *, int) 1729 * 1730 * Probe a the given codec_id for available function groups. 1731 ****************************************************************************/ 1732 static int 1733 hdac_probe_codec(struct hdac_codec *codec) 1734 { 1735 struct hdac_softc *sc = codec->sc; 1736 struct hdac_devinfo *devinfo; 1737 uint32_t vendorid, revisionid, subnode; 1738 int startnode; 1739 int endnode; 1740 int i; 1741 nid_t cad = codec->cad; 1742 1743 HDA_BOOTVERBOSE( 1744 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1745 ); 1746 vendorid = hdac_command(sc, 1747 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1748 cad); 1749 revisionid = hdac_command(sc, 1750 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1751 cad); 1752 subnode = hdac_command(sc, 1753 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1754 cad); 1755 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1756 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1757 1758 HDA_BOOTVERBOSE( 1759 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1760 startnode, endnode); 1761 ); 1762 for (i = startnode; i < endnode; i++) { 1763 devinfo = hdac_probe_function(codec, i); 1764 if (devinfo != NULL) { 1765 /* XXX Ignore other FG. */ 1766 devinfo->vendor_id = 1767 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1768 devinfo->device_id = 1769 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1770 devinfo->revision_id = 1771 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1772 devinfo->stepping_id = 1773 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1774 HDA_BOOTVERBOSE( 1775 device_printf(sc->dev, 1776 "HDA_DEBUG: \tFound AFG nid=%d " 1777 "[startnode=%d endnode=%d]\n", 1778 devinfo->nid, startnode, endnode); 1779 ); 1780 return (1); 1781 } 1782 } 1783 1784 HDA_BOOTVERBOSE( 1785 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1786 ); 1787 return (0); 1788 } 1789 1790 static struct hdac_devinfo * 1791 hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1792 { 1793 struct hdac_softc *sc = codec->sc; 1794 struct hdac_devinfo *devinfo; 1795 uint32_t fctgrptype; 1796 nid_t cad = codec->cad; 1797 1798 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1799 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1800 1801 /* XXX For now, ignore other FG. */ 1802 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1803 return (NULL); 1804 1805 devinfo = (struct hdac_devinfo *)kmalloc(sizeof(*devinfo), M_HDAC, 1806 M_NOWAIT | M_ZERO); 1807 if (devinfo == NULL) { 1808 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1809 __func__); 1810 return (NULL); 1811 } 1812 1813 devinfo->nid = nid; 1814 devinfo->node_type = fctgrptype; 1815 devinfo->codec = codec; 1816 1817 hdac_add_child(sc, devinfo); 1818 1819 return (devinfo); 1820 } 1821 1822 static void 1823 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1824 { 1825 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1826 device_set_ivars(devinfo->dev, (void *)devinfo); 1827 /* XXX - Print more information when booting verbose??? */ 1828 } 1829 1830 static void 1831 hdac_widget_connection_parse(struct hdac_widget *w) 1832 { 1833 struct hdac_softc *sc = w->devinfo->codec->sc; 1834 uint32_t res; 1835 int i, j, max, ents, entnum; 1836 nid_t cad = w->devinfo->codec->cad; 1837 nid_t nid = w->nid; 1838 nid_t cnid, addcnid, prevcnid; 1839 1840 w->nconns = 0; 1841 1842 res = hdac_command(sc, 1843 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1844 1845 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1846 1847 if (ents < 1) 1848 return; 1849 1850 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1851 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1852 prevcnid = 0; 1853 1854 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1855 #define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1856 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1857 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1858 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1859 1860 for (i = 0; i < ents; i += entnum) { 1861 res = hdac_command(sc, 1862 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1863 for (j = 0; j < entnum; j++) { 1864 cnid = CONN_CNID(res, entnum, j); 1865 if (cnid == 0) { 1866 if (w->nconns < ents) 1867 device_printf(sc->dev, 1868 "%s: nid=%d WARNING: zero cnid " 1869 "entnum=%d j=%d index=%d " 1870 "entries=%d found=%d res=0x%08x\n", 1871 __func__, nid, entnum, j, i, 1872 ents, w->nconns, res); 1873 else 1874 goto getconns_out; 1875 } 1876 if (cnid < w->devinfo->startnode || 1877 cnid >= w->devinfo->endnode) { 1878 HDA_BOOTVERBOSE( 1879 device_printf(sc->dev, 1880 "%s: GHOST: nid=%d j=%d " 1881 "entnum=%d index=%d res=0x%08x\n", 1882 __func__, nid, j, entnum, i, res); 1883 ); 1884 } 1885 if (CONN_RANGE(res, entnum, j) == 0) 1886 addcnid = cnid; 1887 else if (prevcnid == 0 || prevcnid >= cnid) { 1888 device_printf(sc->dev, 1889 "%s: WARNING: Invalid child range " 1890 "nid=%d index=%d j=%d entnum=%d " 1891 "prevcnid=%d cnid=%d res=0x%08x\n", 1892 __func__, nid, i, j, entnum, prevcnid, 1893 cnid, res); 1894 addcnid = cnid; 1895 } else 1896 addcnid = prevcnid + 1; 1897 while (addcnid <= cnid) { 1898 if (w->nconns > max) { 1899 device_printf(sc->dev, 1900 "%s: nid=%d: Adding %d: " 1901 "Max connection reached! max=%d\n", 1902 __func__, nid, addcnid, max + 1); 1903 goto getconns_out; 1904 } 1905 w->conns[w->nconns++] = addcnid++; 1906 } 1907 prevcnid = cnid; 1908 } 1909 } 1910 1911 getconns_out: 1912 HDA_BOOTVERBOSE( 1913 device_printf(sc->dev, 1914 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n", 1915 __func__, nid, ents, w->nconns); 1916 ); 1917 return; 1918 } 1919 1920 static uint32_t 1921 hdac_widget_pin_getconfig(struct hdac_widget *w) 1922 { 1923 struct hdac_softc *sc; 1924 uint32_t config, orig, id; 1925 nid_t cad, nid; 1926 1927 sc = w->devinfo->codec->sc; 1928 cad = w->devinfo->codec->cad; 1929 nid = w->nid; 1930 id = hdac_codec_id(w->devinfo); 1931 1932 config = hdac_command(sc, 1933 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1934 cad); 1935 orig = config; 1936 1937 /* 1938 * XXX REWRITE!!!! Don't argue! 1939 */ 1940 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1941 switch (nid) { 1942 case 26: 1943 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1944 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1945 break; 1946 case 27: 1947 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1948 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1949 break; 1950 default: 1951 break; 1952 } 1953 } else if (id == HDA_CODEC_ALC880 && 1954 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1955 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1956 /* 1957 * Super broken BIOS 1958 */ 1959 switch (nid) { 1960 case 20: 1961 break; 1962 case 21: 1963 break; 1964 case 22: 1965 break; 1966 case 23: 1967 break; 1968 case 24: /* MIC1 */ 1969 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1970 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1971 break; 1972 case 25: /* XXX MIC2 */ 1973 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1974 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1975 break; 1976 case 26: /* LINE1 */ 1977 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1978 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1979 break; 1980 case 27: /* XXX LINE2 */ 1981 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1982 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1983 break; 1984 case 28: /* CD */ 1985 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1986 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1987 break; 1988 case 30: 1989 break; 1990 case 31: 1991 break; 1992 default: 1993 break; 1994 } 1995 } else if (id == HDA_CODEC_ALC883 && 1996 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 1997 switch (nid) { 1998 case 25: 1999 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2000 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2001 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2002 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2003 break; 2004 case 28: 2005 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2006 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2007 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2008 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2009 break; 2010 default: 2011 break; 2012 } 2013 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2014 HP_V3000_SUBVENDOR) { 2015 switch (nid) { 2016 case 18: 2017 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2018 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2019 break; 2020 case 20: 2021 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2022 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2023 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2024 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2025 break; 2026 case 21: 2027 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2028 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2029 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2030 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2031 break; 2032 default: 2033 break; 2034 } 2035 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2036 HP_DV5000_SUBVENDOR) { 2037 switch (nid) { 2038 case 20: 2039 case 21: 2040 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2041 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2042 break; 2043 default: 2044 break; 2045 } 2046 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2047 ASUS_W6F_SUBVENDOR) { 2048 switch (nid) { 2049 case 11: 2050 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2051 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2052 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2053 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2054 break; 2055 case 15: 2056 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2057 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2058 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2059 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2060 break; 2061 default: 2062 break; 2063 } 2064 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2065 UNIWILL_9075_SUBVENDOR) { 2066 switch (nid) { 2067 case 15: 2068 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2069 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2070 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2071 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2072 break; 2073 default: 2074 break; 2075 } 2076 } else if (id == HDA_CODEC_AD1986A && 2077 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2078 sc->pci_subvendor == ASUS_VMCSM_SUBVENDOR)) { 2079 switch (nid) { 2080 case 28: /* LINE */ 2081 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2082 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2083 break; 2084 case 29: /* MIC */ 2085 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2086 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2087 break; 2088 default: 2089 break; 2090 } 2091 } 2092 2093 HDA_BOOTVERBOSE( 2094 if (config != orig) 2095 device_printf(sc->dev, 2096 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 2097 nid, orig, config); 2098 ); 2099 2100 return (config); 2101 } 2102 2103 static uint32_t 2104 hdac_widget_pin_getcaps(struct hdac_widget *w) 2105 { 2106 struct hdac_softc *sc; 2107 uint32_t caps, orig, id; 2108 nid_t cad, nid; 2109 2110 sc = w->devinfo->codec->sc; 2111 cad = w->devinfo->codec->cad; 2112 nid = w->nid; 2113 id = hdac_codec_id(w->devinfo); 2114 2115 caps = hdac_command(sc, 2116 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2117 orig = caps; 2118 2119 HDA_BOOTVERBOSE( 2120 if (caps != orig) 2121 device_printf(sc->dev, 2122 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 2123 nid, orig, caps); 2124 ); 2125 2126 return (caps); 2127 } 2128 2129 static void 2130 hdac_widget_pin_parse(struct hdac_widget *w) 2131 { 2132 struct hdac_softc *sc = w->devinfo->codec->sc; 2133 uint32_t config, pincap; 2134 char *devstr, *connstr; 2135 nid_t cad = w->devinfo->codec->cad; 2136 nid_t nid = w->nid; 2137 2138 config = hdac_widget_pin_getconfig(w); 2139 w->wclass.pin.config = config; 2140 2141 pincap = hdac_widget_pin_getcaps(w); 2142 w->wclass.pin.cap = pincap; 2143 2144 w->wclass.pin.ctrl = hdac_command(sc, 2145 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 2146 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 2147 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 2148 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 2149 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 2150 2151 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 2152 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 2153 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 2154 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 2155 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 2156 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 2157 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2158 w->param.eapdbtl = hdac_command(sc, 2159 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2160 w->param.eapdbtl &= 0x7; 2161 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2162 } else 2163 w->param.eapdbtl = HDAC_INVALID; 2164 2165 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 2166 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 2167 devstr = "line out"; 2168 break; 2169 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 2170 devstr = "speaker"; 2171 break; 2172 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 2173 devstr = "headphones out"; 2174 break; 2175 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 2176 devstr = "CD"; 2177 break; 2178 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 2179 devstr = "SPDIF out"; 2180 break; 2181 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 2182 devstr = "digital (other) out"; 2183 break; 2184 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 2185 devstr = "modem, line side"; 2186 break; 2187 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 2188 devstr = "modem, handset side"; 2189 break; 2190 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 2191 devstr = "line in"; 2192 break; 2193 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 2194 devstr = "AUX"; 2195 break; 2196 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 2197 devstr = "Mic in"; 2198 break; 2199 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 2200 devstr = "telephony"; 2201 break; 2202 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 2203 devstr = "SPDIF in"; 2204 break; 2205 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 2206 devstr = "digital (other) in"; 2207 break; 2208 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 2209 devstr = "other"; 2210 break; 2211 default: 2212 devstr = "unknown"; 2213 break; 2214 } 2215 2216 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 2217 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 2218 connstr = "jack"; 2219 break; 2220 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 2221 connstr = "none"; 2222 break; 2223 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 2224 connstr = "fixed"; 2225 break; 2226 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 2227 connstr = "jack / fixed"; 2228 break; 2229 default: 2230 connstr = "unknown"; 2231 break; 2232 } 2233 2234 strlcat(w->name, ": ", sizeof(w->name)); 2235 strlcat(w->name, devstr, sizeof(w->name)); 2236 strlcat(w->name, " (", sizeof(w->name)); 2237 strlcat(w->name, connstr, sizeof(w->name)); 2238 strlcat(w->name, ")", sizeof(w->name)); 2239 } 2240 2241 static void 2242 hdac_widget_parse(struct hdac_widget *w) 2243 { 2244 struct hdac_softc *sc = w->devinfo->codec->sc; 2245 uint32_t wcap, cap; 2246 char *typestr; 2247 nid_t cad = w->devinfo->codec->cad; 2248 nid_t nid = w->nid; 2249 2250 wcap = hdac_command(sc, 2251 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2252 cad); 2253 w->param.widget_cap = wcap; 2254 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2255 2256 switch (w->type) { 2257 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2258 typestr = "audio output"; 2259 break; 2260 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2261 typestr = "audio input"; 2262 break; 2263 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2264 typestr = "audio mixer"; 2265 break; 2266 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2267 typestr = "audio selector"; 2268 break; 2269 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2270 typestr = "pin"; 2271 break; 2272 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2273 typestr = "power widget"; 2274 break; 2275 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2276 typestr = "volume widget"; 2277 break; 2278 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2279 typestr = "beep widget"; 2280 break; 2281 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2282 typestr = "vendor widget"; 2283 break; 2284 default: 2285 typestr = "unknown type"; 2286 break; 2287 } 2288 2289 strlcpy(w->name, typestr, sizeof(w->name)); 2290 2291 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2292 hdac_command(sc, 2293 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2294 cad); 2295 DELAY(1000); 2296 } 2297 2298 hdac_widget_connection_parse(w); 2299 2300 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2301 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2302 w->param.outamp_cap = 2303 hdac_command(sc, 2304 HDA_CMD_GET_PARAMETER(cad, nid, 2305 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2306 else 2307 w->param.outamp_cap = 2308 w->devinfo->function.audio.outamp_cap; 2309 } else 2310 w->param.outamp_cap = 0; 2311 2312 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2313 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2314 w->param.inamp_cap = 2315 hdac_command(sc, 2316 HDA_CMD_GET_PARAMETER(cad, nid, 2317 HDA_PARAM_INPUT_AMP_CAP), cad); 2318 else 2319 w->param.inamp_cap = 2320 w->devinfo->function.audio.inamp_cap; 2321 } else 2322 w->param.inamp_cap = 0; 2323 2324 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2325 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2326 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2327 cap = hdac_command(sc, 2328 HDA_CMD_GET_PARAMETER(cad, nid, 2329 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2330 w->param.supp_stream_formats = (cap != 0) ? cap : 2331 w->devinfo->function.audio.supp_stream_formats; 2332 cap = hdac_command(sc, 2333 HDA_CMD_GET_PARAMETER(cad, nid, 2334 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2335 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2336 w->devinfo->function.audio.supp_pcm_size_rate; 2337 } else { 2338 w->param.supp_stream_formats = 2339 w->devinfo->function.audio.supp_stream_formats; 2340 w->param.supp_pcm_size_rate = 2341 w->devinfo->function.audio.supp_pcm_size_rate; 2342 } 2343 } else { 2344 w->param.supp_stream_formats = 0; 2345 w->param.supp_pcm_size_rate = 0; 2346 } 2347 2348 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2349 hdac_widget_pin_parse(w); 2350 } 2351 2352 static struct hdac_widget * 2353 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2354 { 2355 if (devinfo == NULL || devinfo->widget == NULL || 2356 nid < devinfo->startnode || nid >= devinfo->endnode) 2357 return (NULL); 2358 return (&devinfo->widget[nid - devinfo->startnode]); 2359 } 2360 2361 static __inline int 2362 hda_poll_channel(struct hdac_chan *ch) 2363 { 2364 uint32_t sz, delta; 2365 volatile uint32_t ptr; 2366 2367 if (ch->active == 0) 2368 return (0); 2369 2370 sz = ch->blksz * ch->blkcnt; 2371 if (ch->dmapos != NULL) 2372 ptr = *(ch->dmapos); 2373 else 2374 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2375 ch->off + HDAC_SDLPIB); 2376 ch->ptr = ptr; 2377 ptr %= sz; 2378 ptr &= ~(ch->blksz - 1); 2379 delta = (sz + ptr - ch->prevptr) % sz; 2380 2381 if (delta < ch->blksz) 2382 return (0); 2383 2384 ch->prevptr = ptr; 2385 2386 return (1); 2387 } 2388 2389 #define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 2390 2391 static void 2392 hda_poll_callback(void *arg) 2393 { 2394 struct hdac_softc *sc = arg; 2395 uint32_t trigger = 0; 2396 2397 if (sc == NULL) 2398 return; 2399 2400 hdac_lock(sc); 2401 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2402 hdac_unlock(sc); 2403 return; 2404 } 2405 2406 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2407 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2408 2409 /* XXX */ 2410 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2411 hda_poll_callback, sc); 2412 2413 hdac_unlock(sc); 2414 2415 if (trigger & 1) 2416 chn_intr(sc->play.c); 2417 if (trigger & 2) 2418 chn_intr(sc->rec.c); 2419 } 2420 2421 static int 2422 hdac_rirb_flush(struct hdac_softc *sc) 2423 { 2424 struct hdac_rirb *rirb_base, *rirb; 2425 struct hdac_codec *codec; 2426 struct hdac_command_list *commands; 2427 nid_t cad; 2428 uint32_t resp; 2429 uint8_t rirbwp; 2430 int ret = 0; 2431 2432 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2433 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2434 #if 0 2435 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2436 BUS_DMASYNC_POSTREAD); 2437 #endif 2438 2439 while (sc->rirb_rp != rirbwp) { 2440 sc->rirb_rp++; 2441 sc->rirb_rp %= sc->rirb_size; 2442 rirb = &rirb_base[sc->rirb_rp]; 2443 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2444 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2445 sc->codecs[cad] == NULL) 2446 continue; 2447 resp = rirb->response; 2448 codec = sc->codecs[cad]; 2449 commands = codec->commands; 2450 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2451 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2452 ((resp >> 26) & 0xffff); 2453 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2454 } else if (commands != NULL && commands->num_commands > 0 && 2455 codec->responses_received < commands->num_commands) 2456 commands->responses[codec->responses_received++] = 2457 resp; 2458 ret++; 2459 } 2460 2461 return (ret); 2462 } 2463 2464 static int 2465 hdac_unsolq_flush(struct hdac_softc *sc) 2466 { 2467 nid_t cad; 2468 uint32_t tag; 2469 int ret = 0; 2470 2471 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2472 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2473 while (sc->unsolq_rp != sc->unsolq_wp) { 2474 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2475 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2476 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2477 hdac_unsolicited_handler(sc->codecs[cad], tag); 2478 ret++; 2479 } 2480 sc->unsolq_st = HDAC_UNSOLQ_READY; 2481 } 2482 2483 return (ret); 2484 } 2485 2486 static void 2487 hdac_poll_callback(void *arg) 2488 { 2489 struct hdac_softc *sc = arg; 2490 if (sc == NULL) 2491 return; 2492 2493 hdac_lock(sc); 2494 if (sc->polling == 0 || sc->poll_ival == 0) { 2495 hdac_unlock(sc); 2496 return; 2497 } 2498 hdac_rirb_flush(sc); 2499 hdac_unsolq_flush(sc); 2500 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2501 hdac_unlock(sc); 2502 } 2503 2504 static void 2505 hdac_stream_stop(struct hdac_chan *ch) 2506 { 2507 struct hdac_softc *sc = ch->devinfo->codec->sc; 2508 uint32_t ctl; 2509 2510 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2511 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2512 HDAC_SDCTL_RUN); 2513 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2514 2515 ch->active = 0; 2516 2517 if (sc->polling != 0) { 2518 int pollticks; 2519 2520 if (hda_chan_active(sc) == 0) { 2521 callout_stop(&sc->poll_hda); 2522 sc->poll_ticks = 1; 2523 } else { 2524 if (sc->play.active != 0) 2525 ch = &sc->play; 2526 else 2527 ch = &sc->rec; 2528 pollticks = ((uint64_t)hz * ch->blksz) / 2529 ((uint64_t)sndbuf_getbps(ch->b) * 2530 sndbuf_getspd(ch->b)); 2531 pollticks >>= 2; 2532 if (pollticks > hz) 2533 pollticks = hz; 2534 if (pollticks < 1) { 2535 HDA_BOOTVERBOSE( 2536 device_printf(sc->dev, 2537 "%s: pollticks=%d < 1 !\n", 2538 __func__, pollticks); 2539 ); 2540 pollticks = 1; 2541 } 2542 if (pollticks > sc->poll_ticks) { 2543 HDA_BOOTVERBOSE( 2544 device_printf(sc->dev, 2545 "%s: pollticks %d -> %d\n", 2546 __func__, sc->poll_ticks, 2547 pollticks); 2548 ); 2549 sc->poll_ticks = pollticks; 2550 callout_reset(&sc->poll_hda, 1, 2551 hda_poll_callback, sc); 2552 } 2553 } 2554 } else { 2555 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2556 ctl &= ~(1 << (ch->off >> 5)); 2557 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2558 } 2559 } 2560 2561 static void 2562 hdac_stream_start(struct hdac_chan *ch) 2563 { 2564 struct hdac_softc *sc = ch->devinfo->codec->sc; 2565 uint32_t ctl; 2566 2567 if (sc->polling != 0) { 2568 int pollticks; 2569 2570 pollticks = ((uint64_t)hz * ch->blksz) / 2571 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2572 pollticks >>= 2; 2573 if (pollticks > hz) 2574 pollticks = hz; 2575 if (pollticks < 1) { 2576 HDA_BOOTVERBOSE( 2577 device_printf(sc->dev, 2578 "%s: pollticks=%d < 1 !\n", 2579 __func__, pollticks); 2580 ); 2581 pollticks = 1; 2582 } 2583 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2584 HDA_BOOTVERBOSE( 2585 if (hda_chan_active(sc) == 0) { 2586 device_printf(sc->dev, 2587 "%s: pollticks=%d\n", 2588 __func__, pollticks); 2589 } else { 2590 device_printf(sc->dev, 2591 "%s: pollticks %d -> %d\n", 2592 __func__, sc->poll_ticks, 2593 pollticks); 2594 } 2595 ); 2596 sc->poll_ticks = pollticks; 2597 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2598 sc); 2599 } 2600 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2601 ctl |= HDAC_SDCTL_RUN; 2602 } else { 2603 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2604 ctl |= 1 << (ch->off >> 5); 2605 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2606 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2607 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2608 HDAC_SDCTL_RUN; 2609 } 2610 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2611 2612 ch->active = 1; 2613 } 2614 2615 static void 2616 hdac_stream_reset(struct hdac_chan *ch) 2617 { 2618 struct hdac_softc *sc = ch->devinfo->codec->sc; 2619 int timeout = 1000; 2620 int to = timeout; 2621 uint32_t ctl; 2622 2623 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2624 ctl |= HDAC_SDCTL_SRST; 2625 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2626 do { 2627 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2628 if (ctl & HDAC_SDCTL_SRST) 2629 break; 2630 DELAY(10); 2631 } while (--to); 2632 if (!(ctl & HDAC_SDCTL_SRST)) { 2633 device_printf(sc->dev, "timeout in reset\n"); 2634 } 2635 ctl &= ~HDAC_SDCTL_SRST; 2636 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2637 to = timeout; 2638 do { 2639 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2640 if (!(ctl & HDAC_SDCTL_SRST)) 2641 break; 2642 DELAY(10); 2643 } while (--to); 2644 if (ctl & HDAC_SDCTL_SRST) 2645 device_printf(sc->dev, "can't reset!\n"); 2646 } 2647 2648 static void 2649 hdac_stream_setid(struct hdac_chan *ch) 2650 { 2651 struct hdac_softc *sc = ch->devinfo->codec->sc; 2652 uint32_t ctl; 2653 2654 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2655 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2656 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2657 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2658 } 2659 2660 static void 2661 hdac_bdl_setup(struct hdac_chan *ch) 2662 { 2663 struct hdac_softc *sc = ch->devinfo->codec->sc; 2664 struct hdac_bdle *bdle; 2665 uint64_t addr; 2666 uint32_t blksz, blkcnt; 2667 int i; 2668 2669 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2670 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2671 2672 if (sc->polling != 0) { 2673 blksz = ch->blksz * ch->blkcnt; 2674 blkcnt = 1; 2675 } else { 2676 blksz = ch->blksz; 2677 blkcnt = ch->blkcnt; 2678 } 2679 2680 for (i = 0; i < blkcnt; i++, bdle++) { 2681 bdle->addrl = (uint32_t)addr; 2682 bdle->addrh = (uint32_t)(addr >> 32); 2683 bdle->len = blksz; 2684 bdle->ioc = 1 ^ sc->polling; 2685 addr += blksz; 2686 } 2687 2688 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2689 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2690 addr = ch->bdl_dma.dma_paddr; 2691 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2692 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2693 if (ch->dmapos != NULL && 2694 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2695 addr = sc->pos_dma.dma_paddr; 2696 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2697 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2698 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2699 } 2700 } 2701 2702 static int 2703 hdac_bdl_alloc(struct hdac_chan *ch) 2704 { 2705 struct hdac_softc *sc = ch->devinfo->codec->sc; 2706 int rc; 2707 2708 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2709 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2710 if (rc) { 2711 device_printf(sc->dev, "can't alloc bdl\n"); 2712 return (rc); 2713 } 2714 2715 return (0); 2716 } 2717 2718 static void 2719 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2720 int index, int lmute, int rmute, 2721 int left, int right, int dir) 2722 { 2723 uint16_t v = 0; 2724 2725 if (sc == NULL) 2726 return; 2727 2728 if (left != right || lmute != rmute) { 2729 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2730 (lmute << 7) | left; 2731 hdac_command(sc, 2732 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2733 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2734 (rmute << 7) | right; 2735 } else 2736 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2737 (lmute << 7) | left; 2738 2739 hdac_command(sc, 2740 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2741 } 2742 2743 static void 2744 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2745 int left, int right) 2746 { 2747 struct hdac_softc *sc; 2748 nid_t nid, cad; 2749 int lmute, rmute; 2750 2751 if (ctl == NULL || ctl->widget == NULL || 2752 ctl->widget->devinfo == NULL || 2753 ctl->widget->devinfo->codec == NULL || 2754 ctl->widget->devinfo->codec->sc == NULL) 2755 return; 2756 2757 sc = ctl->widget->devinfo->codec->sc; 2758 cad = ctl->widget->devinfo->codec->cad; 2759 nid = ctl->widget->nid; 2760 2761 if (mute == HDA_AMP_MUTE_DEFAULT) { 2762 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2763 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2764 } else { 2765 lmute = HDA_AMP_LEFT_MUTED(mute); 2766 rmute = HDA_AMP_RIGHT_MUTED(mute); 2767 } 2768 2769 if (ctl->dir & HDA_CTL_OUT) 2770 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2771 lmute, rmute, left, right, 0); 2772 if (ctl->dir & HDA_CTL_IN) 2773 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2774 lmute, rmute, left, right, 1); 2775 ctl->left = left; 2776 ctl->right = right; 2777 } 2778 2779 static void 2780 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2781 { 2782 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2783 return; 2784 hdac_command(w->devinfo->codec->sc, 2785 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2786 w->nid, index), w->devinfo->codec->cad); 2787 w->selconn = index; 2788 } 2789 2790 2791 /**************************************************************************** 2792 * uint32_t hdac_command_sendone_internal 2793 * 2794 * Wrapper function that sends only one command to a given codec 2795 ****************************************************************************/ 2796 static uint32_t 2797 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2798 { 2799 struct hdac_command_list cl; 2800 uint32_t response = HDAC_INVALID; 2801 2802 if (!hdac_lockowned(sc)) 2803 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2804 cl.num_commands = 1; 2805 cl.verbs = &verb; 2806 cl.responses = &response; 2807 2808 hdac_command_send_internal(sc, &cl, cad); 2809 2810 return (response); 2811 } 2812 2813 /**************************************************************************** 2814 * hdac_command_send_internal 2815 * 2816 * Send a command list to the codec via the corb. We queue as much verbs as 2817 * we can and msleep on the codec. When the interrupt get the responses 2818 * back from the rirb, it will wake us up so we can queue the remaining verbs 2819 * if any. 2820 ****************************************************************************/ 2821 static void 2822 hdac_command_send_internal(struct hdac_softc *sc, 2823 struct hdac_command_list *commands, nid_t cad) 2824 { 2825 struct hdac_codec *codec; 2826 int corbrp; 2827 uint32_t *corb; 2828 int timeout; 2829 int retry = 10; 2830 struct hdac_rirb *rirb_base; 2831 2832 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2833 commands->num_commands < 1) 2834 return; 2835 2836 codec = sc->codecs[cad]; 2837 codec->commands = commands; 2838 codec->responses_received = 0; 2839 codec->verbs_sent = 0; 2840 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2841 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2842 2843 do { 2844 if (codec->verbs_sent != commands->num_commands) { 2845 /* Queue as many verbs as possible */ 2846 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2847 #if 0 2848 bus_dmamap_sync(sc->corb_dma.dma_tag, 2849 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2850 #endif 2851 while (codec->verbs_sent != commands->num_commands && 2852 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2853 sc->corb_wp++; 2854 sc->corb_wp %= sc->corb_size; 2855 corb[sc->corb_wp] = 2856 commands->verbs[codec->verbs_sent++]; 2857 } 2858 2859 /* Send the verbs to the codecs */ 2860 #if 0 2861 bus_dmamap_sync(sc->corb_dma.dma_tag, 2862 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2863 #endif 2864 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2865 } 2866 2867 timeout = 1000; 2868 while (hdac_rirb_flush(sc) == 0 && --timeout) 2869 DELAY(10); 2870 } while ((codec->verbs_sent != commands->num_commands || 2871 codec->responses_received != commands->num_commands) && --retry); 2872 2873 if (retry == 0) 2874 device_printf(sc->dev, 2875 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2876 __func__, commands->num_commands, codec->verbs_sent, 2877 codec->responses_received); 2878 2879 codec->commands = NULL; 2880 codec->responses_received = 0; 2881 codec->verbs_sent = 0; 2882 2883 hdac_unsolq_flush(sc); 2884 } 2885 2886 2887 /**************************************************************************** 2888 * Device Methods 2889 ****************************************************************************/ 2890 2891 /**************************************************************************** 2892 * int hdac_probe(device_t) 2893 * 2894 * Probe for the presence of an hdac. If none is found, check for a generic 2895 * match using the subclass of the device. 2896 ****************************************************************************/ 2897 static int 2898 hdac_probe(device_t dev) 2899 { 2900 int i, result; 2901 uint32_t model; 2902 uint16_t class, subclass; 2903 char desc[64]; 2904 2905 model = (uint32_t)pci_get_device(dev) << 16; 2906 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2907 class = pci_get_class(dev); 2908 subclass = pci_get_subclass(dev); 2909 2910 bzero(desc, sizeof(desc)); 2911 result = ENXIO; 2912 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2913 if (hdac_devices[i].model == model) { 2914 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2915 result = BUS_PROBE_DEFAULT; 2916 break; 2917 } 2918 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2919 class == PCIC_MULTIMEDIA && 2920 subclass == PCIS_MULTIMEDIA_HDA) { 2921 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2922 result = BUS_PROBE_GENERIC; 2923 break; 2924 } 2925 } 2926 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2927 subclass == PCIS_MULTIMEDIA_HDA) { 2928 strlcpy(desc, "Generic", sizeof(desc)); 2929 result = BUS_PROBE_GENERIC; 2930 } 2931 if (result != ENXIO) { 2932 strlcat(desc, " High Definition Audio Controller", 2933 sizeof(desc)); 2934 device_set_desc_copy(dev, desc); 2935 } 2936 2937 return (result); 2938 } 2939 2940 static void * 2941 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2942 struct pcm_channel *c, int dir) 2943 { 2944 struct hdac_devinfo *devinfo = data; 2945 struct hdac_softc *sc = devinfo->codec->sc; 2946 struct hdac_chan *ch; 2947 2948 hdac_lock(sc); 2949 if (dir == PCMDIR_PLAY) { 2950 ch = &sc->play; 2951 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2952 devinfo->function.audio.playcnt++; 2953 } else { 2954 ch = &sc->rec; 2955 ch->off = devinfo->function.audio.reccnt << 5; 2956 devinfo->function.audio.reccnt++; 2957 } 2958 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2959 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2960 ch->pcmrates[0] = 48000; 2961 ch->pcmrates[1] = 0; 2962 } 2963 if (sc->pos_dma.dma_vaddr != NULL) 2964 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 2965 (sc->streamcnt * 8)); 2966 else 2967 ch->dmapos = NULL; 2968 ch->sid = ++sc->streamcnt; 2969 ch->dir = dir; 2970 ch->b = b; 2971 ch->c = c; 2972 ch->devinfo = devinfo; 2973 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2974 ch->blkcnt = sc->chan_blkcnt; 2975 hdac_unlock(sc); 2976 2977 if (hdac_bdl_alloc(ch) != 0) { 2978 ch->blkcnt = 0; 2979 return (NULL); 2980 } 2981 2982 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2983 return (NULL); 2984 2985 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), sndbuf_getmaxsize(ch->b), 2986 PAT_UNCACHEABLE); 2987 2988 return (ch); 2989 } 2990 2991 static int 2992 hdac_channel_free(kobj_t obj, void *data) 2993 { 2994 struct hdac_softc *sc; 2995 struct hdac_chan *ch; 2996 2997 ch = (struct hdac_chan *)data; 2998 sc = (ch != NULL && ch->devinfo != NULL && ch->devinfo->codec != NULL) ? 2999 ch->devinfo->codec->sc : NULL; 3000 if (ch != NULL && sc != NULL) { 3001 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), 3002 sndbuf_getmaxsize(ch->b), PAT_WRITE_BACK); 3003 } 3004 3005 return (1); 3006 } 3007 3008 static int 3009 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3010 { 3011 struct hdac_chan *ch = data; 3012 int i; 3013 3014 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3015 if (format == ch->caps.fmtlist[i]) { 3016 ch->fmt = format; 3017 return (0); 3018 } 3019 } 3020 3021 return (EINVAL); 3022 } 3023 3024 static int 3025 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3026 { 3027 struct hdac_chan *ch = data; 3028 uint32_t spd = 0, threshold; 3029 int i; 3030 3031 for (i = 0; ch->pcmrates[i] != 0; i++) { 3032 spd = ch->pcmrates[i]; 3033 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3034 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3035 if (speed < threshold) 3036 break; 3037 } 3038 3039 if (spd == 0) /* impossible */ 3040 ch->spd = 48000; 3041 else 3042 ch->spd = spd; 3043 3044 return (ch->spd); 3045 } 3046 3047 static void 3048 hdac_stream_setup(struct hdac_chan *ch) 3049 { 3050 struct hdac_softc *sc = ch->devinfo->codec->sc; 3051 int i; 3052 nid_t cad = ch->devinfo->codec->cad; 3053 uint16_t fmt; 3054 3055 fmt = 0; 3056 if (ch->fmt & AFMT_S16_LE) 3057 fmt |= ch->bit16 << 4; 3058 else if (ch->fmt & AFMT_S32_LE) 3059 fmt |= ch->bit32 << 4; 3060 else 3061 fmt |= 1 << 4; 3062 3063 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3064 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3065 fmt |= hda_rate_tab[i].base; 3066 fmt |= hda_rate_tab[i].mul; 3067 fmt |= hda_rate_tab[i].div; 3068 break; 3069 } 3070 } 3071 3072 if (ch->fmt & AFMT_STEREO) 3073 fmt |= 1; 3074 3075 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3076 3077 for (i = 0; ch->io[i] != -1; i++) { 3078 HDA_BOOTVERBOSE( 3079 device_printf(sc->dev, 3080 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 3081 "fmt=0x%08x\n", 3082 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3083 ch->io[i], fmt); 3084 ); 3085 hdac_command(sc, 3086 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3087 hdac_command(sc, 3088 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3089 ch->sid << 4), cad); 3090 } 3091 } 3092 3093 static int 3094 hdac_channel_setfragments(kobj_t obj, void *data, 3095 uint32_t blksz, uint32_t blkcnt) 3096 { 3097 struct hdac_chan *ch = data; 3098 struct hdac_softc *sc = ch->devinfo->codec->sc; 3099 3100 blksz &= HDA_BLK_ALIGN; 3101 3102 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3103 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3104 if (blksz < HDA_BLK_MIN) 3105 blksz = HDA_BLK_MIN; 3106 if (blkcnt > HDA_BDL_MAX) 3107 blkcnt = HDA_BDL_MAX; 3108 if (blkcnt < HDA_BDL_MIN) 3109 blkcnt = HDA_BDL_MIN; 3110 3111 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3112 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3113 blkcnt >>= 1; 3114 else if ((blksz >> 1) >= HDA_BLK_MIN) 3115 blksz >>= 1; 3116 else 3117 break; 3118 } 3119 3120 if ((sndbuf_getblksz(ch->b) != blksz || 3121 sndbuf_getblkcnt(ch->b) != blkcnt) && 3122 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3123 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3124 __func__, blksz, blkcnt); 3125 3126 ch->blksz = sndbuf_getblksz(ch->b); 3127 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3128 3129 return (1); 3130 } 3131 3132 static int 3133 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3134 { 3135 struct hdac_chan *ch = data; 3136 struct hdac_softc *sc = ch->devinfo->codec->sc; 3137 3138 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 3139 3140 return (ch->blksz); 3141 } 3142 3143 static void 3144 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3145 { 3146 struct hdac_devinfo *devinfo = ch->devinfo; 3147 nid_t cad = devinfo->codec->cad; 3148 int i; 3149 3150 hdac_stream_stop(ch); 3151 3152 for (i = 0; ch->io[i] != -1; i++) { 3153 hdac_command(sc, 3154 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3155 0), cad); 3156 } 3157 } 3158 3159 static void 3160 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3161 { 3162 ch->ptr = 0; 3163 ch->prevptr = 0; 3164 hdac_stream_stop(ch); 3165 hdac_stream_reset(ch); 3166 hdac_bdl_setup(ch); 3167 hdac_stream_setid(ch); 3168 hdac_stream_setup(ch); 3169 hdac_stream_start(ch); 3170 } 3171 3172 static int 3173 hdac_channel_trigger(kobj_t obj, void *data, int go) 3174 { 3175 struct hdac_chan *ch = data; 3176 struct hdac_softc *sc = ch->devinfo->codec->sc; 3177 3178 if (!(go == PCMTRIG_START || go == PCMTRIG_STOP || go == PCMTRIG_ABORT)) 3179 return (0); 3180 3181 hdac_lock(sc); 3182 switch (go) { 3183 case PCMTRIG_START: 3184 hdac_channel_start(sc, ch); 3185 break; 3186 case PCMTRIG_STOP: 3187 case PCMTRIG_ABORT: 3188 hdac_channel_stop(sc, ch); 3189 break; 3190 default: 3191 break; 3192 } 3193 hdac_unlock(sc); 3194 3195 return (0); 3196 } 3197 3198 static int 3199 hdac_channel_getptr(kobj_t obj, void *data) 3200 { 3201 struct hdac_chan *ch = data; 3202 struct hdac_softc *sc = ch->devinfo->codec->sc; 3203 uint32_t ptr; 3204 3205 hdac_lock(sc); 3206 if (sc->polling != 0) 3207 ptr = ch->ptr; 3208 else if (ch->dmapos != NULL) 3209 ptr = *(ch->dmapos); 3210 else 3211 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3212 hdac_unlock(sc); 3213 3214 /* 3215 * Round to available space and force 128 bytes aligment. 3216 */ 3217 ptr %= ch->blksz * ch->blkcnt; 3218 ptr &= HDA_BLK_ALIGN; 3219 3220 return (ptr); 3221 } 3222 3223 static struct pcmchan_caps * 3224 hdac_channel_getcaps(kobj_t obj, void *data) 3225 { 3226 return (&((struct hdac_chan *)data)->caps); 3227 } 3228 3229 static kobj_method_t hdac_channel_methods[] = { 3230 KOBJMETHOD(channel_init, hdac_channel_init), 3231 KOBJMETHOD(channel_free, hdac_channel_free), 3232 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3233 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3234 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3235 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3236 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3237 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3238 { 0, 0 } 3239 }; 3240 CHANNEL_DECLARE(hdac_channel); 3241 3242 static void 3243 hdac_jack_poll_callback(void *arg) 3244 { 3245 struct hdac_devinfo *devinfo = arg; 3246 struct hdac_softc *sc; 3247 3248 if (devinfo == NULL || devinfo->codec == NULL || 3249 devinfo->codec->sc == NULL) 3250 return; 3251 sc = devinfo->codec->sc; 3252 hdac_lock(sc); 3253 if (sc->poll_ival == 0) { 3254 hdac_unlock(sc); 3255 return; 3256 } 3257 hdac_hp_switch_handler(devinfo); 3258 callout_reset(&sc->poll_jack, sc->poll_ival, 3259 hdac_jack_poll_callback, devinfo); 3260 hdac_unlock(sc); 3261 } 3262 3263 static int 3264 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3265 { 3266 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3267 struct hdac_softc *sc = devinfo->codec->sc; 3268 struct hdac_widget *w, *cw; 3269 struct hdac_audio_ctl *ctl; 3270 uint32_t mask, recmask, id; 3271 int i, j, softpcmvol; 3272 nid_t cad; 3273 3274 hdac_lock(sc); 3275 3276 mask = 0; 3277 recmask = 0; 3278 3279 id = hdac_codec_id(devinfo); 3280 cad = devinfo->codec->cad; 3281 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 3282 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 3283 sc->pci_subvendor) && hdac_hp_switch[i].id == id)) 3284 continue; 3285 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 3286 if (w == NULL || w->enable == 0 || w->type != 3287 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3288 continue; 3289 if (hdac_hp_switch[i].polling != 0) 3290 callout_reset(&sc->poll_jack, 1, 3291 hdac_jack_poll_callback, devinfo); 3292 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 3293 hdac_command(sc, 3294 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 3295 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 3296 HDAC_UNSOLTAG_EVENT_HP), cad); 3297 else 3298 continue; 3299 hdac_hp_switch_handler(devinfo); 3300 HDA_BOOTVERBOSE( 3301 device_printf(sc->dev, 3302 "HDA_DEBUG: Enabling headphone/speaker " 3303 "audio routing switching:\n"); 3304 device_printf(sc->dev, 3305 "HDA_DEBUG: \tindex=%d nid=%d " 3306 "pci_subvendor=0x%08x " 3307 "codec=0x%08x [%s]\n", 3308 i, w->nid, sc->pci_subvendor, id, 3309 (hdac_hp_switch[i].polling != 0) ? "POLL" : 3310 "UNSOL"); 3311 ); 3312 break; 3313 } 3314 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3315 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3316 sc->pci_subvendor) && 3317 hdac_eapd_switch[i].id == id)) 3318 continue; 3319 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3320 if (w == NULL || w->enable == 0) 3321 break; 3322 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3323 w->param.eapdbtl == HDAC_INVALID) 3324 break; 3325 mask |= SOUND_MASK_OGAIN; 3326 break; 3327 } 3328 3329 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3330 w = hdac_widget_get(devinfo, i); 3331 if (w == NULL || w->enable == 0) 3332 continue; 3333 mask |= w->ctlflags; 3334 if (!(w->pflags & HDA_ADC_RECSEL)) 3335 continue; 3336 for (j = 0; j < w->nconns; j++) { 3337 cw = hdac_widget_get(devinfo, w->conns[j]); 3338 if (cw == NULL || cw->enable == 0) 3339 continue; 3340 recmask |= cw->ctlflags; 3341 } 3342 } 3343 3344 if (!(mask & SOUND_MASK_PCM)) { 3345 softpcmvol = 1; 3346 mask |= SOUND_MASK_PCM; 3347 } else 3348 softpcmvol = (devinfo->function.audio.quirks & 3349 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3350 3351 i = 0; 3352 ctl = NULL; 3353 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3354 if (ctl->widget == NULL || ctl->enable == 0) 3355 continue; 3356 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3357 continue; 3358 if (ctl->step > 0) 3359 break; 3360 } 3361 3362 if (softpcmvol == 1 || ctl == NULL) { 3363 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 3364 HDA_BOOTVERBOSE( 3365 device_printf(sc->dev, 3366 "HDA_DEBUG: %s Soft PCM volume\n", 3367 (softpcmvol == 1) ? 3368 "Forcing" : "Enabling"); 3369 ); 3370 i = 0; 3371 /* 3372 * XXX Temporary quirk for STAC9220, until the parser 3373 * become smarter. 3374 */ 3375 if (id == HDA_CODEC_STAC9220) { 3376 mask |= SOUND_MASK_VOLUME; 3377 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3378 NULL) { 3379 if (ctl->widget == NULL || ctl->enable == 0) 3380 continue; 3381 if (ctl->widget->nid == 11 && ctl->index == 0) { 3382 ctl->ossmask = SOUND_MASK_VOLUME; 3383 ctl->ossval = 100 | (100 << 8); 3384 } else 3385 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3386 } 3387 } else if (id == HDA_CODEC_STAC9221) { 3388 mask |= SOUND_MASK_VOLUME; 3389 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3390 NULL) { 3391 if (ctl->widget == NULL) 3392 continue; 3393 if (ctl->widget->type == 3394 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3395 ctl->index == 0 && (ctl->widget->nid == 2 || 3396 ctl->widget->enable != 0)) { 3397 ctl->enable = 1; 3398 ctl->ossmask = SOUND_MASK_VOLUME; 3399 ctl->ossval = 100 | (100 << 8); 3400 } else if (ctl->enable == 0) 3401 continue; 3402 else 3403 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3404 } 3405 } else { 3406 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3407 SOUND_MASK_PCM); 3408 if (!(mask & SOUND_MASK_VOLUME)) 3409 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3410 SOUND_MIXER_NONE); 3411 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3412 NULL) { 3413 if (ctl->widget == NULL || ctl->enable == 0) 3414 continue; 3415 if (!HDA_FLAG_MATCH(ctl->ossmask, 3416 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3417 continue; 3418 if (!(ctl->mute == 1 && ctl->step == 0)) 3419 ctl->enable = 0; 3420 } 3421 } 3422 } 3423 3424 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER | 3425 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN | 3426 SOUND_MASK_OGAIN); 3427 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3428 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3429 3430 mix_setrecdevs(m, recmask); 3431 mix_setdevs(m, mask); 3432 3433 hdac_unlock(sc); 3434 3435 return (0); 3436 } 3437 3438 static int 3439 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3440 unsigned left, unsigned right) 3441 { 3442 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3443 struct hdac_softc *sc = devinfo->codec->sc; 3444 struct hdac_widget *w; 3445 struct hdac_audio_ctl *ctl; 3446 uint32_t id, mute; 3447 int lvol, rvol, mlvol, mrvol; 3448 int i = 0; 3449 3450 hdac_lock(sc); 3451 if (dev == SOUND_MIXER_OGAIN) { 3452 uint32_t orig; 3453 /*if (left != right || !(left == 0 || left == 1)) { 3454 hdac_unlock(sc); 3455 return (-1); 3456 }*/ 3457 id = hdac_codec_id(devinfo); 3458 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3459 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3460 sc->pci_subvendor) && 3461 hdac_eapd_switch[i].id == id) 3462 break; 3463 } 3464 if (i >= HDAC_EAPD_SWITCH_LEN) { 3465 hdac_unlock(sc); 3466 return (-1); 3467 } 3468 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3469 if (w == NULL || 3470 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3471 w->param.eapdbtl == HDAC_INVALID) { 3472 hdac_unlock(sc); 3473 return (-1); 3474 } 3475 orig = w->param.eapdbtl; 3476 if (left == 0) 3477 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3478 else 3479 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3480 if (orig != w->param.eapdbtl) { 3481 uint32_t val; 3482 3483 if (hdac_eapd_switch[i].hp_switch != 0) 3484 hdac_hp_switch_handler(devinfo); 3485 val = w->param.eapdbtl; 3486 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3487 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3488 hdac_command(sc, 3489 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3490 w->nid, val), devinfo->codec->cad); 3491 } 3492 hdac_unlock(sc); 3493 return (left | (left << 8)); 3494 } 3495 if (dev == SOUND_MIXER_VOLUME) 3496 devinfo->function.audio.mvol = left | (right << 8); 3497 3498 mlvol = devinfo->function.audio.mvol & 0x7f; 3499 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3500 lvol = 0; 3501 rvol = 0; 3502 3503 i = 0; 3504 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3505 if (ctl->widget == NULL || ctl->enable == 0 || 3506 !(ctl->ossmask & (1 << dev))) 3507 continue; 3508 switch (dev) { 3509 case SOUND_MIXER_VOLUME: 3510 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3511 lvol = (lvol * ctl->step) / 100; 3512 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3513 rvol = (rvol * ctl->step) / 100; 3514 break; 3515 default: 3516 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3517 lvol = (left * mlvol) / 100; 3518 lvol = (lvol * ctl->step) / 100; 3519 rvol = (right * mrvol) / 100; 3520 rvol = (rvol * ctl->step) / 100; 3521 } else { 3522 lvol = (left * ctl->step) / 100; 3523 rvol = (right * ctl->step) / 100; 3524 } 3525 ctl->ossval = left | (right << 8); 3526 break; 3527 } 3528 mute = 0; 3529 if (ctl->step < 1) { 3530 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3531 (ctl->muted & HDA_AMP_MUTE_LEFT); 3532 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3533 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3534 } else { 3535 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3536 (ctl->muted & HDA_AMP_MUTE_LEFT); 3537 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3538 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3539 } 3540 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3541 } 3542 hdac_unlock(sc); 3543 3544 return (left | (right << 8)); 3545 } 3546 3547 static int 3548 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3549 { 3550 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3551 struct hdac_widget *w, *cw; 3552 struct hdac_softc *sc = devinfo->codec->sc; 3553 uint32_t ret = src, target; 3554 int i, j; 3555 3556 target = 0; 3557 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3558 if (src & (1 << i)) { 3559 target = 1 << i; 3560 break; 3561 } 3562 } 3563 3564 hdac_lock(sc); 3565 3566 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3567 w = hdac_widget_get(devinfo, i); 3568 if (w == NULL || w->enable == 0) 3569 continue; 3570 if (!(w->pflags & HDA_ADC_RECSEL)) 3571 continue; 3572 for (j = 0; j < w->nconns; j++) { 3573 cw = hdac_widget_get(devinfo, w->conns[j]); 3574 if (cw == NULL || cw->enable == 0) 3575 continue; 3576 if ((target == SOUND_MASK_VOLUME && 3577 cw->type != 3578 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3579 (target != SOUND_MASK_VOLUME && 3580 cw->type == 3581 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3582 continue; 3583 if (cw->ctlflags & target) { 3584 if (!(w->pflags & HDA_ADC_LOCKED)) 3585 hdac_widget_connection_select(w, j); 3586 ret = target; 3587 j += w->nconns; 3588 } 3589 } 3590 } 3591 3592 hdac_unlock(sc); 3593 3594 return (ret); 3595 } 3596 3597 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3598 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3599 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3600 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3601 { 0, 0 } 3602 }; 3603 MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3604 3605 /**************************************************************************** 3606 * int hdac_attach(device_t) 3607 * 3608 * Attach the device into the kernel. Interrupts usually won't be enabled 3609 * when this function is called. Setup everything that doesn't require 3610 * interrupts and defer probing of codecs until interrupts are enabled. 3611 ****************************************************************************/ 3612 static int 3613 hdac_attach(device_t dev) 3614 { 3615 struct hdac_softc *sc; 3616 int result; 3617 int i; 3618 uint16_t vendor; 3619 uint8_t v; 3620 3621 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 3622 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3623 sc->dev = dev; 3624 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3625 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3626 vendor = pci_get_vendor(dev); 3627 3628 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3629 /* Screw nx6325 - subdevice/subvendor swapped */ 3630 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3631 } 3632 3633 callout_init(&sc->poll_hda); 3634 callout_init(&sc->poll_hdac); 3635 callout_init(&sc->poll_jack); 3636 3637 sc->poll_ticks = 1; 3638 sc->poll_ival = HDAC_POLL_INTERVAL; 3639 if (resource_int_value(device_get_name(dev), 3640 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3641 sc->polling = 1; 3642 else 3643 sc->polling = 0; 3644 3645 sc->chan_size = pcm_getbuffersize(dev, 3646 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3647 3648 if (resource_int_value(device_get_name(dev), 3649 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 3650 i &= HDA_BLK_ALIGN; 3651 if (i < HDA_BLK_MIN) 3652 i = HDA_BLK_MIN; 3653 sc->chan_blkcnt = sc->chan_size / i; 3654 i = 0; 3655 while (sc->chan_blkcnt >> i) 3656 i++; 3657 sc->chan_blkcnt = 1 << (i - 1); 3658 if (sc->chan_blkcnt < HDA_BDL_MIN) 3659 sc->chan_blkcnt = HDA_BDL_MIN; 3660 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3661 sc->chan_blkcnt = HDA_BDL_MAX; 3662 } else 3663 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3664 3665 result = bus_dma_tag_create(NULL, /* parent */ 3666 HDAC_DMA_ALIGNMENT, /* alignment */ 3667 0, /* boundary */ 3668 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3669 BUS_SPACE_MAXADDR, /* highaddr */ 3670 NULL, /* filtfunc */ 3671 NULL, /* fistfuncarg */ 3672 sc->chan_size, /* maxsize */ 3673 1, /* nsegments */ 3674 sc->chan_size, /* maxsegsz */ 3675 0, /* flags */ 3676 &sc->chan_dmat); /* dmat */ 3677 if (result != 0) { 3678 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3679 __func__, result); 3680 snd_mtxfree(sc->lock); 3681 kfree(sc, M_DEVBUF); 3682 return (ENXIO); 3683 } 3684 3685 3686 sc->hdabus = NULL; 3687 for (i = 0; i < HDAC_CODEC_MAX; i++) 3688 sc->codecs[i] = NULL; 3689 3690 pci_enable_busmaster(dev); 3691 3692 if (vendor == INTEL_VENDORID) { 3693 /* TCSEL -> TC0 */ 3694 v = pci_read_config(dev, 0x44, 1); 3695 pci_write_config(dev, 0x44, v & 0xf8, 1); 3696 HDA_BOOTVERBOSE( 3697 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3698 pci_read_config(dev, 0x44, 1)); 3699 ); 3700 } 3701 3702 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 3703 sc->nocache = 1; 3704 3705 if (resource_int_value(device_get_name(dev), 3706 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3707 #else 3708 sc->nocache = 0; 3709 #endif 3710 /* 3711 * Try to enable PCIe snoop to avoid messing around with 3712 * uncacheable DMA attribute. Since PCIe snoop register 3713 * config is pretty much vendor specific, there are no 3714 * general solutions on how to enable it, forcing us (even 3715 * Microsoft) to enable uncacheable or write combined DMA 3716 * by default. 3717 * 3718 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3719 */ 3720 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3721 if (hdac_pcie_snoop[i].vendor != vendor) 3722 continue; 3723 sc->nocache = 0; 3724 if (hdac_pcie_snoop[i].reg == 0x00) 3725 break; 3726 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3727 if ((v & hdac_pcie_snoop[i].enable) == 3728 hdac_pcie_snoop[i].enable) 3729 break; 3730 v &= hdac_pcie_snoop[i].mask; 3731 v |= hdac_pcie_snoop[i].enable; 3732 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3733 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3734 if ((v & hdac_pcie_snoop[i].enable) != 3735 hdac_pcie_snoop[i].enable) { 3736 HDA_BOOTVERBOSE( 3737 device_printf(dev, 3738 "WARNING: Failed to enable PCIe " 3739 "snoop!\n"); 3740 ); 3741 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 3742 sc->nocache = 1; 3743 #endif 3744 } 3745 break; 3746 } 3747 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 3748 } 3749 #endif 3750 3751 HDA_BOOTVERBOSE( 3752 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3753 (sc->nocache == 0) ? "PCIe snoop" : "Uncacheable", vendor); 3754 ); 3755 3756 /* Allocate resources */ 3757 result = hdac_mem_alloc(sc); 3758 if (result != 0) 3759 goto hdac_attach_fail; 3760 result = hdac_irq_alloc(sc); 3761 if (result != 0) 3762 goto hdac_attach_fail; 3763 3764 /* Get Capabilities */ 3765 result = hdac_get_capabilities(sc); 3766 if (result != 0) 3767 goto hdac_attach_fail; 3768 3769 /* Allocate CORB and RIRB dma memory */ 3770 result = hdac_dma_alloc(sc, &sc->corb_dma, 3771 sc->corb_size * sizeof(uint32_t)); 3772 if (result != 0) 3773 goto hdac_attach_fail; 3774 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3775 sc->rirb_size * sizeof(struct hdac_rirb)); 3776 if (result != 0) 3777 goto hdac_attach_fail; 3778 3779 /* Quiesce everything */ 3780 hdac_reset(sc); 3781 3782 /* Initialize the CORB and RIRB */ 3783 hdac_corb_init(sc); 3784 hdac_rirb_init(sc); 3785 3786 /* Defer remaining of initialization until interrupts are enabled */ 3787 sc->intrhook.ich_func = hdac_attach2; 3788 sc->intrhook.ich_arg = (void *)sc; 3789 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3790 sc->intrhook.ich_func = NULL; 3791 hdac_attach2((void *)sc); 3792 } 3793 3794 return (0); 3795 3796 hdac_attach_fail: 3797 hdac_irq_free(sc); 3798 hdac_dma_free(sc, &sc->rirb_dma); 3799 hdac_dma_free(sc, &sc->corb_dma); 3800 hdac_mem_free(sc); 3801 snd_mtxfree(sc->lock); 3802 kfree(sc, M_DEVBUF); 3803 3804 return (ENXIO); 3805 } 3806 3807 static void 3808 hdac_audio_parse(struct hdac_devinfo *devinfo) 3809 { 3810 struct hdac_softc *sc = devinfo->codec->sc; 3811 struct hdac_widget *w; 3812 uint32_t res; 3813 int i; 3814 nid_t cad, nid; 3815 3816 cad = devinfo->codec->cad; 3817 nid = devinfo->nid; 3818 3819 hdac_command(sc, 3820 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3821 3822 DELAY(100); 3823 3824 res = hdac_command(sc, 3825 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3826 3827 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3828 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3829 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3830 3831 res = hdac_command(sc, 3832 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3833 devinfo->function.audio.gpio = res; 3834 3835 HDA_BOOTVERBOSE( 3836 device_printf(sc->dev, " Vendor: 0x%08x\n", 3837 devinfo->vendor_id); 3838 device_printf(sc->dev, " Device: 0x%08x\n", 3839 devinfo->device_id); 3840 device_printf(sc->dev, " Revision: 0x%08x\n", 3841 devinfo->revision_id); 3842 device_printf(sc->dev, " Stepping: 0x%08x\n", 3843 devinfo->stepping_id); 3844 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3845 sc->pci_subvendor); 3846 device_printf(sc->dev, " Nodes: start=%d " 3847 "endnode=%d total=%d\n", 3848 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3849 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 3850 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 3851 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 3852 sc->num_iss, sc->num_oss, sc->num_bss); 3853 device_printf(sc->dev, " GPIO: 0x%08x\n", 3854 devinfo->function.audio.gpio); 3855 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 3856 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3857 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3858 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3859 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 3860 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 3861 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 3862 ); 3863 3864 res = hdac_command(sc, 3865 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3866 cad); 3867 devinfo->function.audio.supp_stream_formats = res; 3868 3869 res = hdac_command(sc, 3870 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3871 cad); 3872 devinfo->function.audio.supp_pcm_size_rate = res; 3873 3874 res = hdac_command(sc, 3875 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3876 cad); 3877 devinfo->function.audio.outamp_cap = res; 3878 3879 res = hdac_command(sc, 3880 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3881 cad); 3882 devinfo->function.audio.inamp_cap = res; 3883 3884 if (devinfo->nodecnt > 0) 3885 devinfo->widget = (struct hdac_widget *)kmalloc( 3886 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3887 M_NOWAIT | M_ZERO); 3888 else 3889 devinfo->widget = NULL; 3890 3891 if (devinfo->widget == NULL) { 3892 device_printf(sc->dev, "unable to allocate widgets!\n"); 3893 devinfo->endnode = devinfo->startnode; 3894 devinfo->nodecnt = 0; 3895 return; 3896 } 3897 3898 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3899 w = hdac_widget_get(devinfo, i); 3900 if (w == NULL) 3901 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3902 else { 3903 w->devinfo = devinfo; 3904 w->nid = i; 3905 w->enable = 1; 3906 w->selconn = -1; 3907 w->pflags = 0; 3908 w->ctlflags = 0; 3909 w->param.eapdbtl = HDAC_INVALID; 3910 hdac_widget_parse(w); 3911 } 3912 } 3913 } 3914 3915 static void 3916 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3917 { 3918 struct hdac_softc *sc = devinfo->codec->sc; 3919 struct hdac_audio_ctl *ctls; 3920 struct hdac_widget *w, *cw; 3921 int i, j, cnt, max, ocap, icap; 3922 int mute, offset, step, size; 3923 3924 /* XXX This is redundant */ 3925 max = 0; 3926 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3927 w = hdac_widget_get(devinfo, i); 3928 if (w == NULL || w->enable == 0) 3929 continue; 3930 if (w->param.outamp_cap != 0) 3931 max++; 3932 if (w->param.inamp_cap != 0) { 3933 switch (w->type) { 3934 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3935 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3936 for (j = 0; j < w->nconns; j++) { 3937 cw = hdac_widget_get(devinfo, 3938 w->conns[j]); 3939 if (cw == NULL || cw->enable == 0) 3940 continue; 3941 max++; 3942 } 3943 break; 3944 default: 3945 max++; 3946 break; 3947 } 3948 } 3949 } 3950 3951 devinfo->function.audio.ctlcnt = max; 3952 3953 if (max < 1) 3954 return; 3955 3956 ctls = (struct hdac_audio_ctl *)kmalloc( 3957 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3958 3959 if (ctls == NULL) { 3960 /* Blekh! */ 3961 device_printf(sc->dev, "unable to allocate ctls!\n"); 3962 devinfo->function.audio.ctlcnt = 0; 3963 return; 3964 } 3965 3966 cnt = 0; 3967 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3968 if (cnt >= max) { 3969 device_printf(sc->dev, "%s: Ctl overflow!\n", 3970 __func__); 3971 break; 3972 } 3973 w = hdac_widget_get(devinfo, i); 3974 if (w == NULL || w->enable == 0) 3975 continue; 3976 ocap = w->param.outamp_cap; 3977 icap = w->param.inamp_cap; 3978 if (ocap != 0) { 3979 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3980 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3981 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3982 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3983 /*if (offset > step) { 3984 HDA_BOOTVERBOSE( 3985 device_printf(sc->dev, 3986 "HDA_DEBUG: BUGGY outamp: nid=%d " 3987 "[offset=%d > step=%d]\n", 3988 w->nid, offset, step); 3989 ); 3990 offset = step; 3991 }*/ 3992 ctls[cnt].enable = 1; 3993 ctls[cnt].widget = w; 3994 ctls[cnt].mute = mute; 3995 ctls[cnt].step = step; 3996 ctls[cnt].size = size; 3997 ctls[cnt].offset = offset; 3998 ctls[cnt].left = offset; 3999 ctls[cnt].right = offset; 4000 ctls[cnt++].dir = HDA_CTL_OUT; 4001 } 4002 4003 if (icap != 0) { 4004 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4005 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4006 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4007 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4008 /*if (offset > step) { 4009 HDA_BOOTVERBOSE( 4010 device_printf(sc->dev, 4011 "HDA_DEBUG: BUGGY inamp: nid=%d " 4012 "[offset=%d > step=%d]\n", 4013 w->nid, offset, step); 4014 ); 4015 offset = step; 4016 }*/ 4017 switch (w->type) { 4018 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4019 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4020 for (j = 0; j < w->nconns; j++) { 4021 if (cnt >= max) { 4022 device_printf(sc->dev, 4023 "%s: Ctl overflow!\n", 4024 __func__); 4025 break; 4026 } 4027 cw = hdac_widget_get(devinfo, 4028 w->conns[j]); 4029 if (cw == NULL || cw->enable == 0) 4030 continue; 4031 ctls[cnt].enable = 1; 4032 ctls[cnt].widget = w; 4033 ctls[cnt].childwidget = cw; 4034 ctls[cnt].index = j; 4035 ctls[cnt].mute = mute; 4036 ctls[cnt].step = step; 4037 ctls[cnt].size = size; 4038 ctls[cnt].offset = offset; 4039 ctls[cnt].left = offset; 4040 ctls[cnt].right = offset; 4041 ctls[cnt++].dir = HDA_CTL_IN; 4042 } 4043 break; 4044 default: 4045 if (cnt >= max) { 4046 device_printf(sc->dev, 4047 "%s: Ctl overflow!\n", 4048 __func__); 4049 break; 4050 } 4051 ctls[cnt].enable = 1; 4052 ctls[cnt].widget = w; 4053 ctls[cnt].mute = mute; 4054 ctls[cnt].step = step; 4055 ctls[cnt].size = size; 4056 ctls[cnt].offset = offset; 4057 ctls[cnt].left = offset; 4058 ctls[cnt].right = offset; 4059 ctls[cnt++].dir = HDA_CTL_IN; 4060 break; 4061 } 4062 } 4063 } 4064 4065 devinfo->function.audio.ctl = ctls; 4066 } 4067 4068 static const struct { 4069 uint32_t model; 4070 uint32_t id; 4071 uint32_t set, unset; 4072 } hdac_quirks[] = { 4073 /* 4074 * XXX Force stereo quirk. Monoural recording / playback 4075 * on few codecs (especially ALC880) seems broken or 4076 * perhaps unsupported. 4077 */ 4078 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4079 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4080 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4081 HDA_QUIRK_GPIO0, 0 }, 4082 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4083 HDA_QUIRK_GPIO0, 0 }, 4084 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4085 HDA_QUIRK_GPIO0, 0 }, 4086 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4087 HDA_QUIRK_GPIO0, 0 }, 4088 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4089 HDA_QUIRK_GPIO0, 0 }, 4090 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4091 HDA_QUIRK_EAPDINV, 0 }, 4092 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 4093 HDA_QUIRK_EAPDINV, 0 }, 4094 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4095 HDA_QUIRK_OVREF, 0 }, 4096 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861, 4097 HDA_QUIRK_OVREF, 0 }, 4098 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4099 HDA_QUIRK_OVREF, 0 }, 4100 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4101 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4102 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4103 HDA_QUIRK_GPIO1, 0 }, 4104 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4105 HDA_QUIRK_EAPDINV, 0 }, 4106 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4107 HDA_QUIRK_EAPDINV, 0 }, 4108 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4109 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4110 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4111 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4112 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4113 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4114 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4115 0, HDA_QUIRK_FORCESTEREO }, 4116 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 4117 HDA_QUIRK_SOFTPCMVOL, 0 } 4118 }; 4119 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4120 4121 static void 4122 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4123 { 4124 struct hdac_widget *w; 4125 struct hdac_audio_ctl *ctl; 4126 uint32_t id, subvendor; 4127 int i; 4128 4129 id = hdac_codec_id(devinfo); 4130 subvendor = devinfo->codec->sc->pci_subvendor; 4131 4132 /* 4133 * Quirks 4134 */ 4135 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4136 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4137 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4138 continue; 4139 if (hdac_quirks[i].set != 0) 4140 devinfo->function.audio.quirks |= 4141 hdac_quirks[i].set; 4142 if (hdac_quirks[i].unset != 0) 4143 devinfo->function.audio.quirks &= 4144 ~(hdac_quirks[i].unset); 4145 } 4146 4147 switch (id) { 4148 case HDA_CODEC_ALC260: 4149 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4150 w = hdac_widget_get(devinfo, i); 4151 if (w == NULL || w->enable == 0) 4152 continue; 4153 if (w->type != 4154 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4155 continue; 4156 if (w->nid != 5) 4157 w->enable = 0; 4158 } 4159 if (subvendor == HP_XW4300_SUBVENDOR) { 4160 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4161 if (ctl != NULL && ctl->widget != NULL) { 4162 ctl->ossmask = SOUND_MASK_SPEAKER; 4163 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4164 } 4165 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4166 if (ctl != NULL && ctl->widget != NULL) { 4167 ctl->ossmask = SOUND_MASK_SPEAKER; 4168 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4169 } 4170 } else if (subvendor == HP_3010_SUBVENDOR) { 4171 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4172 if (ctl != NULL && ctl->widget != NULL) { 4173 ctl->ossmask = SOUND_MASK_SPEAKER; 4174 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4175 } 4176 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4177 if (ctl != NULL && ctl->widget != NULL) { 4178 ctl->ossmask = SOUND_MASK_SPEAKER; 4179 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4180 } 4181 } 4182 break; 4183 case HDA_CODEC_ALC861: 4184 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1); 4185 if (ctl != NULL) 4186 ctl->muted = HDA_AMP_MUTE_ALL; 4187 break; 4188 case HDA_CODEC_ALC880: 4189 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4190 w = hdac_widget_get(devinfo, i); 4191 if (w == NULL || w->enable == 0) 4192 continue; 4193 if (w->type == 4194 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4195 w->nid != 9 && w->nid != 29) { 4196 w->enable = 0; 4197 } else if (w->type != 4198 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 4199 w->nid == 29) { 4200 w->type = 4201 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4202 w->param.widget_cap &= 4203 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4204 w->param.widget_cap |= 4205 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4206 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4207 strlcpy(w->name, "beep widget", sizeof(w->name)); 4208 } 4209 } 4210 break; 4211 case HDA_CODEC_ALC883: 4212 /* 4213 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4214 * Clear vref cap for jack connectivity. 4215 */ 4216 w = hdac_widget_get(devinfo, 24); 4217 if (w != NULL && w->enable != 0 && w->type == 4218 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4219 (w->wclass.pin.config & 4220 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4221 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4222 w->wclass.pin.cap &= ~( 4223 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4224 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4225 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4226 w = hdac_widget_get(devinfo, 25); 4227 if (w != NULL && w->enable != 0 && w->type == 4228 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4229 (w->wclass.pin.config & 4230 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4231 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4232 w->wclass.pin.cap &= ~( 4233 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4234 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4235 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4236 /* 4237 * nid: 26 = Line-in, leave it alone. 4238 */ 4239 break; 4240 case HDA_CODEC_AD1981HD: 4241 w = hdac_widget_get(devinfo, 11); 4242 if (w != NULL && w->enable != 0 && w->nconns > 3) 4243 w->selconn = 3; 4244 if (subvendor == IBM_M52_SUBVENDOR) { 4245 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 4246 if (ctl != NULL) 4247 ctl->ossmask = SOUND_MASK_SPEAKER; 4248 } 4249 break; 4250 case HDA_CODEC_AD1986A: 4251 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4252 w = hdac_widget_get(devinfo, i); 4253 if (w == NULL || w->enable == 0) 4254 continue; 4255 if (w->type != 4256 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4257 continue; 4258 if (w->nid != 3) 4259 w->enable = 0; 4260 } 4261 if (subvendor == ASUS_M2NPVMX_SUBVENDOR || 4262 subvendor == ASUS_VMCSM_SUBVENDOR) { 4263 /* nid 28 is mic, nid 29 is line-in */ 4264 w = hdac_widget_get(devinfo, 15); 4265 if (w != NULL) 4266 w->selconn = 2; 4267 w = hdac_widget_get(devinfo, 16); 4268 if (w != NULL) 4269 w->selconn = 1; 4270 } 4271 break; 4272 case HDA_CODEC_AD1988: 4273 case HDA_CODEC_AD1988B: 4274 /*w = hdac_widget_get(devinfo, 12); 4275 if (w != NULL) { 4276 w->selconn = 1; 4277 w->pflags |= HDA_ADC_LOCKED; 4278 } 4279 w = hdac_widget_get(devinfo, 13); 4280 if (w != NULL) { 4281 w->selconn = 4; 4282 w->pflags |= HDA_ADC_LOCKED; 4283 } 4284 w = hdac_widget_get(devinfo, 14); 4285 if (w != NULL) { 4286 w->selconn = 2; 4287 w->pflags |= HDA_ADC_LOCKED; 4288 }*/ 4289 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1); 4290 if (ctl != NULL) { 4291 ctl->ossmask = SOUND_MASK_IGAIN; 4292 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4293 } 4294 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1); 4295 if (ctl != NULL) { 4296 ctl->ossmask = SOUND_MASK_IGAIN; 4297 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4298 } 4299 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1); 4300 if (ctl != NULL) { 4301 ctl->ossmask = SOUND_MASK_IGAIN; 4302 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4303 } 4304 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1); 4305 if (ctl != NULL) { 4306 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4307 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4308 } 4309 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1); 4310 if (ctl != NULL) { 4311 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4312 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4313 } 4314 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1); 4315 if (ctl != NULL) { 4316 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4317 ctl->widget->ctlflags |= SOUND_MASK_LINE; 4318 } 4319 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1); 4320 if (ctl != NULL) { 4321 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME; 4322 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4323 } 4324 break; 4325 case HDA_CODEC_STAC9221: 4326 /* 4327 * Dell XPS M1210 need all DACs for each output jacks 4328 */ 4329 if (subvendor == DELL_XPSM1210_SUBVENDOR) 4330 break; 4331 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4332 w = hdac_widget_get(devinfo, i); 4333 if (w == NULL || w->enable == 0) 4334 continue; 4335 if (w->type != 4336 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4337 continue; 4338 if (w->nid != 2) 4339 w->enable = 0; 4340 } 4341 break; 4342 case HDA_CODEC_STAC9221D: 4343 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4344 w = hdac_widget_get(devinfo, i); 4345 if (w == NULL || w->enable == 0) 4346 continue; 4347 if (w->type == 4348 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4349 w->nid != 6) 4350 w->enable = 0; 4351 4352 } 4353 break; 4354 case HDA_CODEC_STAC9227: 4355 w = hdac_widget_get(devinfo, 8); 4356 if (w != NULL) 4357 w->enable = 0; 4358 w = hdac_widget_get(devinfo, 9); 4359 if (w != NULL) 4360 w->enable = 0; 4361 break; 4362 case HDA_CODEC_CXWAIKIKI: 4363 if (subvendor == HP_DV5000_SUBVENDOR) { 4364 w = hdac_widget_get(devinfo, 27); 4365 if (w != NULL) 4366 w->enable = 0; 4367 } 4368 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4369 if (ctl != NULL) 4370 ctl->ossmask = SOUND_MASK_SKIP; 4371 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1); 4372 if (ctl != NULL && ctl->childwidget != NULL && 4373 ctl->childwidget->enable != 0) { 4374 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME; 4375 ctl->childwidget->ctlflags |= SOUND_MASK_PCM; 4376 } 4377 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1); 4378 if (ctl != NULL && ctl->childwidget != NULL && 4379 ctl->childwidget->enable != 0) { 4380 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4381 ctl->childwidget->ctlflags |= SOUND_MASK_LINE; 4382 } 4383 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1); 4384 if (ctl != NULL && ctl->childwidget != NULL && 4385 ctl->childwidget->enable != 0) { 4386 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4387 ctl->childwidget->ctlflags |= SOUND_MASK_MIC; 4388 } 4389 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1); 4390 if (ctl != NULL) { 4391 ctl->ossmask = SOUND_MASK_SKIP; 4392 /* XXX mixer \=rec mic broken.. why?!? */ 4393 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */ 4394 } 4395 break; 4396 default: 4397 break; 4398 } 4399 } 4400 4401 static int 4402 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 4403 { 4404 int *dev = &devinfo->function.audio.ossidx; 4405 4406 while (*dev < SOUND_MIXER_NRDEVICES) { 4407 switch (*dev) { 4408 case SOUND_MIXER_VOLUME: 4409 case SOUND_MIXER_BASS: 4410 case SOUND_MIXER_TREBLE: 4411 case SOUND_MIXER_PCM: 4412 case SOUND_MIXER_SPEAKER: 4413 case SOUND_MIXER_LINE: 4414 case SOUND_MIXER_MIC: 4415 case SOUND_MIXER_CD: 4416 case SOUND_MIXER_RECLEV: 4417 case SOUND_MIXER_IGAIN: 4418 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 4419 (*dev)++; 4420 break; 4421 default: 4422 return (*dev)++; 4423 break; 4424 } 4425 } 4426 4427 return (-1); 4428 } 4429 4430 static int 4431 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4432 { 4433 struct hdac_widget *w; 4434 int i, ret = 0; 4435 4436 if (depth > HDA_PARSE_MAXDEPTH) 4437 return (0); 4438 w = hdac_widget_get(devinfo, nid); 4439 if (w == NULL || w->enable == 0) 4440 return (0); 4441 switch (w->type) { 4442 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4443 w->pflags |= HDA_DAC_PATH; 4444 ret = 1; 4445 break; 4446 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4447 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4448 for (i = 0; i < w->nconns; i++) { 4449 if (hdac_widget_find_dac_path(devinfo, 4450 w->conns[i], depth + 1) != 0) { 4451 if (w->selconn == -1) 4452 w->selconn = i; 4453 ret = 1; 4454 w->pflags |= HDA_DAC_PATH; 4455 } 4456 } 4457 break; 4458 default: 4459 break; 4460 } 4461 return (ret); 4462 } 4463 4464 static int 4465 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4466 { 4467 struct hdac_widget *w; 4468 int i, conndev, ret = 0; 4469 4470 if (depth > HDA_PARSE_MAXDEPTH) 4471 return (0); 4472 w = hdac_widget_get(devinfo, nid); 4473 if (w == NULL || w->enable == 0) 4474 return (0); 4475 switch (w->type) { 4476 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4477 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4478 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4479 for (i = 0; i < w->nconns; i++) { 4480 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 4481 depth + 1) != 0) { 4482 if (w->selconn == -1) 4483 w->selconn = i; 4484 w->pflags |= HDA_ADC_PATH; 4485 ret = 1; 4486 } 4487 } 4488 break; 4489 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4490 conndev = w->wclass.pin.config & 4491 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4492 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4493 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 4494 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 4495 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 4496 w->pflags |= HDA_ADC_PATH; 4497 ret = 1; 4498 } 4499 break; 4500 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4501 if (w->pflags & HDA_DAC_PATH) { 4502 w->pflags |= HDA_ADC_PATH; 4503 ret = 1; 4504 } 4505 break;*/ 4506 default: 4507 break; 4508 } 4509 return (ret); 4510 } 4511 4512 static uint32_t 4513 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 4514 nid_t nid, nid_t pnid, int index, int depth) 4515 { 4516 struct hdac_widget *w, *pw; 4517 struct hdac_audio_ctl *ctl; 4518 uint32_t fl = 0; 4519 int i, ossdev, conndev, strategy; 4520 4521 if (depth > HDA_PARSE_MAXDEPTH) 4522 return (0); 4523 4524 w = hdac_widget_get(devinfo, nid); 4525 if (w == NULL || w->enable == 0) 4526 return (0); 4527 4528 pw = hdac_widget_get(devinfo, pnid); 4529 strategy = devinfo->function.audio.parsing_strategy; 4530 4531 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 4532 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 4533 for (i = 0; i < w->nconns; i++) { 4534 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 4535 w->nid, i, depth + 1); 4536 } 4537 w->ctlflags |= fl; 4538 return (fl); 4539 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4540 (w->pflags & HDA_DAC_PATH)) { 4541 i = 0; 4542 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4543 if (ctl->enable == 0 || ctl->widget == NULL) 4544 continue; 4545 /* XXX This should be compressed! */ 4546 if (((ctl->widget->nid == w->nid) || 4547 (ctl->widget->nid == pnid && ctl->index == index && 4548 (ctl->dir & HDA_CTL_IN)) || 4549 (ctl->widget->nid == pnid && pw != NULL && 4550 pw->type == 4551 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4552 (pw->nconns < 2 || pw->selconn == index || 4553 pw->selconn == -1) && 4554 (ctl->dir & HDA_CTL_OUT)) || 4555 (strategy == HDA_PARSE_DIRECT && 4556 ctl->widget->nid == w->nid)) && 4557 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4558 /*if (pw != NULL && pw->selconn == -1) 4559 pw->selconn = index; 4560 fl |= SOUND_MASK_VOLUME; 4561 fl |= SOUND_MASK_PCM; 4562 ctl->ossmask |= SOUND_MASK_VOLUME; 4563 ctl->ossmask |= SOUND_MASK_PCM; 4564 ctl->ossdev = SOUND_MIXER_PCM;*/ 4565 if (!(w->ctlflags & SOUND_MASK_PCM) || 4566 (pw != NULL && 4567 !(pw->ctlflags & SOUND_MASK_PCM))) { 4568 fl |= SOUND_MASK_VOLUME; 4569 fl |= SOUND_MASK_PCM; 4570 ctl->ossmask |= SOUND_MASK_VOLUME; 4571 ctl->ossmask |= SOUND_MASK_PCM; 4572 ctl->ossdev = SOUND_MIXER_PCM; 4573 w->ctlflags |= SOUND_MASK_VOLUME; 4574 w->ctlflags |= SOUND_MASK_PCM; 4575 if (pw != NULL) { 4576 if (pw->selconn == -1) 4577 pw->selconn = index; 4578 pw->ctlflags |= 4579 SOUND_MASK_VOLUME; 4580 pw->ctlflags |= 4581 SOUND_MASK_PCM; 4582 } 4583 } 4584 } 4585 } 4586 w->ctlflags |= fl; 4587 return (fl); 4588 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4589 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4590 (w->pflags & HDA_ADC_PATH)) { 4591 conndev = w->wclass.pin.config & 4592 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4593 i = 0; 4594 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4595 if (ctl->enable == 0 || ctl->widget == NULL) 4596 continue; 4597 /* XXX This should be compressed! */ 4598 if (((ctl->widget->nid == pnid && ctl->index == index && 4599 (ctl->dir & HDA_CTL_IN)) || 4600 (ctl->widget->nid == pnid && pw != NULL && 4601 pw->type == 4602 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4603 (pw->nconns < 2 || pw->selconn == index || 4604 pw->selconn == -1) && 4605 (ctl->dir & HDA_CTL_OUT)) || 4606 (strategy == HDA_PARSE_DIRECT && 4607 ctl->widget->nid == w->nid)) && 4608 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4609 if (pw != NULL && pw->selconn == -1) 4610 pw->selconn = index; 4611 ossdev = 0; 4612 switch (conndev) { 4613 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4614 ossdev = SOUND_MIXER_MIC; 4615 break; 4616 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4617 ossdev = SOUND_MIXER_LINE; 4618 break; 4619 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4620 ossdev = SOUND_MIXER_CD; 4621 break; 4622 default: 4623 ossdev = 4624 hdac_audio_ctl_ossmixer_getnextdev( 4625 devinfo); 4626 if (ossdev < 0) 4627 ossdev = 0; 4628 break; 4629 } 4630 if (strategy == HDA_PARSE_MIXER) { 4631 fl |= SOUND_MASK_VOLUME; 4632 ctl->ossmask |= SOUND_MASK_VOLUME; 4633 } 4634 fl |= 1 << ossdev; 4635 ctl->ossmask |= 1 << ossdev; 4636 ctl->ossdev = ossdev; 4637 } 4638 } 4639 w->ctlflags |= fl; 4640 return (fl); 4641 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4642 i = 0; 4643 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4644 if (ctl->enable == 0 || ctl->widget == NULL) 4645 continue; 4646 /* XXX This should be compressed! */ 4647 if (((ctl->widget->nid == pnid && ctl->index == index && 4648 (ctl->dir & HDA_CTL_IN)) || 4649 (ctl->widget->nid == pnid && pw != NULL && 4650 pw->type == 4651 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4652 (pw->nconns < 2 || pw->selconn == index || 4653 pw->selconn == -1) && 4654 (ctl->dir & HDA_CTL_OUT)) || 4655 (strategy == HDA_PARSE_DIRECT && 4656 ctl->widget->nid == w->nid)) && 4657 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4658 if (pw != NULL && pw->selconn == -1) 4659 pw->selconn = index; 4660 fl |= SOUND_MASK_VOLUME; 4661 fl |= SOUND_MASK_SPEAKER; 4662 ctl->ossmask |= SOUND_MASK_VOLUME; 4663 ctl->ossmask |= SOUND_MASK_SPEAKER; 4664 ctl->ossdev = SOUND_MIXER_SPEAKER; 4665 } 4666 } 4667 w->ctlflags |= fl; 4668 return (fl); 4669 } 4670 return (0); 4671 } 4672 4673 static uint32_t 4674 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4675 { 4676 struct hdac_widget *w, *cw; 4677 struct hdac_audio_ctl *ctl; 4678 uint32_t fl; 4679 int i; 4680 4681 if (depth > HDA_PARSE_MAXDEPTH) 4682 return (0); 4683 4684 w = hdac_widget_get(devinfo, nid); 4685 if (w == NULL || w->enable == 0) 4686 return (0); 4687 /*if (!(w->pflags & HDA_ADC_PATH)) 4688 return (0); 4689 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4690 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4691 return (0);*/ 4692 i = 0; 4693 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4694 if (ctl->enable == 0 || ctl->widget == NULL) 4695 continue; 4696 if (ctl->widget->nid == nid) { 4697 ctl->ossmask |= SOUND_MASK_RECLEV; 4698 w->ctlflags |= SOUND_MASK_RECLEV; 4699 return (SOUND_MASK_RECLEV); 4700 } 4701 } 4702 for (i = 0; i < w->nconns; i++) { 4703 cw = hdac_widget_get(devinfo, w->conns[i]); 4704 if (cw == NULL || cw->enable == 0) 4705 continue; 4706 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4707 continue; 4708 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4709 if (fl != 0) { 4710 cw->ctlflags |= fl; 4711 w->ctlflags |= fl; 4712 return (fl); 4713 } 4714 } 4715 return (0); 4716 } 4717 4718 static int 4719 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4720 { 4721 struct hdac_widget *w, *cw; 4722 int i, child = 0; 4723 4724 if (depth > HDA_PARSE_MAXDEPTH) 4725 return (0); 4726 4727 w = hdac_widget_get(devinfo, nid); 4728 if (w == NULL || w->enable == 0) 4729 return (0); 4730 /*if (!(w->pflags & HDA_ADC_PATH)) 4731 return (0); 4732 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4733 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4734 return (0);*/ 4735 /* XXX weak! */ 4736 for (i = 0; i < w->nconns; i++) { 4737 cw = hdac_widget_get(devinfo, w->conns[i]); 4738 if (cw == NULL) 4739 continue; 4740 if (++child > 1) { 4741 w->pflags |= HDA_ADC_RECSEL; 4742 return (1); 4743 } 4744 } 4745 for (i = 0; i < w->nconns; i++) { 4746 if (hdac_audio_ctl_recsel_build(devinfo, 4747 w->conns[i], depth + 1) != 0) 4748 return (1); 4749 } 4750 return (0); 4751 } 4752 4753 static int 4754 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4755 { 4756 struct hdac_widget *w, *cw; 4757 int i, j, conndev, found_dac = 0; 4758 int strategy; 4759 4760 strategy = devinfo->function.audio.parsing_strategy; 4761 4762 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4763 w = hdac_widget_get(devinfo, i); 4764 if (w == NULL || w->enable == 0) 4765 continue; 4766 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4767 continue; 4768 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4769 continue; 4770 conndev = w->wclass.pin.config & 4771 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4772 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4773 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4774 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4775 continue; 4776 for (j = 0; j < w->nconns; j++) { 4777 cw = hdac_widget_get(devinfo, w->conns[j]); 4778 if (cw == NULL || cw->enable == 0) 4779 continue; 4780 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4781 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4782 cw->type == 4783 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4784 continue; 4785 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4786 != 0) { 4787 if (w->selconn == -1) 4788 w->selconn = j; 4789 w->pflags |= HDA_DAC_PATH; 4790 found_dac++; 4791 } 4792 } 4793 } 4794 4795 return (found_dac); 4796 } 4797 4798 static void 4799 hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4800 { 4801 struct hdac_widget *w; 4802 struct hdac_audio_ctl *ctl; 4803 int i, j, dacs, strategy; 4804 4805 /* Construct DAC path */ 4806 strategy = HDA_PARSE_MIXER; 4807 devinfo->function.audio.parsing_strategy = strategy; 4808 HDA_BOOTVERBOSE( 4809 device_printf(devinfo->codec->sc->dev, 4810 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4811 HDA_WIDGET_PARSER_REV); 4812 ); 4813 dacs = hdac_audio_build_tree_strategy(devinfo); 4814 if (dacs == 0) { 4815 HDA_BOOTVERBOSE( 4816 device_printf(devinfo->codec->sc->dev, 4817 "HDA_DEBUG: HWiP: 0 DAC path found! " 4818 "Retrying parser " 4819 "using HDA_PARSE_DIRECT strategy.\n"); 4820 ); 4821 strategy = HDA_PARSE_DIRECT; 4822 devinfo->function.audio.parsing_strategy = strategy; 4823 dacs = hdac_audio_build_tree_strategy(devinfo); 4824 } 4825 4826 HDA_BOOTVERBOSE( 4827 device_printf(devinfo->codec->sc->dev, 4828 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4829 "strategy.\n", 4830 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4831 ); 4832 4833 /* Construct ADC path */ 4834 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4835 w = hdac_widget_get(devinfo, i); 4836 if (w == NULL || w->enable == 0) 4837 continue; 4838 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4839 continue; 4840 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4841 } 4842 4843 /* Output mixers */ 4844 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4845 w = hdac_widget_get(devinfo, i); 4846 if (w == NULL || w->enable == 0) 4847 continue; 4848 if ((strategy == HDA_PARSE_MIXER && 4849 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4850 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4851 && (w->pflags & HDA_DAC_PATH)) || 4852 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4853 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4854 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4855 w->nid, devinfo->startnode - 1, 0, 0); 4856 } else if (w->type == 4857 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4858 j = 0; 4859 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4860 NULL) { 4861 if (ctl->enable == 0 || ctl->widget == NULL) 4862 continue; 4863 if (ctl->widget->nid != w->nid) 4864 continue; 4865 ctl->ossmask |= SOUND_MASK_VOLUME; 4866 ctl->ossmask |= SOUND_MASK_SPEAKER; 4867 ctl->ossdev = SOUND_MIXER_SPEAKER; 4868 w->ctlflags |= SOUND_MASK_VOLUME; 4869 w->ctlflags |= SOUND_MASK_SPEAKER; 4870 } 4871 } 4872 } 4873 4874 /* Input mixers (rec) */ 4875 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4876 w = hdac_widget_get(devinfo, i); 4877 if (w == NULL || w->enable == 0) 4878 continue; 4879 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4880 w->pflags & HDA_ADC_PATH)) 4881 continue; 4882 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4883 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4884 } 4885 } 4886 4887 #define HDA_COMMIT_CONN (1 << 0) 4888 #define HDA_COMMIT_CTRL (1 << 1) 4889 #define HDA_COMMIT_EAPD (1 << 2) 4890 #define HDA_COMMIT_GPIO (1 << 3) 4891 #define HDA_COMMIT_MISC (1 << 4) 4892 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4893 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC) 4894 4895 static void 4896 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4897 { 4898 struct hdac_softc *sc = devinfo->codec->sc; 4899 struct hdac_widget *w; 4900 nid_t cad; 4901 int i; 4902 4903 if (!(cfl & HDA_COMMIT_ALL)) 4904 return; 4905 4906 cad = devinfo->codec->cad; 4907 4908 if ((cfl & HDA_COMMIT_MISC)) { 4909 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4910 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4911 0x7e7, 0), cad); 4912 } 4913 4914 if (cfl & HDA_COMMIT_GPIO) { 4915 uint32_t gdata, gmask, gdir; 4916 int commitgpio, numgpio; 4917 4918 gdata = 0; 4919 gmask = 0; 4920 gdir = 0; 4921 commitgpio = 0; 4922 4923 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 4924 devinfo->function.audio.gpio); 4925 4926 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4927 commitgpio = (numgpio > 0) ? 1 : 0; 4928 else { 4929 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 4930 if (!(devinfo->function.audio.quirks & 4931 (1 << i))) 4932 continue; 4933 if (commitgpio == 0) { 4934 commitgpio = 1; 4935 HDA_BOOTVERBOSE( 4936 gdata = hdac_command(sc, 4937 HDA_CMD_GET_GPIO_DATA(cad, 4938 devinfo->nid), cad); 4939 gmask = hdac_command(sc, 4940 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4941 devinfo->nid), cad); 4942 gdir = hdac_command(sc, 4943 HDA_CMD_GET_GPIO_DIRECTION(cad, 4944 devinfo->nid), cad); 4945 device_printf(sc->dev, 4946 "GPIO init: data=0x%08x " 4947 "mask=0x%08x dir=0x%08x\n", 4948 gdata, gmask, gdir); 4949 gdata = 0; 4950 gmask = 0; 4951 gdir = 0; 4952 ); 4953 } 4954 gdata |= 1 << i; 4955 gmask |= 1 << i; 4956 gdir |= 1 << i; 4957 } 4958 } 4959 4960 if (commitgpio != 0) { 4961 HDA_BOOTVERBOSE( 4962 device_printf(sc->dev, 4963 "GPIO commit: data=0x%08x mask=0x%08x " 4964 "dir=0x%08x\n", 4965 gdata, gmask, gdir); 4966 ); 4967 hdac_command(sc, 4968 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4969 gmask), cad); 4970 hdac_command(sc, 4971 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4972 gdir), cad); 4973 hdac_command(sc, 4974 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4975 gdata), cad); 4976 } 4977 } 4978 4979 for (i = 0; i < devinfo->nodecnt; i++) { 4980 w = &devinfo->widget[i]; 4981 if (w == NULL || w->enable == 0) 4982 continue; 4983 if (cfl & HDA_COMMIT_CONN) { 4984 if (w->selconn == -1) 4985 w->selconn = 0; 4986 if (w->nconns > 0) 4987 hdac_widget_connection_select(w, w->selconn); 4988 } 4989 if ((cfl & HDA_COMMIT_CTRL) && 4990 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4991 uint32_t pincap; 4992 4993 pincap = w->wclass.pin.cap; 4994 4995 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4996 (HDA_DAC_PATH | HDA_ADC_PATH)) 4997 device_printf(sc->dev, "WARNING: node %d " 4998 "participate both for DAC/ADC!\n", w->nid); 4999 if (w->pflags & HDA_DAC_PATH) { 5000 w->wclass.pin.ctrl &= 5001 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5002 if ((w->wclass.pin.config & 5003 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 5004 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5005 w->wclass.pin.ctrl &= 5006 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5007 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5008 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5009 w->wclass.pin.ctrl |= 5010 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5011 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5012 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5013 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5014 w->wclass.pin.ctrl |= 5015 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5016 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5017 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5018 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5019 w->wclass.pin.ctrl |= 5020 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5021 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5022 } else if (w->pflags & HDA_ADC_PATH) { 5023 w->wclass.pin.ctrl &= 5024 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5025 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 5026 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5027 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5028 w->wclass.pin.ctrl |= 5029 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5030 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5031 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5032 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5033 w->wclass.pin.ctrl |= 5034 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5035 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5036 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5037 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5038 w->wclass.pin.ctrl |= 5039 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5040 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5041 } else 5042 w->wclass.pin.ctrl &= ~( 5043 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5044 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5045 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5046 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5047 hdac_command(sc, 5048 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5049 w->wclass.pin.ctrl), cad); 5050 } 5051 if ((cfl & HDA_COMMIT_EAPD) && 5052 w->param.eapdbtl != HDAC_INVALID) { 5053 uint32_t val; 5054 5055 val = w->param.eapdbtl; 5056 if (devinfo->function.audio.quirks & 5057 HDA_QUIRK_EAPDINV) 5058 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5059 hdac_command(sc, 5060 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5061 val), cad); 5062 5063 } 5064 DELAY(1000); 5065 } 5066 } 5067 5068 static void 5069 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5070 { 5071 struct hdac_softc *sc = devinfo->codec->sc; 5072 struct hdac_audio_ctl *ctl; 5073 int i; 5074 5075 devinfo->function.audio.mvol = 100 | (100 << 8); 5076 i = 0; 5077 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5078 if (ctl->enable == 0 || ctl->widget == NULL) { 5079 HDA_BOOTVERBOSE( 5080 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5081 i, (ctl->widget != NULL) ? 5082 ctl->widget->nid : -1); 5083 if (ctl->childwidget != NULL) 5084 kprintf(" childnid=%d", 5085 ctl->childwidget->nid); 5086 if (ctl->widget == NULL) 5087 kprintf(" NULL WIDGET!"); 5088 kprintf(" DISABLED\n"); 5089 ); 5090 continue; 5091 } 5092 HDA_BOOTVERBOSE( 5093 if (ctl->ossmask == 0) { 5094 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5095 i, ctl->widget->nid); 5096 if (ctl->childwidget != NULL) 5097 kprintf(" childnid=%d", 5098 ctl->childwidget->nid); 5099 kprintf(" Bind to NONE\n"); 5100 } 5101 ); 5102 if (ctl->step > 0) { 5103 ctl->ossval = (ctl->left * 100) / ctl->step; 5104 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 5105 } else 5106 ctl->ossval = 0; 5107 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 5108 ctl->left, ctl->right); 5109 } 5110 } 5111 5112 static int 5113 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 5114 { 5115 struct hdac_chan *ch; 5116 struct hdac_widget *w; 5117 uint32_t cap, fmtcap, pcmcap, path; 5118 int i, type, ret, max; 5119 5120 if (dir == PCMDIR_PLAY) { 5121 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 5122 ch = &devinfo->codec->sc->play; 5123 path = HDA_DAC_PATH; 5124 } else { 5125 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 5126 ch = &devinfo->codec->sc->rec; 5127 path = HDA_ADC_PATH; 5128 } 5129 5130 ch->caps = hdac_caps; 5131 ch->caps.fmtlist = ch->fmtlist; 5132 ch->bit16 = 1; 5133 ch->bit32 = 0; 5134 ch->pcmrates[0] = 48000; 5135 ch->pcmrates[1] = 0; 5136 5137 ret = 0; 5138 fmtcap = devinfo->function.audio.supp_stream_formats; 5139 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5140 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 5141 5142 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 5143 w = hdac_widget_get(devinfo, i); 5144 if (w == NULL || w->enable == 0 || w->type != type || 5145 !(w->pflags & path)) 5146 continue; 5147 cap = w->param.widget_cap; 5148 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 5149 continue;*/ 5150 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 5151 continue; 5152 cap = w->param.supp_stream_formats; 5153 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 5154 } 5155 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5156 }*/ 5157 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5158 continue; 5159 if (ret == 0) { 5160 fmtcap = w->param.supp_stream_formats; 5161 pcmcap = w->param.supp_pcm_size_rate; 5162 } else { 5163 fmtcap &= w->param.supp_stream_formats; 5164 pcmcap &= w->param.supp_pcm_size_rate; 5165 } 5166 ch->io[ret++] = i; 5167 } 5168 ch->io[ret] = -1; 5169 5170 ch->supp_stream_formats = fmtcap; 5171 ch->supp_pcm_size_rate = pcmcap; 5172 5173 /* 5174 * 8bit = 0 5175 * 16bit = 1 5176 * 20bit = 2 5177 * 24bit = 3 5178 * 32bit = 4 5179 */ 5180 if (ret > 0) { 5181 cap = pcmcap; 5182 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5183 ch->bit16 = 1; 5184 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5185 ch->bit16 = 0; 5186 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5187 ch->bit32 = 4; 5188 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5189 ch->bit32 = 3; 5190 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5191 ch->bit32 = 2; 5192 i = 0; 5193 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 5194 ch->fmtlist[i++] = AFMT_S16_LE; 5195 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 5196 if (ch->bit32 > 0) { 5197 if (!(devinfo->function.audio.quirks & 5198 HDA_QUIRK_FORCESTEREO)) 5199 ch->fmtlist[i++] = AFMT_S32_LE; 5200 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 5201 } 5202 ch->fmtlist[i] = 0; 5203 i = 0; 5204 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5205 ch->pcmrates[i++] = 8000; 5206 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5207 ch->pcmrates[i++] = 11025; 5208 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5209 ch->pcmrates[i++] = 16000; 5210 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5211 ch->pcmrates[i++] = 22050; 5212 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5213 ch->pcmrates[i++] = 32000; 5214 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5215 ch->pcmrates[i++] = 44100; 5216 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 5217 ch->pcmrates[i++] = 48000; 5218 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5219 ch->pcmrates[i++] = 88200; 5220 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5221 ch->pcmrates[i++] = 96000; 5222 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5223 ch->pcmrates[i++] = 176400; 5224 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5225 ch->pcmrates[i++] = 192000; 5226 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 5227 ch->pcmrates[i] = 0; 5228 if (i > 0) { 5229 ch->caps.minspeed = ch->pcmrates[0]; 5230 ch->caps.maxspeed = ch->pcmrates[i - 1]; 5231 } 5232 } 5233 5234 return (ret); 5235 } 5236 5237 static void 5238 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 5239 { 5240 struct hdac_audio_ctl *ctl; 5241 struct hdac_softc *sc = devinfo->codec->sc; 5242 int i; 5243 uint32_t fl = 0; 5244 5245 5246 if (flag == 0) { 5247 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 5248 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 5249 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 5250 } 5251 5252 i = 0; 5253 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5254 if (ctl->enable == 0 || ctl->widget == NULL || 5255 ctl->widget->enable == 0 || (ctl->ossmask & 5256 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))) 5257 continue; 5258 if ((flag == 0 && (ctl->ossmask & ~fl)) || 5259 (flag != 0 && (ctl->ossmask & flag))) { 5260 if (banner != NULL) { 5261 device_printf(sc->dev, "\n"); 5262 device_printf(sc->dev, "%s\n", banner); 5263 } 5264 goto hdac_ctl_dump_it_all; 5265 } 5266 } 5267 5268 return; 5269 5270 hdac_ctl_dump_it_all: 5271 i = 0; 5272 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5273 if (ctl->enable == 0 || ctl->widget == NULL || 5274 ctl->widget->enable == 0) 5275 continue; 5276 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 5277 (flag != 0 && (ctl->ossmask & flag)))) 5278 continue; 5279 if (flag == 0) { 5280 device_printf(sc->dev, "\n"); 5281 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 5282 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 5283 } 5284 device_printf(sc->dev, " |\n"); 5285 device_printf(sc->dev, " +- nid: %2d index: %2d ", 5286 ctl->widget->nid, ctl->index); 5287 if (ctl->childwidget != NULL) 5288 kprintf("(nid: %2d) ", ctl->childwidget->nid); 5289 else 5290 kprintf(" "); 5291 kprintf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 5292 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 5293 ctl->ossmask); 5294 } 5295 } 5296 5297 static void 5298 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 5299 { 5300 uint32_t cap; 5301 5302 cap = fcap; 5303 if (cap != 0) { 5304 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 5305 device_printf(sc->dev, " Format:"); 5306 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 5307 kprintf(" AC3"); 5308 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 5309 kprintf(" FLOAT32"); 5310 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5311 kprintf(" PCM"); 5312 kprintf("\n"); 5313 } 5314 cap = pcmcap; 5315 if (cap != 0) { 5316 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 5317 device_printf(sc->dev, " PCM size:"); 5318 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5319 kprintf(" 8"); 5320 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5321 kprintf(" 16"); 5322 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5323 kprintf(" 20"); 5324 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5325 kprintf(" 24"); 5326 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5327 kprintf(" 32"); 5328 kprintf("\n"); 5329 device_printf(sc->dev, " PCM rate:"); 5330 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5331 kprintf(" 8"); 5332 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5333 kprintf(" 11"); 5334 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5335 kprintf(" 16"); 5336 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5337 kprintf(" 22"); 5338 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5339 kprintf(" 32"); 5340 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5341 kprintf(" 44"); 5342 kprintf(" 48"); 5343 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5344 kprintf(" 88"); 5345 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5346 kprintf(" 96"); 5347 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5348 kprintf(" 176"); 5349 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5350 kprintf(" 192"); 5351 kprintf("\n"); 5352 } 5353 } 5354 5355 static void 5356 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 5357 { 5358 uint32_t pincap, wcap; 5359 5360 pincap = w->wclass.pin.cap; 5361 wcap = w->param.widget_cap; 5362 5363 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 5364 device_printf(sc->dev, " "); 5365 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 5366 kprintf(" ISC"); 5367 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 5368 kprintf(" TRQD"); 5369 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 5370 kprintf(" PDC"); 5371 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 5372 kprintf(" HP"); 5373 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5374 kprintf(" OUT"); 5375 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5376 kprintf(" IN"); 5377 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 5378 kprintf(" BAL"); 5379 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 5380 kprintf(" VREF["); 5381 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5382 kprintf(" 50"); 5383 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5384 kprintf(" 80"); 5385 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5386 kprintf(" 100"); 5387 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 5388 kprintf(" GROUND"); 5389 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 5390 kprintf(" HIZ"); 5391 kprintf(" ]"); 5392 } 5393 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 5394 kprintf(" EAPD"); 5395 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 5396 kprintf(" : UNSOL"); 5397 kprintf("\n"); 5398 device_printf(sc->dev, " Pin config: 0x%08x\n", 5399 w->wclass.pin.config); 5400 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 5401 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 5402 kprintf(" HP"); 5403 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 5404 kprintf(" IN"); 5405 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 5406 kprintf(" OUT"); 5407 kprintf("\n"); 5408 } 5409 5410 static void 5411 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 5412 { 5413 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 5414 device_printf(sc->dev, " " 5415 "mute=%d step=%d size=%d offset=%d\n", 5416 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 5417 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 5418 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 5419 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 5420 } 5421 5422 static void 5423 hdac_dump_nodes(struct hdac_devinfo *devinfo) 5424 { 5425 struct hdac_softc *sc = devinfo->codec->sc; 5426 struct hdac_widget *w, *cw; 5427 int i, j; 5428 5429 device_printf(sc->dev, "\n"); 5430 device_printf(sc->dev, "Default Parameter\n"); 5431 device_printf(sc->dev, "-----------------\n"); 5432 hdac_dump_audio_formats(sc, 5433 devinfo->function.audio.supp_stream_formats, 5434 devinfo->function.audio.supp_pcm_size_rate); 5435 device_printf(sc->dev, " IN amp: 0x%08x\n", 5436 devinfo->function.audio.inamp_cap); 5437 device_printf(sc->dev, " OUT amp: 0x%08x\n", 5438 devinfo->function.audio.outamp_cap); 5439 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5440 w = hdac_widget_get(devinfo, i); 5441 if (w == NULL) { 5442 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 5443 continue; 5444 } 5445 device_printf(sc->dev, "\n"); 5446 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 5447 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 5448 "DIGITAL" : "ANALOG", 5449 (w->enable == 0) ? " [DISABLED]" : ""); 5450 device_printf(sc->dev, " name: %s\n", w->name); 5451 device_printf(sc->dev, " widget_cap: 0x%08x\n", 5452 w->param.widget_cap); 5453 device_printf(sc->dev, " Parse flags: 0x%08x\n", 5454 w->pflags); 5455 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 5456 w->ctlflags); 5457 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5458 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5459 hdac_dump_audio_formats(sc, 5460 w->param.supp_stream_formats, 5461 w->param.supp_pcm_size_rate); 5462 } else if (w->type == 5463 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5464 hdac_dump_pin(sc, w); 5465 if (w->param.eapdbtl != HDAC_INVALID) 5466 device_printf(sc->dev, " EAPD: 0x%08x\n", 5467 w->param.eapdbtl); 5468 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 5469 w->param.outamp_cap != 0) 5470 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 5471 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 5472 w->param.inamp_cap != 0) 5473 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 5474 device_printf(sc->dev, " connections: %d\n", w->nconns); 5475 for (j = 0; j < w->nconns; j++) { 5476 cw = hdac_widget_get(devinfo, w->conns[j]); 5477 device_printf(sc->dev, " |\n"); 5478 device_printf(sc->dev, " + <- nid=%d [%s]", 5479 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 5480 if (cw == NULL) 5481 kprintf(" [UNKNOWN]"); 5482 else if (cw->enable == 0) 5483 kprintf(" [DISABLED]"); 5484 if (w->nconns > 1 && w->selconn == j && w->type != 5485 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5486 kprintf(" (selected)"); 5487 kprintf("\n"); 5488 } 5489 } 5490 5491 } 5492 5493 static int 5494 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5495 { 5496 struct hdac_widget *w, *cw; 5497 struct hdac_softc *sc = devinfo->codec->sc; 5498 int i; 5499 5500 if (depth > HDA_PARSE_MAXDEPTH) 5501 return (0); 5502 5503 w = hdac_widget_get(devinfo, nid); 5504 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 5505 return (0); 5506 5507 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5508 device_printf(sc->dev, "\n"); 5509 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5510 device_printf(sc->dev, " ^\n"); 5511 device_printf(sc->dev, " |\n"); 5512 device_printf(sc->dev, " +-----<------+\n"); 5513 } else { 5514 device_printf(sc->dev, " ^\n"); 5515 device_printf(sc->dev, " |\n"); 5516 device_printf(sc->dev, " "); 5517 kprintf(" nid=%d [%s]\n", w->nid, w->name); 5518 } 5519 5520 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 5521 return (1); 5522 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 5523 for (i = 0; i < w->nconns; i++) { 5524 cw = hdac_widget_get(devinfo, w->conns[i]); 5525 if (cw == NULL || cw->enable == 0 || cw->type == 5526 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5527 continue; 5528 if (hdac_dump_dac_internal(devinfo, cw->nid, 5529 depth + 1) != 0) 5530 return (1); 5531 } 5532 } else if ((w->type == 5533 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 5534 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5535 w->selconn > -1 && w->selconn < w->nconns) { 5536 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 5537 depth + 1) != 0) 5538 return (1); 5539 } 5540 5541 return (0); 5542 } 5543 5544 static void 5545 hdac_dump_dac(struct hdac_devinfo *devinfo) 5546 { 5547 struct hdac_widget *w; 5548 struct hdac_softc *sc = devinfo->codec->sc; 5549 int i, printed = 0; 5550 5551 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5552 w = hdac_widget_get(devinfo, i); 5553 if (w == NULL || w->enable == 0) 5554 continue; 5555 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 5556 !(w->pflags & HDA_DAC_PATH)) 5557 continue; 5558 if (printed == 0) { 5559 printed = 1; 5560 device_printf(sc->dev, "\n"); 5561 device_printf(sc->dev, "Playback path:\n"); 5562 } 5563 hdac_dump_dac_internal(devinfo, w->nid, 0); 5564 } 5565 } 5566 5567 static void 5568 hdac_dump_adc(struct hdac_devinfo *devinfo) 5569 { 5570 struct hdac_widget *w, *cw; 5571 struct hdac_softc *sc = devinfo->codec->sc; 5572 int i, j; 5573 int printed = 0; 5574 char ossdevs[256]; 5575 5576 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5577 w = hdac_widget_get(devinfo, i); 5578 if (w == NULL || w->enable == 0) 5579 continue; 5580 if (!(w->pflags & HDA_ADC_RECSEL)) 5581 continue; 5582 if (printed == 0) { 5583 printed = 1; 5584 device_printf(sc->dev, "\n"); 5585 device_printf(sc->dev, "Recording sources:\n"); 5586 } 5587 device_printf(sc->dev, "\n"); 5588 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5589 for (j = 0; j < w->nconns; j++) { 5590 cw = hdac_widget_get(devinfo, w->conns[j]); 5591 if (cw == NULL || cw->enable == 0) 5592 continue; 5593 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5594 ossdevs, sizeof(ossdevs)); 5595 device_printf(sc->dev, " |\n"); 5596 device_printf(sc->dev, " + <- nid=%d [%s]", 5597 cw->nid, cw->name); 5598 if (strlen(ossdevs) > 0) { 5599 kprintf(" [recsrc: %s]", ossdevs); 5600 } 5601 kprintf("\n"); 5602 } 5603 } 5604 } 5605 5606 static void 5607 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5608 { 5609 nid_t *nids; 5610 5611 if (pcnt > 0) { 5612 device_printf(sc->dev, "\n"); 5613 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5614 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5615 sc->play.supp_pcm_size_rate); 5616 device_printf(sc->dev, " DAC:"); 5617 for (nids = sc->play.io; *nids != -1; nids++) 5618 kprintf(" %d", *nids); 5619 kprintf("\n"); 5620 } 5621 5622 if (rcnt > 0) { 5623 device_printf(sc->dev, "\n"); 5624 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5625 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5626 sc->rec.supp_pcm_size_rate); 5627 device_printf(sc->dev, " ADC:"); 5628 for (nids = sc->rec.io; *nids != -1; nids++) 5629 kprintf(" %d", *nids); 5630 kprintf("\n"); 5631 } 5632 } 5633 5634 static void 5635 hdac_release_resources(struct hdac_softc *sc) 5636 { 5637 struct hdac_devinfo *devinfo = NULL; 5638 device_t *devlist = NULL; 5639 int i, devcount; 5640 5641 if (sc == NULL) 5642 return; 5643 5644 hdac_lock(sc); 5645 sc->polling = 0; 5646 sc->poll_ival = 0; 5647 callout_stop(&sc->poll_hda); 5648 callout_stop(&sc->poll_hdac); 5649 callout_stop(&sc->poll_jack); 5650 hdac_reset(sc); 5651 hdac_unlock(sc); 5652 5653 hdac_irq_free(sc); 5654 5655 /* give pending interrupts stuck on the lock a chance to clear */ 5656 /* bad hack */ 5657 tsleep(&sc->irq, 0, "hdaslp", hz / 10); 5658 5659 device_get_children(sc->dev, &devlist, &devcount); 5660 for (i = 0; devlist != NULL && i < devcount; i++) { 5661 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5662 if (devinfo == NULL) 5663 continue; 5664 if (devinfo->widget != NULL) 5665 kfree(devinfo->widget, M_HDAC); 5666 if (devinfo->node_type == 5667 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5668 devinfo->function.audio.ctl != NULL) 5669 kfree(devinfo->function.audio.ctl, M_HDAC); 5670 kfree(devinfo, M_HDAC); 5671 device_delete_child(sc->dev, devlist[i]); 5672 } 5673 if (devlist != NULL) 5674 kfree(devlist, M_TEMP); 5675 5676 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5677 if (sc->codecs[i] != NULL) 5678 kfree(sc->codecs[i], M_HDAC); 5679 sc->codecs[i] = NULL; 5680 } 5681 5682 hdac_dma_free(sc, &sc->pos_dma); 5683 hdac_dma_free(sc, &sc->rirb_dma); 5684 hdac_dma_free(sc, &sc->corb_dma); 5685 if (sc->play.blkcnt > 0) 5686 hdac_dma_free(sc, &sc->play.bdl_dma); 5687 if (sc->rec.blkcnt > 0) 5688 hdac_dma_free(sc, &sc->rec.bdl_dma); 5689 if (sc->chan_dmat != NULL) { 5690 bus_dma_tag_destroy(sc->chan_dmat); 5691 sc->chan_dmat = NULL; 5692 } 5693 hdac_mem_free(sc); 5694 snd_mtxfree(sc->lock); 5695 kfree(sc, M_DEVBUF); 5696 } 5697 5698 /* This function surely going to make its way into upper level someday. */ 5699 static void 5700 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5701 { 5702 char *res = NULL; 5703 int i = 0, j, k, len, inv; 5704 5705 if (on != NULL) 5706 *on = 0; 5707 if (off != NULL) 5708 *off = 0; 5709 if (sc == NULL) 5710 return; 5711 if (resource_string_value(device_get_name(sc->dev), 5712 device_get_unit(sc->dev), "config", &res) != 0) 5713 return; 5714 if (!(res != NULL && strlen(res) > 0)) 5715 return; 5716 HDA_BOOTVERBOSE( 5717 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5718 ); 5719 for (;;) { 5720 while (res[i] != '\0' && 5721 (res[i] == ',' || isspace(res[i]) != 0)) 5722 i++; 5723 if (res[i] == '\0') { 5724 HDA_BOOTVERBOSE( 5725 kprintf("\n"); 5726 ); 5727 return; 5728 } 5729 j = i; 5730 while (res[j] != '\0' && 5731 !(res[j] == ',' || isspace(res[j]) != 0)) 5732 j++; 5733 len = j - i; 5734 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5735 inv = 2; 5736 else 5737 inv = 0; 5738 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5739 if (strncmp(res + i + inv, 5740 hdac_quirks_tab[k].key, len - inv) != 0) 5741 continue; 5742 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5743 break; 5744 HDA_BOOTVERBOSE( 5745 kprintf(" %s%s", (inv != 0) ? "no" : "", 5746 hdac_quirks_tab[k].key); 5747 ); 5748 if (inv == 0 && on != NULL) 5749 *on |= hdac_quirks_tab[k].value; 5750 else if (inv != 0 && off != NULL) 5751 *off |= hdac_quirks_tab[k].value; 5752 break; 5753 } 5754 i = j; 5755 } 5756 } 5757 5758 #ifdef SND_DYNSYSCTL 5759 static int 5760 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5761 { 5762 struct hdac_softc *sc; 5763 struct hdac_devinfo *devinfo; 5764 device_t dev; 5765 uint32_t ctl; 5766 int err, val; 5767 5768 dev = oidp->oid_arg1; 5769 devinfo = pcm_getdevinfo(dev); 5770 if (devinfo == NULL || devinfo->codec == NULL || 5771 devinfo->codec->sc == NULL) 5772 return (EINVAL); 5773 sc = devinfo->codec->sc; 5774 hdac_lock(sc); 5775 val = sc->polling; 5776 hdac_unlock(sc); 5777 err = sysctl_handle_int(oidp, &val, 0, req); 5778 5779 if (err != 0 || req->newptr == NULL) 5780 return (err); 5781 if (val < 0 || val > 1) 5782 return (EINVAL); 5783 5784 hdac_lock(sc); 5785 if (val != sc->polling) { 5786 if (hda_chan_active(sc) != 0) 5787 err = EBUSY; 5788 else if (val == 0) { 5789 callout_stop(&sc->poll_hdac); 5790 hdac_unlock(sc); 5791 hdac_lock(sc); 5792 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5793 sc->rirb_size / 2); 5794 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5795 ctl |= HDAC_RIRBCTL_RINTCTL; 5796 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5797 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5798 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5799 sc->polling = 0; 5800 DELAY(1000); 5801 } else { 5802 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5803 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5804 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5805 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5806 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5807 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5808 sc); 5809 sc->polling = 1; 5810 DELAY(1000); 5811 } 5812 } 5813 hdac_unlock(sc); 5814 5815 return (err); 5816 } 5817 5818 static int 5819 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 5820 { 5821 struct hdac_softc *sc; 5822 struct hdac_devinfo *devinfo; 5823 device_t dev; 5824 int err, val; 5825 5826 dev = oidp->oid_arg1; 5827 devinfo = pcm_getdevinfo(dev); 5828 if (devinfo == NULL || devinfo->codec == NULL || 5829 devinfo->codec->sc == NULL) 5830 return (EINVAL); 5831 sc = devinfo->codec->sc; 5832 hdac_lock(sc); 5833 val = ((uint64_t)sc->poll_ival * 1000) / hz; 5834 hdac_unlock(sc); 5835 err = sysctl_handle_int(oidp, &val, 0, req); 5836 5837 if (err != 0 || req->newptr == NULL) 5838 return (err); 5839 5840 if (val < 1) 5841 val = 1; 5842 if (val > 5000) 5843 val = 5000; 5844 val = ((uint64_t)val * hz) / 1000; 5845 if (val < 1) 5846 val = 1; 5847 if (val > (hz * 5)) 5848 val = hz * 5; 5849 5850 hdac_lock(sc); 5851 sc->poll_ival = val; 5852 hdac_unlock(sc); 5853 5854 return (err); 5855 } 5856 5857 #ifdef SND_DEBUG 5858 static int 5859 sysctl_hdac_dump(SYSCTL_HANDLER_ARGS) 5860 { 5861 struct hdac_softc *sc; 5862 struct hdac_devinfo *devinfo; 5863 struct hdac_widget *w; 5864 device_t dev; 5865 uint32_t res, execres; 5866 int i, err, val; 5867 nid_t cad; 5868 5869 dev = oidp->oid_arg1; 5870 devinfo = pcm_getdevinfo(dev); 5871 if (devinfo == NULL || devinfo->codec == NULL || 5872 devinfo->codec->sc == NULL) 5873 return (EINVAL); 5874 val = 0; 5875 err = sysctl_handle_int(oidp, &val, 0, req); 5876 if (err != 0 || req->newptr == NULL || val == 0) 5877 return (err); 5878 sc = devinfo->codec->sc; 5879 cad = devinfo->codec->cad; 5880 hdac_lock(sc); 5881 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid); 5882 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5883 w = hdac_widget_get(devinfo, i); 5884 if (w == NULL || w->type != 5885 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5886 continue; 5887 execres = hdac_command(sc, HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), 5888 cad); 5889 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 5890 device_printf(dev, "nid=%-3d exec=0x%08x sense=0x%08x [%s]\n", 5891 w->nid, execres, res, 5892 (w->enable == 0) ? "DISABLED" : "ENABLED"); 5893 } 5894 device_printf(dev, 5895 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 5896 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 5897 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 5898 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 5899 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 5900 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 5901 if (1 || HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 5902 device_printf(dev, " GPI:"); 5903 res = hdac_command(sc, 5904 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 5905 kprintf(" data=0x%08x", res); 5906 res = hdac_command(sc, 5907 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 5908 cad); 5909 kprintf(" wake=0x%08x", res); 5910 res = hdac_command(sc, 5911 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 5912 cad); 5913 kprintf(" unsol=0x%08x", res); 5914 res = hdac_command(sc, 5915 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 5916 kprintf(" sticky=0x%08x\n", res); 5917 } 5918 if (1 || HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 5919 device_printf(dev, " GPO:"); 5920 res = hdac_command(sc, 5921 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 5922 kprintf(" data=0x%08x\n", res); 5923 } 5924 if (1 || HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 5925 device_printf(dev, "GPI0:"); 5926 res = hdac_command(sc, 5927 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 5928 kprintf(" data=0x%08x", res); 5929 res = hdac_command(sc, 5930 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 5931 kprintf(" enable=0x%08x", res); 5932 res = hdac_command(sc, 5933 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 5934 kprintf(" direction=0x%08x\n", res); 5935 res = hdac_command(sc, 5936 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 5937 device_printf(dev, " wake=0x%08x", res); 5938 res = hdac_command(sc, 5939 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 5940 cad); 5941 kprintf(" unsol=0x%08x", res); 5942 res = hdac_command(sc, 5943 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 5944 kprintf(" sticky=0x%08x\n", res); 5945 } 5946 hdac_unlock(sc); 5947 return (0); 5948 } 5949 #endif 5950 #endif 5951 5952 static void 5953 hdac_attach2(void *arg) 5954 { 5955 struct hdac_softc *sc; 5956 struct hdac_widget *w; 5957 struct hdac_audio_ctl *ctl; 5958 uint32_t quirks_on, quirks_off; 5959 int pcnt, rcnt; 5960 int i; 5961 char status[SND_STATUSLEN]; 5962 device_t *devlist = NULL; 5963 int devcount; 5964 struct hdac_devinfo *devinfo = NULL; 5965 5966 sc = (struct hdac_softc *)arg; 5967 5968 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5969 5970 HDA_BOOTVERBOSE( 5971 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5972 quirks_on, quirks_off); 5973 ); 5974 5975 hdac_lock(sc); 5976 5977 /* Remove ourselves from the config hooks */ 5978 if (sc->intrhook.ich_func != NULL) { 5979 config_intrhook_disestablish(&sc->intrhook); 5980 sc->intrhook.ich_func = NULL; 5981 } 5982 5983 /* Start the corb and rirb engines */ 5984 HDA_BOOTVERBOSE( 5985 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5986 ); 5987 hdac_corb_start(sc); 5988 HDA_BOOTVERBOSE( 5989 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5990 ); 5991 hdac_rirb_start(sc); 5992 5993 HDA_BOOTVERBOSE( 5994 device_printf(sc->dev, 5995 "HDA_DEBUG: Enabling controller interrupt...\n"); 5996 ); 5997 if (sc->polling == 0) 5998 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5999 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6000 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 6001 HDAC_GCTL_UNSOL); 6002 6003 DELAY(1000); 6004 6005 HDA_BOOTVERBOSE( 6006 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 6007 ); 6008 hdac_scan_codecs(sc); 6009 6010 device_get_children(sc->dev, &devlist, &devcount); 6011 for (i = 0; devlist != NULL && i < devcount; i++) { 6012 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 6013 if (devinfo != NULL && devinfo->node_type == 6014 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6015 break; 6016 } else 6017 devinfo = NULL; 6018 } 6019 if (devlist != NULL) 6020 kfree(devlist, M_TEMP); 6021 6022 if (devinfo == NULL) { 6023 hdac_unlock(sc); 6024 device_printf(sc->dev, "Audio Function Group not found!\n"); 6025 hdac_release_resources(sc); 6026 return; 6027 } 6028 6029 HDA_BOOTVERBOSE( 6030 device_printf(sc->dev, 6031 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 6032 devinfo->nid, devinfo->codec->cad); 6033 ); 6034 hdac_audio_parse(devinfo); 6035 HDA_BOOTVERBOSE( 6036 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 6037 ); 6038 hdac_audio_ctl_parse(devinfo); 6039 HDA_BOOTVERBOSE( 6040 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 6041 ); 6042 hdac_vendor_patch_parse(devinfo); 6043 if (quirks_on != 0) 6044 devinfo->function.audio.quirks |= quirks_on; 6045 if (quirks_off != 0) 6046 devinfo->function.audio.quirks &= ~quirks_off; 6047 6048 /* XXX Disable all DIGITAL path. */ 6049 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6050 w = hdac_widget_get(devinfo, i); 6051 if (w == NULL) 6052 continue; 6053 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 6054 w->enable = 0; 6055 continue; 6056 } 6057 /* XXX Disable useless pin ? */ 6058 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6059 (w->wclass.pin.config & 6060 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 6061 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 6062 w->enable = 0; 6063 } 6064 i = 0; 6065 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6066 if (ctl->widget == NULL) 6067 continue; 6068 if (ctl->ossmask & SOUND_MASK_DISABLE) 6069 ctl->enable = 0; 6070 w = ctl->widget; 6071 if (w->enable == 0 || 6072 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6073 ctl->enable = 0; 6074 w = ctl->childwidget; 6075 if (w == NULL) 6076 continue; 6077 if (w->enable == 0 || 6078 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6079 ctl->enable = 0; 6080 } 6081 6082 HDA_BOOTVERBOSE( 6083 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 6084 ); 6085 hdac_audio_build_tree(devinfo); 6086 6087 i = 0; 6088 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6089 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)) 6090 ctl->ossmask = 0; 6091 } 6092 HDA_BOOTVERBOSE( 6093 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 6094 ); 6095 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 6096 HDA_BOOTVERBOSE( 6097 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 6098 ); 6099 hdac_audio_ctl_commit(devinfo); 6100 6101 HDA_BOOTVERBOSE( 6102 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 6103 ); 6104 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 6105 HDA_BOOTVERBOSE( 6106 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 6107 ); 6108 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 6109 6110 hdac_unlock(sc); 6111 HDA_BOOTVERBOSE( 6112 device_printf(sc->dev, 6113 "HDA_DEBUG: OSS mixer initialization...\n"); 6114 ); 6115 6116 /* 6117 * There is no point of return after this. If the driver failed, 6118 * so be it. Let the detach procedure do all the cleanup. 6119 */ 6120 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 6121 device_printf(sc->dev, "Can't register mixer\n"); 6122 6123 if (pcnt > 0) 6124 pcnt = 1; 6125 if (rcnt > 0) 6126 rcnt = 1; 6127 6128 HDA_BOOTVERBOSE( 6129 device_printf(sc->dev, 6130 "HDA_DEBUG: Registering PCM channels...\n"); 6131 ); 6132 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 6133 device_printf(sc->dev, "Can't register PCM\n"); 6134 6135 sc->registered++; 6136 6137 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 6138 hdac_dma_alloc(sc, &sc->pos_dma, 6139 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 6140 HDA_BOOTVERBOSE( 6141 device_printf(sc->dev, 6142 "Failed to allocate DMA pos buffer (non-fatal)\n"); 6143 ); 6144 } 6145 6146 for (i = 0; i < pcnt; i++) 6147 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 6148 for (i = 0; i < rcnt; i++) 6149 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 6150 6151 #ifdef SND_DYNSYSCTL 6152 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev), 6153 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO, 6154 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6155 sysctl_hdac_polling, "I", "Enable polling mode"); 6156 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev), 6157 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO, 6158 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 6159 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 6160 "Controller/Jack Sense polling interval (1-1000 ms)"); 6161 #ifdef SND_DEBUG 6162 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev), 6163 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO, 6164 "dump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6165 sysctl_hdac_dump, "I", "Dump states"); 6166 #endif 6167 #endif 6168 6169 ksnprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 6170 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 6171 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 6172 pcm_setstatus(sc->dev, status); 6173 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 6174 HDA_BOOTVERBOSE( 6175 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 6176 hdac_codec_id(devinfo)); 6177 ); 6178 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 6179 HDA_DRV_TEST_REV); 6180 6181 HDA_BOOTVERBOSE( 6182 if (devinfo->function.audio.quirks != 0) { 6183 device_printf(sc->dev, "\n"); 6184 device_printf(sc->dev, "HDA config/quirks:"); 6185 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 6186 if ((devinfo->function.audio.quirks & 6187 hdac_quirks_tab[i].value) == 6188 hdac_quirks_tab[i].value) 6189 kprintf(" %s", hdac_quirks_tab[i].key); 6190 } 6191 kprintf("\n"); 6192 } 6193 device_printf(sc->dev, "\n"); 6194 device_printf(sc->dev, "+-------------------+\n"); 6195 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 6196 device_printf(sc->dev, "+-------------------+\n"); 6197 hdac_dump_nodes(devinfo); 6198 device_printf(sc->dev, "\n"); 6199 device_printf(sc->dev, "+------------------------+\n"); 6200 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 6201 device_printf(sc->dev, "+------------------------+\n"); 6202 device_printf(sc->dev, "\n"); 6203 i = 0; 6204 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6205 device_printf(sc->dev, "%3d: nid=%d", i, 6206 (ctl->widget != NULL) ? ctl->widget->nid : -1); 6207 if (ctl->childwidget != NULL) 6208 kprintf(" cnid=%d", ctl->childwidget->nid); 6209 kprintf(" dir=0x%x index=%d " 6210 "ossmask=0x%08x ossdev=%d%s\n", 6211 ctl->dir, ctl->index, 6212 ctl->ossmask, ctl->ossdev, 6213 (ctl->enable == 0) ? " [DISABLED]" : ""); 6214 } 6215 device_printf(sc->dev, "\n"); 6216 device_printf(sc->dev, "+-----------------------------------+\n"); 6217 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 6218 device_printf(sc->dev, "+-----------------------------------+\n"); 6219 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 6220 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 6221 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 6222 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 6223 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 6224 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 6225 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 6226 hdac_dump_ctls(devinfo, NULL, 0); 6227 hdac_dump_dac(devinfo); 6228 hdac_dump_adc(devinfo); 6229 device_printf(sc->dev, "\n"); 6230 device_printf(sc->dev, "+--------------------------------------+\n"); 6231 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 6232 device_printf(sc->dev, "+--------------------------------------+\n"); 6233 hdac_dump_pcmchannels(sc, pcnt, rcnt); 6234 ); 6235 6236 if (sc->polling != 0) { 6237 hdac_lock(sc); 6238 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6239 hdac_unlock(sc); 6240 } 6241 } 6242 6243 /**************************************************************************** 6244 * int hdac_detach(device_t) 6245 * 6246 * Detach and free up resources utilized by the hdac device. 6247 ****************************************************************************/ 6248 static int 6249 hdac_detach(device_t dev) 6250 { 6251 struct hdac_softc *sc = NULL; 6252 struct hdac_devinfo *devinfo = NULL; 6253 int err; 6254 6255 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 6256 if (devinfo != NULL && devinfo->codec != NULL) 6257 sc = devinfo->codec->sc; 6258 if (sc == NULL) 6259 return (0); 6260 6261 if (sc->registered > 0) { 6262 err = pcm_unregister(dev); 6263 if (err != 0) 6264 return (err); 6265 } 6266 6267 hdac_release_resources(sc); 6268 6269 return (0); 6270 } 6271 6272 static device_method_t hdac_methods[] = { 6273 /* device interface */ 6274 DEVMETHOD(device_probe, hdac_probe), 6275 DEVMETHOD(device_attach, hdac_attach), 6276 DEVMETHOD(device_detach, hdac_detach), 6277 { 0, 0 } 6278 }; 6279 6280 static driver_t hdac_driver = { 6281 "pcm", 6282 hdac_methods, 6283 PCM_SOFTC_SIZE, 6284 }; 6285 6286 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 6287 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 6288 MODULE_VERSION(snd_hda, 1); 6289