1 /* 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/sound/pci/ich.c,v 1.3.2.12 2003/01/20 03:59:42 orion Exp $ 28 * $DragonFly: src/sys/dev/sound/pci/ich.c,v 1.2 2003/06/17 04:28:30 dillon Exp $ 29 */ 30 31 #include <dev/sound/pcm/sound.h> 32 #include <dev/sound/pcm/ac97.h> 33 #include <dev/sound/pci/ich.h> 34 35 #include <pci/pcireg.h> 36 #include <pci/pcivar.h> 37 38 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/ich.c,v 1.2 2003/06/17 04:28:30 dillon Exp $"); 39 40 /* -------------------------------------------------------------------- */ 41 42 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 43 #define ICH_DTBL_LENGTH 32 44 #define ICH_DEFAULT_BUFSZ 16384 45 #define ICH_MAX_BUFSZ 65536 46 47 #define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */ 48 #define ICH4ID 0x24c58086 /* ICH4 needs special handling too */ 49 50 /* buffer descriptor */ 51 struct ich_desc { 52 volatile u_int32_t buffer; 53 volatile u_int32_t length; 54 }; 55 56 struct sc_info; 57 58 /* channel registers */ 59 struct sc_chinfo { 60 u_int32_t num:8, run:1, run_save:1; 61 u_int32_t blksz, blkcnt, spd; 62 u_int32_t regbase, spdreg; 63 u_int32_t imask; 64 u_int32_t civ; 65 66 struct snd_dbuf *buffer; 67 struct pcm_channel *channel; 68 struct sc_info *parent; 69 70 struct ich_desc *dtbl; 71 }; 72 73 /* device private data */ 74 struct sc_info { 75 device_t dev; 76 int hasvra, hasvrm, hasmic; 77 unsigned int chnum, bufsz; 78 int sample_size, swap_reg; 79 80 struct resource *nambar, *nabmbar, *irq; 81 int nambarid, nabmbarid, irqid; 82 bus_space_tag_t nambart, nabmbart; 83 bus_space_handle_t nambarh, nabmbarh; 84 bus_dma_tag_t dmat; 85 bus_dmamap_t dtmap; 86 void *ih; 87 88 struct ac97_info *codec; 89 struct sc_chinfo ch[3]; 90 int ac97rate; 91 struct ich_desc *dtbl; 92 struct intr_config_hook intrhook; 93 int use_intrhook; 94 }; 95 96 /* -------------------------------------------------------------------- */ 97 98 static u_int32_t ich_fmt[] = { 99 AFMT_STEREO | AFMT_S16_LE, 100 0 101 }; 102 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 103 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 104 105 /* -------------------------------------------------------------------- */ 106 /* Hardware */ 107 static u_int32_t 108 ich_rd(struct sc_info *sc, int regno, int size) 109 { 110 switch (size) { 111 case 1: 112 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 113 case 2: 114 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 115 case 4: 116 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 117 default: 118 return 0xffffffff; 119 } 120 } 121 122 static void 123 ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 124 { 125 switch (size) { 126 case 1: 127 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 128 break; 129 case 2: 130 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 131 break; 132 case 4: 133 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 134 break; 135 } 136 } 137 138 /* ac97 codec */ 139 static int 140 ich_waitcd(void *devinfo) 141 { 142 int i; 143 u_int32_t data; 144 struct sc_info *sc = (struct sc_info *)devinfo; 145 146 for (i = 0; i < ICH_TIMEOUT; i++) { 147 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 148 if ((data & 0x01) == 0) 149 return 0; 150 } 151 device_printf(sc->dev, "CODEC semaphore timeout\n"); 152 return ETIMEDOUT; 153 } 154 155 static int 156 ich_rdcd(kobj_t obj, void *devinfo, int regno) 157 { 158 struct sc_info *sc = (struct sc_info *)devinfo; 159 160 regno &= 0xff; 161 ich_waitcd(sc); 162 163 return bus_space_read_2(sc->nambart, sc->nambarh, regno); 164 } 165 166 static int 167 ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 168 { 169 struct sc_info *sc = (struct sc_info *)devinfo; 170 171 regno &= 0xff; 172 ich_waitcd(sc); 173 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 174 175 return 0; 176 } 177 178 static kobj_method_t ich_ac97_methods[] = { 179 KOBJMETHOD(ac97_read, ich_rdcd), 180 KOBJMETHOD(ac97_write, ich_wrcd), 181 { 0, 0 } 182 }; 183 AC97_DECLARE(ich_ac97); 184 185 /* -------------------------------------------------------------------- */ 186 /* common routines */ 187 188 static void 189 ich_filldtbl(struct sc_chinfo *ch) 190 { 191 u_int32_t base; 192 int i; 193 194 base = vtophys(sndbuf_getbuf(ch->buffer)); 195 ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz; 196 if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) { 197 ch->blkcnt = 2; 198 ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt; 199 } 200 201 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 202 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 203 ch->dtbl[i].length = ICH_BDC_IOC 204 | (ch->blksz / ch->parent->sample_size); 205 } 206 } 207 208 static int 209 ich_resetchan(struct sc_info *sc, int num) 210 { 211 int i, cr, regbase; 212 213 if (num == 0) 214 regbase = ICH_REG_PO_BASE; 215 else if (num == 1) 216 regbase = ICH_REG_PI_BASE; 217 else if (num == 2) 218 regbase = ICH_REG_MC_BASE; 219 else 220 return ENXIO; 221 222 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 223 DELAY(100); 224 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 225 for (i = 0; i < ICH_TIMEOUT; i++) { 226 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 227 if (cr == 0) 228 return 0; 229 } 230 231 device_printf(sc->dev, "cannot reset channel %d\n", num); 232 return ENXIO; 233 } 234 235 /* -------------------------------------------------------------------- */ 236 /* channel interface */ 237 238 static void * 239 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 240 { 241 struct sc_info *sc = devinfo; 242 struct sc_chinfo *ch; 243 unsigned int num; 244 245 num = sc->chnum++; 246 ch = &sc->ch[num]; 247 ch->num = num; 248 ch->buffer = b; 249 ch->channel = c; 250 ch->parent = sc; 251 ch->run = 0; 252 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 253 ch->blkcnt = 2; 254 ch->blksz = sc->bufsz / ch->blkcnt; 255 256 switch(ch->num) { 257 case 0: /* play */ 258 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 259 ch->regbase = ICH_REG_PO_BASE; 260 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 261 ch->imask = ICH_GLOB_STA_POINT; 262 break; 263 264 case 1: /* record */ 265 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 266 ch->regbase = ICH_REG_PI_BASE; 267 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 268 ch->imask = ICH_GLOB_STA_PIINT; 269 break; 270 271 case 2: /* mic */ 272 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 273 ch->regbase = ICH_REG_MC_BASE; 274 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 275 ch->imask = ICH_GLOB_STA_MINT; 276 break; 277 278 default: 279 return NULL; 280 } 281 282 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz)) 283 return NULL; 284 285 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 286 287 return ch; 288 } 289 290 static int 291 ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 292 { 293 return 0; 294 } 295 296 static int 297 ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 298 { 299 struct sc_chinfo *ch = data; 300 struct sc_info *sc = ch->parent; 301 302 if (ch->spdreg) { 303 int r; 304 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 305 sc->ac97rate = 48000; 306 r = (speed * 48000) / sc->ac97rate; 307 /* 308 * Cast the return value of ac97_setrate() to u_int so that 309 * the math don't overflow into the negative range. 310 */ 311 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 312 sc->ac97rate) / 48000; 313 } else { 314 ch->spd = 48000; 315 } 316 return ch->spd; 317 } 318 319 static int 320 ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 321 { 322 struct sc_chinfo *ch = data; 323 struct sc_info *sc = ch->parent; 324 325 ch->blksz = blocksize; 326 ich_filldtbl(ch); 327 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 328 329 return ch->blksz; 330 } 331 332 static int 333 ichchan_trigger(kobj_t obj, void *data, int go) 334 { 335 struct sc_chinfo *ch = data; 336 struct sc_info *sc = ch->parent; 337 338 switch (go) { 339 case PCMTRIG_START: 340 ch->run = 1; 341 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 342 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 343 break; 344 345 case PCMTRIG_ABORT: 346 ich_resetchan(sc, ch->num); 347 ch->run = 0; 348 break; 349 } 350 return 0; 351 } 352 353 static int 354 ichchan_getptr(kobj_t obj, void *data) 355 { 356 struct sc_chinfo *ch = data; 357 struct sc_info *sc = ch->parent; 358 u_int32_t pos; 359 360 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 361 362 pos = ch->civ * ch->blksz; 363 364 return pos; 365 } 366 367 static struct pcmchan_caps * 368 ichchan_getcaps(kobj_t obj, void *data) 369 { 370 struct sc_chinfo *ch = data; 371 372 return ch->spdreg? &ich_vrcaps : &ich_caps; 373 } 374 375 static kobj_method_t ichchan_methods[] = { 376 KOBJMETHOD(channel_init, ichchan_init), 377 KOBJMETHOD(channel_setformat, ichchan_setformat), 378 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 379 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 380 KOBJMETHOD(channel_trigger, ichchan_trigger), 381 KOBJMETHOD(channel_getptr, ichchan_getptr), 382 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 383 { 0, 0 } 384 }; 385 CHANNEL_DECLARE(ichchan); 386 387 /* -------------------------------------------------------------------- */ 388 /* The interrupt handler */ 389 390 static void 391 ich_intr(void *p) 392 { 393 struct sc_info *sc = (struct sc_info *)p; 394 struct sc_chinfo *ch; 395 u_int32_t cbi, lbi, lvi, st, gs; 396 int i; 397 398 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 399 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 400 /* Clear resume interrupt(s) - nothing doing with them */ 401 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 402 } 403 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 404 405 for (i = 0; i < 3; i++) { 406 ch = &sc->ch[i]; 407 if ((ch->imask & gs) == 0) 408 continue; 409 gs &= ~ch->imask; 410 st = ich_rd(sc, ch->regbase + 411 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 412 2); 413 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 414 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 415 /* block complete - update buffer */ 416 if (ch->run) 417 chn_intr(ch->channel); 418 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 419 cbi = ch->civ % ch->blkcnt; 420 if (cbi == 0) 421 cbi = ch->blkcnt - 1; 422 else 423 cbi--; 424 lbi = lvi % ch->blkcnt; 425 if (cbi >= lbi) 426 lvi += cbi - lbi; 427 else 428 lvi += cbi + ch->blkcnt - lbi; 429 lvi %= ICH_DTBL_LENGTH; 430 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 431 432 } 433 /* clear status bit */ 434 ich_wr(sc, ch->regbase + 435 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 436 st, 2); 437 } 438 if (gs != 0) { 439 device_printf(sc->dev, 440 "Unhandled interrupt, gs_intr = %x\n", gs); 441 } 442 } 443 444 /* ------------------------------------------------------------------------- */ 445 /* Sysctl to control ac97 speed (some boards overclocked ac97). */ 446 447 static int 448 ich_initsys(struct sc_info* sc) 449 { 450 #ifdef SND_DYNSYSCTL 451 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 452 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 453 OID_AUTO, "ac97rate", CTLFLAG_RW, 454 &sc->ac97rate, 48000, 455 "AC97 link rate (default = 48000)"); 456 #endif /* SND_DYNSYSCTL */ 457 return 0; 458 } 459 460 /* -------------------------------------------------------------------- */ 461 /* Calibrate card (some boards are overclocked and need scaling) */ 462 463 static 464 void ich_calibrate(void *arg) 465 { 466 struct sc_info *sc; 467 struct sc_chinfo *ch; 468 struct timeval t1, t2; 469 u_int8_t ociv, nciv; 470 u_int32_t wait_us, actual_48k_rate, bytes; 471 472 sc = (struct sc_info *)arg; 473 ch = &sc->ch[1]; 474 475 if (sc->use_intrhook) 476 config_intrhook_disestablish(&sc->intrhook); 477 478 /* 479 * Grab audio from input for fixed interval and compare how 480 * much we actually get with what we expect. Interval needs 481 * to be sufficiently short that no interrupts are 482 * generated. 483 */ 484 485 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 486 487 bytes = sndbuf_getsize(ch->buffer) / 2; 488 ichchan_setblocksize(0, ch, bytes); 489 490 /* 491 * our data format is stereo, 16 bit so each sample is 4 bytes. 492 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 493 * we're going to start recording with interrupts disabled and measure 494 * the time taken for one block to complete. we know the block size, 495 * we know the time in microseconds, we calculate the sample rate: 496 * 497 * actual_rate [bps] = bytes / (time [s] * 4) 498 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 499 * actual_rate [Hz] = (bytes * 250000) / time [us] 500 */ 501 502 /* prepare */ 503 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 504 nciv = ociv; 505 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 506 507 /* start */ 508 microtime(&t1); 509 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 510 511 /* wait */ 512 while (nciv == ociv) { 513 microtime(&t2); 514 if (t2.tv_sec - t1.tv_sec > 1) 515 break; 516 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 517 } 518 microtime(&t2); 519 520 /* stop */ 521 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 522 523 /* reset */ 524 DELAY(100); 525 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 526 527 /* turn time delta into us */ 528 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 529 530 if (nciv == ociv) { 531 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 532 return; 533 } 534 535 actual_48k_rate = (bytes * 250000) / wait_us; 536 537 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 538 sc->ac97rate = actual_48k_rate; 539 } else { 540 sc->ac97rate = 48000; 541 } 542 543 if (bootverbose || sc->ac97rate != 48000) { 544 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 545 if (sc->ac97rate != actual_48k_rate) 546 printf(", will use %d Hz", sc->ac97rate); 547 printf("\n"); 548 } 549 return; 550 } 551 552 /* -------------------------------------------------------------------- */ 553 /* Probe and attach the card */ 554 555 static void 556 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 557 { 558 return; 559 } 560 561 static int 562 ich_init(struct sc_info *sc) 563 { 564 u_int32_t stat; 565 int sz; 566 567 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 568 DELAY(600000); 569 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 570 571 if ((stat & ICH_GLOB_STA_PCR) == 0) { 572 /* ICH4 may fail when busmastering is enabled. Continue */ 573 if (pci_get_devid(sc->dev) != ICH4ID) { 574 return ENXIO; 575 } 576 } 577 578 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 579 580 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 581 return ENXIO; 582 if (sc->hasmic && ich_resetchan(sc, 2)) 583 return ENXIO; 584 585 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 586 return ENOSPC; 587 588 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 589 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, NULL, 0)) { 590 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 591 return ENOSPC; 592 } 593 594 return 0; 595 } 596 597 static int 598 ich_pci_probe(device_t dev) 599 { 600 switch(pci_get_devid(dev)) { 601 case 0x71958086: 602 device_set_desc(dev, "Intel 443MX"); 603 return 0; 604 605 case 0x24158086: 606 device_set_desc(dev, "Intel 82801AA (ICH)"); 607 return 0; 608 609 case 0x24258086: 610 device_set_desc(dev, "Intel 82801AB (ICH)"); 611 return 0; 612 613 case 0x24458086: 614 device_set_desc(dev, "Intel 82801BA (ICH2)"); 615 return 0; 616 617 case 0x24858086: 618 device_set_desc(dev, "Intel 82801CA (ICH3)"); 619 return 0; 620 621 case ICH4ID: 622 device_set_desc(dev, "Intel 82801DB (ICH4)"); 623 return 0; 624 625 case SIS7012ID: 626 device_set_desc(dev, "SiS 7012"); 627 return 0; 628 629 case 0x01b110de: 630 device_set_desc(dev, "Nvidia nForce AC97 controller"); 631 return 0; 632 633 case 0x006a10de: 634 device_set_desc(dev, "Nvidia nForce2 AC97 controller"); 635 return 0; 636 637 default: 638 return ENXIO; 639 } 640 } 641 642 static int 643 ich_pci_attach(device_t dev) 644 { 645 u_int16_t extcaps; 646 struct sc_info *sc; 647 char status[SND_STATUSLEN]; 648 649 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) { 650 device_printf(dev, "cannot allocate softc\n"); 651 return ENXIO; 652 } 653 654 bzero(sc, sizeof(*sc)); 655 sc->dev = dev; 656 657 /* 658 * The SiS 7012 register set isn't quite like the standard ich. 659 * There really should be a general "quirks" mechanism. 660 */ 661 if (pci_get_devid(dev) == SIS7012ID) { 662 sc->swap_reg = 1; 663 sc->sample_size = 1; 664 } else { 665 sc->swap_reg = 0; 666 sc->sample_size = 2; 667 } 668 669 /* 670 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 671 * read-only. Need to enable "legacy support", by poking into 672 * pci config space. The driver should use MMBAR and MBBAR, 673 * but doing so will mess things up here. ich4 has enough new 674 * features it warrants it's own driver. 675 */ 676 if (pci_get_devid(dev) == ICH4ID) { 677 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 678 } 679 680 pci_enable_io(dev, SYS_RES_IOPORT); 681 /* 682 * Enable bus master. On ich4 this may prevent the detection of 683 * the primary codec becoming ready in ich_init(). 684 */ 685 pci_enable_busmaster(dev); 686 687 sc->nambarid = PCIR_NAMBAR; 688 sc->nabmbarid = PCIR_NABMBAR; 689 sc->nambar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nambarid, 0, ~0, 1, RF_ACTIVE); 690 sc->nabmbar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE); 691 692 if (!sc->nambar || !sc->nabmbar) { 693 device_printf(dev, "unable to map IO port space\n"); 694 goto bad; 695 } 696 697 sc->nambart = rman_get_bustag(sc->nambar); 698 sc->nambarh = rman_get_bushandle(sc->nambar); 699 sc->nabmbart = rman_get_bustag(sc->nabmbar); 700 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 701 702 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 703 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 704 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, &sc->dmat) != 0) { 705 device_printf(dev, "unable to create dma tag\n"); 706 goto bad; 707 } 708 709 sc->irqid = 0; 710 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 711 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 712 device_printf(dev, "unable to map interrupt\n"); 713 goto bad; 714 } 715 716 if (ich_init(sc)) { 717 device_printf(dev, "unable to initialize the card\n"); 718 goto bad; 719 } 720 721 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 722 if (sc->codec == NULL) 723 goto bad; 724 mixer_init(dev, ac97_getmixerclass(), sc->codec); 725 726 /* check and set VRA function */ 727 extcaps = ac97_getextcaps(sc->codec); 728 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 729 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 730 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 731 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 732 733 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 734 goto bad; 735 736 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 737 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 738 if (sc->hasmic) 739 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 740 741 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u", 742 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz); 743 744 pcm_setstatus(dev, status); 745 746 ich_initsys(sc); 747 748 sc->intrhook.ich_func = ich_calibrate; 749 sc->intrhook.ich_arg = sc; 750 sc->use_intrhook = 1; 751 if (config_intrhook_establish(&sc->intrhook) != 0) { 752 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 753 sc->use_intrhook = 0; 754 ich_calibrate(sc); 755 } 756 757 return 0; 758 759 bad: 760 if (sc->codec) 761 ac97_destroy(sc->codec); 762 if (sc->ih) 763 bus_teardown_intr(dev, sc->irq, sc->ih); 764 if (sc->irq) 765 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 766 if (sc->nambar) 767 bus_release_resource(dev, SYS_RES_IOPORT, 768 sc->nambarid, sc->nambar); 769 if (sc->nabmbar) 770 bus_release_resource(dev, SYS_RES_IOPORT, 771 sc->nabmbarid, sc->nabmbar); 772 free(sc, M_DEVBUF); 773 return ENXIO; 774 } 775 776 static int 777 ich_pci_detach(device_t dev) 778 { 779 struct sc_info *sc; 780 int r; 781 782 r = pcm_unregister(dev); 783 if (r) 784 return r; 785 sc = pcm_getdevinfo(dev); 786 787 bus_teardown_intr(dev, sc->irq, sc->ih); 788 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 789 bus_release_resource(dev, SYS_RES_IOPORT, sc->nambarid, sc->nambar); 790 bus_release_resource(dev, SYS_RES_IOPORT, sc->nabmbarid, sc->nabmbar); 791 bus_dma_tag_destroy(sc->dmat); 792 free(sc, M_DEVBUF); 793 return 0; 794 } 795 796 static int 797 ich_pci_suspend(device_t dev) 798 { 799 struct sc_info *sc; 800 int i; 801 802 sc = pcm_getdevinfo(dev); 803 for (i = 0 ; i < 3; i++) { 804 sc->ch[i].run_save = sc->ch[i].run; 805 if (sc->ch[i].run) { 806 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 807 } 808 } 809 return 0; 810 } 811 812 static int 813 ich_pci_resume(device_t dev) 814 { 815 struct sc_info *sc; 816 int i; 817 818 sc = pcm_getdevinfo(dev); 819 820 /* Reinit audio device */ 821 if (ich_init(sc) == -1) { 822 device_printf(dev, "unable to reinitialize the card\n"); 823 return ENXIO; 824 } 825 /* Reinit mixer */ 826 if (mixer_reinit(dev) == -1) { 827 device_printf(dev, "unable to reinitialize the mixer\n"); 828 return ENXIO; 829 } 830 /* Re-start DMA engines */ 831 for (i = 0 ; i < 3; i++) { 832 struct sc_chinfo *ch = &sc->ch[i]; 833 if (sc->ch[i].run_save) { 834 ichchan_setblocksize(0, ch, ch->blksz); 835 ichchan_setspeed(0, ch, ch->spd); 836 ichchan_trigger(0, ch, PCMTRIG_START); 837 } 838 } 839 return 0; 840 } 841 842 static device_method_t ich_methods[] = { 843 /* Device interface */ 844 DEVMETHOD(device_probe, ich_pci_probe), 845 DEVMETHOD(device_attach, ich_pci_attach), 846 DEVMETHOD(device_detach, ich_pci_detach), 847 DEVMETHOD(device_suspend, ich_pci_suspend), 848 DEVMETHOD(device_resume, ich_pci_resume), 849 { 0, 0 } 850 }; 851 852 static driver_t ich_driver = { 853 "pcm", 854 ich_methods, 855 PCM_SOFTC_SIZE, 856 }; 857 858 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 859 MODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 860 MODULE_VERSION(snd_ich, 1); 861