1 /* 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <dev/sound/pcm/sound.h> 29 #include <dev/sound/pcm/ac97.h> 30 #include <dev/sound/pci/ich.h> 31 32 #include <pci/pcireg.h> 33 #include <pci/pcivar.h> 34 35 SND_DECLARE_FILE("$FreeBSD: src/sys/dev/sound/pci/ich.c,v 1.3.2.12 2003/01/20 03:59:42 orion Exp $"); 36 37 /* -------------------------------------------------------------------- */ 38 39 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40 #define ICH_DTBL_LENGTH 32 41 #define ICH_DEFAULT_BUFSZ 16384 42 #define ICH_MAX_BUFSZ 65536 43 44 #define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */ 45 #define ICH4ID 0x24c58086 /* ICH4 needs special handling too */ 46 47 /* buffer descriptor */ 48 struct ich_desc { 49 volatile u_int32_t buffer; 50 volatile u_int32_t length; 51 }; 52 53 struct sc_info; 54 55 /* channel registers */ 56 struct sc_chinfo { 57 u_int32_t num:8, run:1, run_save:1; 58 u_int32_t blksz, blkcnt, spd; 59 u_int32_t regbase, spdreg; 60 u_int32_t imask; 61 u_int32_t civ; 62 63 struct snd_dbuf *buffer; 64 struct pcm_channel *channel; 65 struct sc_info *parent; 66 67 struct ich_desc *dtbl; 68 }; 69 70 /* device private data */ 71 struct sc_info { 72 device_t dev; 73 int hasvra, hasvrm, hasmic; 74 unsigned int chnum, bufsz; 75 int sample_size, swap_reg; 76 77 struct resource *nambar, *nabmbar, *irq; 78 int nambarid, nabmbarid, irqid; 79 bus_space_tag_t nambart, nabmbart; 80 bus_space_handle_t nambarh, nabmbarh; 81 bus_dma_tag_t dmat; 82 bus_dmamap_t dtmap; 83 void *ih; 84 85 struct ac97_info *codec; 86 struct sc_chinfo ch[3]; 87 int ac97rate; 88 struct ich_desc *dtbl; 89 struct intr_config_hook intrhook; 90 int use_intrhook; 91 }; 92 93 /* -------------------------------------------------------------------- */ 94 95 static u_int32_t ich_fmt[] = { 96 AFMT_STEREO | AFMT_S16_LE, 97 0 98 }; 99 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 100 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 101 102 /* -------------------------------------------------------------------- */ 103 /* Hardware */ 104 static u_int32_t 105 ich_rd(struct sc_info *sc, int regno, int size) 106 { 107 switch (size) { 108 case 1: 109 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 110 case 2: 111 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 112 case 4: 113 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 114 default: 115 return 0xffffffff; 116 } 117 } 118 119 static void 120 ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 121 { 122 switch (size) { 123 case 1: 124 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 125 break; 126 case 2: 127 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 128 break; 129 case 4: 130 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 131 break; 132 } 133 } 134 135 /* ac97 codec */ 136 static int 137 ich_waitcd(void *devinfo) 138 { 139 int i; 140 u_int32_t data; 141 struct sc_info *sc = (struct sc_info *)devinfo; 142 143 for (i = 0; i < ICH_TIMEOUT; i++) { 144 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 145 if ((data & 0x01) == 0) 146 return 0; 147 } 148 device_printf(sc->dev, "CODEC semaphore timeout\n"); 149 return ETIMEDOUT; 150 } 151 152 static int 153 ich_rdcd(kobj_t obj, void *devinfo, int regno) 154 { 155 struct sc_info *sc = (struct sc_info *)devinfo; 156 157 regno &= 0xff; 158 ich_waitcd(sc); 159 160 return bus_space_read_2(sc->nambart, sc->nambarh, regno); 161 } 162 163 static int 164 ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 165 { 166 struct sc_info *sc = (struct sc_info *)devinfo; 167 168 regno &= 0xff; 169 ich_waitcd(sc); 170 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 171 172 return 0; 173 } 174 175 static kobj_method_t ich_ac97_methods[] = { 176 KOBJMETHOD(ac97_read, ich_rdcd), 177 KOBJMETHOD(ac97_write, ich_wrcd), 178 { 0, 0 } 179 }; 180 AC97_DECLARE(ich_ac97); 181 182 /* -------------------------------------------------------------------- */ 183 /* common routines */ 184 185 static void 186 ich_filldtbl(struct sc_chinfo *ch) 187 { 188 u_int32_t base; 189 int i; 190 191 base = vtophys(sndbuf_getbuf(ch->buffer)); 192 ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz; 193 if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) { 194 ch->blkcnt = 2; 195 ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt; 196 } 197 198 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 199 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 200 ch->dtbl[i].length = ICH_BDC_IOC 201 | (ch->blksz / ch->parent->sample_size); 202 } 203 } 204 205 static int 206 ich_resetchan(struct sc_info *sc, int num) 207 { 208 int i, cr, regbase; 209 210 if (num == 0) 211 regbase = ICH_REG_PO_BASE; 212 else if (num == 1) 213 regbase = ICH_REG_PI_BASE; 214 else if (num == 2) 215 regbase = ICH_REG_MC_BASE; 216 else 217 return ENXIO; 218 219 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 220 DELAY(100); 221 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 222 for (i = 0; i < ICH_TIMEOUT; i++) { 223 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 224 if (cr == 0) 225 return 0; 226 } 227 228 device_printf(sc->dev, "cannot reset channel %d\n", num); 229 return ENXIO; 230 } 231 232 /* -------------------------------------------------------------------- */ 233 /* channel interface */ 234 235 static void * 236 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 237 { 238 struct sc_info *sc = devinfo; 239 struct sc_chinfo *ch; 240 unsigned int num; 241 242 num = sc->chnum++; 243 ch = &sc->ch[num]; 244 ch->num = num; 245 ch->buffer = b; 246 ch->channel = c; 247 ch->parent = sc; 248 ch->run = 0; 249 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 250 ch->blkcnt = 2; 251 ch->blksz = sc->bufsz / ch->blkcnt; 252 253 switch(ch->num) { 254 case 0: /* play */ 255 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 256 ch->regbase = ICH_REG_PO_BASE; 257 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 258 ch->imask = ICH_GLOB_STA_POINT; 259 break; 260 261 case 1: /* record */ 262 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 263 ch->regbase = ICH_REG_PI_BASE; 264 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 265 ch->imask = ICH_GLOB_STA_PIINT; 266 break; 267 268 case 2: /* mic */ 269 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 270 ch->regbase = ICH_REG_MC_BASE; 271 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 272 ch->imask = ICH_GLOB_STA_MINT; 273 break; 274 275 default: 276 return NULL; 277 } 278 279 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz)) 280 return NULL; 281 282 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 283 284 return ch; 285 } 286 287 static int 288 ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 289 { 290 return 0; 291 } 292 293 static int 294 ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 295 { 296 struct sc_chinfo *ch = data; 297 struct sc_info *sc = ch->parent; 298 299 if (ch->spdreg) { 300 int r; 301 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 302 sc->ac97rate = 48000; 303 r = (speed * 48000) / sc->ac97rate; 304 /* 305 * Cast the return value of ac97_setrate() to u_int so that 306 * the math don't overflow into the negative range. 307 */ 308 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 309 sc->ac97rate) / 48000; 310 } else { 311 ch->spd = 48000; 312 } 313 return ch->spd; 314 } 315 316 static int 317 ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 318 { 319 struct sc_chinfo *ch = data; 320 struct sc_info *sc = ch->parent; 321 322 ch->blksz = blocksize; 323 ich_filldtbl(ch); 324 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 325 326 return ch->blksz; 327 } 328 329 static int 330 ichchan_trigger(kobj_t obj, void *data, int go) 331 { 332 struct sc_chinfo *ch = data; 333 struct sc_info *sc = ch->parent; 334 335 switch (go) { 336 case PCMTRIG_START: 337 ch->run = 1; 338 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 339 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 340 break; 341 342 case PCMTRIG_ABORT: 343 ich_resetchan(sc, ch->num); 344 ch->run = 0; 345 break; 346 } 347 return 0; 348 } 349 350 static int 351 ichchan_getptr(kobj_t obj, void *data) 352 { 353 struct sc_chinfo *ch = data; 354 struct sc_info *sc = ch->parent; 355 u_int32_t pos; 356 357 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 358 359 pos = ch->civ * ch->blksz; 360 361 return pos; 362 } 363 364 static struct pcmchan_caps * 365 ichchan_getcaps(kobj_t obj, void *data) 366 { 367 struct sc_chinfo *ch = data; 368 369 return ch->spdreg? &ich_vrcaps : &ich_caps; 370 } 371 372 static kobj_method_t ichchan_methods[] = { 373 KOBJMETHOD(channel_init, ichchan_init), 374 KOBJMETHOD(channel_setformat, ichchan_setformat), 375 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 376 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 377 KOBJMETHOD(channel_trigger, ichchan_trigger), 378 KOBJMETHOD(channel_getptr, ichchan_getptr), 379 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 380 { 0, 0 } 381 }; 382 CHANNEL_DECLARE(ichchan); 383 384 /* -------------------------------------------------------------------- */ 385 /* The interrupt handler */ 386 387 static void 388 ich_intr(void *p) 389 { 390 struct sc_info *sc = (struct sc_info *)p; 391 struct sc_chinfo *ch; 392 u_int32_t cbi, lbi, lvi, st, gs; 393 int i; 394 395 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 396 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 397 /* Clear resume interrupt(s) - nothing doing with them */ 398 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 399 } 400 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 401 402 for (i = 0; i < 3; i++) { 403 ch = &sc->ch[i]; 404 if ((ch->imask & gs) == 0) 405 continue; 406 gs &= ~ch->imask; 407 st = ich_rd(sc, ch->regbase + 408 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 409 2); 410 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 411 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 412 /* block complete - update buffer */ 413 if (ch->run) 414 chn_intr(ch->channel); 415 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 416 cbi = ch->civ % ch->blkcnt; 417 if (cbi == 0) 418 cbi = ch->blkcnt - 1; 419 else 420 cbi--; 421 lbi = lvi % ch->blkcnt; 422 if (cbi >= lbi) 423 lvi += cbi - lbi; 424 else 425 lvi += cbi + ch->blkcnt - lbi; 426 lvi %= ICH_DTBL_LENGTH; 427 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 428 429 } 430 /* clear status bit */ 431 ich_wr(sc, ch->regbase + 432 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 433 st, 2); 434 } 435 if (gs != 0) { 436 device_printf(sc->dev, 437 "Unhandled interrupt, gs_intr = %x\n", gs); 438 } 439 } 440 441 /* ------------------------------------------------------------------------- */ 442 /* Sysctl to control ac97 speed (some boards overclocked ac97). */ 443 444 static int 445 ich_initsys(struct sc_info* sc) 446 { 447 #ifdef SND_DYNSYSCTL 448 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 449 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 450 OID_AUTO, "ac97rate", CTLFLAG_RW, 451 &sc->ac97rate, 48000, 452 "AC97 link rate (default = 48000)"); 453 #endif /* SND_DYNSYSCTL */ 454 return 0; 455 } 456 457 /* -------------------------------------------------------------------- */ 458 /* Calibrate card (some boards are overclocked and need scaling) */ 459 460 static 461 void ich_calibrate(void *arg) 462 { 463 struct sc_info *sc; 464 struct sc_chinfo *ch; 465 struct timeval t1, t2; 466 u_int8_t ociv, nciv; 467 u_int32_t wait_us, actual_48k_rate, bytes; 468 469 sc = (struct sc_info *)arg; 470 ch = &sc->ch[1]; 471 472 if (sc->use_intrhook) 473 config_intrhook_disestablish(&sc->intrhook); 474 475 /* 476 * Grab audio from input for fixed interval and compare how 477 * much we actually get with what we expect. Interval needs 478 * to be sufficiently short that no interrupts are 479 * generated. 480 */ 481 482 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 483 484 bytes = sndbuf_getsize(ch->buffer) / 2; 485 ichchan_setblocksize(0, ch, bytes); 486 487 /* 488 * our data format is stereo, 16 bit so each sample is 4 bytes. 489 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 490 * we're going to start recording with interrupts disabled and measure 491 * the time taken for one block to complete. we know the block size, 492 * we know the time in microseconds, we calculate the sample rate: 493 * 494 * actual_rate [bps] = bytes / (time [s] * 4) 495 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 496 * actual_rate [Hz] = (bytes * 250000) / time [us] 497 */ 498 499 /* prepare */ 500 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 501 nciv = ociv; 502 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 503 504 /* start */ 505 microtime(&t1); 506 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 507 508 /* wait */ 509 while (nciv == ociv) { 510 microtime(&t2); 511 if (t2.tv_sec - t1.tv_sec > 1) 512 break; 513 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 514 } 515 microtime(&t2); 516 517 /* stop */ 518 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 519 520 /* reset */ 521 DELAY(100); 522 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 523 524 /* turn time delta into us */ 525 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 526 527 if (nciv == ociv) { 528 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 529 return; 530 } 531 532 actual_48k_rate = (bytes * 250000) / wait_us; 533 534 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 535 sc->ac97rate = actual_48k_rate; 536 } else { 537 sc->ac97rate = 48000; 538 } 539 540 if (bootverbose || sc->ac97rate != 48000) { 541 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 542 if (sc->ac97rate != actual_48k_rate) 543 printf(", will use %d Hz", sc->ac97rate); 544 printf("\n"); 545 } 546 return; 547 } 548 549 /* -------------------------------------------------------------------- */ 550 /* Probe and attach the card */ 551 552 static void 553 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 554 { 555 return; 556 } 557 558 static int 559 ich_init(struct sc_info *sc) 560 { 561 u_int32_t stat; 562 int sz; 563 564 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 565 DELAY(600000); 566 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 567 568 if ((stat & ICH_GLOB_STA_PCR) == 0) { 569 /* ICH4 may fail when busmastering is enabled. Continue */ 570 if (pci_get_devid(sc->dev) != ICH4ID) { 571 return ENXIO; 572 } 573 } 574 575 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 576 577 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 578 return ENXIO; 579 if (sc->hasmic && ich_resetchan(sc, 2)) 580 return ENXIO; 581 582 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 583 return ENOSPC; 584 585 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 586 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, NULL, 0)) { 587 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 588 return ENOSPC; 589 } 590 591 return 0; 592 } 593 594 static int 595 ich_pci_probe(device_t dev) 596 { 597 switch(pci_get_devid(dev)) { 598 case 0x71958086: 599 device_set_desc(dev, "Intel 443MX"); 600 return 0; 601 602 case 0x24158086: 603 device_set_desc(dev, "Intel 82801AA (ICH)"); 604 return 0; 605 606 case 0x24258086: 607 device_set_desc(dev, "Intel 82801AB (ICH)"); 608 return 0; 609 610 case 0x24458086: 611 device_set_desc(dev, "Intel 82801BA (ICH2)"); 612 return 0; 613 614 case 0x24858086: 615 device_set_desc(dev, "Intel 82801CA (ICH3)"); 616 return 0; 617 618 case ICH4ID: 619 device_set_desc(dev, "Intel 82801DB (ICH4)"); 620 return 0; 621 622 case SIS7012ID: 623 device_set_desc(dev, "SiS 7012"); 624 return 0; 625 626 case 0x01b110de: 627 device_set_desc(dev, "Nvidia nForce AC97 controller"); 628 return 0; 629 630 case 0x006a10de: 631 device_set_desc(dev, "Nvidia nForce2 AC97 controller"); 632 return 0; 633 634 default: 635 return ENXIO; 636 } 637 } 638 639 static int 640 ich_pci_attach(device_t dev) 641 { 642 u_int16_t extcaps; 643 struct sc_info *sc; 644 char status[SND_STATUSLEN]; 645 646 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) { 647 device_printf(dev, "cannot allocate softc\n"); 648 return ENXIO; 649 } 650 651 bzero(sc, sizeof(*sc)); 652 sc->dev = dev; 653 654 /* 655 * The SiS 7012 register set isn't quite like the standard ich. 656 * There really should be a general "quirks" mechanism. 657 */ 658 if (pci_get_devid(dev) == SIS7012ID) { 659 sc->swap_reg = 1; 660 sc->sample_size = 1; 661 } else { 662 sc->swap_reg = 0; 663 sc->sample_size = 2; 664 } 665 666 /* 667 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 668 * read-only. Need to enable "legacy support", by poking into 669 * pci config space. The driver should use MMBAR and MBBAR, 670 * but doing so will mess things up here. ich4 has enough new 671 * features it warrants it's own driver. 672 */ 673 if (pci_get_devid(dev) == ICH4ID) { 674 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 675 } 676 677 pci_enable_io(dev, SYS_RES_IOPORT); 678 /* 679 * Enable bus master. On ich4 this may prevent the detection of 680 * the primary codec becoming ready in ich_init(). 681 */ 682 pci_enable_busmaster(dev); 683 684 sc->nambarid = PCIR_NAMBAR; 685 sc->nabmbarid = PCIR_NABMBAR; 686 sc->nambar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nambarid, 0, ~0, 1, RF_ACTIVE); 687 sc->nabmbar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE); 688 689 if (!sc->nambar || !sc->nabmbar) { 690 device_printf(dev, "unable to map IO port space\n"); 691 goto bad; 692 } 693 694 sc->nambart = rman_get_bustag(sc->nambar); 695 sc->nambarh = rman_get_bushandle(sc->nambar); 696 sc->nabmbart = rman_get_bustag(sc->nabmbar); 697 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 698 699 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 700 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 701 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, &sc->dmat) != 0) { 702 device_printf(dev, "unable to create dma tag\n"); 703 goto bad; 704 } 705 706 sc->irqid = 0; 707 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 708 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 709 device_printf(dev, "unable to map interrupt\n"); 710 goto bad; 711 } 712 713 if (ich_init(sc)) { 714 device_printf(dev, "unable to initialize the card\n"); 715 goto bad; 716 } 717 718 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 719 if (sc->codec == NULL) 720 goto bad; 721 mixer_init(dev, ac97_getmixerclass(), sc->codec); 722 723 /* check and set VRA function */ 724 extcaps = ac97_getextcaps(sc->codec); 725 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 726 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 727 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 728 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 729 730 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 731 goto bad; 732 733 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 734 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 735 if (sc->hasmic) 736 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 737 738 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u", 739 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz); 740 741 pcm_setstatus(dev, status); 742 743 ich_initsys(sc); 744 745 sc->intrhook.ich_func = ich_calibrate; 746 sc->intrhook.ich_arg = sc; 747 sc->use_intrhook = 1; 748 if (config_intrhook_establish(&sc->intrhook) != 0) { 749 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 750 sc->use_intrhook = 0; 751 ich_calibrate(sc); 752 } 753 754 return 0; 755 756 bad: 757 if (sc->codec) 758 ac97_destroy(sc->codec); 759 if (sc->ih) 760 bus_teardown_intr(dev, sc->irq, sc->ih); 761 if (sc->irq) 762 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 763 if (sc->nambar) 764 bus_release_resource(dev, SYS_RES_IOPORT, 765 sc->nambarid, sc->nambar); 766 if (sc->nabmbar) 767 bus_release_resource(dev, SYS_RES_IOPORT, 768 sc->nabmbarid, sc->nabmbar); 769 free(sc, M_DEVBUF); 770 return ENXIO; 771 } 772 773 static int 774 ich_pci_detach(device_t dev) 775 { 776 struct sc_info *sc; 777 int r; 778 779 r = pcm_unregister(dev); 780 if (r) 781 return r; 782 sc = pcm_getdevinfo(dev); 783 784 bus_teardown_intr(dev, sc->irq, sc->ih); 785 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 786 bus_release_resource(dev, SYS_RES_IOPORT, sc->nambarid, sc->nambar); 787 bus_release_resource(dev, SYS_RES_IOPORT, sc->nabmbarid, sc->nabmbar); 788 bus_dma_tag_destroy(sc->dmat); 789 free(sc, M_DEVBUF); 790 return 0; 791 } 792 793 static int 794 ich_pci_suspend(device_t dev) 795 { 796 struct sc_info *sc; 797 int i; 798 799 sc = pcm_getdevinfo(dev); 800 for (i = 0 ; i < 3; i++) { 801 sc->ch[i].run_save = sc->ch[i].run; 802 if (sc->ch[i].run) { 803 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 804 } 805 } 806 return 0; 807 } 808 809 static int 810 ich_pci_resume(device_t dev) 811 { 812 struct sc_info *sc; 813 int i; 814 815 sc = pcm_getdevinfo(dev); 816 817 /* Reinit audio device */ 818 if (ich_init(sc) == -1) { 819 device_printf(dev, "unable to reinitialize the card\n"); 820 return ENXIO; 821 } 822 /* Reinit mixer */ 823 if (mixer_reinit(dev) == -1) { 824 device_printf(dev, "unable to reinitialize the mixer\n"); 825 return ENXIO; 826 } 827 /* Re-start DMA engines */ 828 for (i = 0 ; i < 3; i++) { 829 struct sc_chinfo *ch = &sc->ch[i]; 830 if (sc->ch[i].run_save) { 831 ichchan_setblocksize(0, ch, ch->blksz); 832 ichchan_setspeed(0, ch, ch->spd); 833 ichchan_trigger(0, ch, PCMTRIG_START); 834 } 835 } 836 return 0; 837 } 838 839 static device_method_t ich_methods[] = { 840 /* Device interface */ 841 DEVMETHOD(device_probe, ich_pci_probe), 842 DEVMETHOD(device_attach, ich_pci_attach), 843 DEVMETHOD(device_detach, ich_pci_detach), 844 DEVMETHOD(device_suspend, ich_pci_suspend), 845 DEVMETHOD(device_resume, ich_pci_resume), 846 { 0, 0 } 847 }; 848 849 static driver_t ich_driver = { 850 "pcm", 851 ich_methods, 852 PCM_SOFTC_SIZE, 853 }; 854 855 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 856 MODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 857 MODULE_VERSION(snd_ich, 1); 858