1 /* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/kernel.h> 31 #include <sys/ktr.h> 32 #include <sys/bus.h> 33 #include <sys/machintr.h> 34 #include <sys/malloc.h> 35 #include <sys/sysctl.h> 36 #include <machine/globaldata.h> 37 #include <machine/clock.h> 38 #include <machine/limits.h> 39 #include <machine/smp.h> 40 #include <machine/md_var.h> 41 #include <machine/pmap.h> 42 #include <machine/specialreg.h> 43 #include <machine_base/apic/lapic.h> 44 #include <machine_base/apic/ioapic.h> 45 #include <machine_base/apic/ioapic_abi.h> 46 #include <machine_base/apic/apicvar.h> 47 #include <machine_base/icu/icu_var.h> 48 #include <machine/segments.h> 49 #include <sys/spinlock2.h> 50 51 #include <machine/cputypes.h> 52 #include <machine/intr_machdep.h> 53 54 #if !defined(KTR_LAPIC) 55 #define KTR_LAPIC KTR_ALL 56 #endif 57 KTR_INFO_MASTER(lapic); 58 KTR_INFO(KTR_LAPIC, lapic, mem_eoi, 0, "mem_eoi"); 59 KTR_INFO(KTR_LAPIC, lapic, msr_eoi, 0, "msr_eoi"); 60 #define log_lapic(name) KTR_LOG(lapic_ ## name) 61 62 extern int naps; 63 64 volatile lapic_t *lapic_mem; 65 66 static void lapic_timer_calibrate(void); 67 static void lapic_timer_set_divisor(int); 68 static void lapic_timer_fixup_handler(void *); 69 static void lapic_timer_restart_handler(void *); 70 71 static int lapic_timer_c1e_test = -1; /* auto-detect */ 72 TUNABLE_INT("hw.lapic_timer_c1e_test", &lapic_timer_c1e_test); 73 74 static int lapic_timer_enable = 1; 75 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable); 76 77 static int lapic_timer_tscdeadline = 1; 78 TUNABLE_INT("hw.lapic_timer_tscdeadline", &lapic_timer_tscdeadline); 79 80 static int lapic_calibrate_test = 0; 81 TUNABLE_INT("hw.lapic_calibrate_test", &lapic_calibrate_test); 82 83 static int lapic_calibrate_fast = 1; 84 TUNABLE_INT("hw.lapic_calibrate_fast", &lapic_calibrate_fast); 85 86 static void lapic_timer_tscdlt_reload(struct cputimer_intr *, sysclock_t); 87 static void lapic_mem_timer_intr_reload(struct cputimer_intr *, sysclock_t); 88 static void lapic_msr_timer_intr_reload(struct cputimer_intr *, sysclock_t); 89 static void lapic_timer_intr_enable(struct cputimer_intr *); 90 static void lapic_timer_intr_restart(struct cputimer_intr *); 91 static void lapic_timer_intr_pmfixup(struct cputimer_intr *); 92 93 static struct cputimer_intr lapic_cputimer_intr = { 94 .freq = 0, 95 .reload = lapic_mem_timer_intr_reload, 96 .enable = lapic_timer_intr_enable, 97 .config = cputimer_intr_default_config, 98 .restart = lapic_timer_intr_restart, 99 .pmfixup = lapic_timer_intr_pmfixup, 100 .initclock = cputimer_intr_default_initclock, 101 .pcpuhand = NULL, 102 .next = SLIST_ENTRY_INITIALIZER, 103 .name = "lapic", 104 .type = CPUTIMER_INTR_LAPIC, 105 .prio = CPUTIMER_INTR_PRIO_LAPIC, 106 .caps = CPUTIMER_INTR_CAP_NONE, 107 .priv = NULL 108 }; 109 110 static int lapic_timer_divisor_idx = -1; 111 static const uint32_t lapic_timer_divisors[] = { 112 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 113 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1 114 }; 115 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors)) 116 117 static int lapic_use_tscdeadline = 0; 118 119 /* 120 * APIC ID <-> CPU ID mapping structures. 121 */ 122 int cpu_id_to_apic_id[NAPICID]; 123 int apic_id_to_cpu_id[NAPICID]; 124 int lapic_enable = 1; 125 int lapic_usable = 0; 126 int x2apic_enable = 1; 127 128 SYSCTL_INT(_hw, OID_AUTO, x2apic_enable, CTLFLAG_RD, &x2apic_enable, 0, ""); 129 130 /* Separate cachelines for each cpu's info. */ 131 struct deadlines { 132 uint64_t timestamp; 133 uint64_t downcount_time; 134 uint64_t padding[6]; 135 }; 136 struct deadlines *tsc_deadlines = NULL; 137 138 static void lapic_mem_eoi(void); 139 static int lapic_mem_ipi(int dest_type, int vector, int delivery_mode); 140 static void lapic_mem_single_ipi(int cpu, int vector, int delivery_mode); 141 142 static void lapic_msr_eoi(void); 143 static int lapic_msr_ipi(int dest_type, int vector, int delivery_mode); 144 static void lapic_msr_single_ipi(int cpu, int vector, int delivery_mode); 145 146 void (*lapic_eoi)(void); 147 int (*apic_ipi)(int dest_type, int vector, int delivery_mode); 148 void (*single_apic_ipi)(int cpu, int vector, int delivery_mode); 149 150 static __inline void 151 lapic_mem_icr_set(uint32_t apic_id, uint32_t icr_lo_val) 152 { 153 uint32_t icr_lo, icr_hi; 154 155 icr_hi = (LAPIC_MEM_READ(icr_hi) & ~APIC_ID_MASK) | 156 (apic_id << APIC_ID_SHIFT); 157 icr_lo = (LAPIC_MEM_READ(icr_lo) & APIC_ICRLO_RESV_MASK) | icr_lo_val; 158 159 LAPIC_MEM_WRITE(icr_hi, icr_hi); 160 LAPIC_MEM_WRITE(icr_lo, icr_lo); 161 } 162 163 static __inline void 164 lapic_msr_icr_set(uint32_t apic_id, uint32_t icr_lo_val) 165 { 166 LAPIC_MSR_WRITE(MSR_X2APIC_ICR, 167 ((uint64_t)apic_id << 32) | ((uint64_t)icr_lo_val)); 168 } 169 170 /* 171 * Enable LAPIC, configure interrupts. 172 */ 173 void 174 lapic_init(boolean_t bsp) 175 { 176 uint32_t timer; 177 u_int temp; 178 179 if (bsp) { 180 /* Decide whether we want to use TSC Deadline mode. */ 181 if (lapic_timer_tscdeadline != 0 && 182 (cpu_feature2 & CPUID2_TSCDLT) && 183 tsc_invariant && tsc_frequency != 0) { 184 lapic_use_tscdeadline = 1; 185 tsc_deadlines = 186 kmalloc(sizeof(struct deadlines) * (naps + 1), 187 M_DEVBUF, 188 M_WAITOK | M_ZERO | M_CACHEALIGN); 189 } 190 } 191 192 /* 193 * Install vectors 194 * 195 * Since IDT is shared between BSP and APs, these vectors 196 * only need to be installed once; we do it on BSP. 197 */ 198 if (bsp) { 199 if (cpu_vendor_id == CPU_VENDOR_AMD && 200 CPUID_TO_FAMILY(cpu_id) >= 0x0f && 201 CPUID_TO_FAMILY(cpu_id) < 0x17) { /* XXX */ 202 uint32_t tcr; 203 204 /* 205 * Set the LINTEN bit in the HyperTransport 206 * Transaction Control Register. 207 * 208 * This will cause EXTINT and NMI interrupts 209 * routed over the hypertransport bus to be 210 * fed into the LAPIC LINT0/LINT1. If the bit 211 * isn't set, the interrupts will go to the 212 * general cpu INTR/NMI pins. On a dual-core 213 * cpu the interrupt winds up going to BOTH cpus. 214 * The first cpu that does the interrupt ack 215 * cycle will get the correct interrupt. The 216 * second cpu that does it will get a spurious 217 * interrupt vector (typically IRQ 7). 218 */ 219 outl(0x0cf8, 220 (1 << 31) | /* enable */ 221 (0 << 16) | /* bus */ 222 (0x18 << 11) | /* dev (cpu + 0x18) */ 223 (0 << 8) | /* func */ 224 0x68 /* reg */ 225 ); 226 tcr = inl(0xcfc); 227 if ((tcr & 0x00010000) == 0) { 228 kprintf("LAPIC: AMD LINTEN on\n"); 229 outl(0xcfc, tcr|0x00010000); 230 } 231 outl(0x0cf8, 0); 232 } 233 234 /* Install a 'Spurious INTerrupt' vector */ 235 setidt_global(XSPURIOUSINT_OFFSET, Xspuriousint, 236 SDT_SYSIGT, SEL_KPL, 0); 237 238 /* Install a timer vector */ 239 setidt_global(XTIMER_OFFSET, Xtimer, 240 SDT_SYSIGT, SEL_KPL, 0); 241 242 /* Install an inter-CPU IPI for TLB invalidation */ 243 setidt_global(XINVLTLB_OFFSET, Xinvltlb, 244 SDT_SYSIGT, SEL_KPL, 0); 245 246 /* Install an inter-CPU IPI for IPIQ messaging */ 247 setidt_global(XIPIQ_OFFSET, Xipiq, 248 SDT_SYSIGT, SEL_KPL, 0); 249 250 /* Install an inter-CPU IPI for CPU stop/restart */ 251 setidt_global(XCPUSTOP_OFFSET, Xcpustop, 252 SDT_SYSIGT, SEL_KPL, 0); 253 254 /* Install an inter-CPU IPI for TLB invalidation */ 255 setidt_global(XSNIFF_OFFSET, Xsniff, 256 SDT_SYSIGT, SEL_KPL, 0); 257 } 258 259 /* 260 * Setup LINT0 as ExtINT on the BSP. This is theoretically an 261 * aggregate interrupt input from the 8259. The INTA cycle 262 * will be routed to the external controller (the 8259) which 263 * is expected to supply the vector. 264 * 265 * Must be setup edge triggered, active high. 266 * 267 * Disable LINT0 on BSP, if I/O APIC is enabled. 268 * 269 * Disable LINT0 on the APs. It doesn't matter what delivery 270 * mode we use because we leave it masked. 271 */ 272 temp = LAPIC_READ(lvt_lint0); 273 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK | 274 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK); 275 if (bsp) { 276 temp |= APIC_LVT_DM_EXTINT; 277 if (ioapic_enable) 278 temp |= APIC_LVT_MASKED; 279 } else { 280 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED; 281 } 282 LAPIC_WRITE(lvt_lint0, temp); 283 284 /* 285 * Setup LINT1 as NMI. 286 * 287 * Must be setup edge trigger, active high. 288 * 289 * Enable LINT1 on BSP, if I/O APIC is enabled. 290 * 291 * Disable LINT1 on the APs. 292 */ 293 temp = LAPIC_READ(lvt_lint1); 294 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK | 295 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK); 296 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI; 297 if (bsp && ioapic_enable) 298 temp &= ~APIC_LVT_MASKED; 299 LAPIC_WRITE(lvt_lint1, temp); 300 301 /* 302 * Mask the LAPIC error interrupt, LAPIC performance counter 303 * interrupt. 304 */ 305 LAPIC_WRITE(lvt_error, LAPIC_READ(lvt_error) | APIC_LVT_MASKED); 306 LAPIC_WRITE(lvt_pcint, LAPIC_READ(lvt_pcint) | APIC_LVT_MASKED); 307 308 /* 309 * Set LAPIC timer vector and mask the LAPIC timer interrupt. 310 */ 311 timer = LAPIC_READ(lvt_timer); 312 timer &= ~APIC_LVTT_VECTOR; 313 timer |= XTIMER_OFFSET; 314 timer |= APIC_LVTT_MASKED; 315 LAPIC_WRITE(lvt_timer, timer); 316 317 /* 318 * Set the Task Priority Register as needed. At the moment allow 319 * interrupts on all cpus (the APs will remain CLId until they are 320 * ready to deal). 321 */ 322 temp = LAPIC_READ(tpr); 323 temp &= ~APIC_TPR_PRIO; /* clear priority field */ 324 LAPIC_WRITE(tpr, temp); 325 326 /* 327 * AMD specific setup 328 */ 329 if (cpu_vendor_id == CPU_VENDOR_AMD && lapic_mem != NULL && 330 (LAPIC_MEM_READ(version) & APIC_VER_AMD_EXT_SPACE)) { 331 uint32_t ext_feat; 332 uint32_t count; 333 uint32_t max_count; 334 uint32_t lvt; 335 uint32_t i; 336 337 ext_feat = LAPIC_MEM_READ(ext_feat); 338 count = (ext_feat & APIC_EXTFEAT_MASK) >> APIC_EXTFEAT_SHIFT; 339 max_count = sizeof(lapic_mem->ext_lvt) / 340 sizeof(lapic_mem->ext_lvt[0]); 341 if (count > max_count) 342 count = max_count; 343 for (i = 0; i < count; ++i) { 344 lvt = LAPIC_MEM_READ(ext_lvt[i].lvt); 345 346 lvt &= ~(APIC_LVT_POLARITY_MASK | APIC_LVT_TRIG_MASK | 347 APIC_LVT_DM_MASK | APIC_LVT_MASKED); 348 lvt |= APIC_LVT_MASKED | APIC_LVT_DM_FIXED; 349 350 switch(i) { 351 case APIC_EXTLVT_IBS: 352 break; 353 case APIC_EXTLVT_MCA: 354 break; 355 case APIC_EXTLVT_DEI: 356 break; 357 case APIC_EXTLVT_SBI: 358 break; 359 default: 360 break; 361 } 362 if (bsp) { 363 kprintf(" LAPIC AMD elvt%d: 0x%08x", 364 i, LAPIC_MEM_READ(ext_lvt[i].lvt)); 365 if (LAPIC_MEM_READ(ext_lvt[i].lvt) != lvt) 366 kprintf(" -> 0x%08x", lvt); 367 kprintf("\n"); 368 } 369 LAPIC_MEM_WRITE(ext_lvt[i].lvt, lvt); 370 } 371 } 372 373 /* 374 * Enable the LAPIC 375 */ 376 temp = LAPIC_READ(svr); 377 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */ 378 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */ 379 380 if (LAPIC_READ(version) & APIC_VER_EOI_SUPP) { 381 if (temp & APIC_SVR_EOI_SUPP) { 382 temp &= ~APIC_SVR_EOI_SUPP; 383 if (bsp) 384 kprintf(" LAPIC disabling EOI supp\n"); 385 } 386 } 387 388 /* 389 * Set the spurious interrupt vector. The low 4 bits of the vector 390 * must be 1111. 391 */ 392 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F) 393 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET); 394 temp &= ~APIC_SVR_VECTOR; 395 temp |= XSPURIOUSINT_OFFSET; 396 397 LAPIC_WRITE(svr, temp); 398 399 /* 400 * Pump out a few EOIs to clean out interrupts that got through 401 * before we were able to set the TPR. 402 */ 403 LAPIC_WRITE(eoi, 0); 404 LAPIC_WRITE(eoi, 0); 405 LAPIC_WRITE(eoi, 0); 406 407 if (bsp) { 408 lapic_timer_calibrate(); 409 if (lapic_timer_enable) { 410 if (cpu_thermal_feature & CPUID_THERMAL_ARAT) { 411 /* 412 * Local APIC timer will not stop 413 * in deep C-state. 414 */ 415 lapic_cputimer_intr.caps |= 416 CPUTIMER_INTR_CAP_PS; 417 } 418 if (lapic_use_tscdeadline) { 419 lapic_cputimer_intr.reload = 420 lapic_timer_tscdlt_reload; 421 } 422 cputimer_intr_register(&lapic_cputimer_intr); 423 cputimer_intr_select(&lapic_cputimer_intr, 0); 424 } 425 } else if (!lapic_use_tscdeadline) { 426 lapic_timer_set_divisor(lapic_timer_divisor_idx); 427 } 428 429 if (bootverbose) 430 apic_dump("apic_initialize()"); 431 } 432 433 static void 434 lapic_timer_set_divisor(int divisor_idx) 435 { 436 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS); 437 LAPIC_WRITE(dcr_timer, lapic_timer_divisors[divisor_idx]); 438 } 439 440 static void 441 lapic_timer_oneshot(u_int count) 442 { 443 uint32_t value; 444 445 value = LAPIC_READ(lvt_timer); 446 value &= ~(APIC_LVTT_PERIODIC | APIC_LVTT_TSCDLT); 447 LAPIC_WRITE(lvt_timer, value); 448 LAPIC_WRITE(icr_timer, count); 449 } 450 451 static void 452 lapic_timer_oneshot_quick(u_int count) 453 { 454 LAPIC_WRITE(icr_timer, count); 455 } 456 457 static void 458 lapic_timer_tscdeadline_quick(uint64_t diff) 459 { 460 uint64_t val = rdtsc() + diff; 461 462 wrmsr(MSR_TSC_DEADLINE, val); 463 tsc_deadlines[mycpuid].timestamp = val; 464 } 465 466 static uint64_t 467 lapic_scale_to_tsc(unsigned value, unsigned scale) 468 { 469 uint64_t val; 470 471 val = value; 472 val *= tsc_frequency; 473 val += (scale - 1); 474 val /= scale; 475 return val; 476 } 477 478 #define MAX_MEASURE_RETRIES 100 479 480 static u_int64_t 481 do_tsc_calibration(u_int us, u_int64_t apic_delay_tsc) 482 { 483 u_int64_t old_tsc1, old_tsc2, new_tsc1, new_tsc2; 484 u_int64_t diff, count; 485 u_int64_t a; 486 u_int32_t start, end; 487 int retries1 = 0, retries2 = 0; 488 489 retry1: 490 lapic_timer_oneshot_quick(APIC_TIMER_MAX_COUNT); 491 old_tsc1 = rdtsc_ordered(); 492 start = LAPIC_READ(ccr_timer); 493 old_tsc2 = rdtsc_ordered(); 494 if (apic_delay_tsc > 0 && retries1 < MAX_MEASURE_RETRIES && 495 old_tsc2 - old_tsc1 > 2 * apic_delay_tsc) { 496 retries1++; 497 goto retry1; 498 } 499 DELAY(us); 500 retry2: 501 new_tsc1 = rdtsc_ordered(); 502 end = LAPIC_READ(ccr_timer); 503 new_tsc2 = rdtsc_ordered(); 504 if (apic_delay_tsc > 0 && retries2 < MAX_MEASURE_RETRIES && 505 new_tsc2 - new_tsc1 > 2 * apic_delay_tsc) { 506 retries2++; 507 goto retry2; 508 } 509 if (end == 0) 510 return 0; 511 512 count = start - end; 513 514 /* Make sure the lapic can count for up to 2s */ 515 a = (unsigned)APIC_TIMER_MAX_COUNT; 516 if (us < 2000000 && (u_int64_t)count * 2000000 >= a * us) 517 return 0; 518 519 if (lapic_calibrate_test > 0 && (retries1 > 0 || retries2 > 0)) { 520 kprintf("%s: retries1=%d retries2=%d\n", 521 __func__, retries1, retries2); 522 } 523 524 diff = (new_tsc1 - old_tsc1) + (new_tsc2 - old_tsc2); 525 /* XXX First estimate if the total TSC diff value makes sense */ 526 /* This will almost overflow, but only almost :) */ 527 count = (2 * count * tsc_frequency) / diff; 528 529 return count; 530 } 531 532 static uint64_t 533 do_cputimer_calibration(u_int us) 534 { 535 sysclock_t value; 536 sysclock_t start, end; 537 uint32_t beginning, finish; 538 539 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 540 beginning = LAPIC_READ(ccr_timer); 541 start = sys_cputimer->count(); 542 DELAY(us); 543 end = sys_cputimer->count(); 544 finish = LAPIC_READ(ccr_timer); 545 if (finish == 0) 546 return 0; 547 /* value is the LAPIC timer difference. */ 548 value = (uint32_t)(beginning - finish); 549 /* end is the sys_cputimer difference. */ 550 end -= start; 551 if (end == 0) 552 return 0; 553 value = muldivu64(value, sys_cputimer->freq, end); 554 555 return value; 556 } 557 558 static void 559 lapic_timer_calibrate(void) 560 { 561 sysclock_t value; 562 u_int64_t apic_delay_tsc = 0; 563 int use_tsc_calibration = 0; 564 565 /* No need to calibrate lapic_timer, if we will use TSC Deadline mode */ 566 if (lapic_use_tscdeadline) { 567 lapic_cputimer_intr.freq = tsc_frequency; 568 kprintf( 569 "lapic: TSC Deadline Mode: frequency %lu Hz\n", 570 lapic_cputimer_intr.freq); 571 return; 572 } 573 574 /* 575 * On real hardware, tsc_invariant == 0 wouldn't be an issue, but in 576 * a virtual machine the frequency may get changed by the host. 577 */ 578 if (tsc_frequency != 0 && tsc_invariant && lapic_calibrate_fast) 579 use_tsc_calibration = 1; 580 581 if (use_tsc_calibration) { 582 u_int64_t min_apic_tsc = 0, max_apic_tsc = 0; 583 u_int64_t old_tsc, new_tsc; 584 uint32_t val; 585 int i; 586 587 /* warm up */ 588 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 589 for (i = 0; i < 10; i++) 590 val = LAPIC_READ(ccr_timer); 591 592 for (i = 0; i < 100; i++) { 593 old_tsc = rdtsc_ordered(); 594 val = LAPIC_READ(ccr_timer); 595 new_tsc = rdtsc_ordered(); 596 new_tsc -= old_tsc; 597 apic_delay_tsc += new_tsc; 598 if (min_apic_tsc == 0 || 599 min_apic_tsc > new_tsc) { 600 min_apic_tsc = new_tsc; 601 } 602 if (max_apic_tsc < new_tsc) 603 max_apic_tsc = new_tsc; 604 } 605 apic_delay_tsc /= 100; 606 kprintf( 607 "LAPIC latency (in TSC ticks): %lu min: %lu max: %lu\n", 608 apic_delay_tsc, min_apic_tsc, max_apic_tsc); 609 apic_delay_tsc = min_apic_tsc; 610 } 611 612 if (!use_tsc_calibration) { 613 int i; 614 615 /* 616 * Do some exercising of the lapic timer access. This improves 617 * precision of the subsequent calibration run in at least some 618 * virtualization cases. 619 */ 620 lapic_timer_set_divisor(0); 621 for (i = 0; i < 10; i++) 622 (void)do_cputimer_calibration(100); 623 } 624 /* Try to calibrate the local APIC timer. */ 625 for (lapic_timer_divisor_idx = 0; 626 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS; 627 lapic_timer_divisor_idx++) { 628 lapic_timer_set_divisor(lapic_timer_divisor_idx); 629 if (use_tsc_calibration) { 630 value = do_tsc_calibration(200*1000, apic_delay_tsc); 631 } else { 632 value = do_cputimer_calibration(2*1000*1000); 633 } 634 if (value != 0) 635 break; 636 } 637 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS) 638 panic("lapic: no proper timer divisor?!"); 639 lapic_cputimer_intr.freq = value; 640 641 kprintf("lapic: divisor index %d, frequency %lu Hz\n", 642 lapic_timer_divisor_idx, lapic_cputimer_intr.freq); 643 644 if (lapic_calibrate_test > 0) { 645 uint64_t freq; 646 int i; 647 648 for (i = 1; i <= 20; i++) { 649 if (use_tsc_calibration) { 650 freq = do_tsc_calibration(i*100*1000, 651 apic_delay_tsc); 652 } else { 653 freq = do_cputimer_calibration(i*100*1000); 654 } 655 if (freq != 0) 656 kprintf("%ums: %lu\n", i * 100, freq); 657 } 658 } 659 } 660 661 static void 662 lapic_timer_tscdlt_reload(struct cputimer_intr *cti, sysclock_t reload) 663 { 664 struct globaldata *gd = mycpu; 665 uint64_t diff, now, val; 666 667 /* 668 * Set maximum deadline to 60 seconds 669 */ 670 if (reload > sys_cputimer->freq * 60) 671 reload = sys_cputimer->freq * 60; 672 diff = muldivu64(reload, tsc_frequency, sys_cputimer->freq); 673 if (diff < 4) 674 diff = 4; 675 if (cpu_vendor_id == CPU_VENDOR_INTEL) 676 cpu_lfence(); 677 else 678 cpu_mfence(); 679 now = rdtsc(); 680 val = now + diff; 681 if (gd->gd_timer_running) { 682 uint64_t deadline = tsc_deadlines[mycpuid].timestamp; 683 if (deadline == 0 || now > deadline || val < deadline) { 684 wrmsr(MSR_TSC_DEADLINE, val); 685 tsc_deadlines[mycpuid].timestamp = val; 686 } 687 } else { 688 gd->gd_timer_running = 1; 689 wrmsr(MSR_TSC_DEADLINE, val); 690 tsc_deadlines[mycpuid].timestamp = val; 691 } 692 } 693 694 static void 695 lapic_mem_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload) 696 { 697 struct globaldata *gd = mycpu; 698 699 reload = muldivu64(reload, cti->freq, sys_cputimer->freq); 700 if (reload < 2) 701 reload = 2; 702 if (reload > 0xFFFFFFFF) 703 reload = 0xFFFFFFFF; 704 705 if (gd->gd_timer_running) { 706 if (reload < LAPIC_MEM_READ(ccr_timer)) 707 LAPIC_MEM_WRITE(icr_timer, (uint32_t)reload); 708 } else { 709 gd->gd_timer_running = 1; 710 LAPIC_MEM_WRITE(icr_timer, (uint32_t)reload); 711 } 712 } 713 714 static void 715 lapic_msr_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload) 716 { 717 struct globaldata *gd = mycpu; 718 719 reload = muldivu64(reload, cti->freq, sys_cputimer->freq); 720 if (reload < 2) 721 reload = 2; 722 if (reload > 0xFFFFFFFF) 723 reload = 0xFFFFFFFF; 724 725 if (gd->gd_timer_running) { 726 if (reload < LAPIC_MSR_READ(MSR_X2APIC_CCR_TIMER)) 727 LAPIC_MSR_WRITE(MSR_X2APIC_ICR_TIMER, (uint32_t)reload); 728 } else { 729 gd->gd_timer_running = 1; 730 LAPIC_MSR_WRITE(MSR_X2APIC_ICR_TIMER, (uint32_t)reload); 731 } 732 } 733 734 static void 735 lapic_timer_intr_enable(struct cputimer_intr *cti __unused) 736 { 737 uint32_t timer; 738 739 timer = LAPIC_READ(lvt_timer); 740 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC | APIC_LVTT_TSCDLT); 741 if (lapic_use_tscdeadline) 742 timer |= APIC_LVTT_TSCDLT; 743 LAPIC_WRITE(lvt_timer, timer); 744 if (lapic_use_tscdeadline) 745 cpu_mfence(); 746 747 lapic_timer_fixup_handler(NULL); 748 } 749 750 static void 751 lapic_timer_fixup_handler(void *arg) 752 { 753 int *started = arg; 754 755 if (started != NULL) 756 *started = 0; 757 758 if (cpu_vendor_id == CPU_VENDOR_AMD) { 759 int c1e_test = lapic_timer_c1e_test; 760 761 if (c1e_test < 0) { 762 if (vmm_guest == VMM_GUEST_NONE) { 763 c1e_test = 1; 764 } else { 765 /* 766 * Don't do this C1E testing and adjustment 767 * on virtual machines, the best case for 768 * accessing this MSR is a NOOP; the worst 769 * cases could be pretty nasty, e.g. crash. 770 */ 771 c1e_test = 0; 772 } 773 } 774 775 /* 776 * Detect the presence of C1E capability mostly on latest 777 * dual-cores (or future) k8 family. This feature renders 778 * the local APIC timer dead, so we disable it by reading 779 * the Interrupt Pending Message register and clearing both 780 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 781 * 782 * Reference: 783 * "BIOS and Kernel Developer's Guide for AMD NPT 784 * Family 0Fh Processors" 785 * #32559 revision 3.00 786 */ 787 if ((cpu_id & 0x00000f00) == 0x00000f00 && 788 (cpu_id & 0x0fff0000) >= 0x00040000 && 789 c1e_test) { 790 uint64_t msr; 791 792 msr = rdmsr(0xc0010055); 793 if (msr & 0x18000000) { 794 struct globaldata *gd = mycpu; 795 796 kprintf("cpu%d: AMD C1E detected\n", 797 gd->gd_cpuid); 798 wrmsr(0xc0010055, msr & ~0x18000000ULL); 799 800 /* 801 * We are kinda stalled; 802 * kick start again. 803 */ 804 gd->gd_timer_running = 1; 805 if (lapic_use_tscdeadline) { 806 /* Maybe reached in Virtual Machines? */ 807 lapic_timer_tscdeadline_quick(5000); 808 } else { 809 lapic_timer_oneshot_quick(2); 810 } 811 812 if (started != NULL) 813 *started = 1; 814 } 815 } 816 } 817 } 818 819 static void 820 lapic_timer_restart_handler(void *dummy __unused) 821 { 822 int started; 823 824 lapic_timer_fixup_handler(&started); 825 if (!started) { 826 struct globaldata *gd = mycpu; 827 828 gd->gd_timer_running = 1; 829 if (lapic_use_tscdeadline) { 830 /* Maybe reached in Virtual Machines? */ 831 lapic_timer_tscdeadline_quick(5000); 832 } else { 833 lapic_timer_oneshot_quick(2); 834 } 835 } 836 } 837 838 /* 839 * This function is called only by ACPICA code currently: 840 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI 841 * module controls PM. So once ACPICA is attached, we try 842 * to apply the fixup to prevent LAPIC timer from hanging. 843 */ 844 static void 845 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused) 846 { 847 lwkt_send_ipiq_mask(smp_active_mask, 848 lapic_timer_fixup_handler, NULL); 849 } 850 851 static void 852 lapic_timer_intr_restart(struct cputimer_intr *cti __unused) 853 { 854 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL); 855 } 856 857 858 /* 859 * dump contents of local APIC registers 860 */ 861 void 862 apic_dump(char* str) 863 { 864 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str); 865 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 866 LAPIC_READ(lvt_lint0), LAPIC_READ(lvt_lint1), LAPIC_READ(tpr), 867 LAPIC_READ(svr)); 868 } 869 870 /* 871 * Inter Processor Interrupt functions. 872 */ 873 874 static __inline void 875 lapic_mem_icr_unpend(const char *func) 876 { 877 if (LAPIC_MEM_READ(icr_lo) & APIC_DELSTAT_PEND) { 878 int64_t tsc; 879 int loops = 1; 880 881 tsc = rdtsc(); 882 while (LAPIC_MEM_READ(icr_lo) & APIC_DELSTAT_PEND) { 883 cpu_pause(); 884 if ((tsc_sclock_t)(rdtsc() - 885 (tsc + tsc_frequency)) > 0) { 886 tsc = rdtsc(); 887 if (++loops > 30) { 888 panic("%s: cpu%d apic stalled", 889 func, mycpuid); 890 } else { 891 kprintf("%s: cpu%d apic stalled\n", 892 func, mycpuid); 893 } 894 } 895 } 896 } 897 } 898 899 /* 900 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'. 901 * 902 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF 903 * vector is any valid SYSTEM INT vector 904 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO 905 * 906 * WARNINGS! 907 * 908 * We now implement a per-cpu interlock (gd->gd_npoll) to prevent more than 909 * one IPI from being sent to any given cpu at a time. Thus we no longer 910 * have to process incoming IPIs while waiting for the status to clear. 911 * No deadlock should be possible. 912 * 913 * We now physically disable interrupts for the lapic ICR operation. If 914 * we do not do this then it looks like an EOI sent to the lapic (which 915 * occurs even with a critical section) can interfere with the command 916 * register ready status and cause an IPI to be lost. 917 * 918 * e.g. an interrupt can occur, issue the EOI, IRET, and cause the command 919 * register to busy just before we write to icr_lo, resulting in a lost 920 * issuance. This only appears to occur on Intel cpus and is not 921 * documented. It could simply be that cpus are so fast these days that 922 * it was always an issue, but is only now rearing its ugly head. This 923 * is conjecture. 924 */ 925 static int 926 lapic_mem_ipi(int dest_type, int vector, int delivery_mode) 927 { 928 lapic_mem_icr_unpend(__func__); 929 lapic_mem_icr_set(0, 930 dest_type | APIC_LEVEL_ASSERT | delivery_mode | vector); 931 return 0; 932 } 933 934 static int 935 lapic_msr_ipi(int dest_type, int vector, int delivery_mode) 936 { 937 lapic_msr_icr_set(0, 938 dest_type | APIC_LEVEL_ASSERT | delivery_mode | vector); 939 return 0; 940 } 941 942 /* 943 * Interrupts must be hard-disabled by caller 944 */ 945 static void 946 lapic_mem_single_ipi(int cpu, int vector, int delivery_mode) 947 { 948 lapic_mem_icr_unpend(__func__); 949 lapic_mem_icr_set(CPUID_TO_APICID(cpu), 950 APIC_DEST_DESTFLD | APIC_LEVEL_ASSERT | delivery_mode | vector); 951 } 952 953 static void 954 lapic_msr_single_ipi(int cpu, int vector, int delivery_mode) 955 { 956 lapic_msr_icr_set(CPUID_TO_APICID(cpu), 957 APIC_DEST_DESTFLD | APIC_LEVEL_ASSERT | delivery_mode | vector); 958 } 959 960 /* 961 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'. 962 * 963 * target is a bitmask of destination cpus. Vector is any 964 * valid system INT vector. Delivery mode may be either 965 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO. 966 * 967 * Interrupts must be hard-disabled by caller 968 */ 969 void 970 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode) 971 { 972 while (CPUMASK_TESTNZERO(target)) { 973 int n = BSFCPUMASK(target); 974 CPUMASK_NANDBIT(target, n); 975 single_apic_ipi(n, vector, delivery_mode); 976 } 977 } 978 979 /* 980 * Load a 'downcount time' in uSeconds. 981 */ 982 void 983 set_apic_timer(int us) 984 { 985 u_int count; 986 987 if (lapic_use_tscdeadline) { 988 uint64_t val; 989 990 val = lapic_scale_to_tsc(us, 1000000); 991 val += rdtsc(); 992 /* No need to arm the lapic here, just track the timeout. */ 993 tsc_deadlines[mycpuid].downcount_time = val; 994 return; 995 } 996 997 /* 998 * When we reach here, lapic timer's frequency 999 * must have been calculated as well as the 1000 * divisor (lapic->dcr_timer is setup during the 1001 * divisor calculation). 1002 */ 1003 KKASSERT(lapic_cputimer_intr.freq != 0 && 1004 lapic_timer_divisor_idx >= 0); 1005 1006 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000; 1007 lapic_timer_oneshot(count); 1008 } 1009 1010 1011 /* 1012 * Read remaining time in timer, in microseconds (rounded up). 1013 */ 1014 int 1015 read_apic_timer(void) 1016 { 1017 uint64_t val; 1018 1019 if (lapic_use_tscdeadline) { 1020 uint64_t now; 1021 1022 val = tsc_deadlines[mycpuid].downcount_time; 1023 now = rdtsc(); 1024 if (val == 0 || now > val) { 1025 return 0; 1026 } else { 1027 val -= now; 1028 val *= 1000000; 1029 val += (tsc_frequency - 1); 1030 val /= tsc_frequency; 1031 if (val > INT_MAX) 1032 val = INT_MAX; 1033 return val; 1034 } 1035 } 1036 1037 val = LAPIC_READ(ccr_timer); 1038 if (val == 0) 1039 return 0; 1040 1041 KKASSERT(lapic_cputimer_intr.freq > 0); 1042 val *= 1000000; 1043 val += (lapic_cputimer_intr.freq - 1); 1044 val /= lapic_cputimer_intr.freq; 1045 if (val > INT_MAX) 1046 val = INT_MAX; 1047 return val; 1048 } 1049 1050 1051 /* 1052 * Spin-style delay, set delay time in uS, spin till it drains. 1053 */ 1054 void 1055 u_sleep(int count) 1056 { 1057 set_apic_timer(count); 1058 while (read_apic_timer()) 1059 /* spin */ ; 1060 } 1061 1062 int 1063 lapic_unused_apic_id(int start) 1064 { 1065 int i; 1066 1067 for (i = start; i < APICID_MAX; ++i) { 1068 if (APICID_TO_CPUID(i) == -1) 1069 return i; 1070 } 1071 return NAPICID; 1072 } 1073 1074 void 1075 lapic_map(vm_paddr_t lapic_addr) 1076 { 1077 lapic_mem = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC)); 1078 } 1079 1080 void 1081 lapic_x2apic_enter(boolean_t bsp) 1082 { 1083 uint64_t apic_base; 1084 1085 KASSERT(x2apic_enable, ("X2APIC mode is not enabled")); 1086 1087 /* 1088 * X2APIC mode is requested, if it has not been enabled by the BIOS, 1089 * enable it now. 1090 */ 1091 apic_base = rdmsr(MSR_APICBASE); 1092 if ((apic_base & APICBASE_X2APIC) == 0) { 1093 wrmsr(MSR_APICBASE, 1094 apic_base | APICBASE_X2APIC | APICBASE_ENABLED); 1095 } 1096 if (bsp) { 1097 lapic_eoi = lapic_msr_eoi; 1098 apic_ipi = lapic_msr_ipi; 1099 single_apic_ipi = lapic_msr_single_ipi; 1100 lapic_cputimer_intr.reload = lapic_msr_timer_intr_reload; 1101 } 1102 } 1103 1104 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators = 1105 TAILQ_HEAD_INITIALIZER(lapic_enumerators); 1106 1107 int 1108 lapic_config(void) 1109 { 1110 struct lapic_enumerator *e; 1111 uint64_t apic_base; 1112 int error, i, ap_max; 1113 1114 KKASSERT(lapic_enable); 1115 1116 lapic_eoi = lapic_mem_eoi; 1117 apic_ipi = lapic_mem_ipi; 1118 single_apic_ipi = lapic_mem_single_ipi; 1119 1120 TUNABLE_INT_FETCH("hw.x2apic_enable", &x2apic_enable); 1121 if (x2apic_enable < 0) 1122 x2apic_enable = 1; 1123 1124 if ((cpu_feature2 & CPUID2_X2APIC) == 0) { 1125 /* X2APIC is not supported. */ 1126 x2apic_enable = 0; 1127 } else if (!x2apic_enable) { 1128 /* 1129 * If the BIOS enabled the X2APIC mode, then we would stick 1130 * with the X2APIC mode. 1131 */ 1132 apic_base = rdmsr(MSR_APICBASE); 1133 if (apic_base & APICBASE_X2APIC) { 1134 kprintf("LAPIC: BIOS enabled X2APIC mode\n"); 1135 x2apic_enable = 1; 1136 } 1137 } 1138 1139 if (x2apic_enable) { 1140 /* 1141 * Enter X2APIC mode. 1142 */ 1143 kprintf("LAPIC: enter X2APIC mode\n"); 1144 lapic_x2apic_enter(TRUE); 1145 } 1146 1147 for (i = 0; i < NAPICID; ++i) 1148 APICID_TO_CPUID(i) = -1; 1149 1150 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) { 1151 error = e->lapic_probe(e); 1152 if (!error) 1153 break; 1154 } 1155 if (e == NULL) { 1156 kprintf("LAPIC: Can't find LAPIC\n"); 1157 return ENXIO; 1158 } 1159 1160 error = e->lapic_enumerate(e); 1161 if (error) { 1162 kprintf("LAPIC: enumeration failed\n"); 1163 return ENXIO; 1164 } 1165 1166 /* LAPIC is usable now. */ 1167 lapic_usable = 1; 1168 1169 ap_max = MAXCPU - 1; 1170 TUNABLE_INT_FETCH("hw.ap_max", &ap_max); 1171 if (ap_max > MAXCPU - 1) 1172 ap_max = MAXCPU - 1; 1173 1174 if (naps > ap_max) { 1175 kprintf("LAPIC: Warning use only %d out of %d " 1176 "available APs\n", 1177 ap_max, naps); 1178 naps = ap_max; 1179 } 1180 1181 return 0; 1182 } 1183 1184 void 1185 lapic_enumerator_register(struct lapic_enumerator *ne) 1186 { 1187 struct lapic_enumerator *e; 1188 1189 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) { 1190 if (e->lapic_prio < ne->lapic_prio) { 1191 TAILQ_INSERT_BEFORE(e, ne, lapic_link); 1192 return; 1193 } 1194 } 1195 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link); 1196 } 1197 1198 void 1199 lapic_set_cpuid(int cpu_id, int apic_id) 1200 { 1201 CPUID_TO_APICID(cpu_id) = apic_id; 1202 APICID_TO_CPUID(apic_id) = cpu_id; 1203 } 1204 1205 void 1206 lapic_fixup_noioapic(void) 1207 { 1208 u_int temp; 1209 1210 /* Only allowed on BSP */ 1211 KKASSERT(mycpuid == 0); 1212 KKASSERT(!ioapic_enable); 1213 1214 temp = LAPIC_READ(lvt_lint0); 1215 temp &= ~APIC_LVT_MASKED; 1216 LAPIC_WRITE(lvt_lint0, temp); 1217 1218 temp = LAPIC_READ(lvt_lint1); 1219 temp |= APIC_LVT_MASKED; 1220 LAPIC_WRITE(lvt_lint1, temp); 1221 } 1222 1223 static void 1224 lapic_mem_eoi(void) 1225 { 1226 log_lapic(mem_eoi); 1227 LAPIC_MEM_WRITE(eoi, 0); 1228 } 1229 1230 static void 1231 lapic_msr_eoi(void) 1232 { 1233 log_lapic(msr_eoi); 1234 LAPIC_MSR_WRITE(MSR_X2APIC_EOI, 0); 1235 } 1236 1237 static void 1238 lapic_mem_seticr_sync(uint32_t apic_id, uint32_t icr_lo_val) 1239 { 1240 lapic_mem_icr_set(apic_id, icr_lo_val); 1241 while (LAPIC_MEM_READ(icr_lo) & APIC_DELSTAT_PEND) 1242 /* spin */; 1243 } 1244 1245 void 1246 lapic_seticr_sync(uint32_t apic_id, uint32_t icr_lo_val) 1247 { 1248 if (x2apic_enable) 1249 lapic_msr_icr_set(apic_id, icr_lo_val); 1250 else 1251 lapic_mem_seticr_sync(apic_id, icr_lo_val); 1252 } 1253 1254 static void 1255 lapic_sysinit(void *dummy __unused) 1256 { 1257 if (lapic_enable) { 1258 int error; 1259 1260 error = lapic_config(); 1261 if (error) 1262 lapic_enable = 0; 1263 } 1264 if (!lapic_enable) 1265 x2apic_enable = 0; 1266 1267 if (lapic_enable) { 1268 /* Initialize BSP's local APIC */ 1269 lapic_init(TRUE); 1270 } else if (ioapic_enable) { 1271 ioapic_enable = 0; 1272 icu_reinit_noioapic(); 1273 } 1274 } 1275 SYSINIT(lapic, SI_BOOT2_LAPIC, SI_ORDER_FIRST, lapic_sysinit, NULL); 1276