1 /* 2 * Copyright (c) 1991 The Regents of the University of California. 3 * Copyright (c) 2005,2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Matthew Dillon <dillon@backplane.com> 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in 20 * the documentation and/or other materials provided with the 21 * distribution. 22 * 3. Neither the name of The DragonFly Project nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific, prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * $DragonFly: src/sys/platform/pc64/icu/icu_abi.c,v 1.1 2008/08/29 17:07:16 dillon Exp $ 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/machintr.h> 46 #include <sys/interrupt.h> 47 #include <sys/bus.h> 48 49 #include <machine/segments.h> 50 #include <machine/md_var.h> 51 #include <machine/intr_machdep.h> 52 #include <machine/globaldata.h> 53 #include <machine/smp.h> 54 55 #include <sys/thread2.h> 56 57 #include <machine_base/icu/elcr_var.h> 58 59 #include <machine_base/icu/icu.h> 60 #include <machine_base/icu/icu_ipl.h> 61 62 extern inthand_t 63 IDTVEC(icu_intr0), IDTVEC(icu_intr1), 64 IDTVEC(icu_intr2), IDTVEC(icu_intr3), 65 IDTVEC(icu_intr4), IDTVEC(icu_intr5), 66 IDTVEC(icu_intr6), IDTVEC(icu_intr7), 67 IDTVEC(icu_intr8), IDTVEC(icu_intr9), 68 IDTVEC(icu_intr10), IDTVEC(icu_intr11), 69 IDTVEC(icu_intr12), IDTVEC(icu_intr13), 70 IDTVEC(icu_intr14), IDTVEC(icu_intr15); 71 72 static inthand_t *icu_intr[ICU_HWI_VECTORS] = { 73 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1), 74 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3), 75 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5), 76 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7), 77 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9), 78 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11), 79 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13), 80 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15) 81 }; 82 83 static struct icu_irqmap { 84 int im_type; /* ICU_IMT_ */ 85 enum intr_trigger im_trig; 86 } icu_irqmaps[MAX_HARDINTS]; /* XXX MAX_HARDINTS may not be correct */ 87 88 #define ICU_IMT_UNUSED 0 /* KEEP THIS */ 89 #define ICU_IMT_RESERVED 1 90 #define ICU_IMT_LINE 2 91 #define ICU_IMT_SYSCALL 3 92 93 extern void ICU_INTREN(int); 94 extern void ICU_INTRDIS(int); 95 96 static int icu_vectorctl(int, int, int); 97 static int icu_setvar(int, const void *); 98 static int icu_getvar(int, void *); 99 static void icu_finalize(void); 100 static void icu_cleanup(void); 101 static void icu_setdefault(void); 102 static void icu_stabilize(void); 103 static void icu_initmap(void); 104 static void icu_intr_config(int, enum intr_trigger, enum intr_polarity); 105 106 struct machintr_abi MachIntrABI_ICU = { 107 MACHINTR_ICU, 108 .intrdis = ICU_INTRDIS, 109 .intren = ICU_INTREN, 110 .vectorctl = icu_vectorctl, 111 .setvar = icu_setvar, 112 .getvar = icu_getvar, 113 .finalize = icu_finalize, 114 .cleanup = icu_cleanup, 115 .setdefault = icu_setdefault, 116 .stabilize = icu_stabilize, 117 .initmap = icu_initmap, 118 .intr_config = icu_intr_config 119 }; 120 121 /* 122 * WARNING! SMP builds can use the ICU now so this code must be MP safe. 123 */ 124 static int 125 icu_setvar(int varid, const void *buf) 126 { 127 return ENOENT; 128 } 129 130 static int 131 icu_getvar(int varid, void *buf) 132 { 133 return ENOENT; 134 } 135 136 /* 137 * Called before interrupts are physically enabled 138 */ 139 static void 140 icu_stabilize(void) 141 { 142 int intr; 143 144 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) 145 machintr_intrdis(intr); 146 machintr_intren(ICU_IRQ_SLAVE); 147 } 148 149 /* 150 * Called after interrupts physically enabled but before the 151 * critical section is released. 152 */ 153 static void 154 icu_cleanup(void) 155 { 156 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending)); 157 } 158 159 /* 160 * Called after stablize and cleanup; critical section is not 161 * held and interrupts are not physically disabled. 162 */ 163 static void 164 icu_finalize(void) 165 { 166 KKASSERT(MachIntrABI.type == MACHINTR_ICU); 167 168 #ifdef SMP 169 KKASSERT(!apic_io_enable); 170 171 /* 172 * If an IMCR is present, programming bit 0 disconnects the 8259 173 * from the BSP. The 8259 may still be connected to LINT0 on the 174 * BSP's LAPIC. 175 * 176 * If we are running SMP the LAPIC is active, try to use virtual 177 * wire mode so we can use other interrupt sources within the LAPIC 178 * in addition to the 8259. 179 */ 180 if (imcr_present) { 181 outb(0x22, 0x70); 182 outb(0x23, 0x01); 183 } 184 #endif /* SMP */ 185 } 186 187 static int 188 icu_vectorctl(int op, int intr, int flags) 189 { 190 int error; 191 register_t ef; 192 193 if (intr < 0 || intr >= ICU_HWI_VECTORS || intr == ICU_IRQ_SLAVE) 194 return EINVAL; 195 196 ef = read_rflags(); 197 cpu_disable_intr(); 198 error = 0; 199 200 switch(op) { 201 case MACHINTR_VECTOR_SETUP: 202 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYSIGT, 203 SEL_KPL, 0); 204 machintr_intren(intr); 205 break; 206 207 case MACHINTR_VECTOR_TEARDOWN: 208 machintr_intrdis(intr); 209 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYSIGT, 210 SEL_KPL, 0); 211 break; 212 213 default: 214 error = EOPNOTSUPP; 215 break; 216 } 217 write_rflags(ef); 218 return error; 219 } 220 221 static void 222 icu_setdefault(void) 223 { 224 int intr; 225 226 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) { 227 if (intr == ICU_IRQ_SLAVE) 228 continue; 229 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYSIGT, 230 SEL_KPL, 0); 231 } 232 } 233 234 static void 235 icu_initmap(void) 236 { 237 int i; 238 239 for (i = 0; i < ICU_HWI_VECTORS; ++i) 240 icu_irqmaps[i].im_type = ICU_IMT_LINE; 241 icu_irqmaps[ICU_IRQ_SLAVE].im_type = ICU_IMT_RESERVED; 242 243 if (elcr_found) { 244 for (i = 0; i < ICU_HWI_VECTORS; ++i) 245 icu_irqmaps[i].im_trig = elcr_read_trigger(i); 246 } else { 247 /* 248 * NOTE: Trigger mode does not matter at all 249 */ 250 for (i = 0; i < ICU_HWI_VECTORS; ++i) 251 icu_irqmaps[i].im_trig = INTR_TRIGGER_EDGE; 252 } 253 icu_irqmaps[IDT_OFFSET_SYSCALL - IDT_OFFSET].im_type = ICU_IMT_SYSCALL; 254 } 255 256 static void 257 icu_intr_config(int irq, enum intr_trigger trig, 258 enum intr_polarity pola __unused) 259 { 260 struct icu_irqmap *map; 261 262 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL); 263 264 KKASSERT(irq >= 0 && irq < MAX_HARDINTS); 265 map = &icu_irqmaps[irq]; 266 267 KKASSERT(map->im_type == ICU_IMT_LINE); 268 269 /* TODO: Check whether it is configured or not */ 270 271 if (trig == map->im_trig) 272 return; 273 274 if (bootverbose) { 275 kprintf("ICU: irq %d, %s -> %s\n", irq, 276 intr_str_trigger(map->im_trig), 277 intr_str_trigger(trig)); 278 } 279 map->im_trig = trig; 280 281 if (!elcr_found) { 282 if (bootverbose) 283 kprintf("ICU: no ELCR, skip irq %d config\n", irq); 284 return; 285 } 286 elcr_write_trigger(irq, map->im_trig); 287 } 288