1/* 2 * Copyright (c) 2008 The DragonFly Project. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in 12 * the documentation and/or other materials provided with the 13 * distribution. 14 * 3. Neither the name of The DragonFly Project nor the names of its 15 * contributors may be used to endorse or promote products derived 16 * from this software without specific, prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 21 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 22 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * from: vector.s, 386BSD 0.1 unknown origin 32 * $FreeBSD: src/sys/i386/isa/icu_vector.s,v 1.14.2.2 2000/07/18 21:12:42 dfr Exp $ 33 * $DragonFly: src/sys/platform/pc64/icu/icu_vector.s,v 1.1 2008/08/29 17:07:16 dillon Exp $ 34 */ 35/* 36 * WARNING! SMP builds can use the ICU now so this code must be MP safe. 37 */ 38 39#include "opt_auto_eoi.h" 40 41#include <machine/asmacros.h> 42#include <machine/lock.h> 43#include <machine/psl.h> 44#include <machine/trap.h> 45 46#include <machine_base/icu/icu.h> 47#include <bus/isa/i386/isa.h> 48 49#include "assym.s" 50#include "icu_ipl.h" 51 52#ifndef APIC_IO 53 54#define ICU_IMR_OFFSET 1 /* IO_ICU{1,2} + 1 */ 55 56#define ICU_EOI 0x20 /* XXX - define elsewhere */ 57 58#define IRQ_LBIT(irq_num) (1 << (irq_num)) 59#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8)) 60#define IRQ_BYTE(irq_num) ((irq_num) >> 3) 61 62#ifdef AUTO_EOI_1 63#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */ 64#define OUTB_ICU1 65#else 66#define ENABLE_ICU1 \ 67 movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \ 68 OUTB_ICU1 ; /* ... to clear in service bit */ \ 69 70#define OUTB_ICU1 \ 71 outb %al,$IO_ICU1 ; \ 72 73#endif 74 75#ifdef AUTO_EOI_2 76/* 77 * The data sheet says no auto-EOI on slave, but it sometimes works. 78 */ 79#define ENABLE_ICU1_AND_2 ENABLE_ICU1 80#else 81#define ENABLE_ICU1_AND_2 \ 82 movb $ICU_EOI,%al ; /* as above */ \ 83 outb %al,$IO_ICU2 ; /* but do second icu first ... */ \ 84 OUTB_ICU1 ; /* ... then first icu (if !AUTO_EOI_1) */ \ 85 86#endif 87 88/* 89 * Macro helpers 90 */ 91#define ICU_PUSH_FRAME \ 92 PUSH_FRAME ; /* 15 regs + space for 5 extras */ \ 93 movl $0,TF_XFLAGS(%rsp) ; \ 94 movl $0,TF_TRAPNO(%rsp) ; \ 95 movl $0,TF_ADDR(%rsp) ; \ 96 movl $0,TF_FLAGS(%rsp) ; \ 97 movl $0,TF_ERR(%rsp) ; \ 98 cld ; \ 99 100#define MASK_IRQ(icu, irq_num) \ 101 ICU_IMASK_LOCK ; \ 102 movb icu_imen + IRQ_BYTE(irq_num),%al ; \ 103 orb $IRQ_BIT(irq_num),%al ; \ 104 movb %al,icu_imen + IRQ_BYTE(irq_num) ; \ 105 outb %al,$icu+ICU_IMR_OFFSET ; \ 106 ICU_IMASK_UNLOCK ; \ 107 108#define UNMASK_IRQ(icu, irq_num) \ 109 cmpl $0,%eax ; \ 110 jnz 8f ; \ 111 ICU_IMASK_LOCK ; \ 112 movb icu_imen + IRQ_BYTE(irq_num),%al ; \ 113 andb $~IRQ_BIT(irq_num),%al ; \ 114 movb %al,icu_imen + IRQ_BYTE(irq_num) ; \ 115 outb %al,$icu+ICU_IMR_OFFSET ; \ 116 ICU_IMASK_UNLOCK ; \ 1178: ; \ 118 119/* 120 * Fast interrupt call handlers run in the following sequence: 121 * 122 * - Push the trap frame required by doreti. 123 * - Mask the interrupt and reenable its source. 124 * - If we cannot take the interrupt set its fpending bit and 125 * doreti. 126 * - If we can take the interrupt clear its fpending bit, 127 * call the handler, then unmask the interrupt and doreti. 128 * 129 * YYY can cache gd base pointer instead of using hidden %fs 130 * prefixes. 131 */ 132 133#define FAST_INTR(irq_num, vec_name, icu, enable_icus) \ 134 .text ; \ 135 SUPERALIGN_TEXT ; \ 136IDTVEC(vec_name) ; \ 137 ICU_PUSH_FRAME ; \ 138 FAKE_MCOUNT(15*4(%esp)) ; \ 139 MASK_IRQ(icu, irq_num) ; \ 140 enable_icus ; \ 141 movq PCPU(curthread),%rbx ; \ 142 testl $-1,TD_NEST_COUNT(%rbx) ; \ 143 jne 1f ; \ 144 cmpl $TDPRI_CRIT,TD_PRI(%rbx) ; \ 145 jl 2f ; \ 1461: ; \ 147 /* set pending bit and return, leave interrupt masked */ \ 148 orl $IRQ_LBIT(irq_num),PCPU(fpending) ; \ 149 orl $RQF_INTPEND, PCPU(reqflags) ; \ 150 jmp 5f ; \ 1512: ; \ 152 /* clear pending bit, run handler */ \ 153 andl $~IRQ_LBIT(irq_num),PCPU(fpending) ; \ 154 pushq $irq_num ; \ 155 movq %rsp,%rdi ; /* rdi = call argument */ \ 156 call ithread_fast_handler ; /* returns 0 to unmask int */ \ 157 addq $8,%rsp ; /* intr frame -> trap frame */ \ 158 UNMASK_IRQ(icu, irq_num) ; \ 1595: ; \ 160 MEXITCOUNT ; \ 161 jmp doreti ; \ 162 163/* 164 * Slow interrupt call handlers run in the following sequence: 165 * 166 * - Push the trap frame required by doreti. 167 * - Mask the interrupt and reenable its source. 168 * - If we cannot take the interrupt set its ipending bit and 169 * doreti. In addition to checking for a critical section 170 * and cpl mask we also check to see if the thread is still 171 * running. 172 * - If we can take the interrupt clear its ipending bit 173 * and schedule its thread. Leave interrupts masked and doreti. 174 * 175 * sched_ithd() is called with interrupts enabled and outside of a 176 * critical section (so it can preempt us). 177 * 178 * YYY sched_ithd may preempt us synchronously (fix interrupt stacking) 179 * 180 * Note that intr_nesting_level is not bumped during sched_ithd because 181 * blocking allocations are allowed in the preemption case. 182 * 183 * YYY can cache gd base pointer instead of using hidden %fs 184 * prefixes. 185 */ 186 187#define SLOW_INTR(irq_num, vec_name, icu, enable_icus) \ 188 .text ; \ 189 SUPERALIGN_TEXT ; \ 190IDTVEC(vec_name) ; \ 191 ICU_PUSH_FRAME ; \ 192 FAKE_MCOUNT(15*4(%esp)) ; \ 193 MASK_IRQ(icu, irq_num) ; \ 194 incl PCPU(cnt) + V_INTR ; \ 195 enable_icus ; \ 196 movq PCPU(curthread),%rbx ; \ 197 testl $-1,TD_NEST_COUNT(%rbx) ; \ 198 jne 1f ; \ 199 cmpl $TDPRI_CRIT,TD_PRI(%rbx) ; \ 200 jl 2f ; \ 2011: ; \ 202 /* set the pending bit and return, leave interrupt masked */ \ 203 orl $IRQ_LBIT(irq_num), PCPU(ipending) ; \ 204 orl $RQF_INTPEND, PCPU(reqflags) ; \ 205 jmp 5f ; \ 2062: ; \ 207 /* set running bit, clear pending bit, run handler */ \ 208 andl $~IRQ_LBIT(irq_num), PCPU(ipending) ; \ 209 incl TD_NEST_COUNT(%rbx) ; \ 210 sti ; \ 211 movq $irq_num,%rdi ; /* %rdi = argument to call */ \ 212 call sched_ithd ; \ 213 cli ; \ 214 decl TD_NEST_COUNT(%rbx) ; \ 2155: ; \ 216 MEXITCOUNT ; \ 217 jmp doreti ; \ 218 219/* 220 * Unmask a slow interrupt. This function is used by interrupt threads 221 * after they have descheduled themselves to reenable interrupts and 222 * possibly cause a reschedule to occur. 223 */ 224 225#define INTR_UNMASK(irq_num, vec_name, icu) \ 226 .text ; \ 227 SUPERALIGN_TEXT ; \ 228IDTVEC(vec_name) ; \ 229 pushq %rbp ; /* frame for ddb backtrace */ \ 230 movq %rsp, %rbp ; \ 231 subq %rax, %rax ; \ 232 UNMASK_IRQ(icu, irq_num) ; \ 233 popq %rbp ; \ 234 ret ; \ 235 236MCOUNT_LABEL(bintr) 237 FAST_INTR(0,icu_fastintr0, IO_ICU1, ENABLE_ICU1) 238 FAST_INTR(1,icu_fastintr1, IO_ICU1, ENABLE_ICU1) 239 FAST_INTR(2,icu_fastintr2, IO_ICU1, ENABLE_ICU1) 240 FAST_INTR(3,icu_fastintr3, IO_ICU1, ENABLE_ICU1) 241 FAST_INTR(4,icu_fastintr4, IO_ICU1, ENABLE_ICU1) 242 FAST_INTR(5,icu_fastintr5, IO_ICU1, ENABLE_ICU1) 243 FAST_INTR(6,icu_fastintr6, IO_ICU1, ENABLE_ICU1) 244 FAST_INTR(7,icu_fastintr7, IO_ICU1, ENABLE_ICU1) 245 FAST_INTR(8,icu_fastintr8, IO_ICU2, ENABLE_ICU1_AND_2) 246 FAST_INTR(9,icu_fastintr9, IO_ICU2, ENABLE_ICU1_AND_2) 247 FAST_INTR(10,icu_fastintr10, IO_ICU2, ENABLE_ICU1_AND_2) 248 FAST_INTR(11,icu_fastintr11, IO_ICU2, ENABLE_ICU1_AND_2) 249 FAST_INTR(12,icu_fastintr12, IO_ICU2, ENABLE_ICU1_AND_2) 250 FAST_INTR(13,icu_fastintr13, IO_ICU2, ENABLE_ICU1_AND_2) 251 FAST_INTR(14,icu_fastintr14, IO_ICU2, ENABLE_ICU1_AND_2) 252 FAST_INTR(15,icu_fastintr15, IO_ICU2, ENABLE_ICU1_AND_2) 253 254 SLOW_INTR(0,icu_slowintr0, IO_ICU1, ENABLE_ICU1) 255 SLOW_INTR(1,icu_slowintr1, IO_ICU1, ENABLE_ICU1) 256 SLOW_INTR(2,icu_slowintr2, IO_ICU1, ENABLE_ICU1) 257 SLOW_INTR(3,icu_slowintr3, IO_ICU1, ENABLE_ICU1) 258 SLOW_INTR(4,icu_slowintr4, IO_ICU1, ENABLE_ICU1) 259 SLOW_INTR(5,icu_slowintr5, IO_ICU1, ENABLE_ICU1) 260 SLOW_INTR(6,icu_slowintr6, IO_ICU1, ENABLE_ICU1) 261 SLOW_INTR(7,icu_slowintr7, IO_ICU1, ENABLE_ICU1) 262 SLOW_INTR(8,icu_slowintr8, IO_ICU2, ENABLE_ICU1_AND_2) 263 SLOW_INTR(9,icu_slowintr9, IO_ICU2, ENABLE_ICU1_AND_2) 264 SLOW_INTR(10,icu_slowintr10, IO_ICU2, ENABLE_ICU1_AND_2) 265 SLOW_INTR(11,icu_slowintr11, IO_ICU2, ENABLE_ICU1_AND_2) 266 SLOW_INTR(12,icu_slowintr12, IO_ICU2, ENABLE_ICU1_AND_2) 267 SLOW_INTR(13,icu_slowintr13, IO_ICU2, ENABLE_ICU1_AND_2) 268 SLOW_INTR(14,icu_slowintr14, IO_ICU2, ENABLE_ICU1_AND_2) 269 SLOW_INTR(15,icu_slowintr15, IO_ICU2, ENABLE_ICU1_AND_2) 270 271MCOUNT_LABEL(eintr) 272 273 .data 274 275 .text 276 277#endif 278