xref: /dragonfly/sys/platform/pc64/icu/icu_vector.s (revision 73e0051e)
1/*
2 * Copyright (c) 2008 The DragonFly Project.  All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in
12 *    the documentation and/or other materials provided with the
13 *    distribution.
14 * 3. Neither the name of The DragonFly Project nor the names of its
15 *    contributors may be used to endorse or promote products derived
16 *    from this software without specific, prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
22 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * from: vector.s, 386BSD 0.1 unknown origin
32 * $FreeBSD: src/sys/i386/isa/icu_vector.s,v 1.14.2.2 2000/07/18 21:12:42 dfr Exp $
33 * $DragonFly: src/sys/platform/pc64/icu/icu_vector.s,v 1.1 2008/08/29 17:07:16 dillon Exp $
34 */
35/*
36 * WARNING!  SMP builds can use the ICU now so this code must be MP safe.
37 */
38
39#include "opt_auto_eoi.h"
40
41#include <machine/asmacros.h>
42#include <machine/lock.h>
43#include <machine/psl.h>
44#include <machine/trap.h>
45#include <machine/segments.h>
46
47#include <machine_base/icu/icu.h>
48#include <bus/isa/i386/isa.h>
49
50#include "assym.s"
51#include "icu_ipl.h"
52
53#ifndef APIC_IO
54
55#define ICU_IMR_OFFSET		1	/* IO_ICU{1,2} + 1 */
56
57#define	ICU_EOI			0x20	/* XXX - define elsewhere */
58
59#define	IRQ_LBIT(irq_num)	(1 << (irq_num))
60#define	IRQ_BIT(irq_num)	(1 << ((irq_num) % 8))
61#define	IRQ_BYTE(irq_num)	((irq_num) >> 3)
62
63#ifdef AUTO_EOI_1
64#define	ENABLE_ICU1		/* use auto-EOI to reduce i/o */
65#define	OUTB_ICU1
66#else
67#define	ENABLE_ICU1 							\
68	movb	$ICU_EOI,%al ;	/* as soon as possible send EOI ... */ 	\
69	OUTB_ICU1 ;		/* ... to clear in service bit */	\
70
71#define	OUTB_ICU1 							\
72	outb	%al,$IO_ICU1 ;						\
73
74#endif
75
76#ifdef AUTO_EOI_2
77/*
78 * The data sheet says no auto-EOI on slave, but it sometimes works.
79 */
80#define	ENABLE_ICU1_AND_2	ENABLE_ICU1
81#else
82#define	ENABLE_ICU1_AND_2 						\
83	movb	$ICU_EOI,%al ;	/* as above */ 				\
84	outb	%al,$IO_ICU2 ;	/* but do second icu first ... */ 	\
85	OUTB_ICU1 ;	/* ... then first icu (if !AUTO_EOI_1) */	\
86
87#endif
88
89/*
90 * Macro helpers
91 */
92#define ICU_PUSH_FRAME							\
93	PUSH_FRAME ;		/* 15 regs + space for 5 extras */	\
94	movl $0,TF_XFLAGS(%rsp) ;					\
95	movl $0,TF_TRAPNO(%rsp) ;					\
96	movl $0,TF_ADDR(%rsp) ;						\
97	movl $0,TF_FLAGS(%rsp) ;					\
98	movl $0,TF_ERR(%rsp) ;						\
99	cld ;								\
100
101#define MASK_IRQ(icu, irq_num)						\
102	ICU_IMASK_LOCK ;						\
103	movb	icu_imen + IRQ_BYTE(irq_num),%al ;			\
104	orb	$IRQ_BIT(irq_num),%al ;					\
105	movb	%al,icu_imen + IRQ_BYTE(irq_num) ;			\
106	outb	%al,$icu+ICU_IMR_OFFSET ;				\
107	ICU_IMASK_UNLOCK ;						\
108
109#define UNMASK_IRQ(icu, irq_num)					\
110	cmpl	$0,%eax ;						\
111	jnz	8f ;							\
112	ICU_IMASK_LOCK ;						\
113	movb	icu_imen + IRQ_BYTE(irq_num),%al ;			\
114	andb	$~IRQ_BIT(irq_num),%al ;				\
115	movb	%al,icu_imen + IRQ_BYTE(irq_num) ;			\
116	outb	%al,$icu+ICU_IMR_OFFSET ;				\
117	ICU_IMASK_UNLOCK ;						\
1188: ;									\
119
120/*
121 * Fast interrupt call handlers run in the following sequence:
122 *
123 *	- Push the trap frame required by doreti.
124 *	- Mask the interrupt and reenable its source.
125 *	- If we cannot take the interrupt set its fpending bit and
126 *	  doreti.
127 *	- If we can take the interrupt clear its fpending bit,
128 *	  call the handler, then unmask the interrupt and doreti.
129 *
130 *	YYY can cache gd base pointer instead of using hidden %fs
131 *	prefixes.
132 */
133
134#define	FAST_INTR(irq_num, vec_name, icu, enable_icus)			\
135	.text ; 							\
136	SUPERALIGN_TEXT ; 						\
137IDTVEC(vec_name) ; 							\
138	ICU_PUSH_FRAME ;						\
139	FAKE_MCOUNT(15*4(%esp)) ; 					\
140	MASK_IRQ(icu, irq_num) ;					\
141	enable_icus ;							\
142	movq	PCPU(curthread),%rbx ;					\
143	testl	$-1,TD_NEST_COUNT(%rbx) ;				\
144	jne	1f ;							\
145	cmpl	$TDPRI_CRIT,TD_PRI(%rbx) ;				\
146	jl	2f ;							\
1471: ;									\
148	/* set pending bit and return, leave interrupt masked */	\
149	orl	$IRQ_LBIT(irq_num),PCPU(fpending) ;			\
150	orl	$RQF_INTPEND, PCPU(reqflags) ;				\
151	jmp	5f ;							\
1522: ;									\
153	/* clear pending bit, run handler */				\
154	andl	$~IRQ_LBIT(irq_num),PCPU(fpending) ;			\
155	pushq	$irq_num ;						\
156	movq	%rsp,%rdi ;		/* rdi = call argument */	\
157	addl	$TDPRI_CRIT,TD_PRI(%rbx) ;				\
158	call	ithread_fast_handler ;	/* returns 0 to unmask int */	\
159	subl	$TDPRI_CRIT,TD_PRI(%rbx) ;				\
160	addq	$8,%rsp ;		/* intr frame -> trap frame */	\
161	UNMASK_IRQ(icu, irq_num) ;					\
1625: ;									\
163	MEXITCOUNT ;							\
164	jmp	doreti ;						\
165
166/*
167 * Unmask a slow interrupt.  This function is used by interrupt threads
168 * after they have descheduled themselves to reenable interrupts and
169 * possibly cause a reschedule to occur.
170 */
171
172#define INTR_UNMASK(irq_num, vec_name, icu)				\
173	.text ;								\
174	SUPERALIGN_TEXT ;						\
175IDTVEC(vec_name) ;							\
176	pushq	%rbp ;	 /* frame for ddb backtrace */			\
177	movq	%rsp, %rbp ;						\
178	subq	%rax, %rax ;						\
179	UNMASK_IRQ(icu, irq_num) ;					\
180	popq	%rbp ;							\
181	ret ;								\
182
183MCOUNT_LABEL(bintr)
184	FAST_INTR(0,icu_fastintr0, IO_ICU1, ENABLE_ICU1)
185	FAST_INTR(1,icu_fastintr1, IO_ICU1, ENABLE_ICU1)
186	FAST_INTR(2,icu_fastintr2, IO_ICU1, ENABLE_ICU1)
187	FAST_INTR(3,icu_fastintr3, IO_ICU1, ENABLE_ICU1)
188	FAST_INTR(4,icu_fastintr4, IO_ICU1, ENABLE_ICU1)
189	FAST_INTR(5,icu_fastintr5, IO_ICU1, ENABLE_ICU1)
190	FAST_INTR(6,icu_fastintr6, IO_ICU1, ENABLE_ICU1)
191	FAST_INTR(7,icu_fastintr7, IO_ICU1, ENABLE_ICU1)
192	FAST_INTR(8,icu_fastintr8, IO_ICU2, ENABLE_ICU1_AND_2)
193	FAST_INTR(9,icu_fastintr9, IO_ICU2, ENABLE_ICU1_AND_2)
194	FAST_INTR(10,icu_fastintr10, IO_ICU2, ENABLE_ICU1_AND_2)
195	FAST_INTR(11,icu_fastintr11, IO_ICU2, ENABLE_ICU1_AND_2)
196	FAST_INTR(12,icu_fastintr12, IO_ICU2, ENABLE_ICU1_AND_2)
197	FAST_INTR(13,icu_fastintr13, IO_ICU2, ENABLE_ICU1_AND_2)
198	FAST_INTR(14,icu_fastintr14, IO_ICU2, ENABLE_ICU1_AND_2)
199	FAST_INTR(15,icu_fastintr15, IO_ICU2, ENABLE_ICU1_AND_2)
200MCOUNT_LABEL(eintr)
201
202	.data
203
204	.text
205
206#endif
207