1/* 2 * Copyright (c) 2008 The DragonFly Project. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in 12 * the documentation and/or other materials provided with the 13 * distribution. 14 * 3. Neither the name of The DragonFly Project nor the names of its 15 * contributors may be used to endorse or promote products derived 16 * from this software without specific, prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 21 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 22 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * from: vector.s, 386BSD 0.1 unknown origin 32 * $FreeBSD: src/sys/i386/isa/icu_vector.s,v 1.14.2.2 2000/07/18 21:12:42 dfr Exp $ 33 * $DragonFly: src/sys/platform/pc64/icu/icu_vector.s,v 1.1 2008/08/29 17:07:16 dillon Exp $ 34 */ 35/* 36 * WARNING! SMP builds can use the ICU now so this code must be MP safe. 37 */ 38 39#include "opt_auto_eoi.h" 40 41#include <machine/asmacros.h> 42#include <machine/lock.h> 43#include <machine/psl.h> 44#include <machine/trap.h> 45#include <machine/segments.h> 46 47#include <machine_base/icu/icu.h> 48#include <bus/isa/i386/isa.h> 49 50#include "assym.s" 51#include "icu_ipl.h" 52 53#define ICU_IMR_OFFSET 1 /* IO_ICU{1,2} + 1 */ 54 55#define ICU_EOI 0x20 /* XXX - define elsewhere */ 56 57#define IRQ_LBIT(irq_num) (1 << (irq_num)) 58#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8)) 59#define IRQ_BYTE(irq_num) ((irq_num) >> 3) 60 61#ifdef AUTO_EOI_1 62#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */ 63#define OUTB_ICU1 64#else 65#define ENABLE_ICU1 \ 66 movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \ 67 OUTB_ICU1 ; /* ... to clear in service bit */ \ 68 69#define OUTB_ICU1 \ 70 outb %al,$IO_ICU1 ; \ 71 72#endif 73 74#ifdef AUTO_EOI_2 75/* 76 * The data sheet says no auto-EOI on slave, but it sometimes works. 77 */ 78#define ENABLE_ICU1_AND_2 ENABLE_ICU1 79#else 80#define ENABLE_ICU1_AND_2 \ 81 movb $ICU_EOI,%al ; /* as above */ \ 82 outb %al,$IO_ICU2 ; /* but do second icu first ... */ \ 83 OUTB_ICU1 ; /* ... then first icu (if !AUTO_EOI_1) */ \ 84 85#endif 86 87/* 88 * Macro helpers 89 */ 90#define ICU_PUSH_FRAME \ 91 PUSH_FRAME ; /* 15 regs + space for 5 extras */ \ 92 movl $0,TF_XFLAGS(%rsp) ; \ 93 movl $0,TF_TRAPNO(%rsp) ; \ 94 movl $0,TF_ADDR(%rsp) ; \ 95 movl $0,TF_FLAGS(%rsp) ; \ 96 movl $0,TF_ERR(%rsp) ; \ 97 cld ; \ 98 99#define MASK_IRQ(icu, irq_num) \ 100 ICU_IMASK_LOCK ; \ 101 movb icu_imen + IRQ_BYTE(irq_num),%al ; \ 102 orb $IRQ_BIT(irq_num),%al ; \ 103 movb %al,icu_imen + IRQ_BYTE(irq_num) ; \ 104 outb %al,$icu+ICU_IMR_OFFSET ; \ 105 ICU_IMASK_UNLOCK ; \ 106 107#define UNMASK_IRQ(icu, irq_num) \ 108 cmpl $0,%eax ; \ 109 jnz 8f ; \ 110 ICU_IMASK_LOCK ; \ 111 movb icu_imen + IRQ_BYTE(irq_num),%al ; \ 112 andb $~IRQ_BIT(irq_num),%al ; \ 113 movb %al,icu_imen + IRQ_BYTE(irq_num) ; \ 114 outb %al,$icu+ICU_IMR_OFFSET ; \ 115 ICU_IMASK_UNLOCK ; \ 1168: ; \ 117 118/* 119 * Fast interrupt call handlers run in the following sequence: 120 * 121 * - Push the trap frame required by doreti. 122 * - Mask the interrupt and reenable its source. 123 * - If we cannot take the interrupt set its fpending bit and 124 * doreti. 125 * - If we can take the interrupt clear its fpending bit, 126 * call the handler, then unmask the interrupt and doreti. 127 * 128 * YYY can cache gd base pointer instead of using hidden %fs 129 * prefixes. 130 */ 131 132#define FAST_INTR(irq_num, vec_name, icu, enable_icus) \ 133 .text ; \ 134 SUPERALIGN_TEXT ; \ 135IDTVEC(vec_name) ; \ 136 ICU_PUSH_FRAME ; \ 137 FAKE_MCOUNT(TF_RIP(%rsp)) ; \ 138 MASK_IRQ(icu, irq_num) ; \ 139 enable_icus ; \ 140 movq PCPU(curthread),%rbx ; \ 141 testl $-1,TD_NEST_COUNT(%rbx) ; \ 142 jne 1f ; \ 143 testl $-1,TD_CRITCOUNT(%rbx) ; \ 144 je 2f ; \ 1451: ; \ 146 /* set pending bit and return, leave interrupt masked */ \ 147 orl $IRQ_LBIT(irq_num),PCPU(fpending) ; \ 148 orl $RQF_INTPEND, PCPU(reqflags) ; \ 149 jmp 5f ; \ 1502: ; \ 151 /* clear pending bit, run handler */ \ 152 andl $~IRQ_LBIT(irq_num),PCPU(fpending) ; \ 153 pushq $irq_num ; \ 154 movq %rsp,%rdi ; /* rdi = call argument */ \ 155 incl TD_CRITCOUNT(%rbx) ; \ 156 sti ; \ 157 call ithread_fast_handler ; /* returns 0 to unmask int */ \ 158 decl TD_CRITCOUNT(%rbx) ; \ 159 addq $8,%rsp ; /* intr frame -> trap frame */ \ 160 UNMASK_IRQ(icu, irq_num) ; \ 1615: ; \ 162 MEXITCOUNT ; \ 163 jmp doreti ; \ 164 165/* 166 * Unmask a slow interrupt. This function is used by interrupt threads 167 * after they have descheduled themselves to reenable interrupts and 168 * possibly cause a reschedule to occur. 169 */ 170 171#define INTR_UNMASK(irq_num, vec_name, icu) \ 172 .text ; \ 173 SUPERALIGN_TEXT ; \ 174IDTVEC(vec_name) ; \ 175 pushq %rbp ; /* frame for ddb backtrace */ \ 176 movq %rsp, %rbp ; \ 177 subq %rax, %rax ; \ 178 UNMASK_IRQ(icu, irq_num) ; \ 179 popq %rbp ; \ 180 ret ; \ 181 182MCOUNT_LABEL(bintr) 183 FAST_INTR(0,icu_fastintr0, IO_ICU1, ENABLE_ICU1) 184 FAST_INTR(1,icu_fastintr1, IO_ICU1, ENABLE_ICU1) 185 FAST_INTR(2,icu_fastintr2, IO_ICU1, ENABLE_ICU1) 186 FAST_INTR(3,icu_fastintr3, IO_ICU1, ENABLE_ICU1) 187 FAST_INTR(4,icu_fastintr4, IO_ICU1, ENABLE_ICU1) 188 FAST_INTR(5,icu_fastintr5, IO_ICU1, ENABLE_ICU1) 189 FAST_INTR(6,icu_fastintr6, IO_ICU1, ENABLE_ICU1) 190 FAST_INTR(7,icu_fastintr7, IO_ICU1, ENABLE_ICU1) 191 FAST_INTR(8,icu_fastintr8, IO_ICU2, ENABLE_ICU1_AND_2) 192 FAST_INTR(9,icu_fastintr9, IO_ICU2, ENABLE_ICU1_AND_2) 193 FAST_INTR(10,icu_fastintr10, IO_ICU2, ENABLE_ICU1_AND_2) 194 FAST_INTR(11,icu_fastintr11, IO_ICU2, ENABLE_ICU1_AND_2) 195 FAST_INTR(12,icu_fastintr12, IO_ICU2, ENABLE_ICU1_AND_2) 196 FAST_INTR(13,icu_fastintr13, IO_ICU2, ENABLE_ICU1_AND_2) 197 FAST_INTR(14,icu_fastintr14, IO_ICU2, ENABLE_ICU1_AND_2) 198 FAST_INTR(15,icu_fastintr15, IO_ICU2, ENABLE_ICU1_AND_2) 199MCOUNT_LABEL(eintr) 200 201 .data 202 203 .text 204