1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/amd64/include/intr_machdep.h,v 1.18 2007/05/08 21:29:13 jhb Exp $ 28 * $DragonFly: src/sys/platform/pc64/include/intr_machdep.h,v 1.2 2008/08/29 17:07:17 dillon Exp $ 29 */ 30 31 #ifndef __MACHINE_INTR_MACHDEP_H__ 32 #define __MACHINE_INTR_MACHDEP_H__ 33 34 #ifdef _KERNEL 35 36 /* 37 * The maximum number of I/O interrupts we allow. This number is rather 38 * arbitrary as it is just the maximum IRQ resource value. The interrupt 39 * source for a given IRQ maps that I/O interrupt to device interrupt 40 * source whether it be a pin on an interrupt controller or an MSI interrupt. 41 * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device 42 * interrupts allocate IDT vectors on demand. Currently we have 191 IDT 43 * vectors available for device interrupts. On many systems with I/O APICs, 44 * a lot of the IRQs are not used, so this number can be much larger than 45 * 191 and still be safe since only interrupt sources in actual use will 46 * allocate IDT vectors. 47 * 48 * The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs. 49 * IRQ values beyond 256 are used by MSI. We leave 255 unused to avoid 50 * confusion since 255 is used in PCI to indicate an invalid IRQ. 51 */ 52 #define NUM_MSI_INTS 128 53 #define FIRST_MSI_INT 256 54 #define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS) 55 56 /* 57 * Default base address for MSI messages on x86 platforms. 58 */ 59 #define MSI_INTEL_ADDR_BASE 0xfee00000 60 61 /* 62 * - 1 ??? dummy counter. 63 * - 2 counters for each I/O interrupt. 64 * - 1 counter for each CPU for lapic timer. 65 * - 7 counters for each CPU for IPI counters for SMP. 66 */ 67 #ifdef SMP 68 #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 7) * MAXCPU) 69 #else 70 #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1) 71 #endif 72 73 #ifndef LOCORE 74 75 #ifndef JG_defined_inthand_t 76 #define JG_defined_inthand_t 77 typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss); 78 #endif 79 80 #endif /* !LOCORE */ 81 #endif /* _KERNEL */ 82 #endif /* !__MACHINE_INTR_MACHDEP_H__ */ 83