1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/amd64/include/intr_machdep.h,v 1.18 2007/05/08 21:29:13 jhb Exp $ 27 * $DragonFly: src/sys/platform/pc64/include/intr_machdep.h,v 1.1 2007/09/23 04:42:07 yanyh Exp $ 28 */ 29 30 #ifndef __MACHINE_INTR_MACHDEP_H__ 31 #define __MACHINE_INTR_MACHDEP_H__ 32 33 #ifdef _KERNEL 34 35 /* 36 * The maximum number of I/O interrupts we allow. This number is rather 37 * arbitrary as it is just the maximum IRQ resource value. The interrupt 38 * source for a given IRQ maps that I/O interrupt to device interrupt 39 * source whether it be a pin on an interrupt controller or an MSI interrupt. 40 * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device 41 * interrupts allocate IDT vectors on demand. Currently we have 191 IDT 42 * vectors available for device interrupts. On many systems with I/O APICs, 43 * a lot of the IRQs are not used, so this number can be much larger than 44 * 191 and still be safe since only interrupt sources in actual use will 45 * allocate IDT vectors. 46 * 47 * The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs. 48 * IRQ values beyond 256 are used by MSI. We leave 255 unused to avoid 49 * confusion since 255 is used in PCI to indicate an invalid IRQ. 50 */ 51 #define NUM_MSI_INTS 128 52 #define FIRST_MSI_INT 256 53 #define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS) 54 55 /* 56 * Default base address for MSI messages on x86 platforms. 57 */ 58 #define MSI_INTEL_ADDR_BASE 0xfee00000 59 60 /* 61 * - 1 ??? dummy counter. 62 * - 2 counters for each I/O interrupt. 63 * - 1 counter for each CPU for lapic timer. 64 * - 7 counters for each CPU for IPI counters for SMP. 65 */ 66 #ifdef SMP 67 #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 7) * MAXCPU) 68 #else 69 #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1) 70 #endif 71 72 #endif /* _KERNEL */ 73 #endif /* !__MACHINE_INTR_MACHDEP_H__ */ 74