1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz and Don Ahn. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $ 39 * $DragonFly: src/sys/platform/pc64/isa/clock.c,v 1.1 2008/08/29 17:07:19 dillon Exp $ 40 */ 41 42 /* 43 * Routines to handle clock hardware. 44 */ 45 46 /* 47 * inittodr, settodr and support routines written 48 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 49 * 50 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 51 */ 52 53 //#include "use_apm.h" 54 //#include "opt_clock.h" 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/eventhandler.h> 59 #include <sys/time.h> 60 #include <sys/kernel.h> 61 #include <sys/bus.h> 62 #ifndef SMP 63 #include <sys/lock.h> 64 #endif 65 #include <sys/sysctl.h> 66 #include <sys/cons.h> 67 #include <sys/systimer.h> 68 #include <sys/globaldata.h> 69 #include <sys/thread2.h> 70 #include <sys/systimer.h> 71 #include <sys/machintr.h> 72 73 #include <machine/clock.h> 74 #ifdef CLK_CALIBRATION_LOOP 75 #endif 76 #include <machine/cputypes.h> 77 #include <machine/frame.h> 78 #include <machine/ipl.h> 79 #include <machine/limits.h> 80 #include <machine/md_var.h> 81 #include <machine/psl.h> 82 #include <machine/segments.h> 83 #include <machine/smp.h> 84 #include <machine/specialreg.h> 85 86 #include <machine_base/icu/icu.h> 87 #include <bus/isa/isa.h> 88 #include <bus/isa/rtc.h> 89 #include <machine_base/isa/timerreg.h> 90 91 #include <machine_base/isa/intr_machdep.h> 92 93 #ifdef APIC_IO 94 /* The interrupt triggered by the 8254 (timer) chip */ 95 int apic_8254_intr; 96 static void setup_8254_mixed_mode (void); 97 #endif 98 static void i8254_restore(void); 99 static void resettodr_on_shutdown(void *arg __unused); 100 101 /* 102 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 103 * can use a simple formula for leap years. 104 */ 105 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 106 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 107 108 #ifndef TIMER_FREQ 109 #define TIMER_FREQ 1193182 110 #endif 111 112 static uint8_t i8254_walltimer_sel; 113 static uint16_t i8254_walltimer_cntr; 114 115 int adjkerntz; /* local offset from GMT in seconds */ 116 int disable_rtc_set; /* disable resettodr() if != 0 */ 117 int statclock_disable = 1; /* we don't use the statclock right now */ 118 int tsc_present; 119 int64_t tsc_frequency; 120 int tsc_is_broken; 121 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 122 int timer0_running; 123 enum tstate { RELEASED, ACQUIRED }; 124 enum tstate timer0_state; 125 enum tstate timer1_state; 126 enum tstate timer2_state; 127 128 static int beeping = 0; 129 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 130 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 131 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 132 static int rtc_loaded; 133 134 static int i8254_cputimer_div; 135 136 static struct callout sysbeepstop_ch; 137 138 static sysclock_t i8254_cputimer_count(void); 139 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last); 140 static void i8254_cputimer_destruct(struct cputimer *cputimer); 141 142 static struct cputimer i8254_cputimer = { 143 SLIST_ENTRY_INITIALIZER, 144 "i8254", 145 CPUTIMER_PRI_8254, 146 0, 147 i8254_cputimer_count, 148 cputimer_default_fromhz, 149 cputimer_default_fromus, 150 i8254_cputimer_construct, 151 i8254_cputimer_destruct, 152 TIMER_FREQ, 153 0, 0, 0 154 }; 155 156 /* 157 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped 158 * counting as of this interrupt. We use timer1 in free-running mode (not 159 * generating any interrupts) as our main counter. Each cpu has timeouts 160 * pending. 161 * 162 * This code is INTR_MPSAFE and may be called without the BGL held. 163 */ 164 static void 165 clkintr(void *dummy, void *frame_arg) 166 { 167 static sysclock_t sysclock_count; /* NOTE! Must be static */ 168 struct globaldata *gd = mycpu; 169 #ifdef SMP 170 struct globaldata *gscan; 171 int n; 172 #endif 173 174 /* 175 * SWSTROBE mode is a one-shot, the timer is no longer running 176 */ 177 timer0_running = 0; 178 179 /* 180 * XXX the dispatcher needs work. right now we call systimer_intr() 181 * directly or via IPI for any cpu with systimers queued, which is 182 * usually *ALL* of them. We need to use the LAPIC timer for this. 183 */ 184 sysclock_count = sys_cputimer->count(); 185 #ifdef SMP 186 for (n = 0; n < ncpus; ++n) { 187 gscan = globaldata_find(n); 188 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL) 189 continue; 190 if (gscan != gd) { 191 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr, 192 &sysclock_count, 0); 193 } else { 194 systimer_intr(&sysclock_count, 0, frame_arg); 195 } 196 } 197 #else 198 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL) 199 systimer_intr(&sysclock_count, 0, frame_arg); 200 #endif 201 } 202 203 204 /* 205 * NOTE! not MP safe. 206 */ 207 int 208 acquire_timer2(int mode) 209 { 210 if (timer2_state != RELEASED) 211 return (-1); 212 timer2_state = ACQUIRED; 213 214 /* 215 * This access to the timer registers is as atomic as possible 216 * because it is a single instruction. We could do better if we 217 * knew the rate. 218 */ 219 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 220 return (0); 221 } 222 223 int 224 release_timer2(void) 225 { 226 if (timer2_state != ACQUIRED) 227 return (-1); 228 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 229 timer2_state = RELEASED; 230 return (0); 231 } 232 233 /* 234 * This routine receives statistical clock interrupts from the RTC. 235 * As explained above, these occur at 128 interrupts per second. 236 * When profiling, we receive interrupts at a rate of 1024 Hz. 237 * 238 * This does not actually add as much overhead as it sounds, because 239 * when the statistical clock is active, the hardclock driver no longer 240 * needs to keep (inaccurate) statistics on its own. This decouples 241 * statistics gathering from scheduling interrupts. 242 * 243 * The RTC chip requires that we read status register C (RTC_INTR) 244 * to acknowledge an interrupt, before it will generate the next one. 245 * Under high interrupt load, rtcintr() can be indefinitely delayed and 246 * the clock can tick immediately after the read from RTC_INTR. In this 247 * case, the mc146818A interrupt signal will not drop for long enough 248 * to register with the 8259 PIC. If an interrupt is missed, the stat 249 * clock will halt, considerably degrading system performance. This is 250 * why we use 'while' rather than a more straightforward 'if' below. 251 * Stat clock ticks can still be lost, causing minor loss of accuracy 252 * in the statistics, but the stat clock will no longer stop. 253 */ 254 static void 255 rtcintr(void *dummy, void *frame) 256 { 257 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 258 ; 259 /* statclock(frame); no longer used */ 260 } 261 262 #include "opt_ddb.h" 263 #ifdef DDB 264 #include <ddb/ddb.h> 265 266 DB_SHOW_COMMAND(rtc, rtc) 267 { 268 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 269 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 270 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 271 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 272 } 273 #endif /* DDB */ 274 275 /* 276 * Return the current cpu timer count as a 32 bit integer. 277 */ 278 static 279 sysclock_t 280 i8254_cputimer_count(void) 281 { 282 static __uint16_t cputimer_last; 283 __uint16_t count; 284 sysclock_t ret; 285 286 clock_lock(); 287 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH); 288 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */ 289 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8); 290 count = -count; /* -> countup */ 291 if (count < cputimer_last) /* rollover */ 292 i8254_cputimer.base += 0x00010000; 293 ret = i8254_cputimer.base | count; 294 cputimer_last = count; 295 clock_unlock(); 296 return(ret); 297 } 298 299 /* 300 * This function is called whenever the system timebase changes, allowing 301 * us to calculate what is needed to convert a system timebase tick 302 * into an 8254 tick for the interrupt timer. If we can convert to a 303 * simple shift, multiplication, or division, we do so. Otherwise 64 304 * bit arithmatic is required every time the interrupt timer is reloaded. 305 */ 306 void 307 cputimer_intr_config(struct cputimer *timer) 308 { 309 int freq; 310 int div; 311 312 /* 313 * Will a simple divide do the trick? 314 */ 315 div = (timer->freq + (i8254_cputimer.freq / 2)) / i8254_cputimer.freq; 316 freq = i8254_cputimer.freq * div; 317 318 if (freq >= timer->freq - 1 && freq <= timer->freq + 1) 319 i8254_cputimer_div = div; 320 else 321 i8254_cputimer_div = 0; 322 } 323 324 /* 325 * Reload for the next timeout. It is possible for the reload value 326 * to be 0 or negative, indicating that an immediate timer interrupt 327 * is desired. For now make the minimum 2 ticks. 328 * 329 * We may have to convert from the system timebase to the 8254 timebase. 330 */ 331 void 332 cputimer_intr_reload(sysclock_t reload) 333 { 334 __uint16_t count; 335 336 if (i8254_cputimer_div) 337 reload /= i8254_cputimer_div; 338 else 339 reload = (int64_t)reload * i8254_cputimer.freq / sys_cputimer->freq; 340 341 if ((int)reload < 2) 342 reload = 2; 343 344 clock_lock(); 345 if (timer0_running) { 346 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */ 347 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */ 348 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */ 349 if (reload < count) { 350 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 351 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 352 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 353 } 354 } else { 355 timer0_running = 1; 356 if (reload > 0xFFFF) 357 reload = 0; /* full count */ 358 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 359 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 360 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 361 } 362 clock_unlock(); 363 } 364 365 /* 366 * DELAY(usec) - Spin for the specified number of microseconds. 367 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds, 368 * but do a thread switch in the loop 369 * 370 * Relies on timer 1 counting down from (cputimer_freq / hz) 371 * Note: timer had better have been programmed before this is first used! 372 */ 373 static void 374 DODELAY(int n, int doswitch) 375 { 376 int delta, prev_tick, tick, ticks_left; 377 378 #ifdef DELAYDEBUG 379 int getit_calls = 1; 380 int n1; 381 static int state = 0; 382 383 if (state == 0) { 384 state = 1; 385 for (n1 = 1; n1 <= 10000000; n1 *= 10) 386 DELAY(n1); 387 state = 2; 388 } 389 if (state == 1) 390 kprintf("DELAY(%d)...", n); 391 #endif 392 /* 393 * Guard against the timer being uninitialized if we are called 394 * early for console i/o. 395 */ 396 if (timer0_state == RELEASED) 397 i8254_restore(); 398 399 /* 400 * Read the counter first, so that the rest of the setup overhead is 401 * counted. Then calculate the number of hardware timer ticks 402 * required, rounding up to be sure we delay at least the requested 403 * number of microseconds. 404 */ 405 prev_tick = sys_cputimer->count(); 406 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) / 407 1000000; 408 409 /* 410 * Loop until done. 411 */ 412 while (ticks_left > 0) { 413 tick = sys_cputimer->count(); 414 #ifdef DELAYDEBUG 415 ++getit_calls; 416 #endif 417 delta = tick - prev_tick; 418 prev_tick = tick; 419 if (delta < 0) 420 delta = 0; 421 ticks_left -= delta; 422 if (doswitch && ticks_left > 0) 423 lwkt_switch(); 424 } 425 #ifdef DELAYDEBUG 426 if (state == 1) 427 kprintf(" %d calls to getit() at %d usec each\n", 428 getit_calls, (n + 5) / getit_calls); 429 #endif 430 } 431 432 void 433 DELAY(int n) 434 { 435 DODELAY(n, 0); 436 } 437 438 void 439 DRIVERSLEEP(int usec) 440 { 441 globaldata_t gd = mycpu; 442 443 if (gd->gd_intr_nesting_level || 444 gd->gd_spinlock_rd || 445 gd->gd_spinlocks_wr) { 446 DODELAY(usec, 0); 447 } else { 448 DODELAY(usec, 1); 449 } 450 } 451 452 static void 453 sysbeepstop(void *chan) 454 { 455 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 456 beeping = 0; 457 release_timer2(); 458 } 459 460 int 461 sysbeep(int pitch, int period) 462 { 463 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 464 return(-1); 465 /* 466 * Nobody else is using timer2, we do not need the clock lock 467 */ 468 outb(TIMER_CNTR2, pitch); 469 outb(TIMER_CNTR2, (pitch>>8)); 470 if (!beeping) { 471 /* enable counter2 output to speaker */ 472 outb(IO_PPI, inb(IO_PPI) | 3); 473 beeping = period; 474 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL); 475 } 476 return (0); 477 } 478 479 /* 480 * RTC support routines 481 */ 482 483 int 484 rtcin(int reg) 485 { 486 u_char val; 487 488 crit_enter(); 489 outb(IO_RTC, reg); 490 inb(0x84); 491 val = inb(IO_RTC + 1); 492 inb(0x84); 493 crit_exit(); 494 return (val); 495 } 496 497 static __inline void 498 writertc(u_char reg, u_char val) 499 { 500 crit_enter(); 501 inb(0x84); 502 outb(IO_RTC, reg); 503 inb(0x84); 504 outb(IO_RTC + 1, val); 505 inb(0x84); /* XXX work around wrong order in rtcin() */ 506 crit_exit(); 507 } 508 509 static __inline int 510 readrtc(int port) 511 { 512 return(bcd2bin(rtcin(port))); 513 } 514 515 static u_int 516 calibrate_clocks(void) 517 { 518 u_int64_t old_tsc; 519 u_int count, prev_count, tot_count; 520 int sec, start_sec, timeout; 521 522 if (bootverbose) 523 kprintf("Calibrating clock(s) ... "); 524 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 525 goto fail; 526 timeout = 100000000; 527 528 /* Read the mc146818A seconds counter. */ 529 for (;;) { 530 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 531 sec = rtcin(RTC_SEC); 532 break; 533 } 534 if (--timeout == 0) 535 goto fail; 536 } 537 538 /* Wait for the mC146818A seconds counter to change. */ 539 start_sec = sec; 540 for (;;) { 541 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 542 sec = rtcin(RTC_SEC); 543 if (sec != start_sec) 544 break; 545 } 546 if (--timeout == 0) 547 goto fail; 548 } 549 550 /* Start keeping track of the i8254 counter. */ 551 prev_count = sys_cputimer->count(); 552 tot_count = 0; 553 554 if (tsc_present) 555 old_tsc = rdtsc(); 556 else 557 old_tsc = 0; /* shut up gcc */ 558 559 /* 560 * Wait for the mc146818A seconds counter to change. Read the i8254 561 * counter for each iteration since this is convenient and only 562 * costs a few usec of inaccuracy. The timing of the final reads 563 * of the counters almost matches the timing of the initial reads, 564 * so the main cause of inaccuracy is the varying latency from 565 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 566 * rtcin(RTC_SEC) that returns a changed seconds count. The 567 * maximum inaccuracy from this cause is < 10 usec on 486's. 568 */ 569 start_sec = sec; 570 for (;;) { 571 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 572 sec = rtcin(RTC_SEC); 573 count = sys_cputimer->count(); 574 tot_count += (int)(count - prev_count); 575 prev_count = count; 576 if (sec != start_sec) 577 break; 578 if (--timeout == 0) 579 goto fail; 580 } 581 582 /* 583 * Read the cpu cycle counter. The timing considerations are 584 * similar to those for the i8254 clock. 585 */ 586 if (tsc_present) { 587 tsc_frequency = rdtsc() - old_tsc; 588 } 589 590 if (tsc_present) 591 kprintf("TSC clock: %llu Hz, ", tsc_frequency); 592 kprintf("i8254 clock: %u Hz\n", tot_count); 593 return (tot_count); 594 595 fail: 596 kprintf("failed, using default i8254 clock of %u Hz\n", 597 i8254_cputimer.freq); 598 return (i8254_cputimer.freq); 599 } 600 601 static void 602 i8254_restore(void) 603 { 604 timer0_state = ACQUIRED; 605 606 clock_lock(); 607 608 /* 609 * Timer0 is our fine-grained variable clock interrupt 610 */ 611 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 612 outb(TIMER_CNTR0, 2); /* lsb */ 613 outb(TIMER_CNTR0, 0); /* msb */ 614 clock_unlock(); 615 616 /* 617 * Timer1 or timer2 is our free-running clock, but only if another 618 * has not been selected. 619 */ 620 cputimer_register(&i8254_cputimer); 621 cputimer_select(&i8254_cputimer, 0); 622 } 623 624 static void 625 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock) 626 { 627 int which; 628 629 /* 630 * Should we use timer 1 or timer 2 ? 631 */ 632 which = 0; 633 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which); 634 if (which != 1 && which != 2) 635 which = 2; 636 637 switch(which) { 638 case 1: 639 timer->name = "i8254_timer1"; 640 timer->type = CPUTIMER_8254_SEL1; 641 i8254_walltimer_sel = TIMER_SEL1; 642 i8254_walltimer_cntr = TIMER_CNTR1; 643 timer1_state = ACQUIRED; 644 break; 645 case 2: 646 timer->name = "i8254_timer2"; 647 timer->type = CPUTIMER_8254_SEL2; 648 i8254_walltimer_sel = TIMER_SEL2; 649 i8254_walltimer_cntr = TIMER_CNTR2; 650 timer2_state = ACQUIRED; 651 break; 652 } 653 654 timer->base = (oldclock + 0xFFFF) & ~0xFFFF; 655 656 clock_lock(); 657 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT); 658 outb(i8254_walltimer_cntr, 0); /* lsb */ 659 outb(i8254_walltimer_cntr, 0); /* msb */ 660 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */ 661 clock_unlock(); 662 } 663 664 static void 665 i8254_cputimer_destruct(struct cputimer *timer) 666 { 667 switch(timer->type) { 668 case CPUTIMER_8254_SEL1: 669 timer1_state = RELEASED; 670 break; 671 case CPUTIMER_8254_SEL2: 672 timer2_state = RELEASED; 673 break; 674 default: 675 break; 676 } 677 timer->type = 0; 678 } 679 680 static void 681 rtc_restore(void) 682 { 683 /* Restore all of the RTC's "status" (actually, control) registers. */ 684 writertc(RTC_STATUSB, RTCSB_24HR); 685 writertc(RTC_STATUSA, rtc_statusa); 686 writertc(RTC_STATUSB, rtc_statusb); 687 } 688 689 /* 690 * Restore all the timers. 691 * 692 * This function is called to resynchronize our core timekeeping after a 693 * long halt, e.g. from apm_default_resume() and friends. It is also 694 * called if after a BIOS call we have detected munging of the 8254. 695 * It is necessary because cputimer_count() counter's delta may have grown 696 * too large for nanouptime() and friends to handle, or (in the case of 8254 697 * munging) might cause the SYSTIMER code to prematurely trigger. 698 */ 699 void 700 timer_restore(void) 701 { 702 crit_enter(); 703 i8254_restore(); /* restore timer_freq and hz */ 704 rtc_restore(); /* reenable RTC interrupts */ 705 crit_exit(); 706 } 707 708 /* 709 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 710 */ 711 void 712 startrtclock(void) 713 { 714 u_int delta, freq; 715 716 /* 717 * Can we use the TSC? 718 */ 719 if (cpu_feature & CPUID_TSC) 720 tsc_present = 1; 721 else 722 tsc_present = 0; 723 724 /* 725 * Initial RTC state, don't do anything unexpected 726 */ 727 writertc(RTC_STATUSA, rtc_statusa); 728 writertc(RTC_STATUSB, RTCSB_24HR); 729 730 /* 731 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to 732 * generate an interrupt, which we will ignore for now. 733 * 734 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000 735 * (so it counts a full 2^16 and repeats). We will use this timer 736 * for our counting. 737 */ 738 i8254_restore(); 739 freq = calibrate_clocks(); 740 #ifdef CLK_CALIBRATION_LOOP 741 if (bootverbose) { 742 kprintf( 743 "Press a key on the console to abort clock calibration\n"); 744 while (cncheckc() == -1) 745 calibrate_clocks(); 746 } 747 #endif 748 749 /* 750 * Use the calibrated i8254 frequency if it seems reasonable. 751 * Otherwise use the default, and don't use the calibrated i586 752 * frequency. 753 */ 754 delta = freq > i8254_cputimer.freq ? 755 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq; 756 if (delta < i8254_cputimer.freq / 100) { 757 #ifndef CLK_USE_I8254_CALIBRATION 758 if (bootverbose) 759 kprintf( 760 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 761 freq = i8254_cputimer.freq; 762 #endif 763 cputimer_set_frequency(&i8254_cputimer, freq); 764 } else { 765 if (bootverbose) 766 kprintf( 767 "%d Hz differs from default of %d Hz by more than 1%%\n", 768 freq, i8254_cputimer.freq); 769 tsc_frequency = 0; 770 } 771 772 #ifndef CLK_USE_TSC_CALIBRATION 773 if (tsc_frequency != 0) { 774 if (bootverbose) 775 kprintf( 776 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 777 tsc_frequency = 0; 778 } 779 #endif 780 if (tsc_present && tsc_frequency == 0) { 781 /* 782 * Calibration of the i586 clock relative to the mc146818A 783 * clock failed. Do a less accurate calibration relative 784 * to the i8254 clock. 785 */ 786 u_int64_t old_tsc = rdtsc(); 787 788 DELAY(1000000); 789 tsc_frequency = rdtsc() - old_tsc; 790 #ifdef CLK_USE_TSC_CALIBRATION 791 if (bootverbose) { 792 kprintf("TSC clock: %llu Hz (Method B)\n", 793 tsc_frequency); 794 } 795 #endif 796 } 797 798 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST); 799 800 #if !defined(SMP) 801 /* 802 * We can not use the TSC in SMP mode, until we figure out a 803 * cheap (impossible), reliable and precise (yeah right!) way 804 * to synchronize the TSCs of all the CPUs. 805 * Curse Intel for leaving the counter out of the I/O APIC. 806 */ 807 808 #if NAPM > 0 809 /* 810 * We can not use the TSC if we support APM. Precise timekeeping 811 * on an APM'ed machine is at best a fools pursuit, since 812 * any and all of the time spent in various SMM code can't 813 * be reliably accounted for. Reading the RTC is your only 814 * source of reliable time info. The i8254 looses too of course 815 * but we need to have some kind of time... 816 * We don't know at this point whether APM is going to be used 817 * or not, nor when it might be activated. Play it safe. 818 */ 819 return; 820 #endif /* NAPM > 0 */ 821 822 #endif /* !defined(SMP) */ 823 } 824 825 /* 826 * Sync the time of day back to the RTC on shutdown, but only if 827 * we have already loaded it and have not crashed. 828 */ 829 static void 830 resettodr_on_shutdown(void *arg __unused) 831 { 832 if (rtc_loaded && panicstr == NULL) { 833 resettodr(); 834 } 835 } 836 837 /* 838 * Initialize the time of day register, based on the time base which is, e.g. 839 * from a filesystem. 840 */ 841 void 842 inittodr(time_t base) 843 { 844 unsigned long sec, days; 845 int yd; 846 int year, month; 847 int y, m; 848 struct timespec ts; 849 850 if (base) { 851 ts.tv_sec = base; 852 ts.tv_nsec = 0; 853 set_timeofday(&ts); 854 } 855 856 /* Look if we have a RTC present and the time is valid */ 857 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 858 goto wrong_time; 859 860 /* wait for time update to complete */ 861 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 862 crit_enter(); 863 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 864 crit_exit(); 865 crit_enter(); 866 } 867 868 days = 0; 869 #ifdef USE_RTC_CENTURY 870 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 871 #else 872 year = readrtc(RTC_YEAR) + 1900; 873 if (year < 1970) 874 year += 100; 875 #endif 876 if (year < 1970) { 877 crit_exit(); 878 goto wrong_time; 879 } 880 month = readrtc(RTC_MONTH); 881 for (m = 1; m < month; m++) 882 days += daysinmonth[m-1]; 883 if ((month > 2) && LEAPYEAR(year)) 884 days ++; 885 days += readrtc(RTC_DAY) - 1; 886 yd = days; 887 for (y = 1970; y < year; y++) 888 days += DAYSPERYEAR + LEAPYEAR(y); 889 sec = ((( days * 24 + 890 readrtc(RTC_HRS)) * 60 + 891 readrtc(RTC_MIN)) * 60 + 892 readrtc(RTC_SEC)); 893 /* sec now contains the number of seconds, since Jan 1 1970, 894 in the local time zone */ 895 896 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 897 898 y = time_second - sec; 899 if (y <= -2 || y >= 2) { 900 /* badly off, adjust it */ 901 ts.tv_sec = sec; 902 ts.tv_nsec = 0; 903 set_timeofday(&ts); 904 } 905 rtc_loaded = 1; 906 crit_exit(); 907 return; 908 909 wrong_time: 910 kprintf("Invalid time in real time clock.\n"); 911 kprintf("Check and reset the date immediately!\n"); 912 } 913 914 /* 915 * Write system time back to RTC 916 */ 917 void 918 resettodr(void) 919 { 920 struct timeval tv; 921 unsigned long tm; 922 int m; 923 int y; 924 925 if (disable_rtc_set) 926 return; 927 928 microtime(&tv); 929 tm = tv.tv_sec; 930 931 crit_enter(); 932 /* Disable RTC updates and interrupts. */ 933 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 934 935 /* Calculate local time to put in RTC */ 936 937 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 938 939 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 940 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 941 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 942 943 /* We have now the days since 01-01-1970 in tm */ 944 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 945 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 946 tm >= m; 947 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 948 tm -= m; 949 950 /* Now we have the years in y and the day-of-the-year in tm */ 951 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 952 #ifdef USE_RTC_CENTURY 953 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 954 #endif 955 for (m = 0; ; m++) { 956 int ml; 957 958 ml = daysinmonth[m]; 959 if (m == 1 && LEAPYEAR(y)) 960 ml++; 961 if (tm < ml) 962 break; 963 tm -= ml; 964 } 965 966 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 967 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 968 969 /* Reenable RTC updates and interrupts. */ 970 writertc(RTC_STATUSB, rtc_statusb); 971 crit_exit(); 972 } 973 974 975 /* 976 * Start both clocks running. DragonFly note: the stat clock is no longer 977 * used. Instead, 8254 based systimers are used for all major clock 978 * interrupts. statclock_disable is set by default. 979 */ 980 void 981 cpu_initclocks(void *arg __unused) 982 { 983 int diag; 984 #ifdef APIC_IO 985 int apic_8254_trial; 986 void *clkdesc; 987 #endif /* APIC_IO */ 988 989 if (statclock_disable) { 990 /* 991 * The stat interrupt mask is different without the 992 * statistics clock. Also, don't set the interrupt 993 * flag which would normally cause the RTC to generate 994 * interrupts. 995 */ 996 rtc_statusb = RTCSB_24HR; 997 } else { 998 /* Setting stathz to nonzero early helps avoid races. */ 999 stathz = RTC_NOPROFRATE; 1000 profhz = RTC_PROFRATE; 1001 } 1002 1003 /* Finish initializing 8253 timer 0. */ 1004 #ifdef APIC_IO 1005 1006 apic_8254_intr = isa_apic_irq(0); 1007 apic_8254_trial = 0; 1008 if (apic_8254_intr >= 0 ) { 1009 if (apic_int_type(0, 0) == 3) 1010 apic_8254_trial = 1; 1011 } else { 1012 /* look for ExtInt on pin 0 */ 1013 if (apic_int_type(0, 0) == 3) { 1014 apic_8254_intr = apic_irq(0, 0); 1015 setup_8254_mixed_mode(); 1016 } else 1017 panic("APIC_IO: Cannot route 8254 interrupt to CPU"); 1018 } 1019 1020 clkdesc = register_int(apic_8254_intr, clkintr, NULL, "clk", 1021 NULL, 1022 INTR_EXCL | INTR_FAST | 1023 INTR_NOPOLL | INTR_MPSAFE | 1024 INTR_NOENTROPY); 1025 machintr_intren(apic_8254_intr); 1026 1027 #else /* APIC_IO */ 1028 1029 register_int(0, clkintr, NULL, "clk", NULL, 1030 INTR_EXCL | INTR_FAST | 1031 INTR_NOPOLL | INTR_MPSAFE | 1032 INTR_NOENTROPY); 1033 machintr_intren(ICU_IRQ0); 1034 1035 #endif /* APIC_IO */ 1036 1037 /* Initialize RTC. */ 1038 writertc(RTC_STATUSA, rtc_statusa); 1039 writertc(RTC_STATUSB, RTCSB_24HR); 1040 1041 if (statclock_disable == 0) { 1042 diag = rtcin(RTC_DIAG); 1043 if (diag != 0) 1044 kprintf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1045 1046 #ifdef APIC_IO 1047 if (isa_apic_irq(8) != 8) 1048 panic("APIC RTC != 8"); 1049 #endif /* APIC_IO */ 1050 1051 register_int(8, (inthand2_t *)rtcintr, NULL, "rtc", NULL, 1052 INTR_EXCL | INTR_FAST | INTR_NOPOLL | 1053 INTR_NOENTROPY); 1054 machintr_intren(8); 1055 1056 writertc(RTC_STATUSB, rtc_statusb); 1057 } 1058 1059 #ifdef APIC_IO 1060 if (apic_8254_trial) { 1061 sysclock_t base; 1062 long lastcnt; 1063 1064 lastcnt = get_interrupt_counter(apic_8254_intr); 1065 1066 /* 1067 * XXX this assumes the 8254 is the cpu timer. Force an 1068 * 8254 Timer0 interrupt and wait 1/100s for it to happen, 1069 * then see if we got it. 1070 */ 1071 kprintf("APIC_IO: Testing 8254 interrupt delivery\n"); 1072 cputimer_intr_reload(2); /* XXX assumes 8254 */ 1073 base = sys_cputimer->count(); 1074 while (sys_cputimer->count() - base < sys_cputimer->freq / 100) 1075 ; /* nothing */ 1076 if (get_interrupt_counter(apic_8254_intr) - lastcnt == 0) { 1077 /* 1078 * The MP table is broken. 1079 * The 8254 was not connected to the specified pin 1080 * on the IO APIC. 1081 * Workaround: Limited variant of mixed mode. 1082 */ 1083 machintr_intrdis(apic_8254_intr); 1084 unregister_int(clkdesc); 1085 kprintf("APIC_IO: Broken MP table detected: " 1086 "8254 is not connected to " 1087 "IOAPIC #%d intpin %d\n", 1088 int_to_apicintpin[apic_8254_intr].ioapic, 1089 int_to_apicintpin[apic_8254_intr].int_pin); 1090 /* 1091 * Revoke current ISA IRQ 0 assignment and 1092 * configure a fallback interrupt routing from 1093 * the 8254 Timer via the 8259 PIC to the 1094 * an ExtInt interrupt line on IOAPIC #0 intpin 0. 1095 * We reuse the low level interrupt handler number. 1096 */ 1097 if (apic_irq(0, 0) < 0) { 1098 revoke_apic_irq(apic_8254_intr); 1099 assign_apic_irq(0, 0, apic_8254_intr); 1100 } 1101 apic_8254_intr = apic_irq(0, 0); 1102 setup_8254_mixed_mode(); 1103 register_int(apic_8254_intr, clkintr, NULL, "clk", 1104 NULL, 1105 INTR_EXCL | INTR_FAST | 1106 INTR_NOPOLL | INTR_MPSAFE | 1107 INTR_NOENTROPY); 1108 machintr_intren(apic_8254_intr); 1109 } 1110 1111 } 1112 if (apic_int_type(0, 0) != 3 || 1113 int_to_apicintpin[apic_8254_intr].ioapic != 0 || 1114 int_to_apicintpin[apic_8254_intr].int_pin != 0) { 1115 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n", 1116 int_to_apicintpin[apic_8254_intr].ioapic, 1117 int_to_apicintpin[apic_8254_intr].int_pin); 1118 } else { 1119 kprintf("APIC_IO: " 1120 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n"); 1121 } 1122 #endif 1123 callout_init(&sysbeepstop_ch); 1124 } 1125 SYSINIT(clocks8254, SI_BOOT2_CLOCKREG, SI_ORDER_FIRST, cpu_initclocks, NULL) 1126 1127 #ifdef APIC_IO 1128 1129 static void 1130 setup_8254_mixed_mode(void) 1131 { 1132 /* 1133 * Allow 8254 timer to INTerrupt 8259: 1134 * re-initialize master 8259: 1135 * reset; prog 4 bytes, single ICU, edge triggered 1136 */ 1137 outb(IO_ICU1, 0x13); 1138 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */ 1139 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1140 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1141 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1142 1143 /* program IO APIC for type 3 INT on INT0 */ 1144 if (ext_int_setup(0, 0) < 0) 1145 panic("8254 redirect via APIC pin0 impossible!"); 1146 } 1147 #endif 1148 1149 void 1150 setstatclockrate(int newhz) 1151 { 1152 if (newhz == RTC_PROFRATE) 1153 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1154 else 1155 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1156 writertc(RTC_STATUSA, rtc_statusa); 1157 } 1158 1159 #if 0 1160 static unsigned 1161 tsc_get_timecount(struct timecounter *tc) 1162 { 1163 return (rdtsc()); 1164 } 1165 #endif 1166 1167 #ifdef KERN_TIMESTAMP 1168 #define KERN_TIMESTAMP_SIZE 16384 1169 static u_long tsc[KERN_TIMESTAMP_SIZE] ; 1170 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc, 1171 sizeof(tsc), "LU", "Kernel timestamps"); 1172 void 1173 _TSTMP(u_int32_t x) 1174 { 1175 static int i; 1176 1177 tsc[i] = (u_int32_t)rdtsc(); 1178 tsc[i+1] = x; 1179 i = i + 2; 1180 if (i >= KERN_TIMESTAMP_SIZE) 1181 i = 0; 1182 tsc[i] = 0; /* mark last entry */ 1183 } 1184 #endif /* KERN_TIMESTAMP */ 1185 1186 /* 1187 * 1188 */ 1189 1190 static int 1191 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS) 1192 { 1193 sysclock_t count; 1194 __uint64_t tscval; 1195 char buf[32]; 1196 1197 crit_enter(); 1198 if (sys_cputimer == &i8254_cputimer) 1199 count = sys_cputimer->count(); 1200 else 1201 count = 0; 1202 if (tsc_present) 1203 tscval = rdtsc(); 1204 else 1205 tscval = 0; 1206 crit_exit(); 1207 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval); 1208 return(SYSCTL_OUT(req, buf, strlen(buf) + 1)); 1209 } 1210 1211 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254"); 1212 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0, 1213 "frequency"); 1214 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD, 1215 0, 0, hw_i8254_timestamp, "A", ""); 1216 1217 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD, 1218 &tsc_present, 0, "TSC Available"); 1219 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD, 1220 &tsc_frequency, 0, "TSC Frequency"); 1221 1222