1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz and Don Ahn. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $ 39 */ 40 41 /* 42 * Routines to handle clock hardware. 43 */ 44 45 /* 46 * inittodr, settodr and support routines written 47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 48 * 49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 50 */ 51 52 #if 0 53 #include "use_apm.h" 54 #include "opt_clock.h" 55 #endif 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/eventhandler.h> 60 #include <sys/time.h> 61 #include <sys/kernel.h> 62 #include <sys/bus.h> 63 #ifndef SMP 64 #include <sys/lock.h> 65 #endif 66 #include <sys/sysctl.h> 67 #include <sys/cons.h> 68 #include <sys/systimer.h> 69 #include <sys/globaldata.h> 70 #include <sys/thread2.h> 71 #include <sys/systimer.h> 72 #include <sys/machintr.h> 73 74 #include <machine/clock.h> 75 #ifdef CLK_CALIBRATION_LOOP 76 #endif 77 #include <machine/cputypes.h> 78 #include <machine/frame.h> 79 #include <machine/ipl.h> 80 #include <machine/limits.h> 81 #include <machine/md_var.h> 82 #include <machine/psl.h> 83 #include <machine/segments.h> 84 #include <machine/smp.h> 85 #include <machine/specialreg.h> 86 87 #include <machine_base/icu/icu.h> 88 #include <bus/isa/isa.h> 89 #include <bus/isa/rtc.h> 90 #include <machine_base/isa/timerreg.h> 91 92 #include <machine_base/isa/intr_machdep.h> 93 94 #ifdef SMP /* APIC-IO */ 95 /* The interrupt triggered by the 8254 (timer) chip */ 96 int apic_8254_intr; 97 static void setup_8254_mixed_mode (void); 98 #endif 99 static void i8254_restore(void); 100 static void resettodr_on_shutdown(void *arg __unused); 101 102 /* 103 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 104 * can use a simple formula for leap years. 105 */ 106 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 107 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 108 109 #ifndef TIMER_FREQ 110 #define TIMER_FREQ 1193182 111 #endif 112 113 static uint8_t i8254_walltimer_sel; 114 static uint16_t i8254_walltimer_cntr; 115 116 int adjkerntz; /* local offset from GMT in seconds */ 117 int disable_rtc_set; /* disable resettodr() if != 0 */ 118 int statclock_disable = 1; /* we don't use the statclock right now */ 119 int tsc_present; 120 int64_t tsc_frequency; 121 int tsc_is_broken; 122 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 123 int timer0_running; 124 enum tstate { RELEASED, ACQUIRED }; 125 enum tstate timer0_state; 126 enum tstate timer1_state; 127 enum tstate timer2_state; 128 129 static int beeping = 0; 130 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 131 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 132 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 133 static int rtc_loaded; 134 135 static int i8254_cputimer_div; 136 137 static int i8254_nointr; 138 static int i8254_intr_disable = 0; 139 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable); 140 141 static struct callout sysbeepstop_ch; 142 143 static sysclock_t i8254_cputimer_count(void); 144 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last); 145 static void i8254_cputimer_destruct(struct cputimer *cputimer); 146 147 static struct cputimer i8254_cputimer = { 148 SLIST_ENTRY_INITIALIZER, 149 "i8254", 150 CPUTIMER_PRI_8254, 151 0, 152 i8254_cputimer_count, 153 cputimer_default_fromhz, 154 cputimer_default_fromus, 155 i8254_cputimer_construct, 156 i8254_cputimer_destruct, 157 TIMER_FREQ, 158 0, 0, 0 159 }; 160 161 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t); 162 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *); 163 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t); 164 165 static struct cputimer_intr i8254_cputimer_intr = { 166 .freq = TIMER_FREQ, 167 .reload = i8254_intr_reload, 168 .enable = cputimer_intr_default_enable, 169 .config = i8254_intr_config, 170 .restart = cputimer_intr_default_restart, 171 .pmfixup = cputimer_intr_default_pmfixup, 172 .initclock = i8254_intr_initclock, 173 .next = SLIST_ENTRY_INITIALIZER, 174 .name = "i8254", 175 .type = CPUTIMER_INTR_8254, 176 .prio = CPUTIMER_INTR_PRIO_8254, 177 .caps = CPUTIMER_INTR_CAP_PS 178 }; 179 180 /* 181 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped 182 * counting as of this interrupt. We use timer1 in free-running mode (not 183 * generating any interrupts) as our main counter. Each cpu has timeouts 184 * pending. 185 * 186 * This code is INTR_MPSAFE and may be called without the BGL held. 187 */ 188 static void 189 clkintr(void *dummy, void *frame_arg) 190 { 191 static sysclock_t sysclock_count; /* NOTE! Must be static */ 192 struct globaldata *gd = mycpu; 193 #ifdef SMP 194 struct globaldata *gscan; 195 int n; 196 #endif 197 198 /* 199 * SWSTROBE mode is a one-shot, the timer is no longer running 200 */ 201 timer0_running = 0; 202 203 /* 204 * XXX the dispatcher needs work. right now we call systimer_intr() 205 * directly or via IPI for any cpu with systimers queued, which is 206 * usually *ALL* of them. We need to use the LAPIC timer for this. 207 */ 208 sysclock_count = sys_cputimer->count(); 209 #ifdef SMP 210 for (n = 0; n < ncpus; ++n) { 211 gscan = globaldata_find(n); 212 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL) 213 continue; 214 if (gscan != gd) { 215 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr, 216 &sysclock_count, 0); 217 } else { 218 systimer_intr(&sysclock_count, 0, frame_arg); 219 } 220 } 221 #else 222 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL) 223 systimer_intr(&sysclock_count, 0, frame_arg); 224 #endif 225 } 226 227 228 /* 229 * NOTE! not MP safe. 230 */ 231 int 232 acquire_timer2(int mode) 233 { 234 if (timer2_state != RELEASED) 235 return (-1); 236 timer2_state = ACQUIRED; 237 238 /* 239 * This access to the timer registers is as atomic as possible 240 * because it is a single instruction. We could do better if we 241 * knew the rate. 242 */ 243 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 244 return (0); 245 } 246 247 int 248 release_timer2(void) 249 { 250 if (timer2_state != ACQUIRED) 251 return (-1); 252 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 253 timer2_state = RELEASED; 254 return (0); 255 } 256 257 /* 258 * This routine receives statistical clock interrupts from the RTC. 259 * As explained above, these occur at 128 interrupts per second. 260 * When profiling, we receive interrupts at a rate of 1024 Hz. 261 * 262 * This does not actually add as much overhead as it sounds, because 263 * when the statistical clock is active, the hardclock driver no longer 264 * needs to keep (inaccurate) statistics on its own. This decouples 265 * statistics gathering from scheduling interrupts. 266 * 267 * The RTC chip requires that we read status register C (RTC_INTR) 268 * to acknowledge an interrupt, before it will generate the next one. 269 * Under high interrupt load, rtcintr() can be indefinitely delayed and 270 * the clock can tick immediately after the read from RTC_INTR. In this 271 * case, the mc146818A interrupt signal will not drop for long enough 272 * to register with the 8259 PIC. If an interrupt is missed, the stat 273 * clock will halt, considerably degrading system performance. This is 274 * why we use 'while' rather than a more straightforward 'if' below. 275 * Stat clock ticks can still be lost, causing minor loss of accuracy 276 * in the statistics, but the stat clock will no longer stop. 277 */ 278 static void 279 rtcintr(void *dummy, void *frame) 280 { 281 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 282 ; 283 /* statclock(frame); no longer used */ 284 } 285 286 #include "opt_ddb.h" 287 #ifdef DDB 288 #include <ddb/ddb.h> 289 290 DB_SHOW_COMMAND(rtc, rtc) 291 { 292 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 293 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 294 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 295 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 296 } 297 #endif /* DDB */ 298 299 /* 300 * Return the current cpu timer count as a 32 bit integer. 301 */ 302 static 303 sysclock_t 304 i8254_cputimer_count(void) 305 { 306 static __uint16_t cputimer_last; 307 __uint16_t count; 308 sysclock_t ret; 309 310 clock_lock(); 311 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH); 312 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */ 313 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8); 314 count = -count; /* -> countup */ 315 if (count < cputimer_last) /* rollover */ 316 i8254_cputimer.base += 0x00010000; 317 ret = i8254_cputimer.base | count; 318 cputimer_last = count; 319 clock_unlock(); 320 return(ret); 321 } 322 323 /* 324 * This function is called whenever the system timebase changes, allowing 325 * us to calculate what is needed to convert a system timebase tick 326 * into an 8254 tick for the interrupt timer. If we can convert to a 327 * simple shift, multiplication, or division, we do so. Otherwise 64 328 * bit arithmatic is required every time the interrupt timer is reloaded. 329 */ 330 static void 331 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer) 332 { 333 int freq; 334 int div; 335 336 /* 337 * Will a simple divide do the trick? 338 */ 339 div = (timer->freq + (cti->freq / 2)) / cti->freq; 340 freq = cti->freq * div; 341 342 if (freq >= timer->freq - 1 && freq <= timer->freq + 1) 343 i8254_cputimer_div = div; 344 else 345 i8254_cputimer_div = 0; 346 } 347 348 /* 349 * Reload for the next timeout. It is possible for the reload value 350 * to be 0 or negative, indicating that an immediate timer interrupt 351 * is desired. For now make the minimum 2 ticks. 352 * 353 * We may have to convert from the system timebase to the 8254 timebase. 354 */ 355 static void 356 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload) 357 { 358 __uint16_t count; 359 360 if (i8254_cputimer_div) 361 reload /= i8254_cputimer_div; 362 else 363 reload = (int64_t)reload * cti->freq / sys_cputimer->freq; 364 365 if ((int)reload < 2) 366 reload = 2; 367 368 clock_lock(); 369 if (timer0_running) { 370 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */ 371 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */ 372 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */ 373 if (reload < count) { 374 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 375 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 376 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 377 } 378 } else { 379 timer0_running = 1; 380 if (reload > 0xFFFF) 381 reload = 0; /* full count */ 382 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 383 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 384 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 385 } 386 clock_unlock(); 387 } 388 389 /* 390 * DELAY(usec) - Spin for the specified number of microseconds. 391 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds, 392 * but do a thread switch in the loop 393 * 394 * Relies on timer 1 counting down from (cputimer_freq / hz) 395 * Note: timer had better have been programmed before this is first used! 396 */ 397 static void 398 DODELAY(int n, int doswitch) 399 { 400 int delta, prev_tick, tick, ticks_left; 401 402 #ifdef DELAYDEBUG 403 int getit_calls = 1; 404 int n1; 405 static int state = 0; 406 407 if (state == 0) { 408 state = 1; 409 for (n1 = 1; n1 <= 10000000; n1 *= 10) 410 DELAY(n1); 411 state = 2; 412 } 413 if (state == 1) 414 kprintf("DELAY(%d)...", n); 415 #endif 416 /* 417 * Guard against the timer being uninitialized if we are called 418 * early for console i/o. 419 */ 420 if (timer0_state == RELEASED) 421 i8254_restore(); 422 423 /* 424 * Read the counter first, so that the rest of the setup overhead is 425 * counted. Then calculate the number of hardware timer ticks 426 * required, rounding up to be sure we delay at least the requested 427 * number of microseconds. 428 */ 429 prev_tick = sys_cputimer->count(); 430 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) / 431 1000000; 432 433 /* 434 * Loop until done. 435 */ 436 while (ticks_left > 0) { 437 tick = sys_cputimer->count(); 438 #ifdef DELAYDEBUG 439 ++getit_calls; 440 #endif 441 delta = tick - prev_tick; 442 prev_tick = tick; 443 if (delta < 0) 444 delta = 0; 445 ticks_left -= delta; 446 if (doswitch && ticks_left > 0) 447 lwkt_switch(); 448 cpu_pause(); 449 } 450 #ifdef DELAYDEBUG 451 if (state == 1) 452 kprintf(" %d calls to getit() at %d usec each\n", 453 getit_calls, (n + 5) / getit_calls); 454 #endif 455 } 456 457 /* 458 * DELAY() never switches. 459 */ 460 void 461 DELAY(int n) 462 { 463 DODELAY(n, 0); 464 } 465 466 /* 467 * Returns non-zero if the specified time period has elapsed. Call 468 * first with last_clock set to 0. 469 */ 470 int 471 CHECKTIMEOUT(TOTALDELAY *tdd) 472 { 473 sysclock_t delta; 474 int us; 475 476 if (tdd->started == 0) { 477 if (timer0_state == RELEASED) 478 i8254_restore(); 479 tdd->last_clock = sys_cputimer->count(); 480 tdd->started = 1; 481 return(0); 482 } 483 delta = sys_cputimer->count() - tdd->last_clock; 484 us = (u_int64_t)delta * (u_int64_t)1000000 / 485 (u_int64_t)sys_cputimer->freq; 486 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq / 487 1000000; 488 tdd->us -= us; 489 return (tdd->us < 0); 490 } 491 492 493 /* 494 * DRIVERSLEEP() does not switch if called with a spinlock held or 495 * from a hard interrupt. 496 */ 497 void 498 DRIVERSLEEP(int usec) 499 { 500 globaldata_t gd = mycpu; 501 502 if (gd->gd_intr_nesting_level || gd->gd_spinlocks_wr) { 503 DODELAY(usec, 0); 504 } else { 505 DODELAY(usec, 1); 506 } 507 } 508 509 static void 510 sysbeepstop(void *chan) 511 { 512 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 513 beeping = 0; 514 release_timer2(); 515 } 516 517 int 518 sysbeep(int pitch, int period) 519 { 520 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 521 return(-1); 522 if (sysbeep_enable == 0) 523 return(-1); 524 /* 525 * Nobody else is using timer2, we do not need the clock lock 526 */ 527 outb(TIMER_CNTR2, pitch); 528 outb(TIMER_CNTR2, (pitch>>8)); 529 if (!beeping) { 530 /* enable counter2 output to speaker */ 531 outb(IO_PPI, inb(IO_PPI) | 3); 532 beeping = period; 533 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL); 534 } 535 return (0); 536 } 537 538 /* 539 * RTC support routines 540 */ 541 542 int 543 rtcin(int reg) 544 { 545 u_char val; 546 547 crit_enter(); 548 outb(IO_RTC, reg); 549 inb(0x84); 550 val = inb(IO_RTC + 1); 551 inb(0x84); 552 crit_exit(); 553 return (val); 554 } 555 556 static __inline void 557 writertc(u_char reg, u_char val) 558 { 559 crit_enter(); 560 inb(0x84); 561 outb(IO_RTC, reg); 562 inb(0x84); 563 outb(IO_RTC + 1, val); 564 inb(0x84); /* XXX work around wrong order in rtcin() */ 565 crit_exit(); 566 } 567 568 static __inline int 569 readrtc(int port) 570 { 571 return(bcd2bin(rtcin(port))); 572 } 573 574 static u_int 575 calibrate_clocks(void) 576 { 577 u_int64_t old_tsc; 578 u_int count, prev_count, tot_count; 579 int sec, start_sec, timeout; 580 581 if (bootverbose) 582 kprintf("Calibrating clock(s) ... "); 583 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 584 goto fail; 585 timeout = 100000000; 586 587 /* Read the mc146818A seconds counter. */ 588 for (;;) { 589 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 590 sec = rtcin(RTC_SEC); 591 break; 592 } 593 if (--timeout == 0) 594 goto fail; 595 } 596 597 /* Wait for the mC146818A seconds counter to change. */ 598 start_sec = sec; 599 for (;;) { 600 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 601 sec = rtcin(RTC_SEC); 602 if (sec != start_sec) 603 break; 604 } 605 if (--timeout == 0) 606 goto fail; 607 } 608 609 /* Start keeping track of the i8254 counter. */ 610 prev_count = sys_cputimer->count(); 611 tot_count = 0; 612 613 if (tsc_present) 614 old_tsc = rdtsc(); 615 else 616 old_tsc = 0; /* shut up gcc */ 617 618 /* 619 * Wait for the mc146818A seconds counter to change. Read the i8254 620 * counter for each iteration since this is convenient and only 621 * costs a few usec of inaccuracy. The timing of the final reads 622 * of the counters almost matches the timing of the initial reads, 623 * so the main cause of inaccuracy is the varying latency from 624 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 625 * rtcin(RTC_SEC) that returns a changed seconds count. The 626 * maximum inaccuracy from this cause is < 10 usec on 486's. 627 */ 628 start_sec = sec; 629 for (;;) { 630 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 631 sec = rtcin(RTC_SEC); 632 count = sys_cputimer->count(); 633 tot_count += (int)(count - prev_count); 634 prev_count = count; 635 if (sec != start_sec) 636 break; 637 if (--timeout == 0) 638 goto fail; 639 } 640 641 /* 642 * Read the cpu cycle counter. The timing considerations are 643 * similar to those for the i8254 clock. 644 */ 645 if (tsc_present) { 646 tsc_frequency = rdtsc() - old_tsc; 647 } 648 649 if (tsc_present) 650 kprintf("TSC clock: %llu Hz, ", (long long)tsc_frequency); 651 kprintf("i8254 clock: %u Hz\n", tot_count); 652 return (tot_count); 653 654 fail: 655 kprintf("failed, using default i8254 clock of %u Hz\n", 656 i8254_cputimer.freq); 657 return (i8254_cputimer.freq); 658 } 659 660 static void 661 i8254_restore(void) 662 { 663 timer0_state = ACQUIRED; 664 665 clock_lock(); 666 667 /* 668 * Timer0 is our fine-grained variable clock interrupt 669 */ 670 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 671 outb(TIMER_CNTR0, 2); /* lsb */ 672 outb(TIMER_CNTR0, 0); /* msb */ 673 clock_unlock(); 674 675 if (!i8254_nointr) { 676 cputimer_intr_register(&i8254_cputimer_intr); 677 cputimer_intr_select(&i8254_cputimer_intr, 0); 678 } 679 680 /* 681 * Timer1 or timer2 is our free-running clock, but only if another 682 * has not been selected. 683 */ 684 cputimer_register(&i8254_cputimer); 685 cputimer_select(&i8254_cputimer, 0); 686 } 687 688 static void 689 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock) 690 { 691 int which; 692 693 /* 694 * Should we use timer 1 or timer 2 ? 695 */ 696 which = 0; 697 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which); 698 if (which != 1 && which != 2) 699 which = 2; 700 701 switch(which) { 702 case 1: 703 timer->name = "i8254_timer1"; 704 timer->type = CPUTIMER_8254_SEL1; 705 i8254_walltimer_sel = TIMER_SEL1; 706 i8254_walltimer_cntr = TIMER_CNTR1; 707 timer1_state = ACQUIRED; 708 break; 709 case 2: 710 timer->name = "i8254_timer2"; 711 timer->type = CPUTIMER_8254_SEL2; 712 i8254_walltimer_sel = TIMER_SEL2; 713 i8254_walltimer_cntr = TIMER_CNTR2; 714 timer2_state = ACQUIRED; 715 break; 716 } 717 718 timer->base = (oldclock + 0xFFFF) & ~0xFFFF; 719 720 clock_lock(); 721 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT); 722 outb(i8254_walltimer_cntr, 0); /* lsb */ 723 outb(i8254_walltimer_cntr, 0); /* msb */ 724 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */ 725 clock_unlock(); 726 } 727 728 static void 729 i8254_cputimer_destruct(struct cputimer *timer) 730 { 731 switch(timer->type) { 732 case CPUTIMER_8254_SEL1: 733 timer1_state = RELEASED; 734 break; 735 case CPUTIMER_8254_SEL2: 736 timer2_state = RELEASED; 737 break; 738 default: 739 break; 740 } 741 timer->type = 0; 742 } 743 744 static void 745 rtc_restore(void) 746 { 747 /* Restore all of the RTC's "status" (actually, control) registers. */ 748 writertc(RTC_STATUSB, RTCSB_24HR); 749 writertc(RTC_STATUSA, rtc_statusa); 750 writertc(RTC_STATUSB, rtc_statusb); 751 } 752 753 /* 754 * Restore all the timers. 755 * 756 * This function is called to resynchronize our core timekeeping after a 757 * long halt, e.g. from apm_default_resume() and friends. It is also 758 * called if after a BIOS call we have detected munging of the 8254. 759 * It is necessary because cputimer_count() counter's delta may have grown 760 * too large for nanouptime() and friends to handle, or (in the case of 8254 761 * munging) might cause the SYSTIMER code to prematurely trigger. 762 */ 763 void 764 timer_restore(void) 765 { 766 crit_enter(); 767 i8254_restore(); /* restore timer_freq and hz */ 768 rtc_restore(); /* reenable RTC interrupts */ 769 crit_exit(); 770 } 771 772 /* 773 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 774 */ 775 void 776 startrtclock(void) 777 { 778 u_int delta, freq; 779 780 /* 781 * Can we use the TSC? 782 */ 783 if (cpu_feature & CPUID_TSC) 784 tsc_present = 1; 785 else 786 tsc_present = 0; 787 788 /* 789 * Initial RTC state, don't do anything unexpected 790 */ 791 writertc(RTC_STATUSA, rtc_statusa); 792 writertc(RTC_STATUSB, RTCSB_24HR); 793 794 /* 795 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to 796 * generate an interrupt, which we will ignore for now. 797 * 798 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000 799 * (so it counts a full 2^16 and repeats). We will use this timer 800 * for our counting. 801 */ 802 i8254_restore(); 803 freq = calibrate_clocks(); 804 #ifdef CLK_CALIBRATION_LOOP 805 if (bootverbose) { 806 kprintf( 807 "Press a key on the console to abort clock calibration\n"); 808 while (cncheckc() == -1) 809 calibrate_clocks(); 810 } 811 #endif 812 813 /* 814 * Use the calibrated i8254 frequency if it seems reasonable. 815 * Otherwise use the default, and don't use the calibrated i586 816 * frequency. 817 */ 818 delta = freq > i8254_cputimer.freq ? 819 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq; 820 if (delta < i8254_cputimer.freq / 100) { 821 #ifndef CLK_USE_I8254_CALIBRATION 822 if (bootverbose) 823 kprintf( 824 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 825 freq = i8254_cputimer.freq; 826 #endif 827 /* 828 * NOTE: 829 * Interrupt timer's freq must be adjusted 830 * before we change the cuptimer's frequency. 831 */ 832 i8254_cputimer_intr.freq = freq; 833 cputimer_set_frequency(&i8254_cputimer, freq); 834 } else { 835 if (bootverbose) 836 kprintf( 837 "%d Hz differs from default of %d Hz by more than 1%%\n", 838 freq, i8254_cputimer.freq); 839 tsc_frequency = 0; 840 } 841 842 #ifndef CLK_USE_TSC_CALIBRATION 843 if (tsc_frequency != 0) { 844 if (bootverbose) 845 kprintf( 846 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 847 tsc_frequency = 0; 848 } 849 #endif 850 if (tsc_present && tsc_frequency == 0) { 851 /* 852 * Calibration of the i586 clock relative to the mc146818A 853 * clock failed. Do a less accurate calibration relative 854 * to the i8254 clock. 855 */ 856 u_int64_t old_tsc = rdtsc(); 857 858 DELAY(1000000); 859 tsc_frequency = rdtsc() - old_tsc; 860 #ifdef CLK_USE_TSC_CALIBRATION 861 if (bootverbose) { 862 kprintf("TSC clock: %llu Hz (Method B)\n", 863 tsc_frequency); 864 } 865 #endif 866 } 867 868 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST); 869 870 #if !defined(SMP) 871 /* 872 * We can not use the TSC in SMP mode, until we figure out a 873 * cheap (impossible), reliable and precise (yeah right!) way 874 * to synchronize the TSCs of all the CPUs. 875 * Curse Intel for leaving the counter out of the I/O APIC. 876 */ 877 878 #if NAPM > 0 879 /* 880 * We can not use the TSC if we support APM. Precise timekeeping 881 * on an APM'ed machine is at best a fools pursuit, since 882 * any and all of the time spent in various SMM code can't 883 * be reliably accounted for. Reading the RTC is your only 884 * source of reliable time info. The i8254 looses too of course 885 * but we need to have some kind of time... 886 * We don't know at this point whether APM is going to be used 887 * or not, nor when it might be activated. Play it safe. 888 */ 889 return; 890 #endif /* NAPM > 0 */ 891 892 #endif /* !defined(SMP) */ 893 } 894 895 /* 896 * Sync the time of day back to the RTC on shutdown, but only if 897 * we have already loaded it and have not crashed. 898 */ 899 static void 900 resettodr_on_shutdown(void *arg __unused) 901 { 902 if (rtc_loaded && panicstr == NULL) { 903 resettodr(); 904 } 905 } 906 907 /* 908 * Initialize the time of day register, based on the time base which is, e.g. 909 * from a filesystem. 910 */ 911 void 912 inittodr(time_t base) 913 { 914 unsigned long sec, days; 915 int year, month; 916 int y, m; 917 struct timespec ts; 918 919 if (base) { 920 ts.tv_sec = base; 921 ts.tv_nsec = 0; 922 set_timeofday(&ts); 923 } 924 925 /* Look if we have a RTC present and the time is valid */ 926 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 927 goto wrong_time; 928 929 /* wait for time update to complete */ 930 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 931 crit_enter(); 932 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 933 crit_exit(); 934 crit_enter(); 935 } 936 937 days = 0; 938 #ifdef USE_RTC_CENTURY 939 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 940 #else 941 year = readrtc(RTC_YEAR) + 1900; 942 if (year < 1970) 943 year += 100; 944 #endif 945 if (year < 1970) { 946 crit_exit(); 947 goto wrong_time; 948 } 949 month = readrtc(RTC_MONTH); 950 for (m = 1; m < month; m++) 951 days += daysinmonth[m-1]; 952 if ((month > 2) && LEAPYEAR(year)) 953 days ++; 954 days += readrtc(RTC_DAY) - 1; 955 for (y = 1970; y < year; y++) 956 days += DAYSPERYEAR + LEAPYEAR(y); 957 sec = ((( days * 24 + 958 readrtc(RTC_HRS)) * 60 + 959 readrtc(RTC_MIN)) * 60 + 960 readrtc(RTC_SEC)); 961 /* sec now contains the number of seconds, since Jan 1 1970, 962 in the local time zone */ 963 964 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 965 966 y = time_second - sec; 967 if (y <= -2 || y >= 2) { 968 /* badly off, adjust it */ 969 ts.tv_sec = sec; 970 ts.tv_nsec = 0; 971 set_timeofday(&ts); 972 } 973 rtc_loaded = 1; 974 crit_exit(); 975 return; 976 977 wrong_time: 978 kprintf("Invalid time in real time clock.\n"); 979 kprintf("Check and reset the date immediately!\n"); 980 } 981 982 /* 983 * Write system time back to RTC 984 */ 985 void 986 resettodr(void) 987 { 988 struct timeval tv; 989 unsigned long tm; 990 int m; 991 int y; 992 993 if (disable_rtc_set) 994 return; 995 996 microtime(&tv); 997 tm = tv.tv_sec; 998 999 crit_enter(); 1000 /* Disable RTC updates and interrupts. */ 1001 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1002 1003 /* Calculate local time to put in RTC */ 1004 1005 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1006 1007 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1008 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1009 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1010 1011 /* We have now the days since 01-01-1970 in tm */ 1012 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1013 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1014 tm >= m; 1015 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1016 tm -= m; 1017 1018 /* Now we have the years in y and the day-of-the-year in tm */ 1019 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1020 #ifdef USE_RTC_CENTURY 1021 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1022 #endif 1023 for (m = 0; ; m++) { 1024 int ml; 1025 1026 ml = daysinmonth[m]; 1027 if (m == 1 && LEAPYEAR(y)) 1028 ml++; 1029 if (tm < ml) 1030 break; 1031 tm -= ml; 1032 } 1033 1034 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1035 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1036 1037 /* Reenable RTC updates and interrupts. */ 1038 writertc(RTC_STATUSB, rtc_statusb); 1039 crit_exit(); 1040 } 1041 1042 1043 /* 1044 * Start both clocks running. DragonFly note: the stat clock is no longer 1045 * used. Instead, 8254 based systimers are used for all major clock 1046 * interrupts. statclock_disable is set by default. 1047 */ 1048 static void 1049 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected) 1050 { 1051 int diag; 1052 #ifdef SMP /* APIC-IO */ 1053 int apic_8254_trial = 0; 1054 void *clkdesc = NULL; 1055 #endif 1056 1057 callout_init(&sysbeepstop_ch); 1058 1059 if (!selected && i8254_intr_disable) { 1060 i8254_nointr = 1; /* don't try to register again */ 1061 cputimer_intr_deregister(cti); 1062 return; 1063 } 1064 1065 if (statclock_disable) { 1066 /* 1067 * The stat interrupt mask is different without the 1068 * statistics clock. Also, don't set the interrupt 1069 * flag which would normally cause the RTC to generate 1070 * interrupts. 1071 */ 1072 rtc_statusb = RTCSB_24HR; 1073 } else { 1074 /* Setting stathz to nonzero early helps avoid races. */ 1075 stathz = RTC_NOPROFRATE; 1076 profhz = RTC_PROFRATE; 1077 } 1078 1079 /* Finish initializing 8253 timer 0. */ 1080 #ifdef SMP /* APIC-IO */ 1081 if (apic_io_enable) { 1082 apic_8254_intr = isa_apic_irq(0); 1083 if (apic_8254_intr >= 0 ) { 1084 if (apic_int_type(0, 0) == 3) 1085 apic_8254_trial = 1; 1086 } else { 1087 /* look for ExtInt on pin 0 */ 1088 if (apic_int_type(0, 0) == 3) { 1089 apic_8254_intr = apic_irq(0, 0); 1090 setup_8254_mixed_mode(); 1091 } else 1092 panic("APIC_IO: Cannot route 8254 interrupt to CPU"); 1093 } 1094 1095 clkdesc = register_int(apic_8254_intr, clkintr, NULL, "clk", 1096 NULL, 1097 INTR_EXCL | INTR_CLOCK | 1098 INTR_NOPOLL | INTR_MPSAFE | 1099 INTR_NOENTROPY); 1100 machintr_intren(apic_8254_intr); 1101 } else { 1102 #endif 1103 register_int(0, clkintr, NULL, "clk", NULL, 1104 INTR_EXCL | INTR_CLOCK | 1105 INTR_NOPOLL | INTR_MPSAFE | 1106 INTR_NOENTROPY); 1107 machintr_intren(ICU_IRQ0); 1108 #ifdef SMP /* APIC-IO */ 1109 } 1110 #endif 1111 1112 /* Initialize RTC. */ 1113 writertc(RTC_STATUSA, rtc_statusa); 1114 writertc(RTC_STATUSB, RTCSB_24HR); 1115 1116 if (statclock_disable == 0) { 1117 diag = rtcin(RTC_DIAG); 1118 if (diag != 0) 1119 kprintf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1120 1121 #ifdef SMP /* APIC-IO */ 1122 if (apic_io_enable) { 1123 if (isa_apic_irq(8) != 8) 1124 panic("APIC RTC != 8"); 1125 } 1126 #endif 1127 1128 register_int(8, (inthand2_t *)rtcintr, NULL, "rtc", NULL, 1129 INTR_EXCL | INTR_CLOCK | INTR_NOPOLL | 1130 INTR_NOENTROPY); 1131 machintr_intren(8); 1132 1133 writertc(RTC_STATUSB, rtc_statusb); 1134 } 1135 1136 #ifdef SMP /* APIC-IO */ 1137 if (apic_io_enable) { 1138 if (apic_8254_trial) { 1139 sysclock_t base; 1140 long lastcnt; 1141 1142 /* 1143 * Following code assumes the 8254 is the cpu timer, 1144 * so make sure it is. 1145 */ 1146 KKASSERT(sys_cputimer == &i8254_cputimer); 1147 KKASSERT(cti == &i8254_cputimer_intr); 1148 1149 lastcnt = get_interrupt_counter(apic_8254_intr); 1150 1151 /* 1152 * Force an 8254 Timer0 interrupt and wait 1/100s for 1153 * it to happen, then see if we got it. 1154 */ 1155 kprintf("APIC_IO: Testing 8254 interrupt delivery\n"); 1156 i8254_intr_reload(cti, 2); 1157 base = sys_cputimer->count(); 1158 while (sys_cputimer->count() - base < sys_cputimer->freq / 100) 1159 ; /* nothing */ 1160 if (get_interrupt_counter(apic_8254_intr) - lastcnt == 0) { 1161 /* 1162 * The MP table is broken. 1163 * The 8254 was not connected to the specified pin 1164 * on the IO APIC. 1165 * Workaround: Limited variant of mixed mode. 1166 */ 1167 machintr_intrdis(apic_8254_intr); 1168 unregister_int(clkdesc); 1169 kprintf("APIC_IO: Broken MP table detected: " 1170 "8254 is not connected to " 1171 "IOAPIC #%d intpin %d\n", 1172 int_to_apicintpin[apic_8254_intr].ioapic, 1173 int_to_apicintpin[apic_8254_intr].int_pin); 1174 /* 1175 * Revoke current ISA IRQ 0 assignment and 1176 * configure a fallback interrupt routing from 1177 * the 8254 Timer via the 8259 PIC to the 1178 * an ExtInt interrupt line on IOAPIC #0 intpin 0. 1179 * We reuse the low level interrupt handler number. 1180 */ 1181 if (apic_irq(0, 0) < 0) { 1182 revoke_apic_irq(apic_8254_intr); 1183 assign_apic_irq(0, 0, apic_8254_intr); 1184 } 1185 apic_8254_intr = apic_irq(0, 0); 1186 setup_8254_mixed_mode(); 1187 register_int(apic_8254_intr, clkintr, NULL, "clk", 1188 NULL, 1189 INTR_EXCL | INTR_CLOCK | 1190 INTR_NOPOLL | INTR_MPSAFE | 1191 INTR_NOENTROPY); 1192 machintr_intren(apic_8254_intr); 1193 } 1194 } 1195 if (apic_int_type(0, 0) != 3 || 1196 int_to_apicintpin[apic_8254_intr].ioapic != 0 || 1197 int_to_apicintpin[apic_8254_intr].int_pin != 0) { 1198 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n", 1199 int_to_apicintpin[apic_8254_intr].ioapic, 1200 int_to_apicintpin[apic_8254_intr].int_pin); 1201 } else { 1202 kprintf("APIC_IO: " 1203 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n"); 1204 } 1205 } 1206 #endif 1207 } 1208 1209 #ifdef SMP /* APIC-IO */ 1210 1211 static void 1212 setup_8254_mixed_mode(void) 1213 { 1214 /* 1215 * Allow 8254 timer to INTerrupt 8259: 1216 * re-initialize master 8259: 1217 * reset; prog 4 bytes, single ICU, edge triggered 1218 */ 1219 outb(IO_ICU1, 0x13); 1220 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */ 1221 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1222 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1223 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1224 1225 /* program IO APIC for type 3 INT on INT0 */ 1226 if (ext_int_setup(0, 0) < 0) 1227 panic("8254 redirect via APIC pin0 impossible!"); 1228 } 1229 #endif 1230 1231 void 1232 setstatclockrate(int newhz) 1233 { 1234 if (newhz == RTC_PROFRATE) 1235 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1236 else 1237 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1238 writertc(RTC_STATUSA, rtc_statusa); 1239 } 1240 1241 #if 0 1242 static unsigned 1243 tsc_get_timecount(struct timecounter *tc) 1244 { 1245 return (rdtsc()); 1246 } 1247 #endif 1248 1249 #ifdef KERN_TIMESTAMP 1250 #define KERN_TIMESTAMP_SIZE 16384 1251 static u_long tsc[KERN_TIMESTAMP_SIZE] ; 1252 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc, 1253 sizeof(tsc), "LU", "Kernel timestamps"); 1254 void 1255 _TSTMP(u_int32_t x) 1256 { 1257 static int i; 1258 1259 tsc[i] = (u_int32_t)rdtsc(); 1260 tsc[i+1] = x; 1261 i = i + 2; 1262 if (i >= KERN_TIMESTAMP_SIZE) 1263 i = 0; 1264 tsc[i] = 0; /* mark last entry */ 1265 } 1266 #endif /* KERN_TIMESTAMP */ 1267 1268 /* 1269 * 1270 */ 1271 1272 static int 1273 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS) 1274 { 1275 sysclock_t count; 1276 __uint64_t tscval; 1277 char buf[32]; 1278 1279 crit_enter(); 1280 if (sys_cputimer == &i8254_cputimer) 1281 count = sys_cputimer->count(); 1282 else 1283 count = 0; 1284 if (tsc_present) 1285 tscval = rdtsc(); 1286 else 1287 tscval = 0; 1288 crit_exit(); 1289 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval); 1290 return(SYSCTL_OUT(req, buf, strlen(buf) + 1)); 1291 } 1292 1293 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254"); 1294 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0, 1295 "frequency"); 1296 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD, 1297 0, 0, hw_i8254_timestamp, "A", ""); 1298 1299 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD, 1300 &tsc_present, 0, "TSC Available"); 1301 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD, 1302 &tsc_frequency, 0, "TSC Frequency"); 1303 1304