1/*- 2 * Copyright (c) 1989, 1990 William F. Jolitz. 3 * Copyright (c) 1990 The Regents of the University of California. 4 * Copyright (c) 2007 The FreeBSD Foundation 5 * Copyright (c) 2008 The DragonFly Project. 6 * Copyright (c) 2008 Jordan Gordeev. 7 * All rights reserved. 8 * 9 * Portions of this software were developed by A. Joseph Koshy under 10 * sponsorship from the FreeBSD Foundation and Google, Inc. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37#if JG 38#include "opt_atpic.h" 39#endif 40#include "opt_compat.h" 41 42#include <machine/asmacros.h> 43#include <machine/psl.h> 44#include <machine/trap.h> 45#include <machine/segments.h> 46 47#include "assym.s" 48 49 .text 50 51/*****************************************************************************/ 52/* Trap handling */ 53/*****************************************************************************/ 54/* 55 * Trap and fault vector routines. 56 * 57 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes 58 * state on the stack but also disables interrupts. This is important for 59 * us for the use of the swapgs instruction. We cannot be interrupted 60 * until the GS.base value is correct. For most traps, we automatically 61 * then enable interrupts if the interrupted context had them enabled. 62 * This is equivalent to the i386 port's use of SDT_SYS386TGT. 63 * 64 * The cpu will push a certain amount of state onto the kernel stack for 65 * the current process. See x86_64/include/frame.h. 66 * This includes the current RFLAGS (status register, which includes 67 * the interrupt disable state prior to the trap), the code segment register, 68 * and the return instruction pointer are pushed by the cpu. The cpu 69 * will also push an 'error' code for certain traps. We push a dummy 70 * error code for those traps where the cpu doesn't in order to maintain 71 * a consistent frame. We also push a contrived 'trap number'. 72 * 73 * The cpu does not push the general registers, we must do that, and we 74 * must restore them prior to calling 'iret'. The cpu adjusts the %cs and 75 * %ss segment registers, but does not mess with %ds, %es, or %fs. Thus we 76 * must load them with appropriate values for supervisor mode operation. 77 */ 78 79MCOUNT_LABEL(user) 80MCOUNT_LABEL(btrap) 81 82/* Traps that we leave interrupts disabled for.. */ 83#define TRAP_NOEN(a) \ 84 subq $TF_RIP,%rsp; \ 85 movq $0,TF_XFLAGS(%rsp) ; \ 86 movq $(a),TF_TRAPNO(%rsp) ; \ 87 movq $0,TF_ADDR(%rsp) ; \ 88 movq $0,TF_ERR(%rsp) ; \ 89 jmp alltraps_noen 90IDTVEC(dbg) 91 TRAP_NOEN(T_TRCTRAP) 92IDTVEC(bpt) 93 TRAP_NOEN(T_BPTFLT) 94 95/* Regular traps; The cpu does not supply tf_err for these. */ 96#define TRAP(a) \ 97 subq $TF_RIP,%rsp; \ 98 movq $0,TF_XFLAGS(%rsp) ; \ 99 movq $(a),TF_TRAPNO(%rsp) ; \ 100 movq $0,TF_ADDR(%rsp) ; \ 101 movq $0,TF_ERR(%rsp) ; \ 102 jmp alltraps 103IDTVEC(div) 104 TRAP(T_DIVIDE) 105IDTVEC(ofl) 106 TRAP(T_OFLOW) 107IDTVEC(bnd) 108 TRAP(T_BOUND) 109IDTVEC(ill) 110 TRAP(T_PRIVINFLT) 111IDTVEC(dna) 112 TRAP(T_DNA) 113IDTVEC(fpusegm) 114 TRAP(T_FPOPFLT) 115IDTVEC(mchk) 116 TRAP(T_MCHK) 117IDTVEC(rsvd) 118 TRAP(T_RESERVED) 119IDTVEC(fpu) 120 TRAP(T_ARITHTRAP) 121IDTVEC(xmm) 122 TRAP(T_XMMFLT) 123 124/* This group of traps have tf_err already pushed by the cpu */ 125#define TRAP_ERR(a) \ 126 subq $TF_ERR,%rsp; \ 127 movq $(a),TF_TRAPNO(%rsp) ; \ 128 movq $0,TF_ADDR(%rsp) ; \ 129 movq $0,TF_XFLAGS(%rsp) ; \ 130 jmp alltraps 131IDTVEC(tss) 132 TRAP_ERR(T_TSSFLT) 133IDTVEC(missing) 134 TRAP_ERR(T_SEGNPFLT) 135IDTVEC(stk) 136 TRAP_ERR(T_STKFLT) 137IDTVEC(align) 138 TRAP_ERR(T_ALIGNFLT) 139 140 /* 141 * alltraps entry point. Use swapgs if this is the first time in the 142 * kernel from userland. Reenable interrupts if they were enabled 143 * before the trap. This approximates SDT_SYS386TGT on the i386 port. 144 */ 145 146 SUPERALIGN_TEXT 147 .globl alltraps 148 .type alltraps,@function 149alltraps: 150 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 151 jz alltraps_testi /* already running with kernel GS.base */ 152 swapgs 153alltraps_testi: 154 testq $PSL_I,TF_RFLAGS(%rsp) 155 jz alltraps_pushregs 156 sti 157alltraps_pushregs: 158 movq %rdi,TF_RDI(%rsp) 159alltraps_pushregs_no_rdi: 160 movq %rsi,TF_RSI(%rsp) 161 movq %rdx,TF_RDX(%rsp) 162 movq %rcx,TF_RCX(%rsp) 163 movq %r8,TF_R8(%rsp) 164 movq %r9,TF_R9(%rsp) 165 movq %rax,TF_RAX(%rsp) 166 movq %rbx,TF_RBX(%rsp) 167 movq %rbp,TF_RBP(%rsp) 168 movq %r10,TF_R10(%rsp) 169 movq %r11,TF_R11(%rsp) 170 movq %r12,TF_R12(%rsp) 171 movq %r13,TF_R13(%rsp) 172 movq %r14,TF_R14(%rsp) 173 movq %r15,TF_R15(%rsp) 174 FAKE_MCOUNT(TF_RIP(%rsp)) 175 .globl calltrap 176 .type calltrap,@function 177calltrap: 178 movq %rsp, %rdi 179 call trap 180 MEXITCOUNT 181 jmp doreti /* Handle any pending ASTs */ 182 183 /* 184 * alltraps_noen entry point. Unlike alltraps above, we want to 185 * leave the interrupts disabled. This corresponds to 186 * SDT_SYS386IGT on the i386 port. 187 */ 188 SUPERALIGN_TEXT 189 .globl alltraps_noen 190 .type alltraps_noen,@function 191alltraps_noen: 192 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 193 jz alltraps_pushregs /* already running with kernel GS.base */ 194 swapgs 195 jmp alltraps_pushregs 196 197IDTVEC(dblfault) 198 subq $TF_ERR,%rsp 199 movq $T_DOUBLEFLT,TF_TRAPNO(%rsp) 200 movq $0,TF_ADDR(%rsp) 201 movq $0,TF_ERR(%rsp) 202 movq $0,TF_XFLAGS(%rsp) 203 movq %rdi,TF_RDI(%rsp) 204 movq %rsi,TF_RSI(%rsp) 205 movq %rdx,TF_RDX(%rsp) 206 movq %rcx,TF_RCX(%rsp) 207 movq %r8,TF_R8(%rsp) 208 movq %r9,TF_R9(%rsp) 209 movq %rax,TF_RAX(%rsp) 210 movq %rbx,TF_RBX(%rsp) 211 movq %rbp,TF_RBP(%rsp) 212 movq %r10,TF_R10(%rsp) 213 movq %r11,TF_R11(%rsp) 214 movq %r12,TF_R12(%rsp) 215 movq %r13,TF_R13(%rsp) 216 movq %r14,TF_R14(%rsp) 217 movq %r15,TF_R15(%rsp) 218 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 219 jz 1f /* already running with kernel GS.base */ 220 swapgs 2211: movq %rsp, %rdi 222 call dblfault_handler 2232: hlt 224 jmp 2b 225 226IDTVEC(page) 227 subq $TF_ERR,%rsp 228 movq $T_PAGEFLT,TF_TRAPNO(%rsp) 229 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 230 jz 1f /* already running with kernel GS.base */ 231 swapgs 2321: 233 movq %rdi,TF_RDI(%rsp) /* free up a GP register */ 234 movq %cr2,%rdi /* preserve %cr2 before .. */ 235 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */ 236 movq $0,TF_XFLAGS(%rsp) 237 testq $PSL_I,TF_RFLAGS(%rsp) 238 jz alltraps_pushregs_no_rdi 239 sti 240 jmp alltraps_pushregs_no_rdi 241 242 /* 243 * We have to special-case this one. If we get a trap in doreti() at 244 * the iretq stage, we'll reenter with the wrong gs state. We'll have 245 * to do a special the swapgs in this case even coming from the kernel. 246 * XXX linux has a trap handler for their equivalent of load_gs(). 247 */ 248IDTVEC(prot) 249 subq $TF_ERR,%rsp 250 movq $T_PROTFLT,TF_TRAPNO(%rsp) 251 movq $0,TF_ADDR(%rsp) 252 movq $0,TF_XFLAGS(%rsp) 253 movq %rdi,TF_RDI(%rsp) /* free up a GP register */ 254 leaq doreti_iret(%rip),%rdi 255 cmpq %rdi,TF_RIP(%rsp) 256 je 2f /* kernel but with user gsbase!! */ 257 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 258 jz 1f /* already running with kernel GS.base */ 2592: 260 swapgs 2611: 262 testq $PSL_I,TF_RFLAGS(%rsp) 263 jz alltraps_pushregs_no_rdi 264 sti 265 jmp alltraps_pushregs_no_rdi 266 267/* 268 * Fast syscall entry point. We enter here with just our new %cs/%ss set, 269 * and the new privilige level. We are still running on the old user stack 270 * pointer. We have to juggle a few things around to find our stack etc. 271 * swapgs gives us access to our PCPU space only. 272 */ 273IDTVEC(fast_syscall) 274 swapgs 275 movq %rsp,PCPU(scratch_rsp) 276 movq PCPU(rsp0),%rsp 277 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */ 278 subq $TF_SIZE,%rsp 279 /* defer TF_RSP till we have a spare register */ 280 movq %r11,TF_RFLAGS(%rsp) 281 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */ 282 movq PCPU(scratch_rsp),%r11 /* %r11 already saved */ 283 movq %r11,TF_RSP(%rsp) /* user stack pointer */ 284 sti 285 movq $KUDSEL,TF_SS(%rsp) 286 movq $KUCSEL,TF_CS(%rsp) 287 movq $2,TF_ERR(%rsp) 288 movq $T_FAST_SYSCALL,TF_TRAPNO(%rsp) /* for the vkernel */ 289 movq $0,TF_XFLAGS(%rsp) /* note: used in signal frame */ 290 movq %rdi,TF_RDI(%rsp) /* arg 1 */ 291 movq %rsi,TF_RSI(%rsp) /* arg 2 */ 292 movq %rdx,TF_RDX(%rsp) /* arg 3 */ 293 movq %r10,TF_RCX(%rsp) /* arg 4 */ 294 movq %r8,TF_R8(%rsp) /* arg 5 */ 295 movq %r9,TF_R9(%rsp) /* arg 6 */ 296 movq %rax,TF_RAX(%rsp) /* syscall number */ 297 movq %rbx,TF_RBX(%rsp) /* C preserved */ 298 movq %rbp,TF_RBP(%rsp) /* C preserved */ 299 movq %r12,TF_R12(%rsp) /* C preserved */ 300 movq %r13,TF_R13(%rsp) /* C preserved */ 301 movq %r14,TF_R14(%rsp) /* C preserved */ 302 movq %r15,TF_R15(%rsp) /* C preserved */ 303 FAKE_MCOUNT(TF_RIP(%rsp)) 304 movq %rsp, %rdi 305 call syscall2 306 MEXITCOUNT 307 jmp doreti 308 309/* 310 * Here for CYA insurance, in case a "syscall" instruction gets 311 * issued from 32 bit compatability mode. MSR_CSTAR has to point 312 * to *something* if EFER_SCE is enabled. 313 */ 314IDTVEC(fast_syscall32) 315 sysret 316 317/* 318 * NMI handling is special. 319 * 320 * First, NMIs do not respect the state of the processor's RFLAGS.IF 321 * bit and the NMI handler may be invoked at any time, including when 322 * the processor is in a critical section with RFLAGS.IF == 0. In 323 * particular, this means that the processor's GS.base values could be 324 * inconsistent on entry to the handler, and so we need to read 325 * MSR_GSBASE to determine if a 'swapgs' is needed. We use '%ebx', a 326 * C-preserved register, to remember whether to swap GS back on the 327 * exit path. 328 * 329 * Second, the processor treats NMIs specially, blocking further NMIs 330 * until an 'iretq' instruction is executed. We therefore need to 331 * execute the NMI handler with interrupts disabled to prevent a 332 * nested interrupt from executing an 'iretq' instruction and 333 * inadvertently taking the processor out of NMI mode. 334 * 335 * Third, the NMI handler runs on its own stack (tss_ist1), shared 336 * with the double fault handler. 337 */ 338 339IDTVEC(nmi) 340 subq $TF_RIP,%rsp 341 movq $(T_NMI),TF_TRAPNO(%rsp) 342 movq $0,TF_ADDR(%rsp) 343 movq $0,TF_ERR(%rsp) 344 movq $0,TF_XFLAGS(%rsp) 345 movq %rdi,TF_RDI(%rsp) 346 movq %rsi,TF_RSI(%rsp) 347 movq %rdx,TF_RDX(%rsp) 348 movq %rcx,TF_RCX(%rsp) 349 movq %r8,TF_R8(%rsp) 350 movq %r9,TF_R9(%rsp) 351 movq %rax,TF_RAX(%rsp) 352 movq %rbx,TF_RBX(%rsp) 353 movq %rbp,TF_RBP(%rsp) 354 movq %r10,TF_R10(%rsp) 355 movq %r11,TF_R11(%rsp) 356 movq %r12,TF_R12(%rsp) 357 movq %r13,TF_R13(%rsp) 358 movq %r14,TF_R14(%rsp) 359 movq %r15,TF_R15(%rsp) 360 xorl %ebx,%ebx 361 testb $SEL_RPL_MASK,TF_CS(%rsp) 362 jnz nmi_needswapgs /* we came from userland */ 363 movl $MSR_GSBASE,%ecx 364 rdmsr 365 cmpl $VM_MAX_USER_ADDRESS >> 32,%edx 366 jae nmi_calltrap /* GS.base holds a kernel VA */ 367nmi_needswapgs: 368 incl %ebx 369 swapgs 370/* Note: this label is also used by ddb and gdb: */ 371nmi_calltrap: 372 FAKE_MCOUNT(TF_RIP(%rsp)) 373 movq %rsp, %rdi 374 call trap 375 MEXITCOUNT 376 testl %ebx,%ebx 377 jz nmi_restoreregs 378 swapgs 379nmi_restoreregs: 380 movq TF_RDI(%rsp),%rdi 381 movq TF_RSI(%rsp),%rsi 382 movq TF_RDX(%rsp),%rdx 383 movq TF_RCX(%rsp),%rcx 384 movq TF_R8(%rsp),%r8 385 movq TF_R9(%rsp),%r9 386 movq TF_RAX(%rsp),%rax 387 movq TF_RBX(%rsp),%rbx 388 movq TF_RBP(%rsp),%rbp 389 movq TF_R10(%rsp),%r10 390 movq TF_R11(%rsp),%r11 391 movq TF_R12(%rsp),%r12 392 movq TF_R13(%rsp),%r13 393 movq TF_R14(%rsp),%r14 394 movq TF_R15(%rsp),%r15 395 addq $TF_RIP,%rsp 396 iretq 397 398/* 399 * This function is what cpu_heavy_restore jumps to after a new process 400 * is created. The LWKT subsystem switches while holding a critical 401 * section and we maintain that abstraction here (e.g. because 402 * cpu_heavy_restore needs it due to PCB_*() manipulation), then get out of 403 * it before calling the initial function (typically fork_return()) and/or 404 * returning to user mode. 405 * 406 * The MP lock is held on entry, but for processes fork_return(esi) 407 * releases it. 'doreti' always runs without the MP lock. 408 */ 409ENTRY(fork_trampoline) 410 movq PCPU(curthread),%rax 411 subl $TDPRI_CRIT,TD_PRI(%rax) 412 413 /* 414 * cpu_set_fork_handler intercepts this function call to 415 * have this call a non-return function to stay in kernel mode. 416 * 417 * initproc has its own fork handler, start_init(), which DOES 418 * return. 419 * 420 * %rbx - chaining function (typically fork_return) 421 * %r12 -> %rdi (argument) 422 * frame-> %rsi (trap frame) 423 * 424 * void (func:rbx)(arg:rdi, trapframe:rsi) 425 */ 426 movq %rsp, %rsi /* pass trapframe by reference */ 427 movq %r12, %rdi /* arg1 */ 428 call *%rbx /* function */ 429 430 /* cut from syscall */ 431 432 sti 433 call splz 434 435#if defined(INVARIANTS) && defined(SMP) 436 movq PCPU(curthread),%rax 437 cmpl $0,TD_MPCOUNT(%rax) 438 je 1f 439 movq $pmsg4, %rdi 440 movl TD_MPCOUNT(%rax), %esi 441 movq %rbx, %rdx 442 xorl %eax, %eax 443 call panic 444pmsg4: .asciz "fork_trampoline mpcount %d after calling %p" 445 /* JG what's the purpose of this alignment and is it enough on x86_64? */ 446 .p2align 2 4471: 448#endif 449 /* 450 * Return via doreti to handle ASTs. 451 * 452 * trapframe is at the top of the stack. 453 */ 454 MEXITCOUNT 455 jmp doreti 456 457/* 458 * To efficiently implement classification of trap and interrupt handlers 459 * for profiling, there must be only trap handlers between the labels btrap 460 * and bintr, and only interrupt handlers between the labels bintr and 461 * eintr. This is implemented (partly) by including files that contain 462 * some of the handlers. Before including the files, set up a normal asm 463 * environment so that the included files doen't need to know that they are 464 * included. 465 */ 466 467#ifdef COMPAT_IA32 468 .data 469 .p2align 4 470 .text 471 SUPERALIGN_TEXT 472 473#include <x86_64/ia32/ia32_exception.S> 474#endif 475 476 .data 477 .p2align 4 478 .text 479 SUPERALIGN_TEXT 480MCOUNT_LABEL(bintr) 481 482#if JG 483#include <x86_64/x86_64/apic_vector.S> 484#endif 485 486#ifdef DEV_ATPIC 487 .data 488 .p2align 4 489 .text 490 SUPERALIGN_TEXT 491 492#include <x86_64/isa/atpic_vector.S> 493#endif 494 495 .text 496MCOUNT_LABEL(eintr) 497 498