1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * Copyright (c) 2008 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 40 */ 41 42 #include "opt_cpu.h" 43 44 #include <sys/param.h> 45 #include <sys/bus.h> 46 #include <sys/eventhandler.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/sysctl.h> 50 #include <sys/power.h> 51 52 #include <machine/asmacros.h> 53 #include <machine/clock.h> 54 #include <machine/cputypes.h> 55 #include <machine/frame.h> 56 #include <machine/segments.h> 57 #include <machine/specialreg.h> 58 #include <machine/md_var.h> 59 60 /* XXX - should be in header file: */ 61 void printcpuinfo(void); 62 void identify_cpu(void); 63 void earlysetcpuclass(void); 64 void panicifcpuunsupported(void); 65 66 static u_int find_cpu_vendor_id(void); 67 static void print_AMD_info(void); 68 static void print_AMD_assoc(int i); 69 static void print_via_padlock_info(void); 70 71 int cpu_class; 72 char machine[] = "x86_64"; 73 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 74 machine, 0, "Machine class"); 75 76 static char cpu_model[128]; 77 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 78 cpu_model, 0, "Machine model"); 79 80 static int hw_clockrate; 81 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 82 &hw_clockrate, 0, "CPU instruction clock rate"); 83 84 static char cpu_brand[48]; 85 86 static struct { 87 char *cpu_name; 88 int cpu_class; 89 } x86_64_cpus[] = { 90 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ 91 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ 92 }; 93 94 static struct { 95 char *vendor; 96 u_int vendor_id; 97 } cpu_vendors[] = { 98 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 99 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 100 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 101 }; 102 103 #ifdef foo 104 static int cpu_cores; 105 static int cpu_logical; 106 #endif 107 108 extern int pq_l2size; 109 extern int pq_l2nways; 110 111 void 112 printcpuinfo(void) 113 { 114 u_int regs[4], i; 115 char *brand; 116 117 cpu_class = x86_64_cpus[cpu].cpu_class; 118 kprintf("CPU: "); 119 strncpy(cpu_model, x86_64_cpus[cpu].cpu_name, sizeof (cpu_model)); 120 121 /* Check for extended CPUID information and a processor name. */ 122 if (cpu_exthigh >= 0x80000004) { 123 brand = cpu_brand; 124 for (i = 0x80000002; i < 0x80000005; i++) { 125 do_cpuid(i, regs); 126 memcpy(brand, regs, sizeof(regs)); 127 brand += sizeof(regs); 128 } 129 } 130 131 switch (cpu_vendor_id) { 132 case CPU_VENDOR_INTEL: 133 /* Please make up your mind folks! */ 134 strcat(cpu_model, "EM64T"); 135 break; 136 case CPU_VENDOR_AMD: 137 /* 138 * Values taken from AMD Processor Recognition 139 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 140 * (also describes ``Features'' encodings. 141 */ 142 strcpy(cpu_model, "AMD "); 143 if ((cpu_id & 0xf00) == 0xf00) 144 strcat(cpu_model, "AMD64 Processor"); 145 else 146 strcat(cpu_model, "Unknown"); 147 break; 148 case CPU_VENDOR_CENTAUR: 149 strcpy(cpu_model, "VIA "); 150 if ((cpu_id & 0xff0) == 0x6f0) 151 strcat(cpu_model, "Nano Processor"); 152 else 153 strcat(cpu_model, "Unknown"); 154 break; 155 default: 156 strcat(cpu_model, "Unknown"); 157 break; 158 } 159 160 /* 161 * Replace cpu_model with cpu_brand minus leading spaces if 162 * we have one. 163 */ 164 brand = cpu_brand; 165 while (*brand == ' ') 166 ++brand; 167 if (*brand != '\0') 168 strcpy(cpu_model, brand); 169 170 kprintf("%s (", cpu_model); 171 switch(cpu_class) { 172 case CPUCLASS_K8: 173 hw_clockrate = (tsc_frequency + 5000) / 1000000; 174 kprintf("%jd.%02d-MHz ", 175 (intmax_t)(tsc_frequency + 4999) / 1000000, 176 (u_int)((tsc_frequency + 4999) / 10000) % 100); 177 kprintf("K8"); 178 break; 179 default: 180 kprintf("Unknown"); /* will panic below... */ 181 } 182 kprintf("-class CPU)\n"); 183 if (*cpu_vendor) 184 kprintf(" Origin = \"%s\"", cpu_vendor); 185 if (cpu_id) 186 kprintf(" Id = 0x%x", cpu_id); 187 188 if (cpu_vendor_id == CPU_VENDOR_INTEL || 189 cpu_vendor_id == CPU_VENDOR_AMD || 190 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 191 kprintf(" Stepping = %u", cpu_id & 0xf); 192 if (cpu_high > 0) { 193 #if 0 194 u_int cmp = 1, htt = 1; 195 #endif 196 197 /* 198 * Here we should probably set up flags indicating 199 * whether or not various features are available. 200 * The interesting ones are probably VME, PSE, PAE, 201 * and PGE. The code already assumes without bothering 202 * to check that all CPUs >= Pentium have a TSC and 203 * MSRs. 204 */ 205 kprintf("\n Features=0x%b", cpu_feature, 206 "\020" 207 "\001FPU" /* Integral FPU */ 208 "\002VME" /* Extended VM86 mode support */ 209 "\003DE" /* Debugging Extensions (CR4.DE) */ 210 "\004PSE" /* 4MByte page tables */ 211 "\005TSC" /* Timestamp counter */ 212 "\006MSR" /* Machine specific registers */ 213 "\007PAE" /* Physical address extension */ 214 "\010MCE" /* Machine Check support */ 215 "\011CX8" /* CMPEXCH8 instruction */ 216 "\012APIC" /* SMP local APIC */ 217 "\013oldMTRR" /* Previous implementation of MTRR */ 218 "\014SEP" /* Fast System Call */ 219 "\015MTRR" /* Memory Type Range Registers */ 220 "\016PGE" /* PG_G (global bit) support */ 221 "\017MCA" /* Machine Check Architecture */ 222 "\020CMOV" /* CMOV instruction */ 223 "\021PAT" /* Page attributes table */ 224 "\022PSE36" /* 36 bit address space support */ 225 "\023PN" /* Processor Serial number */ 226 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 227 "\025<b20>" 228 "\026DTS" /* Debug Trace Store */ 229 "\027ACPI" /* ACPI support */ 230 "\030MMX" /* MMX instructions */ 231 "\031FXSR" /* FXSAVE/FXRSTOR */ 232 "\032SSE" /* Streaming SIMD Extensions */ 233 "\033SSE2" /* Streaming SIMD Extensions #2 */ 234 "\034SS" /* Self snoop */ 235 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 236 "\036TM" /* Thermal Monitor clock slowdown */ 237 "\037IA64" /* CPU can execute IA64 instructions */ 238 "\040PBE" /* Pending Break Enable */ 239 ); 240 241 if (cpu_feature2 != 0) { 242 kprintf("\n Features2=0x%b", cpu_feature2, 243 "\020" 244 "\001SSE3" /* SSE3 */ 245 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 246 "\003DTES64" /* 64-bit Debug Trace */ 247 "\004MON" /* MONITOR/MWAIT Instructions */ 248 "\005DS_CPL" /* CPL Qualified Debug Store */ 249 "\006VMX" /* Virtual Machine Extensions */ 250 "\007SMX" /* Safer Mode Extensions */ 251 "\010EST" /* Enhanced SpeedStep */ 252 "\011TM2" /* Thermal Monitor 2 */ 253 "\012SSSE3" /* SSSE3 */ 254 "\013CNXT-ID" /* L1 context ID available */ 255 "\014<b11>" 256 "\015FMA" /* Fused Multiply Add */ 257 "\016CX16" /* CMPXCHG16B Instruction */ 258 "\017xTPR" /* Send Task Priority Messages */ 259 "\020PDCM" /* Perf/Debug Capability MSR */ 260 "\021<b16>" 261 "\022PCID" /* Process-context Identifiers */ 262 "\023DCA" /* Direct Cache Access */ 263 "\024SSE4.1" /* SSE 4.1 */ 264 "\025SSE4.2" /* SSE 4.2 */ 265 "\026x2APIC" /* xAPIC Extensions */ 266 "\027MOVBE" /* MOVBE Instruction */ 267 "\030POPCNT" /* POPCNT Instruction */ 268 "\031TSCDLT" /* TSC-Deadline Timer */ 269 "\032AESNI" /* AES Crypto */ 270 "\033XSAVE" /* XSAVE/XRSTOR States */ 271 "\034OSXSAVE" /* OS-Enabled State Management */ 272 "\035AVX" /* Advanced Vector Extensions */ 273 "\036F16C" /* Half-precision conversions */ 274 "\037RDRND" /* RDRAND RNG function */ 275 "\040VMM" /* Running on a hypervisor */ 276 ); 277 } 278 279 /* 280 * AMD64 Architecture Programmer's Manual Volume 3: 281 * General-Purpose and System Instructions 282 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf 283 * 284 * IA-32 Intel Architecture Software Developer's Manual, 285 * Volume 2A: Instruction Set Reference, A-M 286 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf 287 */ 288 if (amd_feature != 0) { 289 kprintf("\n AMD Features=0x%b", amd_feature, 290 "\020" /* in hex */ 291 "\001<s0>" /* Same */ 292 "\002<s1>" /* Same */ 293 "\003<s2>" /* Same */ 294 "\004<s3>" /* Same */ 295 "\005<s4>" /* Same */ 296 "\006<s5>" /* Same */ 297 "\007<s6>" /* Same */ 298 "\010<s7>" /* Same */ 299 "\011<s8>" /* Same */ 300 "\012<s9>" /* Same */ 301 "\013<b10>" /* Undefined */ 302 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 303 "\015<s12>" /* Same */ 304 "\016<s13>" /* Same */ 305 "\017<s14>" /* Same */ 306 "\020<s15>" /* Same */ 307 "\021<s16>" /* Same */ 308 "\022<s17>" /* Same */ 309 "\023<b18>" /* Reserved, unknown */ 310 "\024MP" /* Multiprocessor Capable */ 311 "\025NX" /* Has EFER.NXE, NX */ 312 "\026<b21>" /* Undefined */ 313 "\027MMX+" /* AMD MMX Extensions */ 314 "\030<s23>" /* Same */ 315 "\031<s24>" /* Same */ 316 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 317 "\033Page1GB" /* 1-GB large page support */ 318 "\034RDTSCP" /* RDTSCP */ 319 "\035<b28>" /* Undefined */ 320 "\036LM" /* 64 bit long mode */ 321 "\0373DNow!+" /* AMD 3DNow! Extensions */ 322 "\0403DNow!" /* AMD 3DNow! */ 323 ); 324 } 325 326 if (amd_feature2 != 0) { 327 kprintf("\n AMD Features2=0x%b", amd_feature2, 328 "\020" 329 "\001LAHF" /* LAHF/SAHF in long mode */ 330 "\002CMP" /* CMP legacy */ 331 "\003SVM" /* Secure Virtual Mode */ 332 "\004ExtAPIC" /* Extended APIC register */ 333 "\005CR8" /* CR8 in legacy mode */ 334 "\006ABM" /* LZCNT instruction */ 335 "\007SSE4A" /* SSE4A */ 336 "\010MAS" /* Misaligned SSE mode */ 337 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 338 "\012OSVW" /* OS visible workaround */ 339 "\013IBS" /* Instruction based sampling */ 340 "\014XOP" /* XOP extended instructions */ 341 "\015SKINIT" /* SKINIT/STGI */ 342 "\016WDT" /* Watchdog timer */ 343 "\017<b14>" 344 "\020LWP" /* Lightweight Profiling */ 345 "\021FMA4" /* 4-operand FMA instructions */ 346 "\022TCE" /* Translation Cache Extension */ 347 "\023<b18>" 348 "\024NodeId" /* NodeId MSR support */ 349 "\025<b20>" 350 "\026TBM" /* Trailing Bit Manipulation */ 351 "\027Topology" /* Topology Extensions */ 352 "\030PCX_CORE" /* Core Performance Counter */ 353 "\031PCX_NB" /* NB Performance Counter */ 354 "\032<b25>" 355 "\033<b26>" 356 "\034<b27>" 357 "\035<b28>" 358 "\036<b29>" 359 "\037<b30>" 360 "\040<b31>" 361 ); 362 } 363 364 if (cpu_vendor_id == CPU_VENDOR_CENTAUR) 365 print_via_padlock_info(); 366 /* 367 * INVALID CPU TOPOLOGY INFORMATION PRINT 368 * DEPRECATED - CPU_TOPOLOGY_DETECTION moved to 369 * - sys/platform/pc64/x86_64/mp_machdep.c 370 * - sys/kern/subr_cpu_topology 371 */ 372 373 #if 0 374 if ((cpu_feature & CPUID_HTT) && 375 cpu_vendor_id == CPU_VENDOR_AMD) 376 cpu_feature &= ~CPUID_HTT; 377 #endif 378 379 /* 380 * If this CPU supports HTT or CMP then mention the 381 * number of physical/logical cores it contains. 382 */ 383 #if 0 384 if (cpu_feature & CPUID_HTT) 385 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 386 if (cpu_vendor_id == CPU_VENDOR_AMD && 387 (amd_feature2 & AMDID2_CMP)) 388 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 389 else if (cpu_vendor_id == CPU_VENDOR_INTEL && 390 (cpu_high >= 4)) { 391 cpuid_count(4, 0, regs); 392 if ((regs[0] & 0x1f) != 0) 393 cmp = ((regs[0] >> 26) & 0x3f) + 1; 394 } 395 #endif 396 #ifdef foo 397 /* 398 * XXX For Intel CPUs, this is max number of cores per 399 * package, not the actual cores per package. 400 */ 401 #if 0 402 cpu_cores = cmp; 403 cpu_logical = htt / cmp; 404 405 if (cpu_cores > 1) 406 kprintf("\n Cores per package: %d", cpu_cores); 407 if (cpu_logical > 1) { 408 kprintf("\n Logical CPUs per core: %d", 409 cpu_logical); 410 } 411 #endif 412 #endif 413 } 414 } 415 /* Avoid ugly blank lines: only print newline when we have to. */ 416 if (*cpu_vendor || cpu_id) 417 kprintf("\n"); 418 419 if (!bootverbose) 420 return; 421 422 if (cpu_vendor_id == CPU_VENDOR_AMD) 423 print_AMD_info(); 424 } 425 426 void 427 panicifcpuunsupported(void) 428 { 429 430 #ifndef HAMMER_CPU 431 #error "You need to specify a cpu type" 432 #endif 433 /* 434 * Now that we have told the user what they have, 435 * let them know if that machine type isn't configured. 436 */ 437 switch (cpu_class) { 438 case CPUCLASS_X86: 439 #ifndef HAMMER_CPU 440 case CPUCLASS_K8: 441 #endif 442 panic("CPU class not configured"); 443 default: 444 break; 445 } 446 } 447 448 449 #if JG 450 /* Update TSC freq with the value indicated by the caller. */ 451 static void 452 tsc_freq_changed(void *arg, const struct cf_level *level, int status) 453 { 454 /* If there was an error during the transition, don't do anything. */ 455 if (status != 0) 456 return; 457 458 /* Total setting for this level gives the new frequency in MHz. */ 459 hw_clockrate = level->total_set.freq; 460 } 461 462 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL, 463 EVENTHANDLER_PRI_ANY); 464 #endif 465 466 /* 467 * Final stage of CPU identification. 468 */ 469 void 470 identify_cpu(void) 471 { 472 u_int regs[4]; 473 474 do_cpuid(0, regs); 475 cpu_high = regs[0]; 476 ((u_int *)&cpu_vendor)[0] = regs[1]; 477 ((u_int *)&cpu_vendor)[1] = regs[3]; 478 ((u_int *)&cpu_vendor)[2] = regs[2]; 479 cpu_vendor[12] = '\0'; 480 cpu_vendor_id = find_cpu_vendor_id(); 481 482 do_cpuid(1, regs); 483 cpu_id = regs[0]; 484 cpu_procinfo = regs[1]; 485 cpu_feature = regs[3]; 486 cpu_feature2 = regs[2]; 487 488 if (cpu_vendor_id == CPU_VENDOR_INTEL || 489 cpu_vendor_id == CPU_VENDOR_AMD || 490 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 491 do_cpuid(0x80000000, regs); 492 cpu_exthigh = regs[0]; 493 } 494 if (cpu_exthigh >= 0x80000001) { 495 do_cpuid(0x80000001, regs); 496 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 497 amd_feature2 = regs[2]; 498 } 499 if (cpu_exthigh >= 0x80000008) { 500 do_cpuid(0x80000008, regs); 501 cpu_procinfo2 = regs[2]; 502 } 503 504 /* XXX */ 505 cpu = CPU_CLAWHAMMER; 506 507 if (cpu_feature & CPUID_SSE2) 508 cpu_mi_feature |= CPU_MI_BZERONT; 509 510 if (cpu_feature2 & CPUID2_MON) 511 cpu_mi_feature |= CPU_MI_MONITOR; 512 } 513 514 static u_int 515 find_cpu_vendor_id(void) 516 { 517 int i; 518 519 for (i = 0; i < NELEM(cpu_vendors); i++) 520 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 521 return (cpu_vendors[i].vendor_id); 522 return (0); 523 } 524 525 static void 526 print_AMD_assoc(int i) 527 { 528 if (i == 255) 529 kprintf(", fully associative\n"); 530 else 531 kprintf(", %d-way associative\n", i); 532 } 533 534 static void 535 print_AMD_l2_assoc(int i) 536 { 537 switch (i & 0x0f) { 538 case 0: kprintf(", disabled/not present\n"); break; 539 case 1: kprintf(", direct mapped\n"); break; 540 case 2: kprintf(", 2-way associative\n"); break; 541 case 4: kprintf(", 4-way associative\n"); break; 542 case 6: kprintf(", 8-way associative\n"); break; 543 case 8: kprintf(", 16-way associative\n"); break; 544 case 15: kprintf(", fully associative\n"); break; 545 default: kprintf(", reserved configuration\n"); break; 546 } 547 } 548 549 static void 550 print_AMD_info(void) 551 { 552 u_int regs[4]; 553 554 if (cpu_exthigh < 0x80000005) 555 return; 556 557 do_cpuid(0x80000005, regs); 558 kprintf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 559 print_AMD_assoc(regs[0] >> 24); 560 561 kprintf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 562 print_AMD_assoc((regs[0] >> 8) & 0xff); 563 564 kprintf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 565 print_AMD_assoc(regs[1] >> 24); 566 567 kprintf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 568 print_AMD_assoc((regs[1] >> 8) & 0xff); 569 570 kprintf("L1 data cache: %d kbytes", regs[2] >> 24); 571 kprintf(", %d bytes/line", regs[2] & 0xff); 572 kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff); 573 print_AMD_assoc((regs[2] >> 16) & 0xff); 574 575 kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24); 576 kprintf(", %d bytes/line", regs[3] & 0xff); 577 kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff); 578 print_AMD_assoc((regs[3] >> 16) & 0xff); 579 580 if (cpu_exthigh >= 0x80000006) { 581 do_cpuid(0x80000006, regs); 582 if ((regs[0] >> 16) != 0) { 583 kprintf("L2 2MB data TLB: %d entries", 584 (regs[0] >> 16) & 0xfff); 585 print_AMD_l2_assoc(regs[0] >> 28); 586 kprintf("L2 2MB instruction TLB: %d entries", 587 regs[0] & 0xfff); 588 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 589 } else { 590 kprintf("L2 2MB unified TLB: %d entries", 591 regs[0] & 0xfff); 592 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 593 } 594 if ((regs[1] >> 16) != 0) { 595 kprintf("L2 4KB data TLB: %d entries", 596 (regs[1] >> 16) & 0xfff); 597 print_AMD_l2_assoc(regs[1] >> 28); 598 599 kprintf("L2 4KB instruction TLB: %d entries", 600 (regs[1] >> 16) & 0xfff); 601 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 602 } else { 603 kprintf("L2 4KB unified TLB: %d entries", 604 (regs[1] >> 16) & 0xfff); 605 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 606 } 607 kprintf("L2 unified cache: %d kbytes", regs[2] >> 16); 608 kprintf(", %d bytes/line", regs[2] & 0xff); 609 kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 610 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 611 } 612 } 613 614 static void 615 print_via_padlock_info(void) 616 { 617 u_int regs[4]; 618 619 /* Check for supported models. */ 620 switch (cpu_id & 0xff0) { 621 case 0x690: 622 if ((cpu_id & 0xf) < 3) 623 return; 624 case 0x6a0: 625 case 0x6d0: 626 case 0x6f0: 627 break; 628 default: 629 return; 630 } 631 632 do_cpuid(0xc0000000, regs); 633 if (regs[0] >= 0xc0000001) 634 do_cpuid(0xc0000001, regs); 635 else 636 return; 637 638 kprintf("\n VIA Padlock Features=0x%b", regs[3], 639 "\020" 640 "\003RNG" /* RNG */ 641 "\007AES" /* ACE */ 642 "\011AES-CTR" /* ACE2 */ 643 "\013SHA1,SHA256" /* PHE */ 644 "\015RSA" /* PMM */ 645 ); 646 } 647