1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * Copyright (c) 2008 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 40 */ 41 42 #include "opt_cpu.h" 43 44 #include <sys/param.h> 45 #include <sys/bus.h> 46 #include <sys/eventhandler.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/sysctl.h> 50 #include <sys/power.h> 51 52 #include <machine/asmacros.h> 53 #include <machine/clock.h> 54 #include <machine/cputypes.h> 55 #include <machine/frame.h> 56 #include <machine/segments.h> 57 #include <machine/specialreg.h> 58 #include <machine/md_var.h> 59 60 /* XXX - should be in header file: */ 61 void printcpuinfo(void); 62 void identify_cpu(void); 63 void earlysetcpuclass(void); 64 void panicifcpuunsupported(void); 65 66 static u_int find_cpu_vendor_id(void); 67 static void print_AMD_info(void); 68 static void print_AMD_assoc(int i); 69 static void print_via_padlock_info(void); 70 71 int cpu_class; 72 char machine[] = "x86_64"; 73 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 74 machine, 0, "Machine class"); 75 76 static char cpu_model[128]; 77 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 78 cpu_model, 0, "Machine model"); 79 80 static int hw_clockrate; 81 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 82 &hw_clockrate, 0, "CPU instruction clock rate"); 83 84 static char cpu_brand[48]; 85 86 static struct { 87 char *cpu_name; 88 int cpu_class; 89 } x86_64_cpus[] = { 90 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ 91 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ 92 }; 93 94 static struct { 95 char *vendor; 96 u_int vendor_id; 97 } cpu_vendors[] = { 98 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 99 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 100 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 101 }; 102 103 #ifdef foo 104 static int cpu_cores; 105 static int cpu_logical; 106 #endif 107 108 void 109 printcpuinfo(void) 110 { 111 u_int regs[4], i; 112 char *brand; 113 114 cpu_class = x86_64_cpus[cpu].cpu_class; 115 kprintf("CPU: "); 116 strncpy(cpu_model, x86_64_cpus[cpu].cpu_name, sizeof (cpu_model)); 117 118 /* Check for extended CPUID information and a processor name. */ 119 if (cpu_exthigh >= 0x80000004) { 120 brand = cpu_brand; 121 for (i = 0x80000002; i < 0x80000005; i++) { 122 do_cpuid(i, regs); 123 memcpy(brand, regs, sizeof(regs)); 124 brand += sizeof(regs); 125 } 126 } 127 128 switch (cpu_vendor_id) { 129 case CPU_VENDOR_INTEL: 130 /* Please make up your mind folks! */ 131 strcat(cpu_model, "EM64T"); 132 break; 133 case CPU_VENDOR_AMD: 134 /* 135 * Values taken from AMD Processor Recognition 136 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 137 * (also describes ``Features'' encodings. 138 */ 139 strcpy(cpu_model, "AMD "); 140 if ((cpu_id & 0xf00) == 0xf00) 141 strcat(cpu_model, "AMD64 Processor"); 142 else 143 strcat(cpu_model, "Unknown"); 144 break; 145 case CPU_VENDOR_CENTAUR: 146 strcpy(cpu_model, "VIA "); 147 if ((cpu_id & 0xff0) == 0x6f0) 148 strcat(cpu_model, "Nano Processor"); 149 else 150 strcat(cpu_model, "Unknown"); 151 break; 152 default: 153 strcat(cpu_model, "Unknown"); 154 break; 155 } 156 157 /* 158 * Replace cpu_model with cpu_brand minus leading spaces if 159 * we have one. 160 */ 161 brand = cpu_brand; 162 while (*brand == ' ') 163 ++brand; 164 if (*brand != '\0') 165 strcpy(cpu_model, brand); 166 167 kprintf("%s (", cpu_model); 168 switch(cpu_class) { 169 case CPUCLASS_K8: 170 hw_clockrate = (tsc_frequency + 5000) / 1000000; 171 kprintf("%jd.%02d-MHz ", 172 (intmax_t)(tsc_frequency + 4999) / 1000000, 173 (u_int)((tsc_frequency + 4999) / 10000) % 100); 174 kprintf("K8"); 175 break; 176 default: 177 kprintf("Unknown"); /* will panic below... */ 178 } 179 kprintf("-class CPU)\n"); 180 if (*cpu_vendor) 181 kprintf(" Origin = \"%s\"", cpu_vendor); 182 if (cpu_id) 183 kprintf(" Id = 0x%x", cpu_id); 184 185 if (cpu_vendor_id == CPU_VENDOR_INTEL || 186 cpu_vendor_id == CPU_VENDOR_AMD || 187 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 188 kprintf(" Stepping = %u", cpu_id & 0xf); 189 if (cpu_high > 0) { 190 #if 0 191 u_int cmp = 1, htt = 1; 192 #endif 193 194 /* 195 * Here we should probably set up flags indicating 196 * whether or not various features are available. 197 * The interesting ones are probably VME, PSE, PAE, 198 * and PGE. The code already assumes without bothering 199 * to check that all CPUs >= Pentium have a TSC and 200 * MSRs. 201 */ 202 kprintf("\n Features=0x%b", cpu_feature, 203 "\020" 204 "\001FPU" /* Integral FPU */ 205 "\002VME" /* Extended VM86 mode support */ 206 "\003DE" /* Debugging Extensions (CR4.DE) */ 207 "\004PSE" /* 4MByte page tables */ 208 "\005TSC" /* Timestamp counter */ 209 "\006MSR" /* Machine specific registers */ 210 "\007PAE" /* Physical address extension */ 211 "\010MCE" /* Machine Check support */ 212 "\011CX8" /* CMPEXCH8 instruction */ 213 "\012APIC" /* SMP local APIC */ 214 "\013oldMTRR" /* Previous implementation of MTRR */ 215 "\014SEP" /* Fast System Call */ 216 "\015MTRR" /* Memory Type Range Registers */ 217 "\016PGE" /* PG_G (global bit) support */ 218 "\017MCA" /* Machine Check Architecture */ 219 "\020CMOV" /* CMOV instruction */ 220 "\021PAT" /* Page attributes table */ 221 "\022PSE36" /* 36 bit address space support */ 222 "\023PN" /* Processor Serial number */ 223 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 224 "\025<b20>" 225 "\026DTS" /* Debug Trace Store */ 226 "\027ACPI" /* ACPI support */ 227 "\030MMX" /* MMX instructions */ 228 "\031FXSR" /* FXSAVE/FXRSTOR */ 229 "\032SSE" /* Streaming SIMD Extensions */ 230 "\033SSE2" /* Streaming SIMD Extensions #2 */ 231 "\034SS" /* Self snoop */ 232 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 233 "\036TM" /* Thermal Monitor clock slowdown */ 234 "\037IA64" /* CPU can execute IA64 instructions */ 235 "\040PBE" /* Pending Break Enable */ 236 ); 237 238 if (cpu_feature2 != 0) { 239 kprintf("\n Features2=0x%b", cpu_feature2, 240 "\020" 241 "\001SSE3" /* SSE3 */ 242 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 243 "\003DTES64" /* 64-bit Debug Trace */ 244 "\004MON" /* MONITOR/MWAIT Instructions */ 245 "\005DS_CPL" /* CPL Qualified Debug Store */ 246 "\006VMX" /* Virtual Machine Extensions */ 247 "\007SMX" /* Safer Mode Extensions */ 248 "\010EST" /* Enhanced SpeedStep */ 249 "\011TM2" /* Thermal Monitor 2 */ 250 "\012SSSE3" /* SSSE3 */ 251 "\013CNXT-ID" /* L1 context ID available */ 252 "\014<b11>" 253 "\015FMA" /* Fused Multiply Add */ 254 "\016CX16" /* CMPXCHG16B Instruction */ 255 "\017xTPR" /* Send Task Priority Messages */ 256 "\020PDCM" /* Perf/Debug Capability MSR */ 257 "\021<b16>" 258 "\022PCID" /* Process-context Identifiers */ 259 "\023DCA" /* Direct Cache Access */ 260 "\024SSE4.1" /* SSE 4.1 */ 261 "\025SSE4.2" /* SSE 4.2 */ 262 "\026x2APIC" /* xAPIC Extensions */ 263 "\027MOVBE" /* MOVBE Instruction */ 264 "\030POPCNT" /* POPCNT Instruction */ 265 "\031TSCDLT" /* TSC-Deadline Timer */ 266 "\032AESNI" /* AES Crypto */ 267 "\033XSAVE" /* XSAVE/XRSTOR States */ 268 "\034OSXSAVE" /* OS-Enabled State Management */ 269 "\035AVX" /* Advanced Vector Extensions */ 270 "\036F16C" /* Half-precision conversions */ 271 "\037RDRND" /* RDRAND RNG function */ 272 "\040VMM" /* Running on a hypervisor */ 273 ); 274 } 275 276 /* 277 * AMD64 Architecture Programmer's Manual Volume 3: 278 * General-Purpose and System Instructions 279 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf 280 * 281 * IA-32 Intel Architecture Software Developer's Manual, 282 * Volume 2A: Instruction Set Reference, A-M 283 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf 284 */ 285 if (amd_feature != 0) { 286 kprintf("\n AMD Features=0x%b", amd_feature, 287 "\020" /* in hex */ 288 "\001<s0>" /* Same */ 289 "\002<s1>" /* Same */ 290 "\003<s2>" /* Same */ 291 "\004<s3>" /* Same */ 292 "\005<s4>" /* Same */ 293 "\006<s5>" /* Same */ 294 "\007<s6>" /* Same */ 295 "\010<s7>" /* Same */ 296 "\011<s8>" /* Same */ 297 "\012<s9>" /* Same */ 298 "\013<b10>" /* Undefined */ 299 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 300 "\015<s12>" /* Same */ 301 "\016<s13>" /* Same */ 302 "\017<s14>" /* Same */ 303 "\020<s15>" /* Same */ 304 "\021<s16>" /* Same */ 305 "\022<s17>" /* Same */ 306 "\023<b18>" /* Reserved, unknown */ 307 "\024MP" /* Multiprocessor Capable */ 308 "\025NX" /* Has EFER.NXE, NX */ 309 "\026<b21>" /* Undefined */ 310 "\027MMX+" /* AMD MMX Extensions */ 311 "\030<s23>" /* Same */ 312 "\031<s24>" /* Same */ 313 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 314 "\033Page1GB" /* 1-GB large page support */ 315 "\034RDTSCP" /* RDTSCP */ 316 "\035<b28>" /* Undefined */ 317 "\036LM" /* 64 bit long mode */ 318 "\0373DNow!+" /* AMD 3DNow! Extensions */ 319 "\0403DNow!" /* AMD 3DNow! */ 320 ); 321 } 322 323 if (amd_feature2 != 0) { 324 kprintf("\n AMD Features2=0x%b", amd_feature2, 325 "\020" 326 "\001LAHF" /* LAHF/SAHF in long mode */ 327 "\002CMP" /* CMP legacy */ 328 "\003SVM" /* Secure Virtual Mode */ 329 "\004ExtAPIC" /* Extended APIC register */ 330 "\005CR8" /* CR8 in legacy mode */ 331 "\006ABM" /* LZCNT instruction */ 332 "\007SSE4A" /* SSE4A */ 333 "\010MAS" /* Misaligned SSE mode */ 334 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 335 "\012OSVW" /* OS visible workaround */ 336 "\013IBS" /* Instruction based sampling */ 337 "\014XOP" /* XOP extended instructions */ 338 "\015SKINIT" /* SKINIT/STGI */ 339 "\016WDT" /* Watchdog timer */ 340 "\017<b14>" 341 "\020LWP" /* Lightweight Profiling */ 342 "\021FMA4" /* 4-operand FMA instructions */ 343 "\022TCE" /* Translation Cache Extension */ 344 "\023<b18>" 345 "\024NodeId" /* NodeId MSR support */ 346 "\025<b20>" 347 "\026TBM" /* Trailing Bit Manipulation */ 348 "\027Topology" /* Topology Extensions */ 349 "\030PCX_CORE" /* Core Performance Counter */ 350 "\031PCX_NB" /* NB Performance Counter */ 351 "\032<b25>" 352 "\033<b26>" 353 "\034<b27>" 354 "\035<b28>" 355 "\036<b29>" 356 "\037<b30>" 357 "\040<b31>" 358 ); 359 } 360 361 if (cpu_vendor_id == CPU_VENDOR_CENTAUR) 362 print_via_padlock_info(); 363 /* 364 * INVALID CPU TOPOLOGY INFORMATION PRINT 365 * DEPRECATED - CPU_TOPOLOGY_DETECTION moved to 366 * - sys/platform/pc64/x86_64/mp_machdep.c 367 * - sys/kern/subr_cpu_topology 368 */ 369 370 #if 0 371 if ((cpu_feature & CPUID_HTT) && 372 cpu_vendor_id == CPU_VENDOR_AMD) 373 cpu_feature &= ~CPUID_HTT; 374 #endif 375 376 /* 377 * If this CPU supports HTT or CMP then mention the 378 * number of physical/logical cores it contains. 379 */ 380 #if 0 381 if (cpu_feature & CPUID_HTT) 382 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 383 if (cpu_vendor_id == CPU_VENDOR_AMD && 384 (amd_feature2 & AMDID2_CMP)) 385 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 386 else if (cpu_vendor_id == CPU_VENDOR_INTEL && 387 (cpu_high >= 4)) { 388 cpuid_count(4, 0, regs); 389 if ((regs[0] & 0x1f) != 0) 390 cmp = ((regs[0] >> 26) & 0x3f) + 1; 391 } 392 #endif 393 #ifdef foo 394 /* 395 * XXX For Intel CPUs, this is max number of cores per 396 * package, not the actual cores per package. 397 */ 398 #if 0 399 cpu_cores = cmp; 400 cpu_logical = htt / cmp; 401 402 if (cpu_cores > 1) 403 kprintf("\n Cores per package: %d", cpu_cores); 404 if (cpu_logical > 1) { 405 kprintf("\n Logical CPUs per core: %d", 406 cpu_logical); 407 } 408 #endif 409 #endif 410 } 411 } 412 /* Avoid ugly blank lines: only print newline when we have to. */ 413 if (*cpu_vendor || cpu_id) 414 kprintf("\n"); 415 416 if (!bootverbose) 417 return; 418 419 if (cpu_vendor_id == CPU_VENDOR_AMD) 420 print_AMD_info(); 421 } 422 423 void 424 panicifcpuunsupported(void) 425 { 426 427 #ifndef HAMMER_CPU 428 #error "You need to specify a cpu type" 429 #endif 430 /* 431 * Now that we have told the user what they have, 432 * let them know if that machine type isn't configured. 433 */ 434 switch (cpu_class) { 435 case CPUCLASS_X86: 436 #ifndef HAMMER_CPU 437 case CPUCLASS_K8: 438 #endif 439 panic("CPU class not configured"); 440 default: 441 break; 442 } 443 } 444 445 446 #if JG 447 /* Update TSC freq with the value indicated by the caller. */ 448 static void 449 tsc_freq_changed(void *arg, const struct cf_level *level, int status) 450 { 451 /* If there was an error during the transition, don't do anything. */ 452 if (status != 0) 453 return; 454 455 /* Total setting for this level gives the new frequency in MHz. */ 456 hw_clockrate = level->total_set.freq; 457 } 458 459 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL, 460 EVENTHANDLER_PRI_ANY); 461 #endif 462 463 /* 464 * Final stage of CPU identification. 465 */ 466 void 467 identify_cpu(void) 468 { 469 u_int regs[4]; 470 471 do_cpuid(0, regs); 472 cpu_high = regs[0]; 473 ((u_int *)&cpu_vendor)[0] = regs[1]; 474 ((u_int *)&cpu_vendor)[1] = regs[3]; 475 ((u_int *)&cpu_vendor)[2] = regs[2]; 476 cpu_vendor[12] = '\0'; 477 cpu_vendor_id = find_cpu_vendor_id(); 478 479 do_cpuid(1, regs); 480 cpu_id = regs[0]; 481 cpu_procinfo = regs[1]; 482 cpu_feature = regs[3]; 483 cpu_feature2 = regs[2]; 484 485 if (cpu_vendor_id == CPU_VENDOR_INTEL || 486 cpu_vendor_id == CPU_VENDOR_AMD || 487 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 488 do_cpuid(0x80000000, regs); 489 cpu_exthigh = regs[0]; 490 } 491 if (cpu_exthigh >= 0x80000001) { 492 do_cpuid(0x80000001, regs); 493 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 494 amd_feature2 = regs[2]; 495 } 496 if (cpu_exthigh >= 0x80000008) { 497 do_cpuid(0x80000008, regs); 498 cpu_procinfo2 = regs[2]; 499 } 500 501 /* XXX */ 502 cpu = CPU_CLAWHAMMER; 503 504 if (cpu_feature & CPUID_SSE2) 505 cpu_mi_feature |= CPU_MI_BZERONT; 506 507 if (cpu_feature2 & CPUID2_MON) 508 cpu_mi_feature |= CPU_MI_MONITOR; 509 } 510 511 static u_int 512 find_cpu_vendor_id(void) 513 { 514 int i; 515 516 for (i = 0; i < NELEM(cpu_vendors); i++) 517 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 518 return (cpu_vendors[i].vendor_id); 519 return (0); 520 } 521 522 static void 523 print_AMD_assoc(int i) 524 { 525 if (i == 255) 526 kprintf(", fully associative\n"); 527 else 528 kprintf(", %d-way associative\n", i); 529 } 530 531 static void 532 print_AMD_l2_assoc(int i) 533 { 534 switch (i & 0x0f) { 535 case 0: kprintf(", disabled/not present\n"); break; 536 case 1: kprintf(", direct mapped\n"); break; 537 case 2: kprintf(", 2-way associative\n"); break; 538 case 4: kprintf(", 4-way associative\n"); break; 539 case 6: kprintf(", 8-way associative\n"); break; 540 case 8: kprintf(", 16-way associative\n"); break; 541 case 15: kprintf(", fully associative\n"); break; 542 default: kprintf(", reserved configuration\n"); break; 543 } 544 } 545 546 static void 547 print_AMD_info(void) 548 { 549 u_int regs[4]; 550 551 if (cpu_exthigh < 0x80000005) 552 return; 553 554 do_cpuid(0x80000005, regs); 555 kprintf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 556 print_AMD_assoc(regs[0] >> 24); 557 558 kprintf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 559 print_AMD_assoc((regs[0] >> 8) & 0xff); 560 561 kprintf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 562 print_AMD_assoc(regs[1] >> 24); 563 564 kprintf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 565 print_AMD_assoc((regs[1] >> 8) & 0xff); 566 567 kprintf("L1 data cache: %d kbytes", regs[2] >> 24); 568 kprintf(", %d bytes/line", regs[2] & 0xff); 569 kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff); 570 print_AMD_assoc((regs[2] >> 16) & 0xff); 571 572 kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24); 573 kprintf(", %d bytes/line", regs[3] & 0xff); 574 kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff); 575 print_AMD_assoc((regs[3] >> 16) & 0xff); 576 577 if (cpu_exthigh >= 0x80000006) { 578 do_cpuid(0x80000006, regs); 579 if ((regs[0] >> 16) != 0) { 580 kprintf("L2 2MB data TLB: %d entries", 581 (regs[0] >> 16) & 0xfff); 582 print_AMD_l2_assoc(regs[0] >> 28); 583 kprintf("L2 2MB instruction TLB: %d entries", 584 regs[0] & 0xfff); 585 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 586 } else { 587 kprintf("L2 2MB unified TLB: %d entries", 588 regs[0] & 0xfff); 589 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 590 } 591 if ((regs[1] >> 16) != 0) { 592 kprintf("L2 4KB data TLB: %d entries", 593 (regs[1] >> 16) & 0xfff); 594 print_AMD_l2_assoc(regs[1] >> 28); 595 596 kprintf("L2 4KB instruction TLB: %d entries", 597 (regs[1] >> 16) & 0xfff); 598 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 599 } else { 600 kprintf("L2 4KB unified TLB: %d entries", 601 (regs[1] >> 16) & 0xfff); 602 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 603 } 604 kprintf("L2 unified cache: %d kbytes", regs[2] >> 16); 605 kprintf(", %d bytes/line", regs[2] & 0xff); 606 kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 607 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 608 } 609 } 610 611 static void 612 print_via_padlock_info(void) 613 { 614 u_int regs[4]; 615 616 /* Check for supported models. */ 617 switch (cpu_id & 0xff0) { 618 case 0x690: 619 if ((cpu_id & 0xf) < 3) 620 return; 621 case 0x6a0: 622 case 0x6d0: 623 case 0x6f0: 624 break; 625 default: 626 return; 627 } 628 629 do_cpuid(0xc0000000, regs); 630 if (regs[0] >= 0xc0000001) 631 do_cpuid(0xc0000001, regs); 632 else 633 return; 634 635 kprintf("\n VIA Padlock Features=0x%b", regs[3], 636 "\020" 637 "\003RNG" /* RNG */ 638 "\007AES" /* ACE */ 639 "\011AES-CTR" /* ACE2 */ 640 "\013SHA1,SHA256" /* PHE */ 641 "\015RSA" /* PMM */ 642 ); 643 } 644